Display substrate, display device, and display substrate testing method

Abstract

A display substrate, a display device, and a method for testing a display substrate. The display substrate includes a display area and a peripheral area disposed outside the display area. A first guide trace extending along a first direction is disposed in the peripheral area, the first guide trace including a first end and a second end; a first test line is also disposed in the peripheral area, the first test line being electrically connected to the first guide trace at a first position on the first guide trace, the first position being located between the first end and the second end; the display area includes a first group of multiple first signal lines extending along a second direction different from the first direction and arranged side by side, the two outermost first signal lines in the multiple first group of first signal lines being coupled to the first end and the second end, respectively, and the remaining first signal lines in the multiple first group of first signal lines being coupled to the first guide trace between the first end and the second end.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display substrate, a display device, and a method for testing the display substrate. Background Art

[0002] In order to improve the yield rate of display devices and reduce the production cost of display devices, defect detection and repair processes are set up in multiple key process links of display device production. The following is an example of a liquid crystal display device. The production process of a liquid crystal display device includes an array substrate production process, a color filter substrate production process, a liquid crystal cell production process, and a liquid crystal module production process. For example, to improve the yield rate of the liquid crystal module production process and reduce the production cost of the liquid crystal module production process, after the liquid crystal cell is cut from the motherboard (Qpanel) (that is, after the liquid crystal cell production process is completed), the liquid crystal cell will be tested (for example, defect detection) to prevent defective liquid crystal cells from entering the subsequent liquid crystal module production process as much as possible. In addition, improving the defect detection rate of the liquid crystal cell test stage has a significant impact on the production cost and production yield of the liquid crystal module production process. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a display substrate, which includes a display area and a peripheral area arranged outside the display area. A first guide trace extending along a first direction is provided in the peripheral area, and the first guide trace includes a first end and a second end; a first test line is also provided in the peripheral area, and the first test line is electrically connected to the first guide trace at a first position on the first guide trace, and the first position is located between the first end and the second end; the display area includes a plurality of first groups of first signal lines extending along a second direction different from the first direction and arranged side by side, the two outermost first signal lines in the plurality of first groups of first signal lines are coupled to the first end and the second end respectively, and the remaining first signal lines in the plurality of first groups of first signal lines are coupled to the first guide trace between the first end and the second end.

[0004] For example, in at least one example of the display substrate, the first position is a midpoint of resistance between a first end and a second end of the first guide trace.

[0005] For example, in at least one example of the display substrate, the first test line is further electrically connected to the first guide trace at a second position on the first guide trace, where the second position is between the first end and the second end and is different from the first position.

[0006] For example, in at least one example of the display substrate, the first position and the second position are respectively located at a resistance 1 / 3 point and a resistance 2 / 3 point between the first end and the second end of the first guide trace.

[0007] For example, in at least one example of the display substrate, the display area also includes a plurality of second signal lines extending along the first direction and arranged side by side, the plurality of second signal lines cross and are insulated from the first group of first signal lines, and the first guide wiring and the plurality of second signal lines are arranged on the same layer.

[0008] For example, in at least one example of the display substrate, the first test line includes a first portion extending along the second direction, and the first portion and the first group of first signal lines are provided in the same layer.

[0009] For example, in at least one example of the display substrate, the peripheral area includes a bonding area and a bonding opposing area; the bonding area and the bonding opposing area are respectively located on both sides of the display area along the second direction; and the first guide trace is arranged in the bonding opposing area.

[0010] For example, in at least one example of the display substrate, the bonding region includes a first test pad, one end of the first test line is electrically connected to the first test pad, and the other end of the first test line is electrically connected to the first position.

[0011] For example, in at least one example of the display substrate, the bonding region includes a plurality of first signal pads of a first group, and the plurality of first signal lines are coupled to the plurality of first signal pads of the first group in a one-to-one correspondence.

[0012] For example, in at least one example of the display substrate, the bonding opposing area also includes a plurality of first-group control switches, the first ends of the plurality of first-group control switches are electrically connected one-to-one with the plurality of first-group first signal lines, and the second ends of the plurality of first-group control switches are electrically connected with the first guide traces.

[0013] For example, in at least one example of the display substrate, the bonding opposing area is further provided with a second guide trace, the second guide trace extends along the first direction and includes a third end and a fourth end; the peripheral area is further provided with a second test line, the second test line is electrically connected to the second guide trace at a third position on the second guide trace, and the third position is located between the third end and the fourth end; the display area also includes a plurality of second groups of first signal lines extending along the second direction and arranged side by side, the two outermost first signal lines in the plurality of second groups of first signal lines are coupled to the third end and the fourth end respectively, and the remaining first signal lines in the plurality of second groups of first signal lines are coupled to the second guide trace between the third end and the fourth end.

[0014] For example, in at least one example of the display substrate, the bonding area further includes a second test pad, one end of the second test line is electrically connected to the second test pad, and the other end of the second test line is electrically connected to the third position.

[0015] For example, in at least one example of the display substrate, the bonding opposing area is further provided with a third guide trace, the third guide trace extending along the first direction and including a fifth end and a sixth end; the peripheral area is further provided with a third test line, the third test line is electrically connected to the third guide trace at a fourth position on the third guide trace, and the fourth position is located between the fifth end and the sixth end; the display area also includes a plurality of third groups of first signal lines extending along the second direction and arranged side by side, the two outermost first signal lines in the plurality of third groups of first signal lines are coupled to the fifth end and the sixth end respectively, and the remaining first signal lines in the plurality of third groups of first signal lines are coupled to the third guide trace between the fifth end and the sixth end; the bonding area also includes a third test pad, one end of the third test line is electrically connected to the third test pad, and the other end of the third test line is electrically connected to the fourth position.

[0016] For example, in at least one example of the display substrate, the bonding area further includes a first test pad, one end of the first test line is electrically connected to the first test pad and the other end of the first test line is electrically connected to the first position; the first test pad and the second test pad are located on one side of the display area in the first direction, and the third test pad is located on the other side of the display area in the first direction.

[0017] For example, in at least one example of the display substrate, the first resistance ratio, the second resistance ratio and the third resistance ratio are equal to each other; the first resistance ratio is the ratio of the resistance value between the first end and the first position of the first guide trace to the resistance value between the first position and the second end of the first guide trace; the second resistance ratio is the ratio of the resistance value between the third end and the third position of the second guide trace to the resistance value between the third position and the fourth end of the second guide trace; the third resistance ratio is the ratio of the resistance value between the fifth end and the fourth position of the third guide trace to the resistance value between the fourth position and the sixth end of the third guide trace.

[0018] For example, in at least one example of the display substrate, the first position is the midpoint of the resistance between the first end and the second end of the first guide trace; the third position is the midpoint of the resistance between the third end and the fourth end of the second guide trace; and the fourth position is the midpoint of the resistance between the fifth end and the sixth end of the third guide trace.

[0019] For example, in at least one example of the display substrate, the plurality of first signal lines of the first group, the plurality of second signal lines of the first group, and the plurality of third signal lines of the first group are respectively used to transmit data signals of sub-pixels displaying light of different colors.

[0020] For example, in at least one example of the display substrate, resistances of the first test line, the second test line, and the third test line are equal to each other.

[0021] At least one embodiment of the present disclosure further provides a display device, which includes the display substrate provided by any embodiment of the present disclosure.

[0022] At least one embodiment of the present disclosure further provides a method for testing the display substrate, comprising: applying a first signal to a first group of multiple first signal lines via a first test line and a first guide line, and performing detection based on a display condition of the display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0024] Figure 1 It is a planar schematic diagram showing a substrate;

[0025] Figure 2A yes Figure 1The test timing diagram of the voltage signals at the first position and the third position on the second test line of the display substrate is shown;

[0026] Figure 2B yes Figure 2A An enlarged view of the voltage signal of the local area shown;

[0027] Figure 3 yes Figure 1 The simulation timing diagram of the voltage signals at the first position and the third position on the second test line of the display substrate is shown;

[0028] Figure 4 yes Figure 1 The brightness distribution diagram of the first display sub-pixel, the second display sub-pixel and the third display sub-pixel of the display substrate shown in FIG. Figure 1 The display pixel color distribution diagram of the display substrate shown;

[0029] Figure 5 is a schematic plan view of a display substrate provided by some embodiments of the present disclosure;

[0030] Figure 6 yes Figure 5 A curve showing changes in voltage signals at a first end and a second end of a first guide trace of a display substrate over time;

[0031] Figure 7 yes Figure 5 The brightness distribution diagram of the first display sub-pixel, the second display sub-pixel and the third display sub-pixel of the display substrate shown in FIG. Figure 5 The display pixel color and brightness distribution diagram of the display substrate shown;

[0032] Figure 8 Another structure of a first test line and a first guide line provided by some embodiments of the present disclosure;

[0033] Figure 9 is an exemplary block diagram of a display device provided by some embodiments of the present disclosure; and

[0034] Figure 10 is a planar schematic diagram of another display substrate provided by some embodiments of the present disclosure. DETAILED DESCRIPTION

[0035] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0036] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the field to which the present disclosure pertains. The terms "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are merely used to distinguish between different components. Similarly, terms such as "include" or "comprise" and the like mean that the elements or objects preceding the term encompass the elements or objects listed following the term and their equivalents, without excluding other elements or objects. Terms such as "connect" or "connected" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "upper", "lower", "left", and "right" are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0037] The inventors of the present disclosure have noticed that the current test trace design of the display substrate causes, during testing (e.g., defect detection), the display substrate to have uneven brightness and / or color deviation problems caused by the test trace (e.g., the resistance and parasitic capacitance of the test trace). Therefore, the defects related to brightness and / or color deviation in the display substrate are easily masked by the brightness differences and / or color deviation caused by the test trace design of the display substrate, or the inspection personnel and / or the inspection device (e.g., the optical automatic inspection device) tend to ignore the defects related to brightness and / or color deviation in the display sub-pixels. This reduces the defect detection rate of the display substrate test (i.e., increases the defect missed detection rate), increases the waste of resources in subsequent processes, and thus increases the production cost of the display substrate and the display device including the display substrate.

[0038] The following combination Figure 1 The display substrate is shown for illustrative purposes only.

[0039] Figure 1 A schematic plan view of a display substrate 500 is shown. The display substrate 500 may be a liquid crystal display substrate (eg, an array substrate of a liquid crystal cell) or a self-luminous display substrate (eg, an array substrate of a display panel of an organic light emitting diode).

[0040] like Figure 1 As shown, the display substrate 500 includes a display area 540 and a peripheral area disposed outside the display area (e.g., around the display area 540). The peripheral area includes a bonding area 530 and a bonding opposing area 520 disposed opposite to the bonding area 530, and the bonding area 530 and the bonding opposing area 520 are respectively located on opposite sides of the display area 540 along a second direction D2 different from the first direction D1 (e.g., respectively located on the sides of the display area 540). Figure 1The bonding opposing region 520 extends along the first direction D1.

[0041] like Figure 1 As shown, the display area 540 includes a first group of multiple first signal lines 541 extending and arranged in parallel along the second direction D2, a second group of multiple first signal lines 542 extending and arranged in parallel along the second direction D2, and a third group of multiple first signal lines 543 extending and arranged in parallel along the second direction D2. The first group of multiple first signal lines 541, the second group of multiple first signal lines 542, and the third group of multiple first signal lines 543 are respectively used to transmit data signals of sub-pixels that display light of different colors.

[0042] For example, the first signal lines are data lines. For example, the first plurality of signal lines 541 are used to transmit data signals for sub-pixels displaying green light, the second plurality of signal lines 542 are used to transmit data signals for sub-pixels displaying red light, and the third plurality of signal lines 543 are used to transmit data signals for sub-pixels displaying blue light.

[0043] like Figure 1 As shown, the display area 540 further includes a plurality of second signal lines 544 extending in parallel along the first direction D1. The plurality of second signal lines 544 intersect and are insulated from the plurality of first signal lines (i.e., the plurality of first signal lines 541 of the first group, the plurality of first signal lines 542 of the second group, and the plurality of first signal lines 543 of the third group), thereby defining a plurality of display sub-pixels arranged in an array. For example, the second signal lines 544 are gate lines and are used to transmit scanning signals.

[0044] For example, the display area 540 includes a plurality of display pixels arranged in an array ( Figure 1 (not shown), each display pixel includes a first display sub-pixel, a second display sub-pixel, and a third display sub-pixel, which are electrically connected to the first group of first signal lines 541, the second group of first signal lines 542, and the third group of first signal lines 543, respectively, to emit light based on data signals provided by the first group of first signal lines 541, the second group of first signal lines 542, and the third group of first signal lines 543. For example, the first display sub-pixel, the second display sub-pixel, and the third display sub-pixel are configured to emit green light, red light, and blue light, respectively.

[0045] like Figure 1As shown, bonding region 530 includes a first plurality of first signal pads 535, a second plurality of first signal pads 536, and a third plurality of first signal pads 537. A first plurality of first signal lines 541 are coupled to the first plurality of first signal pads 535 in a one-to-one relationship. A second plurality of first signal lines 542 are coupled to the second plurality of first signal pads 536 in a one-to-one relationship. A third plurality of first signal lines 543 are coupled to the third plurality of first signal pads 537 in a one-to-one relationship. For example, the first plurality of first signal pads 535, the second plurality of first signal pads 536, and the third plurality of first signal pads 537 are connected to a data driver via, for example, a flexible printed circuit board in a subsequent process to receive data signals from the data driver and provide the data signals to the corresponding first signal lines.

[0046] like Figure 1 As shown, the bonding area 530 further includes a plurality of second signal pads 538, and the plurality of second signal lines 544 are coupled to the plurality of second signal pads 538 in a one-to-one correspondence. For example, the plurality of second signal pads 538 are used to connect to a gate driver via, for example, a flexible printed circuit board in a subsequent process to receive a plurality of scan signals from the gate driver and provide the plurality of scan signals to the corresponding second signal lines 544.

[0047] like Figure 1 As shown, the bonding area 530 further includes a first test pad 531 , a second test pad 532 , a third test pad 533 and a control signal pad 534 .

[0048] like Figure 1 As shown, the peripheral area is provided with a first test line 511, a second test line 512, a third test line 513 and a test control line 514, the first test line 511 is connected to the first test pad 531 and is included in a first portion extending along the first direction D1 in the bonding opposing area 520, the second test line 512 is connected to the second test pad 532 and is included in a second portion extending along the first direction D1 in the bonding opposing area 520, the third test line 513 is connected to the third test pad 533 and is included in a third portion extending along the first direction D1 in the bonding opposing area 520, and the test control line 514 is connected to the control signal pad 534 and is included in a fourth portion extending along the first direction D1 in the bonding opposing area 520.

[0049] For example, the bonding area 530 further includes a scan signal pad (not shown in the figure), and a scan test line (not shown in the figure) is further provided in the peripheral area, with both ends of the scan test line electrically connected to the scan signal pad and the second data line respectively.

[0050] like Figure 1 As shown, the bonding region 520 further includes a plurality of first control switches 524 , a plurality of second control switches 525 , and a plurality of third control switches 526 .

[0051] like Figure 1 As shown, the first ends of the multiple first group control switches 524 are electrically connected to the multiple first group first signal lines 541 in a one-to-one correspondence, and the second ends of the multiple first group control switches 524 are electrically connected to the first part of the first test line 511; the third ends (control ends) of the multiple first group control switches 524 are electrically connected to the fourth part of the test control line 514 to control the opening and closing of the multiple first group control switches 524 based on the control signal applied to the control signal pad 534, thereby controlling whether the first test data signal applied to the first test pad 531 is applied to the multiple first group first signal lines 541 via the first part of the first test line 511.

[0052] like Figure 1 As shown, the first ends of the multiple second-group control switches 525 are electrically connected to the multiple second-group first signal lines 542 in a one-to-one correspondence, and the second ends of the multiple second-group control switches 525 are electrically connected to the second part of the second test line 512; the third ends (control ends) of the multiple second-group control switches 525 are electrically connected to the fourth part of the test control line 514 to control the opening and closing of the multiple second-group control switches 525 based on the control signal applied to the control signal pad 534, thereby controlling whether the second test data signal applied to the second test pad 532 is applied to the multiple second-group first signal lines 542 via the second part of the second test line 512.

[0053] like Figure 1 As shown, the first ends of the multiple third groups of control switches 526 are electrically connected to the multiple third groups of first signal lines 543 in a one-to-one correspondence, and the second ends of the multiple third groups of control switches 526 are electrically connected to the third part; the third ends (control ends) of the multiple third groups of control switches 526 are electrically connected to the fourth part of the test control line 514 to control the opening and closing of the multiple third groups of control switches 526 based on the control signal applied to the control signal pad 534, thereby controlling whether the third test data signal applied to the third test pad 533 is applied to the multiple third groups of first signal lines 543 via the third part of the third test line 513.

[0054] For example, in the Figure 1 When the display device of the display substrate 500 is performing normal display, an invalid signal can be applied to the control signal pad 534 to turn off the control switch. For example, when the control switch is an N-type transistor, the invalid signal is a low-level signal, or the control signal pad 534 is grounded or left floating. Turning off the control switch can prevent the first test line 511, the second test line 512, and the third test line 513 from adversely affecting the display device.

[0055] For example, when testing the display substrate 500 (e.g., a liquid crystal cell test), a data signal can be applied to at least one of the first test pad 531, the second test pad 532, and the third test pad 533. A valid signal (a level signal that turns on a control switch) can be applied to the control signal pad 534 to turn on the control switch, thereby transmitting the data signal applied to at least one of the first test pad 531, the second test pad 532, and the third test pad 533 to the corresponding signal line (data line). Simultaneously, a gate scan signal can be applied to the scan signal pad so that the data signal transmitted to the corresponding signal line (data line) can be written into the display sub-pixel to drive the corresponding display sub-pixel to emit light.

[0056] For example, Figure 1 As shown, the first test pad 531 and the second test pad 532 are located on one side of the display area 540 in the first direction D1, and the third test pad 533 and the control signal pad 534 are located on the other side of the display area 540 in the first direction D1. Figure 1 As shown, the first test line 511 and the second test line 512 extend from the lower left corner of the display substrate 500 to the upper right corner of the display substrate 500 , and the third test line 513 and the test control line 514 extend from the lower right corner of the display substrate 500 to the upper left corner of the display substrate 500 .

[0057] The inventors of the present disclosure noted that arranging the first test pad 531, the second test pad 532, and the third test pad 533 on both sides of the display area 540 in the first direction D1 can meet the wiring requirements of a specific display substrate (for example, a display substrate based on gate driver integration on an array substrate) (for example, a small wiring space) and can also increase the range of test equipment selection (for example, the requirement for the number of test signal channels of the test equipment is reduced).

[0058] However, the inventors of the present disclosure noticed in their research that for the same test line (for example, the first test line 511, the second test line 512 or the third test line 513), due to the presence of resistance and parasitic capacitance in the test line, after the current flows through the test line, the phase delay and signal amplitude (or voltage drop) of the signal at different positions of the test line are different, thereby causing the display area 540 to have brightness differences at different positions (at the same moment), that is, when the display substrate is tested, the display area 540 has a brightness unevenness problem. For example, when the test data signal applied to the test pad changes, the phase delay of the signal at different positions of the test line is different, causing the brightness of the display sub-pixels at different positions of the display area 540 to change inconsistently, for example, causing the brightness of the display sub-pixels at some positions of the display area 540 to reach the maximum brightness or minimum brightness in advance or be delayed. For example, the voltage drop of the signal at different positions of the test line is different, causing the brightness of the display sub-pixels at different positions of the display area 540 (the brightness in a stable brightness state) to be inconsistent.

[0059] In addition, for Figure 1 In the illustrated display substrate, when test data signals are simultaneously applied to multiple test lines, the gradient directions of the voltage drops (IR drops) on different test lines differ. For example, the voltage drops on the first test line 511 and the second test line 512 gradually increase from left to right, while the voltage drop on the third test line 513 gradually decreases from left to right. Consequently, the luminous intensities of the first, second, and third display sub-pixels of the same display pixel on the display substrate 500 do not match. For example, when a data signal with a value of 255 (a value range of 0 to 255) is applied to each of them, the red, green, and blue lights emitted by them cannot mix to form the desired white light, resulting in a color shift in at least a portion of the display area 540 of the display substrate 500.

[0060] The following combination Figure 1 、 Figure 2A 、 Figure 2B 、 Figure 3 as well as Figure 4 An exemplary description is given.

[0061] like Figure 1As shown, the first test line 511 includes a first position 5111 of the first test line 511, a second position 5112 of the first test line 511, and a third position 5113 of the first test line 511, which are sequentially arranged in the first direction D1. The second test line 512 includes a first position 5121 of the second test line 512, a second position 5122 of the second test line 512, and a third position 5123 of the second test line 512, which are sequentially arranged in the first direction D1. The third test line 513 includes a first position 5131 of the third test line 513, a second position 5132 of the third test line 513, and a third position 5133 of the third test line 513, which are sequentially arranged in the first direction D1.

[0062] Figure 2A 5121 from the first position of the second test line 512 and the timing diagram of the voltage signal taken out from the third position 5123 of the second test line 512. Figure 2A The unit of the horizontal direction is time, and the unit of the vertical direction is voltage). Figure 2B Shown Figure 2A The local area shown ( Figure 2A FIG. 1 is an enlarged view of the voltage signal (ie, the rising edge of the voltage signal) in the dotted box area in FIG.

[0063] like Figure 2A As shown, the amplitude of the voltage signal taken from the first position 5121 of the second test line 512 is slightly greater than the amplitude of the voltage signal taken from the third position 5123 of the second test line 512, which indicates that the voltage drop at the third position 5123 of the second test line 512 is larger than that at the first position 5121 of the second test line 512; Figure 2B As shown, the steepness of the rising edge of the voltage signal taken out from the first position 5121 of the second test line 512 is greater than the steepness of the rising edge of the voltage signal taken out from the third position 5123 of the second test line 512, which indicates that the time delay of the voltage signal taken out from the third position 5123 of the second test line 512 is larger than that of the voltage signal taken out from the first position 5121 of the second test line 512.

[0064] In order to more clearly show the difference between the voltage drop and time delay at the first position 5121 of the second test line 512 and the third position 5123 of the second test line 512, the inventors of the present disclosure simulated the time-varying characteristics of the voltage signal taken from the first position 5121 of the second test line 512 and the voltage signal taken from the third position 5123 of the second test line 512. The simulation results are shown in FIG. Figure 3 shown. Figure 3 The horizontal axis is time, where u represents microseconds and m represents milliseconds.

[0065] like Figure 3 As shown in FIG. 5 , when a square wave pulse 570 is applied to the second test pad 532, the steepness of the rising edge of the voltage signal 571 obtained from the first position 5121 of the second test line 512 is greater than the steepness of the rising edge of the voltage signal 572 obtained from the third position 5123 of the second test line 512, and the amplitude of the voltage signal 571 obtained from the first position 5121 of the second test line 512 is greater than the amplitude of the voltage signal 572 obtained from the third position 5123 of the second test line 512, which indicates that the voltage drop and time delay at the third position 5123 of the second test line 512 are greater than those at the first position 5121 of the second test line 512. For example, Figure 3 As shown, the rise time of the voltage signal obtained from the first position 5121 of the second test line 512 is approximately 162 microseconds, the rise time of the voltage signal obtained from the third position 5123 of the second test line 512 is approximately 224 microseconds, and the difference between the amplitude of the voltage signal 571 obtained from the first position 5121 of the second test line 512 and the amplitude of the voltage signal 572 obtained from the third position 5123 of the second test line 512 is approximately 213 millivolts. For example, the signal obtained from the first test line 511 and the signal obtained from the third test line 513 have similar voltage drop characteristics and time delay characteristics, which will not be described in detail here.

[0066] Similarly, due to the influence of the test line resistance, the voltage drops at the first position 5111, the second position 5112, and the third position 5113 of the first test line 511 gradually increase. Therefore, the amplitude of the voltage signal obtained from the first position 5111 of the first test line 511, the amplitude of the voltage signal obtained from the second position 5112 of the first test line 511, and the amplitude of the voltage signal obtained from the third position 5113 of the first test line 511 gradually decrease. The voltage drops at the first position 5131, the second position 5132, and the third position 5133 of the third test line 513 gradually decrease, and therefore the obtained voltage gradually increases. Due to the influence of the capacitance of the test line, the time delay of the voltage signal at the first position 5111 of the first test line 511, the second position 5112 of the first test line 511 and the third position 5113 of the first test line 511 gradually increases; the time delay of the voltage signal at the first position 5131 of the third test line 513, the second position 5132 of the third test line 513 and the third position 5133 of the third test line 513 gradually decreases.

[0067] For example, due to the uneven distribution (e.g., gradually increasing) of the signal amplitude on the test line, in the test of the display substrate 500, the luminance of the display sub-pixel is unevenly distributed (e.g., gradually decreasing) along the first direction D1. Figure 4 An exemplary description is given.

[0068] Figure 4 A brightness distribution diagram 561 of the first display sub-pixel in the first direction D1, a brightness distribution diagram 562 of the second display sub-pixel in the first direction D1, and a brightness distribution diagram 563 of the third display sub-pixel in the first direction D1 are shown. Here, the size of the brightness distribution diagram in the longitudinal direction represents the brightness of the display sub-pixel corresponding to the brightness distribution diagram.

[0069] It should be noted that Figure 4 The brightness distribution diagram shown is obtained based on the following assumption, that is, when multiple display sub-pixels (e.g., first display sub-pixels) receive predetermined data signals (e.g., the received data signals are equal to each other), multiple display sub-pixels (e.g., first display sub-pixels) distributed in the first direction D1 have the same brightness.

[0070] like Figure 4 As shown, the brightness of the first display sub-pixel (i.e., the first display sub-pixel corresponding to the first position) driven by the test data signal taken out from the first position 5111 of the first test line 511, the brightness of the first display sub-pixel driven by the test data signal taken out from the second position 5112 of the first test line 511, and the brightness of the first display sub-pixel driven by the test data signal taken out from the third position 5113 of the first test line 511 gradually decrease. The brightness of the second display sub-pixel driven by the test data signal taken out from the first position 5121 of the second test line 512, the brightness of the second display sub-pixel driven by the test data signal taken out from the second position 5122 of the second test line 512, and the brightness of the second display sub-pixel driven by the test data signal taken out from the third position 5123 of the second test line 512 gradually decrease. The brightness of the third display sub-pixel driven by the test data signal taken out from the first position 5131 of the third test line 513, the brightness of the third display sub-pixel driven by the test data signal taken out from the second position 5132 of the third test line 513, and the brightness of the third display sub-pixel driven by the test data signal taken out from the third position 5133 of the third test line 513 gradually increase.

[0071] For example, in the test of the display substrate 500, the brightness of the first display sub-pixel and the second display sub-pixel gradually decreases from the left side of the display area 540 to the right side of the display area 540, and the brightness of the third display sub-pixel gradually increases. Figure 1 The design of the test lines of the display substrate 500 shown results in Figure 1 The display substrate 500 shown has a brightness non-uniformity problem during testing.

[0072] Figure 4 A distribution diagram of the colors displayed by the display substrate 500 along the first direction D1 is also shown, where it is assumed that the first display sub-pixel, the second display sub-pixel, and the third display sub-pixel emit green light, red light, and blue light, respectively.

[0073] like Figure 4 As shown, since the brightness of the red and green lights emitted by the display pixels corresponding to the first position of the display substrate 500 is greater than the brightness of the blue light, the color of the light emitted by the display pixels corresponding to the first position (ie, the mixed light) is yellowish. Figure 4 As shown, since the brightness of the red and green lights emitted by the display pixels corresponding to the third position of the display substrate 500 is lower than the brightness of the blue light, the color of the light emitted by the display pixels corresponding to the third position is blue. Figure 1 The design of the test lines of the display substrate 500 shown results in Figure 1 The display substrate 500 shown has a color shift problem during testing.

[0074] For example, Figure 1 The display substrate 500 shown has a brightness unevenness problem and / or a color deviation problem during testing (e.g., defect detection), which may cause the brightness-related defects in the display substrate 500 due to other reasons to be masked by the brightness differences and / or color deviations caused by the test wiring design of the display substrate 500, or cause the inspection personnel and / or inspection equipment (e.g., optical automatic inspection equipment) to tend to ignore the brightness and / or color deviation-related defects in the display sub-pixels. This reduces the defect detection rate in the test of the display substrate 500 (i.e., increases the defect missed detection rate), increases resource waste in subsequent processes, and increases the production cost of the display substrate 500 and the display device including the display substrate 500. For example, when the amplitude of the test data signal is weak, the brightness unevenness problem and / or color deviation problem of the display substrate 500 during testing (e.g., defect detection) will be more obvious.

[0075] At least one embodiment of the present disclosure provides a display substrate, a display device, and a test method for a display substrate. The display substrate includes a display area and a peripheral area arranged outside the display area. A first guide trace extending along a first direction is provided in the peripheral area, and the first guide trace includes a first end and a second end; a first test line is also provided in the peripheral area, and the first test line is electrically connected to the first guide trace at a first position on the first guide trace, and the first position is located between the first end and the second end; the display area includes a plurality of first groups of first signal lines extending along a second direction different from the first direction and arranged side by side, the two outermost first signal lines in the plurality of first groups of first signal lines are coupled to the first end and the second end respectively, and the remaining first signal lines in the plurality of first groups of first signal lines are coupled to the first guide trace between the first end and the second end.

[0076] In some examples, the display substrate can reduce the brightness difference of the display substrate during testing and improve the uniformity of the display brightness of the display substrate, thereby reducing missed detection caused by uneven brightness of the display substrate and improving the defect detection rate in the display substrate testing stage.

[0077] In some examples, the display substrate can also reduce color deviation of the display substrate during testing, thereby reducing missed detection caused by color deviation of the display substrate and further improving the defect detection rate during the display substrate testing phase.

[0078] The following non-restrictive description of the display substrate provided according to the embodiments of the present disclosure is given by means of several examples. As described below, different features in these specific examples can be combined with each other without conflicting with each other to obtain new examples, and these new examples also fall within the scope of protection of the present disclosure.

[0079] Figure 5 A schematic plan view of a display substrate 100 provided in accordance with at least one embodiment of the present disclosure is shown. The display substrate 100 may be a liquid crystal display substrate (e.g., an array substrate for manufacturing a liquid crystal cell) or a self-luminous display substrate (e.g., an array substrate for an organic light-emitting diode (OLED) display panel). The display substrate is formed using a semiconductor manufacturing process and includes a laminated structure.

[0080] like Figure 5 As shown, the display substrate 100 includes a display area 140 and a peripheral area arranged outside the display area 140; a first guide trace 121 extending along a first direction D1 is arranged in the peripheral area, and the first guide trace 121 includes a first end 1211 and a second end 1212; a first test line 111 is also arranged in the peripheral area, and the first test line 111 is electrically connected to the first guide trace 121 at a first position 1213 on the first guide trace 121, and the first position 1213 is located between the first end 1211 and the second end 1212.

[0081] In some examples, by providing a first guide trace 121 extending along a first direction D1 and connecting the first test line 111 to the first position 1213 of the first guide trace 121, the amplitude of the voltage signal on the first guide trace 121 can be made to first increase and then decrease along the first direction D1. That is, the amplitude of the voltage signal at the first position 1213 of the first guide trace 121 is the largest, and the amplitude of the voltage signal gradually decreases from the first position 1213 to both sides of the first position 1213. In addition, the phase delay of the voltage signal on the first guide trace 121 first decreases and then increases along the first direction D1. Therefore, compared to Figure 1 The illustrated scheme shows that the amplitude and signal delay of the voltage signal on the test line in the display substrate 500 monotonically change along the first direction D1. Figure 5 The display substrate 100 shown can reduce the difference in the voltage signal amplitude and phase delay on the first guide line 121, and thus can reduce the brightness difference of the display substrate 100 along the first direction D1, improve the brightness uniformity of the display substrate 100, thereby reducing the missed detection caused by the uneven brightness of the display substrate 100 and improving the defect detection rate in the display substrate test phase. Figure 5 The display substrate 100 is shown for exemplary purposes.

[0082] like Figure 5 As shown, a second guide trace 122 is further provided in the peripheral area, and the second guide trace 122 extends along the first direction D1 and includes a third end 1221 and a fourth end 1222; a second test line 112 is also provided in the peripheral area, and the second test line 112 is electrically connected to the second guide trace 122 at a third position 1223 on the second guide trace 122, and the third position 1223 is located between the third end 1221 and the fourth end 1222.

[0083] like Figure 5 As shown, a third guide trace 123 is further provided in the peripheral area, and the third guide trace 123 extends along the first direction D1 and includes a fifth end 1231 and a sixth end 1232; a third test line 113 is also provided in the peripheral area, and the third test line 113 is electrically connected to the third guide trace 123 at a fourth position 1233 on the third guide trace 123, and the fourth position 1233 is located between the fifth end 1231 and the sixth end 1232.

[0084] The first end 1211 and the second end 1212 may or may not be the physical ends of the first guide trace 121. In the latter case, although the first guide trace 121 may extend beyond the first end 1211 and the second end 1212, this portion does not participate in signal transmission and thus does not affect the technical effect of the above-mentioned wiring.

[0085] For example, in order to clearly indicate the display area 140, Figure 5 The spacing between adjacent signal lines is exaggerated, thus making Figure 5The illustrated first end 1211 and second end 1212 do not appear to be the physical ends of the first guide trace 121. For example, in some actual products, the distance between the first end 1211 and the first guide trace 121 (e.g., a few hundred microns) is negligible compared to the length of the first guide trace 121 (e.g., a few hundred millimeters). Therefore, in some actual products, the first end 1211 and the second end 1212 may serve as the physical ends of the first guide trace 121. For example, in some actual products, the third end 1221 and the fourth end 1222 may also serve as the physical ends of the second guide trace 122, and the fifth end 1231 and the sixth end 1232 may also serve as the physical ends of the third guide trace 123.

[0086] In other examples, the first end 1211 and the second end 1212 may not be the physical ends of the first guide wiring 121, the third end 1221 and the fourth end 1222 may not be the physical ends of the second guide wiring 122, and the fifth end 1231 and the sixth end 1232 may not be the physical ends of the third guide wiring 123. For the sake of clarity, this example will be explained in detail later and will not be repeated here.

[0087] For example, the first guide trace 121, the second guide trace 122, and the third guide trace 123 are arranged on the same layer. In this case, the first guide trace 121, the second guide trace 122, and the third guide trace 123 can be obtained by patterning the same film layer using the same patterning process, thereby simplifying the manufacturing process of the display substrate 100. The same-layer arrangement can be located in the same plane or not in the same horizontal plane. For example, other same-layer arrangements in some embodiments of the present disclosure can also have similar definitions, which will not be repeated hereafter.

[0088] In some examples, the first guide trace 121, the second guide trace 122, and the third guide trace 123 may each be located in at least two structural layers. For example, the first guide trace 121 and the second guide trace 122 may be located in the same structural layer, and the third guide trace 123 may be located in another structural layer. For another example, the first guide trace 121, the second guide trace 122, and the third guide trace 123 may each be located in a single structural layer. In this case, the first guide trace 121, the second guide trace 122, and the third guide trace 123 may be located in three structural layers as a whole.

[0089] like Figure 5As shown, the first test line 111 includes a first portion 1111 extending along the second direction D2, and a first extending portion extending from the first test pad 131 to one end of the first portion 1111 and connected to the one end of the first portion 1111. The second test line 112 includes a second portion 1121 extending along the second direction D2, and a second extending portion extending from the second test pad 132 to one end of the second portion 1121 and connected to the one end of the second portion 1121. The third test line 113 includes a third portion 1131 extending along the second direction D2, and a third extending portion extending from the third test pad 133 to one end of the third portion 1131 and connected to the one end of the third portion 1131.

[0090] For example, Figure 5 As shown, the first portion 1111, the second portion 1121, and the third portion 1131 are arranged in the same layer and side by side with each other. For example, the second portion 1121 and the third portion 1131 are arranged on both sides of the first portion 1111 in the first direction D1. It should be noted that the spacing between the second portion 1121 and the first portion 1111 in the first direction D1, and the spacing between the third portion 1131 and the first portion 1111 in the first direction D1 (for example, approximately several micrometers to tens of micrometers) are negligible compared to the length of the guide traces (the first guide trace 121, the second guide trace 122, and the third guide trace 123) in the first direction D1 (for example, approximately several hundred millimeters).

[0091] In this case, if the first guide trace 121, the second guide trace 122 and the third guide trace 123 have the same length, the same width distribution (for example, the same width) and the same thickness distribution (the same thickness), it can be considered that the ratio of the resistance value between the first end 1211 and the first position 1213 of the first guide trace 121 to the resistance value between the first position 1213 and the second end 1212 of the first guide trace 121 (that is, the first resistance ratio), the ratio of the resistance value between the third end 1221 and the third position 1223 of the second guide trace 122 to the resistance value between the third position 1223 and the fourth end 1222 of the second guide trace 122 (that is, the second resistance ratio), and the ratio of the resistance value between the fifth end 1231 and the fourth position 1233 of the third guide trace 123 to the resistance value between the fourth position 1233 and the sixth end 1232 of the third guide trace 123 (that is, the third resistance ratio) are equal to each other.

[0092] For example, Figure 5As shown, the first extension portion includes a first transverse extension portion and a first longitudinal extension portion connected to each other, the second extension portion includes a second transverse extension portion and a second longitudinal extension portion connected to each other, and the third extension portion includes a third transverse extension portion and a third longitudinal extension portion connected to each other. Figure 5 As shown, the first transverse extending portion, the second transverse extending portion and the third transverse extending portion extend along the first direction D1, respectively, and the first longitudinal extending portion, the second longitudinal extending portion and the third longitudinal extending portion extend along the second direction D2, respectively. It should be noted that the structures of the first extending portion, the second extending portion and the third extending portion are not limited to Figure 5 For example, the first extension portion, the second extension portion and the third extension portion are arranged on the same layer.

[0093] For example, the first test line 111, the second test line 112, and the third test line 113 are electrically insulated from each other. For example, the first test line 111, the second test line 112, and the third test line 113 are all made of metal (e.g., aluminum or an aluminum alloy, copper or a copper alloy, etc.) to reduce the resistance of the first test line 111, the second test line 112, and the third test line 113 and the voltage drop caused by the first test line 111, the second test line 112, and the third test line 113.

[0094] like Figure 5 As shown, the peripheral area includes a bonding area 130 and a bonding opposing area 120 disposed opposite the bonding area. The bonding area 130 and the bonding opposing area 120 are located on opposite sides of the display area 140 along a second direction D2 that is different from the first direction D1. The bonding area 130 and the bonding opposing area 120 extend along the first direction D1. For example, the first direction D1 and the second direction D2 are perpendicular to each other.

[0095] like Figure 5 As shown, the first guide trace 121, the second guide trace 122, and the third guide trace 123 are arranged in the bonding opposing area 120. The following describes the embodiments of the present disclosure by taking the first guide trace 121, the second guide trace 122, and the third guide trace 123 arranged in the bonding opposing area 120 as an example, but the embodiments of the present disclosure are not limited thereto.

[0096] like Figure 5 As shown, the display area 140 includes a first group of first signal lines 141 extending and arranged in parallel along the second direction D2, a second group of first signal lines 142 extending and arranged in parallel along the second direction D2, and a third group of first signal lines 143 extending and arranged in parallel along the third direction.

[0097] like Figure 5As shown, the two outermost first signal lines in the plurality of first groups of first signal lines 141 are coupled to the first end 1211 and the second end 1212, respectively, and the remaining first signal lines in the plurality of first groups of first signal lines 141 are coupled to the first guide trace 121 between the first end 1211 and the second end 1212. In this case, the first end 1211 and the second end 1212 refer to the points of the first guide trace 121 that are coupled to the two outermost first signal lines in the plurality of first groups of first signal lines 141. The first end 1211 and the second end 1212 may be the physical ends of the first guide trace 121, or may not be the physical ends of the first guide trace 121.

[0098] like Figure 5 As shown, the two outermost first signal lines in the plurality of second group first signal lines 142 are coupled to the third end 1221 and the fourth end 1222, respectively, and the remaining first signal lines in the plurality of second group first signal lines 142 are coupled to the second guide trace 122 between the third end 1221 and the fourth end 1222. In this case, the third end 1221 and the fourth end 1222 refer to the points of the second guide trace 122 that are coupled to the two outermost first signal lines in the plurality of second group first signal lines 142. The third end 1221 and the fourth end 1222 may be the physical ends of the second guide trace 122, or may not be the physical ends of the second guide trace 122.

[0099] like Figure 5 As shown, the two outermost first signal lines in the plurality of third groups of first signal lines 143 are coupled to the fifth end 1231 and the sixth end 1232, respectively, and the remaining first signal lines in the plurality of third groups of first signal lines 143 are coupled to the third guide trace 123 between the fifth end 1231 and the sixth end 1232. In this case, the fifth end 1231 and the sixth end 1232 refer to the points of the third guide trace 123 that are coupled to the two outermost first signal lines in the plurality of third groups of first signal lines 143. The fifth end 1231 and the sixth end 1232 may be the physical ends of the third guide trace 123, or may not be the physical ends of the third guide trace 123.

[0100] For example, for the adjacent first group of first signal lines 141, the second group of first signal lines 142, and the third group of first signal lines 143, the coupling points between the first group of first signal lines 141 and the first guide lines 121, the coupling points between the second group of first signal lines 142 and the second guide lines 122, and the coupling points between the third group of first signal lines 143 and the third guide lines 123 are arranged sequentially in the first direction D1 and are closely adjacent to each other. That is, there are no other coupling points between the guide lines 141-143 and the first signal lines 141 between the three coupling points. For example, the spacing between the coupling points between the first group of first signal lines 141 and the first guide lines 121 and the coupling points between the third group of first signal lines 143 and the third guide lines 123 is negligible compared to the length of the guide lines 141-143. Therefore, the data signals received by the adjacent first group of first signal lines 141, the second group of first signal lines 142, and the third group of first signal lines 143 can match each other. For example, the data signals received by the adjacent first group of first signal lines 141, the second group of first signal lines 142, and the third group of first signal lines 143 can be respectively connected to the first display sub-pixel, the second display sub-pixel, and the third display sub-pixel in the same display pixel, so that the data signals received by the first display sub-pixel, the second display sub-pixel, and the third display sub-pixel can match each other, and then the light emitted by the first display sub-pixel, the second display sub-pixel, and the third display sub-pixel can be mixed into white light. It should be noted that the guide wiring is a conductive structure extending with uniform thickness and width.

[0101] For example, the first signal lines are data lines; the first plurality of first signal lines 141, the second plurality of first signal lines 142, and the third plurality of first signal lines 143 are each used to transmit data signals for sub-pixels displaying different colors of light. For example, the first plurality of first signal lines 141 are used to transmit data signals for sub-pixels displaying green light, the second plurality of first signal lines 142 are used to transmit data signals for sub-pixels displaying red light, and the third plurality of first signal lines 143 are used to transmit data signals for sub-pixels displaying blue light.

[0102] like Figure 5 As shown, the display area 140 also includes a plurality of second signal lines 144 extending along the first direction D1 and arranged side by side. The plurality of second signal lines 144 intersect and are insulated from the plurality of first signal lines. The intersection defines a plurality of display sub-pixels arranged in an array. For example, the second signal lines 144 are gate lines; the plurality of second signal lines 144 are used to transmit scanning signals. For example, the structural layer where the plurality of first signal lines are located and the structural layer where the plurality of second signal lines 144 are located are provided with an insulating layer. For example, each display sub-pixel includes a pixel driving circuit, which may include devices such as transistors and capacitors. In the case where the display substrate is a self-luminous display substrate, each display sub-pixel may also include a light-emitting device.

[0103] For example, the display area 140 includes a plurality of display pixels arranged in an array ( Figure 5 (not shown), each display pixel includes a first display sub-pixel, a second display sub-pixel, and a third display sub-pixel. The first display sub-pixel, the second display sub-pixel, and the third display sub-pixel are electrically connected to the first group of first signal lines 141, the second group of first signal lines 142, and the third group of first signal lines 143, respectively, to emit light based on data signals provided by the first group of first signal lines 141, the second group of first signal lines 142, and the third group of first signal lines 143. For example, the first display sub-pixel, the second display sub-pixel, and the third display sub-pixel are configured to emit green light, red light, and blue light, respectively.

[0104] It should be noted that the arrangement of the first display sub-pixel, the second display sub-pixel, and the third display sub-pixel can be set according to actual application requirements. For example, the arrangement of the first display sub-pixel, the second display sub-pixel, and the third display sub-pixel can adopt an island type arrangement, a stripe type arrangement, a delta type arrangement, or a mosaic type arrangement, and the arrangement of the signal line can be in Figure 5 The arrangement of the signal lines shown is adaptively adjusted according to the arrangement of the first display sub-pixel, the second display sub-pixel, and the third display sub-pixel, and will not be described in detail here.

[0105] For example, the first part 1111, the second part 1121 and the third part 1131 are arranged on the same layer as the first signal line, and the first extension part, the second extension part, the third extension part, the first guide trace 121, the second guide trace 122 and the third guide trace 123 are arranged on the same layer as the second signal line 144, which can further simplify the manufacturing process of the display substrate 100; in this case, the first extension part, the second extension part and the third extension part are respectively connected to the first part 1111, the second part 1121 and the third part 1131 via vias, and the first part 1111, the second part 1121 and the third part 1131 are respectively connected to the first guide trace 121, the second guide trace 122 and the third guide trace 123 via vias. In some examples, the first extension part, the second extension part and the third extension part can also be set on the same layer as the first signal. In this case, the first extension part, the second extension part and the third extension part can be electrically connected to the first part 1111, the second part 1121 and the third part 1131 respectively through overlapping.

[0106] like Figure 5As shown, bonding area 130 further includes a plurality of first-group first signal pads 135, a plurality of second-group first signal pads 136, and a plurality of third-group first signal pads 137; a plurality of first-group first signal lines 141 are coupled to the plurality of first-group first signal pads 135 in a one-to-one correspondence; a plurality of second-group first signal lines 142 are coupled to the plurality of second-group first signal pads 136 in a one-to-one correspondence; and a plurality of third-group first signal lines 143 are coupled to the plurality of third-group first signal pads 137 in a one-to-one correspondence. For example, the plurality of first-group first signal pads 135, the plurality of second-group first signal pads 136, and the plurality of third-group first signal pads 137 are used to connect to a data driver via a flexible printed circuit board in a subsequent process to receive a plurality of data signals from the data driver and provide the plurality of data signals to the corresponding first signal lines.

[0107] like Figure 5 As shown, the bonding area 130 further includes a plurality of second signal pads 138, and a plurality of second signal lines 144 are coupled to the plurality of second signal pads 138 in a one-to-one correspondence. For example, the plurality of second signal pads 138 are used to connect to a gate driver via a flexible printed circuit board in a subsequent process to receive a plurality of scan signals from the gate driver and provide the plurality of scan signals to the corresponding second signal lines 144. In other embodiments, a gate driver circuit (i.e., GOA) is integrated on the display substrate. Accordingly, the bonding area 130 further includes signal pads for providing a scan start signal (STV), a clock signal, etc. to the gate driver circuit, and for contacting a test probe during testing to receive the corresponding signals.

[0108] For example, the bonding area 130 may not be provided with the first signal pads 135 to 137 and the second signal pad 138. In this case, multiple traces can be used to couple with the first signal line and the second signal line, and in subsequent processes, the multiple traces can be connected to the gate driver and the data driver.

[0109] like Figure 5 As shown, the bonding area 130 also includes a first test pad 131, a second test pad 132, and a third test pad 133, which are used to contact the test probe during testing to receive corresponding test data signals. For example, the bonding area 130 may also include a scan signal pad (not shown in the figure).

[0110] like Figure 5As shown, one end of the first test line 111 is electrically connected to the first test pad 131, and the other end of the first test line 111 is electrically connected to the first position 1213. Therefore, the first test data signal applied to the first test pad 131 can be applied to the first plurality of first signal lines 141 via the first test line 111 and the first guide trace 121. One end of the second test line 112 is electrically connected to the second test pad 132, and the other end of the second test line 112 is electrically connected to the third position 1223. Therefore, the second test data signal applied to the second test pad 132 can be applied to the second plurality of first signal lines 142 via the second test line 112 and the second guide trace 122. One end of the third test line 113 is electrically connected to the third test pad 133, and the other end of the third test line 113 is electrically connected to the fourth position 1233. Therefore, the third test data signal applied to the third test pad 133 can be applied to the third plurality of first signal lines 143 via the third test line 113 and the third guide trace 123.

[0111] For example, the overall resistances of the first test line 111, the second test line 112, and the third test line 113 are equal, thereby making the voltage drops caused by the first test line 111, the second test line 112, and the third test line 113 equal. For example, if the width, thickness, and manufacturing materials of the first test line 111, the second test line 112, and the third test line 113 are the same, the lengths of the first test line 111, the second test line 112, and the third test line 113 can be equal. For example, when the amplitude of the first test data signal applied on the first test pad 131, the amplitude of the second test data signal applied on the second test pad 132, and the amplitude of the third test data signal applied on the third test pad 133 are equal to each other, since the voltage drops caused by the first test line 111, the second test line 112 and the third test line 113 are equal to each other, the amplitude of the data signal at the first position 1213, the amplitude of the data signal at the second position 1214 and the amplitude of the data signal at the third position 1223 match each other (for example, are equal).

[0112] In other examples, the overall resistance and length of the first test line 111, the second test line 112, and the third test line 113 may also be unequal to each other. In this case, the voltage drop difference between the first test line 111, the second test line 112, and the third test line 113 can be obtained based on the resistance difference information of the first test line 111, the second test line 112, and the third test line 113, and the corrected first test data signal, the corrected second test data signal, and the corrected third test data signal are obtained based on the above-mentioned voltage drop difference, so that after the corrected first test data signal, the corrected second test data signal, and the corrected third test data signal are applied to the first test pad 131, the second test pad 132, and the third test pad 133, respectively, the amplitude of the data signal at the first position 1213, the amplitude of the data signal at the second position 1214, and the amplitude of the data signal at the third position 1223 match each other (for example, are equal). Therefore, in some examples of the present disclosure, the requirements for the first test line 111, the second test line 112, and the third test line 113 (for example, resistance consistency or length consistency requirements) can be reduced on the basis of ensuring or improving the brightness uniformity of the display substrate during the test phase, thereby improving the design flexibility and wiring difficulty of the test lines.

[0113] like Figure 5 As shown, the bonding area 130 further includes a control signal pad 134, and a test control line 114 is provided in the peripheral area. The test control line 114 is connected to the control signal pad 134 and includes a horizontal portion 1141 extending along the first direction D1 in the bonding opposing area 120. Figure 5 As shown, the bonding region 120 further includes a plurality of first control switches 124 , a plurality of second control switches 125 , and a plurality of third control switches 126 .

[0114] like Figure 5 As shown, the first ends of the multiple first-group control switches 124 are electrically connected to the multiple first-group first signal lines 141 in a one-to-one correspondence, and the second ends of the multiple first-group control switches 124 are electrically connected to the first guide trace 121; the third ends (control ends) of the multiple first-group control switches 124 are electrically connected to the horizontal portion 1141 to control the opening and closing of the multiple first-group control switches 124 based on the control signal applied to the control signal pad 134, thereby controlling whether the first test data signal applied to the first test pad 131 is applied to the multiple first-group first signal lines 141 via the first test line 111 and the first guide trace 121.

[0115] like Figure 5As shown, the first ends of the multiple second-group control switches 125 are electrically connected to the multiple second-group first signal lines 142 in a one-to-one correspondence, and the second ends of the multiple second-group control switches 125 are electrically connected to the second guide trace 122; the third ends (control ends) of the multiple second-group control switches 125 are electrically connected to the horizontal portion 1141 to control the opening and closing of the multiple second-group control switches 125 based on the control signal applied to the control signal pad 134, thereby controlling whether the second test data signal applied to the second test pad 132 is applied to the multiple second-group first signal lines 142 via the second test line 112 and the second guide trace 122.

[0116] like Figure 5 As shown, the first ends of the multiple third groups of control switches 126 are electrically connected to the multiple third groups of first signal lines 143 in a one-to-one correspondence, and the second ends of the multiple third groups of control switches 126 are electrically connected to the third guide trace 123; the third ends (control ends) of the multiple third groups of control switches 126 are electrically connected to the horizontal part 1141 to control the opening and closing of the multiple third groups of control switches 126 based on the control signal applied to the control signal pad 134, thereby controlling whether the third test data signal applied to the third test pad 133 is applied to the multiple third groups of first signal lines 143 via the third test line 113 and the third guide trace 123.

[0117] For example, the control switches 124 to 126 may be transistors, such as N-type transistors or P-type transistors, one of the first and second terminals of which may be a source, the other a drain, and the third terminal a gate. The transistors serving as the control switches 124 to 126 may be formed together with other transistors in the display sub-pixels in the display area during the process of manufacturing the display substrate, thereby simplifying the manufacturing process. For example, in a display substrate including Figure 5 When the display device of the display substrate 100 shown is performing normal display, an invalid signal (a level signal that turns off the control switch) can be applied to the control signal pad 134 to turn off the control switch, thereby avoiding the first test line 111, the second test line 112 and the third test line 113 from adversely affecting the normal display of the display device.

[0118] It should be noted that, according to actual application requirements, some embodiments of the present disclosure provide that the display substrate 100 may not be provided with a control switch, a control signal pad and a control line. In this case, after completing the test of the display substrate 100, the first guide trace 121, the second guide trace 122 and the third guide trace 123 located in the bonding opposing area 120 can be removed by cutting, which will not be repeated here.

[0119] For example, in testing the display substrate 100 (for example, a liquid crystal box test), a test data signal can be applied to at least one of the first test pad 131, the second test pad 132, and the third test pad 133, and a valid signal (a level signal that turns on the control switch) is applied to the control signal pad 134 to turn on the control switch, so that the test data signal applied to at least one of the first test pad 131, the second test pad 132, and the third test pad 133 can be transmitted to the corresponding first signal line (data line), and a gate scan signal is applied to the scan signal pad so that the test data signal transmitted to the corresponding first signal line (data line) can drive the corresponding display sub-pixel to emit light.

[0120] like Figure 5 As shown, the first test pad 131 and the second test pad 132 are located on one side of the display area 140 in the first direction D1, and the third test pad 133 and the control signal pad 134 are located on the other side of the display area 140 in the first direction D1. For example, arranging the first test pad 131, the second test pad 132, and the third test pad 133 on both sides of the display area 140 in the first direction D1 can meet the wiring requirements of a specific display substrate 100 (e.g., a GOA-based display substrate 100) (e.g., small wiring space) and / or increase the range of test equipment options (e.g., reducing the requirement for the number of test signal channels of the test equipment).

[0121] For example, the first test line 111 and the second test line 112 can extend from the bonding area 130 (for example, the lower left corner of the display substrate 100) to the middle area of the bonding opposing area 120, the third test line 113 can extend from the bonding area 130 (for example, the lower right corner of the display substrate 100) to the middle area of the bonding opposing area 120, and the test control line 114 can extend from the bonding area 130 (for example, the lower right corner of the display substrate 100) to the left side of the bonding opposing area 120 (for example, the upper left corner of the display substrate 100).

[0122] In some examples, when the display substrate 100 further includes a control guide trace 190, as shown in FIG. Figure 10As shown, test control line 114 can also extend from bonding region 130 (e.g., the lower right corner of display substrate 100) to the middle region of bonding opposing region 120. In this case, test control line 114 includes a seventh end 191 and an eighth end 192, and is connected to control guide trace 190 via connection points located at seventh and eighth ends 191 and 192 on control guide trace 190. Here, seventh and eighth ends 191 and 192 refer to the points on test control line 114 that couple to the two outermost control switches of the plurality of control switches 124-126, and seventh and eighth ends 191 and 192 may or may not be physical endpoints of control guide trace 190. For example, by providing control guide trace 190, the time delay between control signals (valid or invalid) received by different control switches can be reduced, thereby making the brightness variations of display sub-pixels located at different locations more consistent and improving the instantaneous brightness uniformity of the display substrate.

[0123] For example, the specific design of the control guide trace 190 and the connection relationship between the test control line 114 and the control guide trace 190 can be designed with reference to the first guide trace 121 and the first test line 111, and will not be repeated here.

[0124] For example, the first position 1213 is the "resistance midpoint" between the first end 1211 and the second end 1212 of the first guide trace 121 (hereinafter referred to as the resistance midpoint of the first guide trace 121). In the present disclosure, the "resistance midpoint" refers to a point between two points on a trace such that the resistances to the two points are equal; accordingly, the "resistance 1 / 3 point" mentioned in the following description refers to a point between two points (the starting point and the end point) on the trace such that the resistance to the starting point is equal to 1 / 3 of the resistance between the starting point and the end point, and the "resistance 2 / 3 point" refers to a point between two points (the starting point and the end point) on the trace such that the resistance to the starting point is equal to 2 / 3 of the resistance between the starting point and the end point.

[0125] When the first position 1213 is the "resistor midpoint", the amplitude of the voltage signal at the first end 1211 is equal to the amplitude of the voltage signal at the second end 1212, and the maximum voltage drop on the first guide trace 121 is the difference between the amplitude of the voltage signal at the first position 1213 and the amplitude of the voltage signal at the first end 1211 (or the second end 1212). Therefore, Figure 5 The maximum voltage drop on the first guide trace 121 of the display substrate 100 is Figure 1 For example, half of the maximum voltage drop on the first portion 1111 of the first test line 111 of the display substrate 100 is shown. Figure 5 The voltage drop on the first guide trace 121 of the display substrate 100 is symmetrically distributed along the first position 1213. Figure 6 and Figure 7 An exemplary description is given.

[0126] Figure 6 Shown Figure 5 1 and 2. A simulation curve showing the change of voltage signals at the first end 1211 and the second end 1212 of the first guide trace 121 of the display substrate 100 over time is shown. Figure 6 The horizontal axis is time, where u represents microseconds and m represents milliseconds.

[0127] Figure 7 A brightness distribution diagram 161 of the first display sub-pixel in the first direction D1, a brightness distribution diagram 162 of the second display sub-pixel in the first direction D1, and a brightness distribution diagram 163 of the third display sub-pixel in the first direction D1 are shown. Here, the size of the brightness distribution diagram in the longitudinal direction represents the brightness of the display sub-pixel corresponding to the brightness distribution diagram.

[0128] like Figure 6 As shown, when a square wave pulse 170 is applied to the first test pad 131, the steepness of the rising edge of the voltage signal 171 at the first end 1211 of the first guide trace 121 is well matched with the steepness of the rising edge of the voltage signal 172 at the second end 1212 of the first guide trace 121, and the amplitude of the voltage signal 171 at the first end 1211 of the first guide trace 121 is well matched with the amplitude of the voltage signal 172 at the second end 1212 of the first guide trace 121, which indicates that the first end 1211 of the first guide trace 121 and the second end 1212 of the first guide trace 121 have similar voltage drops and time delays. Figure 5 The display substrate 100 shown reduces the maximum voltage drop on the first guide trace 121. Figure 6 As shown, the rising edge of the voltage signal 171 at the first end 1211 of the first guiding trace 121 has a rise time of approximately 199 microseconds, the rising edge of the voltage signal 172 at the second end 1212 of the first guiding trace 121 has a rise time of approximately 211 microseconds, and the difference between the amplitudes of the voltage signal 171 at the first end 1211 of the first guiding trace 121 and the amplitude of the voltage signal 172 at the second end 1212 of the first guiding trace 121 is approximately 53 millivolts. For example, the signal of the second guiding trace 122 and the signal of the third guiding trace 123 have similar voltage drop characteristics and time delay characteristics, which will not be further described here.

[0129] For example, the amplitude of the voltage signal on the first guide line 121 first increases and then decreases along the first direction D1 (that is, the amplitude of the voltage signal at the first position 1213 of the first guide line 121 is the largest, and the amplitude of the voltage signal gradually decreases from the first position 1213 to both sides of the first position 1213). The phase delay of the voltage signal on the first guide line 121 first decreases and then increases along the first direction D1. Correspondingly, in the first direction D1, the luminance of the first sub-pixel first increases and then decreases (see Figure 7 ).

[0130] For example, by making the amplitude of the voltage signal on the first guide trace 121 increase first and then decrease along the first direction D1, the maximum voltage drop on the first guide trace 121 can be reduced, thereby reducing Figure 5 The brightness difference of the first display pixels of the display substrate 100 in the first direction D1 is shown. That is, at the same time, the difference in luminance between the first display pixel with the maximum luminance and the first display pixel with the minimum luminance is reduced. This improves the luminance uniformity of the display substrate 100, thereby reducing missed detections caused by uneven brightness of the display substrate 100 and improving the defect detection rate during the display substrate testing phase.

[0131] For example, the third position 1223 may be the midpoint of the resistance between the third end 1221 and the fourth end 1222 of the second guide wire 122 (hereinafter referred to as the midpoint of the resistance of the second guide wire 122), and the fourth position 1233 may be the midpoint of the resistance between the fifth end 1231 and the sixth end 1232 of the third guide wire 123 (hereinafter referred to as the midpoint of the resistance of the third guide wire 123). In this case, Figure 5 The maximum voltage drop on the second guide trace 122 and the maximum voltage drop on the third guide trace 123 of the display substrate 100 are respectively Figure 1 The maximum voltage drop on the second portion 1121 of the second test line 112 of the display substrate 100 and the maximum voltage drop on the third portion 1131 of the third test line 113 are shown, for example, half, and so that Figure 5 As shown, the voltage drop on the second guiding trace 122 of the display substrate 100 is, for example, symmetrically distributed along the third position 1223 , and the voltage drop on the third guiding trace 123 is, for example, symmetrically distributed along the fourth position 1233 .

[0132] For example, the amplitude of the voltage signal on the second guiding wire 122 and the amplitude of the voltage signal on the third guiding wire 123 first increase and then decrease along the first direction D1, and the phase delay of the voltage signal on the second guiding wire 122 and the third guiding wire 123 first decreases and then increases along the first direction D1. Correspondingly, in the first direction D1, the luminance of the second sub-pixel and the luminance of the third sub-pixel first increase and then decrease (see Figure 7 ).

[0133] For example, by making the amplitude of the voltage signal on the second guiding trace 122 and the third guiding trace 123 increase first and then decrease along the first direction D1, the maximum voltage drop on the second guiding trace 122 and the third guiding trace 123 can be reduced, thereby reducing Figure 5 The brightness difference of the second display pixel of the display substrate 100 in the first direction D1 and the brightness difference of the third display pixel in the first direction D1 shown in the display substrate 100 improve the brightness uniformity of the display substrate 100, thereby reducing missed detection caused by uneven brightness of the display substrate 100 and improving the defective detection rate in the display substrate testing stage.

[0134] For example, when the first guide line 121, the second guide line 122 and the third guide line 123 respectively have uniform thickness, width and material distribution and the first resistance ratio, the second resistance ratio and the third resistance ratio are equal to each other, the voltage drops on the first guide line 121, the second guide line 122 and the third guide line 123 are consistent and match each other, thereby making the data signals received by the first display sub-pixel, the second display sub-pixel and the third display sub-pixel in the same display pixel match each other, and making the luminous intensity of the first display sub-pixel, the second display sub-pixel and the third display sub-pixel of the same display pixel of the display substrate 100 match (for example, they can be mixed to form white light), thereby suppressing the color deviation problem of the display substrate 100.

[0135] In this case, the first position 1213 is the midpoint of the resistance between the first end 1211 and the second end 1212 of the first guide trace 121 (hereinafter referred to as the midpoint of the resistance of the first guide trace 121), the third position 1223 is the midpoint of the resistance between the third end 1221 and the fourth end 1222 of the second guide trace 122, and the fourth position 1233 is the midpoint of the resistance between the fifth end 1231 and the sixth end 1232 of the third guide trace 123. The midpoint of the resistance between the first end 1211 and the second end 1212 of the first guide trace 121 is the midpoint between the first end 1211 and the second end 1212. The midpoint of the resistance between the third end 1221 and the fourth end 1222 of the second guide routing 122 can be the midpoint between the third end 1221 and the fourth end 1222, and the midpoint of the resistance between the fifth end 1231 and the sixth end 1232 of the third guide routing 123 can be the midpoint between the fifth end 1231 and the sixth end 1232, thereby enabling the first display sub-pixel corresponding to the midpoint of the resistance of the first guide routing 121, the second display sub-pixel corresponding to the midpoint of the resistance of the second guide routing 122, and the third display sub-pixel corresponding to the midpoint of the resistance of the third guide routing 123 to be located in the same display pixel of the display substrate 100.

[0136] Figure 7 A distribution diagram of the colors displayed by the display substrate 100 along the first direction D1 is also shown, where it is assumed that the first display sub-pixel, the second display sub-pixel, and the third display sub-pixel emit green light, red light, and blue light, respectively.

[0137] like Figure 7 As shown, since the voltage drops of the first guide wiring 121, the second guide wiring 122 and the third guide wiring 123 are consistent and match each other, the luminous intensity of the first display sub-pixel, the second display sub-pixel and the third display sub-pixel of the same display pixel of the display substrate 100 are matched (for example, when they are respectively applied with a data signal with a value of 255 (the value range is 0 to 255), the red light, green light and blue light emitted can be mixed to form white light), thereby suppressing the color deviation problem of the display substrate 100.

[0138] For example, since the amplitude of the voltage signal of the guide line gradually decreases from the midpoint of the resistor to the two ends of the guide line, the luminous brightness (for example, white light brightness) of the display pixel of the display substrate 100 in the first direction D1 gradually decreases from the position corresponding to the midpoint of the resistor in the display area 140 to both sides of the display area 140 (on both sides in the first direction D1).

[0139] For example, due to Figure 5 The display substrate 100 shown can suppress the color shift problem of the display substrate 100 , thereby reducing missed inspections caused by the color shift of the display substrate 100 and further improving the defect detection rate in the display substrate testing phase.

[0140] It should be noted that the first position 1213 is not limited to the midpoint of the resistor between the first end 1211 and the second end 1212 of the first guide trace 121. The first position 1213 can also be any other position between the first end 1211 and the second end 1212 of the first guide trace 121. In this case, the corresponding display substrate 100 also has a certain technical effect of reducing brightness differences. Similarly, the third position 1223 can also be any other position between the third end 1221 and the fourth end 1222 of the second guide trace 122, and the fourth position 1233 can also be any other position between the fifth end 1231 and the sixth end 1232 of the third guide trace 123. The corresponding display substrate 100 also has a certain technical effect of reducing brightness differences.

[0141] It should be noted that the first resistance ratio, the second resistance ratio and the third resistance ratio are not limited to being set equal to each other. According to actual application requirements, the first resistance ratio, the second resistance ratio and the third resistance ratio may also have certain differences. In this case, Figure 5 The display substrate 100 shown has a certain degree of color shift, but Figure 5The color shift of the display substrate 100 shown can still be weaker than Figure 1 The color shift of the display substrate 100 is shown.

[0142] It should be noted that the first test pads 131, the second test pads 132, and the third test pads 133 are not limited to being disposed on opposite sides of the display area 140 in the first direction D1. Depending on actual application requirements, the first test pads 131, the second test pads 132, and the third test pads 133 can be disposed on the same side of the display area 140 in the first direction D1. In this case, by providing the first guide traces 121, the second guide traces 122, and the third guide traces 123, brightness variations on the display substrate 100 in the first direction D1 can be reduced, thereby improving the brightness uniformity of the display substrate 100. This can reduce missed detections caused by uneven brightness on the display substrate and improve the defect detection rate during the display substrate testing phase.

[0143] For example, when the display substrate 100 is a liquid crystal display substrate, the display substrate 100 includes an array substrate and a color filter substrate. In the second direction, the size of the array substrate is larger than the size of the color filter substrate, and the bonding area 130 is located in the area where the array substrate does not overlap with the color filter substrate (that is, the area where the array substrate is exposed by the color filter substrate). Therefore, during the test of the display substrate, a test data signal can be applied to the first test pad 131, the second test pad 132, and the third test pad 133, and in a subsequent process, the first signal line and the second signal line can be coupled to the gate driver and the data driver, respectively.

[0144] In other examples, the first test line 111 is also electrically connected to the first guide trace 121 at a second position 1214 on the first guide trace 121, and the second position 1214 is located between the first end 1211 and the second end 1212 and is different from the first position 1213, thereby further reducing the brightness difference of the first display sub-pixel along the first direction D1, improving the brightness uniformity of the display substrate 100 and the defective detection rate in the display substrate testing stage.

[0145] For example, the first position 1213 and the second position 1214 are located at the resistance 1 / 3 point and the resistance 2 / 3 point respectively between the first end 1211 and the second end 1212 of the first guide line 121, thereby further reducing the brightness difference of the first display sub-pixel along the first direction D1, improving the brightness uniformity of the display substrate 100 and the defect detection rate in the display substrate testing phase. Figure 8 The first test line 111 is shown for exemplary purposes.

[0146] like Figure 8As shown, in addition to the first portion 1111 extending along the second direction D2 and the first extension portion 1112 extending from the first test pad 131 to one end of the first portion 1111 and connected to one end of the first portion 1111, the first test line 111 also includes a first sub-line 1113, a second sub-line 1114 and a third sub-line 1115.

[0147] like Figure 8 As shown, the first sub-route 1113 extends along the first direction D1 and includes a first end of the first sub-route 1113, a second end of the first sub-route 1113, and a first position of the first sub-route 1113. The other end of the first portion 1111 is connected to the first sub-route 1113 via the first position of the first sub-route 1113; one end of the second sub-route 1114 is connected to the first end of the first sub-route 1113, and the other end of the second sub-route 1114 is connected to the first position 1213 of the first guide route 121; one end of the third sub-route 1115 is connected to the second end of the first sub-route 1113, and the other end of the third sub-route 1115 is connected to the second position 1214 of the first guide route 121.

[0148] For example, the first position of the first sub-route 1113 is the middle value of the resistance of the first sub-route 1113 at the first end of the first sub-route 1113 and the second end of the first sub-route 1113, so that the amplitudes of the voltage signals at the first end of the first sub-route 1113 and the second end of the first sub-route 1113 are equal; when the resistance values of the second sub-route 1114 and the third sub-route 1115 are equal, the amplitude of the voltage signal at the first position of the first sub-route 1113 is equal to the amplitude of the voltage signal at the second position 1214 of the first sub-route 1113, and, Figure 8 The maximum voltage drop on the first sub-trace 1113 is shown as Figure 1 The maximum voltage drop on the first portion 1111 of the first test line 111 of the display substrate 100 is, for example, one third. In other embodiments, the first sub-line 1113 can be electrically connected to the first guide line 121 through more (greater than or equal to 3) positions, so that the voltage drop difference on the first guide line 121 is smaller.

[0149] For example, in Figure 8 The first test line 111 and the first guide trace 121 are shown to be applied to Figure 5 In the display substrate 100 shown, the difference in the voltage signal amplitude and phase delay on the first guide line 121 can be further reduced, and thus the brightness difference of the display substrate 100 along the first direction D1 can be further reduced, thereby improving the brightness uniformity of the display substrate 100, thereby further reducing the missed detection caused by the uneven brightness of the display substrate 100 and improving the defective detection rate in the display substrate testing stage.

[0150] For example, according to actual application requirements, the first test line 111 can also be electrically connected to the first guide trace 121 at more positions on the first guide trace 121, for example, electrically connected to the resistor 1 / 5 point, the resistor 2 / 5 point, the resistor 3 / 5 point and the resistor 4 / 5 point between the first end 1211 and the second end 1212 of the first guide trace 121, thereby further improving the brightness uniformity of the display substrate 100 and the defective detection rate in the display substrate testing stage, which will not be repeated here.

[0151] It should be noted that Figure 5 The second test line 112 and the second guide line 122 as well as the third test line 113 and the third guide line 123 in the display substrate 100 shown in FIG. 1 may also be formed by using a similar method to that shown in FIG. Figure 8 The design shown can further reduce the difference in voltage signal amplitude and phase delay on the second guide line 122 and the third guide line 123, and thus can further reduce the brightness difference of the display substrate 100 along the first direction D1, thereby improving the defect detection rate in the display substrate testing stage.

[0152] It should be noted that, for the sake of clarity, the above embodiments mainly illustrate the effect of reducing the amplitude difference of the voltage signal on the guide line of the display substrate 100 (for example, the first guide line 121) on improving the brightness uniformity of the display substrate 100 and suppressing color deviation. However, reducing the time delay difference of the voltage signal on the guide line will also have a certain effect on improving the brightness uniformity of the display substrate 100 and suppressing color deviation, which will not be repeated here.

[0153] At least one embodiment of the present disclosure further provides a display device, which includes the display substrate 1 provided by any embodiment of the present disclosure.

[0154] Figure 9 FIG. 1 shows a display device 10 provided by some embodiments of the present disclosure. Figure 9 As shown, the display device 10 includes a display substrate 100 provided by any embodiment of the present disclosure.

[0155] It should be noted that other components of the display device 10 (for example, image data encoding / decoding device, gate driver, data driver, clock circuit, etc.) can adopt applicable conventional components, which will not be elaborated here and should not be regarded as a limitation of the present disclosure.

[0156] Some embodiments of the present disclosure further provide a method for testing the display substrate, which includes: applying a first signal to a first group of multiple first signal lines via a first test line and a first guide line, and performing detection based on a display condition of the display substrate.

[0157] Below Figure 5 Taking the display substrate shown as an example, a method for testing the display substrate provided by at least one embodiment of the present disclosure is exemplarily described.

[0158] For example, the method for testing a display substrate includes at least one of steps S101 to S103 .

[0159] Step S101 : applying a first signal to a first group of a plurality of first signal lines via a first test line and a first guide line, and performing detection based on a display condition of a display substrate.

[0160] Step S102: applying a second signal to a second group of first signal lines via a second test line and a second guide line, and performing detection based on a display condition of the display substrate.

[0161] Step S103: applying a third signal to a third group of first signal lines via a third test line and a third guide line, and performing detection based on a display condition of the display substrate.

[0162] For example, in step S101, a first signal (i.e., a test data signal) can be applied to the first test pad, and a valid signal (e.g., a level signal that turns on the control switch) can be applied to the control signal pad so that the test data signal applied to the first test pad can be transmitted to multiple first-group first signal lines, and a gate scan signal can be applied to the scan signal pad so that the first signal transmitted to multiple first-group first signal lines can drive the corresponding first display sub-pixels to emit light. Then, detection can be performed based on the luminescence of the first display sub-pixels. For example, it can be determined whether the display area of the display substrate itself has defects, such as uneven brightness (MURA), based on the luminescence of multiple first display sub-pixels in the display area. For another example, it can be determined whether the display area of the display substrate itself has bright spot defects or dark spot defects based on whether there are first display sub-pixels with zero brightness or low brightness during the full white test.

[0163] For example, the specific methods of steps S102 and S103 are similar to those of step S101 and are not further described here. For example, when testing a display substrate, at least one of steps S101 through S103 may be performed as needed. When performing multiple steps of steps S101 through S103, the multiple steps may be performed sequentially or simultaneously. The following exemplary description uses the simultaneous execution of steps S101 through S103 as an example.

[0164] For example, when steps S101 to S103 are performed simultaneously, the first signal, the second signal, and the third signal can be applied to the first test pad, the second test pad, and the third test pad, respectively, and a valid signal (a level signal that turns on the control switch) is applied to the control signal pad to turn on the control switch, so that the first signal, the second signal, and the third signal applied to the first test pad, the second test pad, and the third test pad can be transmitted to the corresponding signal line, and a gate scan signal is applied to the scan signal pad so that the signal transmitted to the corresponding signal line can drive the corresponding display sub-pixel to emit light. In this case, it is possible to detect whether the display substrate has, for example, chromaticity deviation.

[0165] Since the display substrate provided by some embodiments of the present disclosure can reduce the brightness difference and / or color deviation caused by the test leads of the display substrate, it can reduce the missed detection caused by the brightness difference and / or color deviation of the display substrate and improve the defect detection rate in the display substrate test stage.

[0166] Although the present disclosure has been described in detail above using general descriptions and specific embodiments, it will be apparent to those skilled in the art that modifications or improvements may be made based on the embodiments of the present disclosure. Therefore, such modifications or improvements, as long as they do not depart from the spirit of the present disclosure, are within the scope of protection claimed by the present disclosure.

[0167] The foregoing description is merely an exemplary embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. The scope of protection of the present disclosure is determined by the appended claims.

Claims

1. A display substrate comprising a display area and a peripheral area arranged outside the display area, in, A first guide line extending along a first direction is provided in the peripheral area, and the first guide line includes a first end and a second end; A first test line is further provided in the peripheral area, the first test line being electrically connected to the first guide line at a first position on the first guide line, the first position being located between the first end and the second end; and The display area includes a first group of multiple first signal lines extending along a second direction different from the first direction and arranged side by side, two outermost first signal lines in the first group of multiple first signal lines are coupled to the first end and the second end respectively, and the remaining first signal lines in the first group of multiple first signal lines are coupled to the first guide trace between the first end and the second end; A second guide line is further provided in the peripheral area, the second guide line extending along the first direction and including a third end and a fourth end; A second test line is further provided in the peripheral area, the second test line being electrically connected to the second guide line at a third position on the second guide line, the third position being located between the third end and the fourth end; and The display area further includes a second group of multiple first signal lines extending along the second direction and arranged side by side, two outermost first signal lines in the second group of multiple first signal lines are coupled to the third end and the fourth end respectively, and the remaining first signal lines in the second group of multiple first signal lines are coupled to the second guide trace between the third end and the fourth end; The bonding opposing area is further provided with a third guide line, the third guide line extending along the first direction and including a fifth end and a sixth end; The peripheral area is further provided with a third test line, the third test line is electrically connected to the third guide line at a fourth position on the third guide line, and the fourth position is located between the fifth end and the sixth end; The display area further includes a third group of first signal lines extending along the second direction and arranged side by side, two outermost first signal lines in the third group of first signal lines being coupled to the fifth end and the sixth end, respectively, and the remaining first signal lines in the third group of first signal lines being coupled to the third guide trace between the fifth end and the sixth end; The peripheral area includes a bonding area and a bonding opposing area, the bonding area and the bonding opposing area are respectively located on both sides of the display area along the second direction, and the first guide wire, the second guide wire and the third guide wire are all arranged in the bonding opposing area; and For the sequentially adjacent second group of first signal lines, first group of first signal lines, and third group of first signal lines, the coupling points between the second group of first signal lines and the second guide wire, the coupling points between the first group of first signal lines and the first guide wire, and the coupling points between the third group of first signal lines and the third guide wire are sequentially arranged in the first direction and are closely adjacent to each other. The first test line is further electrically connected to the first guide line at a second position on the first guide line, where the second position is located between the first end and the second end and is different from the first position.

2. The display substrate according to claim 1, wherein The first position is a midpoint of the resistance between the first end and the second end of the first guide trace.

3. The display substrate according to claim 1, wherein The first position and the second position are respectively located at a resistance 1 / 3 point and a resistance 2 / 3 point between a first end and a second end of the first guide trace.

4. The display substrate according to claim 1, wherein: The display area further includes a plurality of second signal lines extending along the first direction and arranged side by side; The plurality of second signal lines cross and are insulated from the first group of first signal lines; and The first guide traces and the plurality of second signal traces are arranged on the same layer.

5. The display substrate according to claim 4, wherein: The first test line includes a first portion extending along the second direction, and the first portion and the first group of first signal lines are arranged in the same layer. The display substrate according to claim 1 , wherein: The bonding area includes a first test pad, one end of the first test line is electrically connected to the first test pad, and the other end of the first test line is electrically connected to the first location.

7. The display substrate according to claim 1, wherein: The bonding area includes a plurality of first signal pads of a first group, and the plurality of first signal lines are coupled to the plurality of first signal pads of the first group in a one-to-one correspondence.

8. The display substrate according to claim 1, wherein: The bonding opposing area further includes a plurality of first group control switches, wherein first ends of the plurality of first group control switches are electrically connected to the plurality of first group first signal lines in a one-to-one correspondence, and second ends of the plurality of first group control switches are electrically connected to the first guide traces.

9. The display substrate according to claim 1, wherein: The bonding area further includes a second test pad, one end of the second test line is electrically connected to the second test pad, and the other end of the second test line is electrically connected to the third position.

10. The display substrate according to claim 9, wherein: The bonding area further includes a third test pad, one end of the third test line is electrically connected to the third test pad, and the other end of the third test line is electrically connected to the fourth position.

11. The display substrate according to claim 10, wherein: The bonding area further includes a first test pad, one end of the first test line is electrically connected to the first test pad and the other end of the first test line is electrically connected to the first position; and The first test pad and the second test pad are located on one side of the display area in the first direction, and the third test pad is located on the other side of the display area in the first direction.

12. The display substrate according to claim 10, wherein: The first resistance ratio, the second resistance ratio, and the third resistance ratio are equal to each other; The first resistance ratio is a ratio of a resistance value between the first end and the first position of the first guiding trace to a resistance value between the first position and the second end of the first guiding trace; The second resistance ratio is a ratio of a resistance value between the third end and the third position of the second guiding trace to a resistance value between the third position and the fourth end of the second guiding trace; as well as The third resistance ratio is a ratio of a resistance value between the fifth end and the fourth position of the third guiding trace to a resistance value between the fourth position and the sixth end of the third guiding trace.

13. The display substrate according to claim 12, wherein: The first position is a midpoint of resistance between the first end and the second end of the first guide trace; The third position is a midpoint of the resistance between the third end and the fourth end of the second guide trace; and The fourth position is a midpoint of the resistance between the fifth end and the sixth end of the third guiding trace.

14. The display substrate according to claim 11, wherein The plurality of first signal lines of the first group, the plurality of second signal lines of the second group, and the plurality of third signal lines of the first group are respectively used to transmit data signals of sub-pixels displaying light of different colors.

15. The display substrate according to claim 14, wherein: Resistances of the first test line, the second test line, and the third test line are equal to each other.

16. A display device comprising the display substrate according to any one of claims 1 to 15.

17. A method for testing a display substrate according to any one of claims 1 to 15, comprising: A first signal is applied to the plurality of first signal lines of the first group via the first test line and the first guide line, and detection is performed based on a display condition of the display substrate.

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