Stage of scan driver for display device and scan driver having the stage

Abstract

Disclosed are a stage of a scan driver for a display device and a scan driver having the stage, the stage comprising: an output unit, which outputs a signal supplied to a first clock terminal to an output terminal according to a voltage of a first drive node or outputs a voltage of a second power supply to an output terminal according to a voltage of a second drive node; an input unit, which controls the voltage of the first drive node according to a signal supplied to a first input terminal, and the input unit controls the voltage of the second drive node according to signals supplied to a second input terminal and a second clock terminal; a first signal processor, which controls the voltage of the second drive node according to signals supplied to a third clock terminal and a fourth clock terminal; and a second signal processor, which controls the voltage of the first drive node according to a signal supplied to the first clock terminal.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2018-0172287, filed on December 28, 2018, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0002] Exemplary embodiments of the invention relate generally to a display device, and more particularly, to a stage of the display device that outputs scan signals having pulses of opposite polarities to drive the stage and a scan driver having the stage. Background Art

[0003] An organic light emitting display (OLED) is a display device that has a fast response speed and is driven with low power consumption.

[0004] The OLED includes a scan driver that supplies scan signals to scan lines to control the supply of data signals to pixels. To this end, the scan driver includes a plurality of stages coupled to the respective scan lines.

[0005] Each stage can be constructed using multiple transistors and capacitors. However, the continuous charging and discharging of capacitors in the stages will increase the power consumption of OLEDs driven at low power.

[0006] The above information disclosed in this Background section is only for understanding the background of the inventive concept and therefore it may contain information that does not constitute the prior art. Summary of the invention

[0007] A scan driver constructed in accordance with the principles and exemplary embodiments of the invention is capable of supplying a scan signal to activate pixels controlled by N-type transistors in a display.

[0008] A stage in a scan driver constructed according to the principles and exemplary embodiments of the invention can prevent charging and discharging of a capacitor in the stage while an output scan signal maintains a low voltage.

[0009] Additional features of the inventive concepts will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the inventive concepts.

[0010] According to one aspect of the invention, a stage of a scan driver for a display device includes: an output unit, which outputs a signal supplied to a first clock terminal to an output terminal according to a voltage of a first drive node or outputs a voltage of a second power supply to an output terminal according to a voltage of a second drive node; an input unit, which controls the voltage of the first drive node according to a signal supplied to a first input terminal, and the input unit is configured to control the voltage of the second drive node according to signals supplied to a second input terminal and a second clock terminal; a first signal processor, which controls the voltage of the second drive node according to signals supplied to a third clock terminal and a fourth clock terminal; and a second signal processor, which controls the voltage of the first drive node according to a signal supplied to the first clock terminal.

[0011] The input unit may include: a first transistor coupled between a second input terminal and a second driving node, the first transistor having a gate electrode coupled to a second clock terminal; a second transistor, a diode coupled between the first input terminal and the first driving node; and a third transistor coupled between the second input terminal and the first signal processor, the third transistor having a gate electrode coupled to the second clock terminal.

[0012] The stage may further include a third signal processor coupled between the input unit and the first driving node to control a voltage of the first driving node.

[0013] The third signal processor may include a fourth transistor coupled between the second transistor and the first driving node, the fourth transistor having a gate electrode coupled to a third input terminal operable to receive the control signal.

[0014] The control signal may be supplied as a gate-on voltage of the fourth transistor during the high frequency driving mode, and supplied as a gate-off voltage of the fourth transistor in at least one frame during the low frequency driving mode to perform biasing.

[0015] The stage may also include: a first stabilizer, coupled between the first signal processor and the second driving node, the first stabilizer controlling the voltage drop of the second driving node; and a second stabilizer, coupled between the input unit and the first signal processor, the second stabilizer controlling the voltage drop of the first node in the first signal processor.

[0016] The first stabilizer may include a fifth transistor coupled between the first transistor and the second driving node, the fifth transistor having a gate electrode operable to receive a voltage from a second power supply.

[0017] The second stabilizer may include a sixth transistor coupled between the third transistor and the first node, the sixth transistor having a gate electrode operable to receive a voltage from a second power supply.

[0018] The input unit may include: a first transistor coupled between the second input terminal and the second driving node, the first transistor having a gate electrode coupled to the second clock terminal; a second transistor, a diode coupled between the second node and the first driving node; a third transistor coupled between the second input terminal and the first signal processor, the third transistor having a gate electrode coupled to the second clock terminal; a seventh transistor coupled between the first power supply and the second node, the seventh transistor having a gate electrode coupled to the first input terminal; and an eighth transistor coupled between the second node and the second power supply, the eighth transistor having a gate electrode coupled to the first input terminal. The seventh transistor may be a p-type transistor, and the eighth transistor may be an n-type transistor.

[0019] The first signal processor may further include: a ninth transistor coupled between the first power supply and the third node, the ninth transistor having a gate electrode coupled to the fourth clock terminal; a tenth transistor coupled between the third node and the third clock terminal, the tenth transistor having a gate electrode coupled to the first node; an eleventh transistor, a diode coupled between the first node and the second driving node; and a first capacitor coupled between the first node and the third node, the potential difference between the two ends of the first capacitor being controllable according to a signal supplied to the fourth clock terminal.

[0020] When the voltage of the second power supply is output to the output terminal, the potential difference between both ends of the first capacitor can be kept substantially constant.

[0021] The output terminal may be operable to output a scan signal having a first polarity, the second input terminal may be operable to receive a first polarity scan signal of a previous stage, and the first input terminal may be operable to receive a scan signal of a previous stage having a second polarity. The first polarity and the second polarity may be opposite to each other.

[0022] According to another aspect of the invention, a scan driver including multiple stages for supplying scan signals to scan lines of a display device, the scan driver including: a first stage array having multiple first stages for supplying scan signals of a first polarity to the scan lines; and a second stage array having multiple second stages for supplying scan signals of a second polarity to the scan lines. At least one of the multiple first stages includes: an output unit for outputting a signal supplied to a first clock terminal to an output terminal according to a voltage of a first drive node or outputting a voltage of a second power supply to an output terminal according to a voltage of a second drive node; an input unit for controlling the voltage of the first drive node according to a signal supplied to a first input terminal, the input unit for controlling the voltage of the second drive node according to signals supplied to a second input terminal and a second clock terminal; a first signal processor for controlling the voltage of the second drive node according to signals supplied to a third clock terminal and a fourth clock terminal; and a second signal processor for controlling the voltage of the first drive node according to a signal supplied to the first clock terminal.

[0023] The input unit may include: a first transistor coupled between a second input terminal and a second driving node, the first transistor having a gate electrode coupled to a second clock terminal; a second transistor, a diode coupled between the first input terminal and the first driving node; and a third transistor coupled between the second input terminal and the first signal processor, the third transistor having a gate electrode coupled to the second clock terminal.

[0024] The scan driver may further include: a third signal processor coupled between the input unit and the first driving node to control a voltage of the first driving node.

[0025] The third signal processor may include a fourth transistor coupled between the second transistor and the first driving node, the fourth transistor having a gate electrode coupled to a third input terminal operable to receive the control signal.

[0026] The control signal may be supplied as a gate-on voltage of the fourth transistor during the high frequency driving mode, and supplied as a gate-off voltage of the fourth transistor in at least one frame during the low frequency driving mode to perform biasing.

[0027] The scan driver may also include: a first stabilizer, coupled between the first signal processor and the second driving node, the first stabilizer being operable to control the amount of voltage drop at the second driving node; and a second stabilizer, coupled between the input unit and the first signal processor, the second stabilizer controlling the amount of voltage drop at the first node in the first signal processor.

[0028] The first stabilizer may include a fifth transistor coupled between the first transistor and the second driving node, the fifth transistor having a gate electrode supplied with a voltage of a second power supply, and the second stabilizer may include a sixth transistor coupled between the third transistor and the first node, the sixth transistor having a gate electrode operable to receive a voltage from the second power supply.

[0029] The input unit may include: a first transistor coupled between the second input terminal and the second driving node, the first transistor having a gate electrode coupled to the second clock terminal; a second transistor, a diode coupled between the second node and the first driving node; a third transistor coupled between the second input terminal and the first signal processor, the third transistor having a gate electrode coupled to the second clock terminal; a seventh transistor coupled between the first power supply and the second node, the seventh transistor having a gate electrode coupled to the first input terminal; and an eighth transistor coupled between the second node and the second power supply, the eighth transistor having a gate electrode coupled to the first input terminal. The seventh transistor may be a p-type transistor, and the eighth transistor may be an n-type transistor.

[0030] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the inventive concept.

[0032] Figure 1 is a block diagram of an exemplary embodiment of a display device constructed according to the principles of the invention.

[0033] Figure 2 yes Figure 1 A circuit diagram of a typical pixel of a display device.

[0034] Figure 3 is a block diagram of an exemplary embodiment of a first stage array of scan drivers constructed according to the principles of the invention.

[0035] Figure 4 is a block diagram of an exemplary embodiment of a second stage array of scan drivers constructed according to the principles of the invention.

[0036] Figure 5 yes Figure 3 A circuit diagram of a first exemplary embodiment of the first stage is shown in FIG.

[0037] Figure 6 It is shown Figure 5Graph of exemplary high frequency operation of the first stage shown in .

[0038] Figure 7 It is shown Figure 5 An exemplary timing diagram for high frequency operation of the first stage is shown in FIG.

[0039] Figure 8 It is shown Figure 5 Graph of exemplary low frequency operation of the first stage shown in .

[0040] Fig. 9 It is shown Figure 5 FIG. 4 is a diagram of another exemplary embodiment of low frequency operation of the first stage shown in FIG.

[0041] Fig.10 It is shown Figure 5 An exemplary timing diagram for low frequency operation of the first stage is shown in .

[0042] Fig.11 yes Figure 3 A circuit diagram of a second exemplary embodiment of the first stage is shown in FIG.

[0043] Fig.12 yes Figure 3 0047] A circuit diagram of a third exemplary embodiment of the first stage shown in FIG.

[0044] Fig.13 It is shown Figure 3 0047 is a circuit diagram of a fourth exemplary embodiment of the first stage shown in FIG.

[0045] Fig.14 It is shown Figure 3 0047 is a circuit diagram of a fifth exemplary embodiment of the first stage shown in FIG.

[0046] Fig.15 It is shown Fig.14 An exemplary timing diagram of an exemplary driving method of the first stage is shown in FIG. DETAILED DESCRIPTION

[0047] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of various exemplary embodiments or implementations of the invention. "Embodiment" and "implementation" as used herein are interchangeable words as non-limiting examples of devices or methods that adopt one or more inventive concepts disclosed herein. However, it is apparent that various exemplary embodiments can be implemented without these specific details or with one or more equivalent arrangements. In other cases, in order to avoid making various exemplary embodiments unnecessarily obscure, known structures and devices are shown in block diagram form. In addition, various exemplary embodiments may be different, but need not be exclusive. For example, without departing from the inventive concept, the specific shape, construction and characteristics of the exemplary embodiment may be used or implemented in another exemplary embodiment.

[0048] Unless otherwise specified, the exemplary embodiments shown will be understood as providing exemplary features of details of variations in some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter, individually or collectively referred to as "elements") of the various embodiments may be further combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0049] The use of cross hatching and / or shading is usually provided in the drawings to make the boundaries between adjacent elements clear. Thus, unless otherwise specified, the presence and absence of cross hatching or shading do not express or indicate any preference or requirement for the specific material, material properties, size, ratio, commonality between the elements shown and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for clarity and / or descriptive purposes. When the exemplary embodiments may be implemented differently, the specific process sequence may be performed differently from the described sequence. For example, two continuously described processes may be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0050] When an element or layer is referred to as being "on" another element or layer, "connected to" or "bonded to" another element or layer, the element or layer may be directly on, directly connected to or directly bonded to the other element or layer, or there may be an intermediate element or intermediate layer. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly bonded to" another element or layer, there is no intermediate element or intermediate layer. For this reason, the term "connection" may refer to a physical connection, an electrical connection and / or a fluid connection with or without an intermediate element. In addition, the D1 axis, the D2 axis and the D3 axis are not limited to the three axes of a rectangular coordinate system (such as, the x-axis, the y-axis and the z-axis), and may be interpreted in a broader sense. For example, the D1 axis, the D2 axis and the D3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as any combination of only X, only Y, only Z, or two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items.

[0051] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the disclosed teachings, the first element discussed below may be referred to as the second element.

[0052] For descriptive purposes, spatially relative terms such as "under," "below," "under," "down," "above," "upper," "above," "higher," "side" (e.g., as in "sidewall"), etc., may be used herein to describe the relationship of one element to another (other) element as shown in the accompanying drawings. In addition to the orientation depicted in the accompanying drawings, the spatially relative terms are also intended to include different orientations of the device in use, operation, and / or manufacture. For example, if the device in the accompanying drawings is turned over, the elements described as "under" or "beneath" other elements or features will subsequently be positioned as "above" the other elements or features. Thus, the exemplary term "under" can include both above and below orientations. In addition, the device can be positioned otherwise (e.g., rotated 90 degrees or in other orientations), so the spatially relative descriptors used herein are interpreted accordingly.

[0053] The terms used here are for the purpose of describing specific embodiments, and are not intended to be limited. As used here, unless the context clearly indicates otherwise, the singular forms "one", "one (kind / person)" and "said (the)" are also intended to include plural forms. In addition, when the terms "comprise" and / or "include" and their variations are used in this specification, the characteristics, integral bodies, steps, operations, elements, components and / or their groups stated are explained, but one or more other characteristics, integral bodies, steps, operations, elements, components and / or their groups are not excluded from existence or addition. It should also be noted that, as used here, the terms "substantially", "approximately" and other similar terms are used as approximate terms and not as terms of degree, so that they are used to explain the inherent deviations of measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art of which this disclosure is a part. Unless explicitly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense.

[0055] Figure 1 is a block diagram of a display device according to an exemplary embodiment of a display device constructed in accordance with the principles of the invention.

[0056] Reference Figure 1 , a display device 1 according to an exemplary embodiment may include a timing controller 10 , a data driver 20 , a scan driver 30 , an emission driver 40 , and a display unit 50 .

[0057] The timing controller 10 may provide the data driver 20 with grayscale values ​​and control signals that comply with the specifications of the data driver 20. In addition, the timing controller 10 may provide the scan driver 30 with a clock signal, a scan start signal, etc. that comply with the specifications of the scan driver 30. In addition, the timing controller 10 may provide the emission driver 40 with a clock signal, an emission stop signal, etc. that comply with the specifications of the emission driver 40.

[0058] The data driver 20 may generate data voltages to be supplied to the data lines D1 to Dm using the grayscale values ​​and control signals received from the timing controller 10. For example, the data driver 20 may sample the grayscale values ​​using the clock signal and apply data voltages corresponding to the grayscale values ​​to the data lines D1 to Dm in units of pixel rows. Here, m may be a natural number.

[0059] The scan driver 30 may generate scan signals to be supplied to the scan lines G11 to G1n, G21 to G2n, G31 to G3n, and G41 to G4n by receiving a clock signal, a scan start signal, etc. Here, n may be a natural number.

[0060] The scan driver 30 may provide a scan signal having a pulse of opposite polarity. The polarity may represent a logic level of the pulse, such as a high level or a low level, or a negative level or a positive level. In an example, the scan driver 30 may provide a scan signal of a first polarity to the first scan lines G11 to G1n and the second scan lines G21 to G2n, and provide a scan signal of a second polarity opposite to the first polarity to the third scan lines G31 to G3n and the fourth scan lines G41 to G4n. To this end, the scan driver 30 may include a first stage that provides a scan signal of a first polarity and a second stage that provides a scan signal of a second polarity.

[0061] In an exemplary embodiment, the first polarity scan signals respectively supplied to the first scan lines G11 to G1n and the second scan lines G21 to G2n may have the same wavelength or different wavelengths. Similarly, the second polarity scan signals respectively supplied to the third scan lines G31 to G3n and the fourth scan lines G41 to G4n may have the same wavelength or different wavelengths.

[0062] When the pulse has a first polarity, the pulse may have a high level of gate-on voltage. When the gate-on voltage of the pulse of the first polarity is supplied to the gate electrode of the N-type transistor, the N-type transistor may be turned on. Assume that a sufficiently low level voltage is applied to the source electrode of the N-type transistor compared to the gate electrode of the N-type transistor. For example, the N-type transistor may be an NMOS transistor.

[0063] In addition, when the pulse has the second polarity, the pulse may have a low level of gate-on voltage. When the gate-on voltage of the pulse of the second polarity is supplied to the gate electrode of the P-type transistor, the P-type transistor may be turned on. Assume that a sufficiently high level of voltage is applied to the source electrode of the P-type transistor compared to the gate electrode of the P-type transistor. For example, the P-type transistor may be a PMOS transistor.

[0064] The emission driver 40 may generate an emission signal to be supplied to the emission control lines E1 to En by receiving a clock signal, an emission stop signal, etc. from the timing controller 10. For example, the emission driver 40 may sequentially supply an emission signal having a pulse of an off level to the emission control lines E1 to En. For example, the emission driver 40 may be constructed in the form of a shift register, and generate an emission signal under the control of a clock signal in such a manner that an emission stop signal having a pulse of an off level is sequentially transmitted to a next emission stage circuit.

[0065] The display unit 50 includes pixels PX. For example, each pixel PX may be coupled to a corresponding data line, corresponding first to fourth scan lines, and a corresponding emission control line.

[0066] Figure 2 yes Figure 1 A circuit diagram of a typical pixel of a display device.

[0067] Reference Figure 2 , a pixel PX according to an exemplary embodiment includes first to seventh transistors T1 to T7 , a storage capacitor Cst, and an organic light emitting diode OLED.

[0068] The first transistor T1 is coupled between the first node N1 and the second node N2. A gate electrode of the first transistor T1 is coupled to a third node N3. The first transistor T1 may be referred to as a driving transistor.

[0069] The second transistor T2 is coupled between the data line Dm and the first node N1. A gate electrode of the second transistor T2 is coupled to the third scan line G3n. The second transistor T2 may be referred to as a switching transistor, a scan transistor, or the like.

[0070] The third transistor T3 may be coupled between the third node N3 and the second node N2. A gate electrode of the third transistor T3 is coupled to the first scan line G1n. The third transistor T3 may be referred to as a diode-coupled transistor.

[0071] The fourth transistor T4 is coupled between the third node N3 and the initialization power source Vint. A gate electrode of the fourth transistor T4 is coupled to the second scan line G2n. The fourth transistor T4 may be referred to as a gate electrode initialization transistor.

[0072] The fifth transistor T5 is coupled between the first driving power source ELVDD and the first node N1. A gate electrode of the fifth transistor T5 is coupled to the emission control line En. The fifth transistor T5 may be referred to as a first emission transistor.

[0073] The sixth transistor T6 is coupled between the second node N2 and the anode of the organic light emitting diode OLED. A gate electrode of the sixth transistor T6 is coupled to the emission control line En. The sixth transistor T6 may be referred to as a second emission transistor.

[0074] The seventh transistor T7 is coupled between the organic light emitting diode OLED and the initialization power source Vint. A gate electrode of the seventh transistor T7 is coupled to the fourth scan line G4n. The seventh transistor T7 may be referred to as an anode initialization transistor.

[0075] The storage capacitor Cst is coupled between the first driving power source ELVDD and the third node N3.

[0076] An anode electrode of the organic light emitting diode OLED is coupled to the second node N2, and a cathode electrode of the organic light emitting diode OLED may be coupled to a second driving power source ELVSS. The second driving power source ELVSS may be set lower than the first driving power source ELVDD.

[0077] The first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 can be implemented as P-type transistors. The channel of the P-type transistor can be constructed with polysilicon. The polysilicon transistor can be a low temperature polysilicon (LTPS) transistor. The polysilicon transistor has high electron mobility and therefore has fast driving characteristics.

[0078] The third transistor T3 and the fourth transistor T4 can be implemented as N-type transistors. The channel of the N-type transistor can be constructed with an oxide semiconductor. The oxide semiconductor transistor can be formed by a low temperature process and has a charge mobility lower than that of a polysilicon transistor. Therefore, the oxide semiconductor transistor has a certain amount of leakage current generated in the off state, and the amount of leakage current of the oxide semiconductor transistor is less than the amount of leakage current of the polysilicon transistor.

[0079] In some exemplary embodiments, the seventh transistor T7 may be configured with an N-type oxide semiconductor transistor instead of a polysilicon transistor. In this case, instead of the fourth scan line G4n, the first scan line G1n or the second scan line G2n may be coupled to the gate electrode of the seventh transistor T7.

[0080] Figure 3 is a block diagram of an exemplary embodiment of a first stage array of scan drivers constructed according to the principles of the invention.

[0081] Reference Figure 3 The scan driver 30 constructed according to the principles of the invention and exemplary embodiments includes a first stage array ST1 having a plurality of first stages ST11 to ST14 for providing a scan signal of a first polarity to the first scan lines G11 to G1n and / or the second scan lines G21 to G2n. For ease of description, Figure 3 Four first stages ST11 to ST14 are shown in FIG.

[0082] The first stages ST11 to ST14 may supply first polarity scan signals nSC(1), nSC(2), nSC(3), and nSC(4) to scan lines G1 (e.g., G11 or G21), G2 (e.g., G12 or G22), G3 (e.g., G13 or G23), and G4 (e.g., G14 or G24) in response to a scan start signal SSP. For example, the nth first stage ST1n may output the nth first polarity scan signal nSC(n) to the nth scan line Gn (e.g., G1n or G2n).

[0083] like Figure 3 Each of the first stages ST11 to ST14 shown in the figure may include a first input terminal IN1, a second input terminal IN2, a third input terminal IN3, a first clock terminal CK1, a second clock terminal CK2, a third clock terminal CK3, a fourth clock terminal CK4, a first power supply terminal V1, a second power supply terminal V2, and an output terminal OUT.

[0084] A scan start signal SSP or a first polarity scan signal of a previous first stage may be input to the first input terminal IN1. In an exemplary embodiment, the scan start signal SSP is supplied to the first input terminal IN1 of the first first stage ST11, and a scan signal of a previous first stage may be supplied to the first input terminal IN1 of each of the first stages except the first first stage ST11 and the second first stage ST12, as shown in FIG. Figure 3 In the same manner, the first polarity scan signal nSC(n-2) of the n-2 th first stage ST1n-2 may be supplied to the first input terminal IN1 of the n th first stage ST1n. Here, n is a natural number of 3 or more.

[0085] The control signal PEN may be input to the second input terminal IN2. The control signal PEN may maintain the gate-on voltage when the display device 1 is driven at a high frequency, and may be output during a period (eg, a period of time) including a plurality of frames when the display device 1 is driven at a low frequency. Figure 6 , Figure 8 and Fig. 9 The gate-on voltage is maintained during at least one frame of the display (as shown in ), and the gate-off voltage is maintained during the other frames.

[0086] The second polarity scan signal pSC output from the previous second stage (to be described later) is input to the third input terminal IN3. In an exemplary embodiment, the second polarity scan signal pSC(n-1) output from the n-1 second stage ST2(n-1) may be input to the third input terminal IN3 of the n-2 second stage ST2n.

[0087] In another exemplary embodiment, the first polarity scan signal nSC output from the previous first stage may be input to the third input terminal IN3. In an exemplary embodiment, the n-1th first polarity scan signal nSC(n-1) may be input to the third input terminal IN3 of the nth first stage ST1n.

[0088] Any one of the first to fourth n-type clock signals nCLK1 to nCLK4 may be applied to the first clock terminal CK1. In an exemplary embodiment, when the first n-type clock signal nCLK1 is input to the first clock terminal CK1 of the nth first stage ST1n, the second n-type clock signal nCLK2 may be input to the first clock terminal CK1 of the n+1th first stage ST1n+1, the third n-type clock signal nCLK3 may be input to the first clock terminal CK1 of the n+2th first stage ST1n+2, and the fourth n-type clock signal nCLK4 may be input to the first clock terminal CK1 of the n+3th first stage ST1n+3. In an exemplary embodiment, the first n-type clock signal nCLK1 and the third n-type clock signal nCLK3 may be signals having a difference of a half horizontal period, and the second n-type clock signal nCLK2 and the fourth n-type clock signal nCLK4 may be signals having a difference of a half horizontal period.

[0089] In an exemplary embodiment, the gate-on voltage period of each of the n-type clock signals nCLK1 to nCLK4 may correspond to two horizontal periods 2H. In addition, the gate-on voltage period of the first n-type clock signal nCLK1 and the gate-on voltage period of the second n-type clock signal nCLK2 may overlap each other during one horizontal period 1H. However, this is merely exemplary, and the wavelength relationship between the n-type clock signals nCLK1 to nCLK4 is not limited thereto. In addition, the number of n-type clock signals supplied to one stage is not limited thereto.

[0090] Each of the first to fourth n-type clock signals nCLK1 to nCLK4 may be set as a square wave signal in which a logic high level and a logic low level are alternately repeated. The logic high level may correspond to a gate-on voltage, and the logic low level may correspond to a gate-off voltage.

[0091] Any one of the first to fourth p-type clock signals pCLK1 to pCLK4 may be applied to the second clock terminal CK2, another one of the first to fourth p-type clock signals pCLK1 to pCLK4 may be applied to the third clock terminal CK3, and yet another one of the first to fourth p-type clock signals pCLK1 to pCLK4 may be applied to the fourth clock terminal CK4. In an exemplary embodiment, when the first n-type clock signal nCLK1 is applied to the first clock terminal CK1 of the first stage, the third to fourth p-type clock signals pCLK3, pCLK4, and pCLK2 may be input to the second to fourth clock terminals CK2 to CK4, respectively. In an exemplary embodiment, the third to fourth p-type clock signals pCLK3 and pCLK4 may be signals having a difference of 1 / 4 horizontal period, and the fourth to second p-type clock signals pCLK4 and pCLK2 may be signals having a difference of half horizontal period.

[0092] In an exemplary embodiment, when the third p-type clock signal pCLK3 is input to the second clock terminal CK2 of the nth first stage ST1n, the fourth p-type clock signal pCLK4 may be input to the second clock terminal CK2 of the n+1th first stage ST1n+1, and the first p-type clock signal pCLK1 may be input to the n+2th first stage ST1n+1.

[0093] The second p-type clock signal pCLK2 may be input to the second clock terminal CK2 of the first stage ST1n+2, and the second p-type clock signal pCLK2 may be input to the second clock terminal CK2 of the n+3 th first stage ST1n+3.

[0094] The first power terminal V1 may receive a voltage of a first power source VGH, and the second power terminal V2 may receive a voltage of a second power source VGL.

[0095] The output terminal OUT may output the first polarity scan signals nSC(1), nSC(2), nSC(3), and nSC(4). The first polarity scan signal nSC(n) output to the output terminal OUT of the nth first stage ST1n may be supplied to the first input terminal IN1 of the following first stage (e.g., the n+2th first stage ST1n+2).

[0096] Figure 4 is a block diagram of an exemplary embodiment of a second stage array of scan drivers constructed according to the principles of the invention. Figure 4 In the example, the p-type clock signals pCLK1 to pCLK4 are Figure 3 The same signal as shown in .

[0097] Reference Figure 1 , Figure 3 and Figure 4 The scan driver 30 constructed according to the principles of the invention and exemplary embodiments includes a second stage array ST2 having a plurality of second stages ST21 to ST24 for providing a scan signal of a second polarity to the third scan lines G31 to G3n and / or the fourth scan lines G41 to G4n. For ease of description, Figure 4 Four second stages ST21 to ST24 are shown in FIG.

[0098] The second stages ST21 to ST24 may supply the second polarity scan signals pSC(1), pSC(2), pSC(3), and pSC(4) to the scan lines G1 (e.g., G31 or G41), G2 (e.g., G32 or G42), G3 (e.g., G33 or G43), and G4 (e.g., G34 or G44) in response to the scan start signal SSP. For example, the nth second stage ST2n may output the nth second polarity scan signal pSC(n) to the nth scan line Gn (e.g., G3n or G4n).

[0099] like Figure 4 Each of the second stages ST21 to ST24 shown in FIG. 5 may include an input terminal IN, a first clock terminal CK1 , a second clock terminal CK2 , a first power supply terminal V1 , a second power supply terminal V2 , and an output terminal OUT.

[0100] The scan start signal SSP or the second polarity scan signal of the previous second stage may be input to the input terminal IN. In an exemplary embodiment, the scan start signal SSP may be supplied to the input terminal IN of the first second stage ST21, and the scan signal of the previous second stage may be supplied to the input terminal IN of each of the second stages except the first second stage ST21. In an exemplary embodiment, the second polarity scan signal pSC(n-1) of the n-1th second stage ST2n-1 may be supplied to the input terminal IN of the n-th second stage ST2n. Here, n is a natural number of 2 or more.

[0101] Any one of the first to fourth p-type clock signals pCLK1 to pCLK4 may be applied to the first clock terminal CK1, and another one of the first to fourth p-type clock signals pCLK1 to pCLK4 may be applied to the second clock terminal CK2. In an exemplary embodiment, when the first p-type clock signal pCLK1 is applied to the n-th second stage ST2n, the other one of the p-type clock signals may be the third p-type clock signal pCLK3. In addition, when the second p-type clock signal pCLK2 is applied to the n-th second stage ST2n, the other one of the p-type clock signals may be the fourth p-type clock signal pCLK4.

[0102] In an exemplary embodiment, when the first p-type clock signal pCLK1 is input to the first clock terminal CK1 of the n-th second stage ST2n and the third p-type clock signal pCLK3 is input to the second clock terminal CK2 of the n-th second stage ST2n, the second p-type clock signal pCLK2 may be input to the first clock terminal CK1 of the n+1-th second stage ST2n+1, and the fourth p-type clock signal pCLK4 may be input to the second clock terminal CK2 of the n+1-th second stage ST2n+1. In addition, the third p-type clock signal pCLK3 may be input to the first clock terminal CK1 of the n+2-th second stage ST2n+2, the first p-type clock signal pCLK1 may be input to the second clock terminal CK2 of the n+2-th second stage ST2n+2, the fourth p-type clock signal pCLK4 may be input to the first clock terminal CK1 of the n+3-th second stage ST2n+3, and the second p-type clock signal pCLK2 may be input to the second clock terminal CK2 of the n+3-th second stage ST2n+3. In an exemplary embodiment, the first and third p-type clock signals pCLK1 and pCLK3 may be signals having a difference of a half horizontal period, and the second and fourth p-type clock signals pCLK2 and pCLK4 may be signals having a difference of a half horizontal period.

[0103] In an exemplary embodiment, the gate-on voltage period of each of the p-type clock signals pCLK1 to pCLK4 may correspond to two horizontal periods 2H. In addition, the gate-on voltage period of the first p-type clock signal pCLK1 and the gate-on voltage period of the second p-type clock signal pCLK2 may overlap each other during one horizontal period 1H. However, this is merely exemplary, and the wavelength relationship between the p-type clock signals pCLK1 to pCLK4 is not limited thereto. In addition, the number of p-type clock signals supplied to one stage is not limited thereto.

[0104] Each of the first to fourth p-type clock signals pCLK1 to pCLK4 may be set as a square wave signal in which a logic high level and a logic low level are alternately repeated. The logic high level may correspond to a gate-off voltage, and the logic low level may correspond to a gate-on voltage.

[0105] The first power terminal V1 may receive a voltage of a first power source VGH, and the second power terminal V2 may receive a voltage of a second power source VGL.

[0106] The output terminal OUT can output the second polarity scan signals pSC(1), pSC(2), pSC(3) and pSC(4). The second polarity scan signal pSC(n) output to the output terminal OUT of the nth second stage ST2n can be supplied to the input terminal IN of the next second stage (e.g., the n+1th second stage ST2n+1). In addition, the second polarity scan signal pSC(n) output to the output terminal OUT of the nth second stage ST2n can be supplied to the third input terminal IN3 of the next first stage (e.g., the n+1th first stage ST1n+1). For example, the first second polarity scan signal pSC(1) of the first second stage ST21 can be supplied to the third input terminal IN3 of the second first stage ST12, as shown in FIG. Figure 3 as shown in .

[0107] Figure 5 yes Figure 3 A circuit diagram of a first exemplary embodiment of the first stage is shown in FIG.

[0108] For ease of description, Figure 5 Only the nth first stage ST1n is shown, but Figure 3 All of the first stages (such as ST11, ST12, ST13, and ST14) shown in FIG. 1 may have the same or substantially the same structure as an nth first stage ST1n described below.

[0109] Reference Figure 1 , Figure 3 and Figure 5 The nth first stage ST1n according to the first exemplary embodiment includes an input unit 110 , an output unit 120 , a first signal processor 130 , a second signal processor 140 , a third signal processor 150 , and first and second stabilizers 161 and 162 .

[0110] The output unit 120 outputs the third n-type clock signal nCLK3 or the voltage of the second power supply VGL to the output terminal OUT in response to the voltages of the first and second driving nodes Q and QB. To this end, the output unit 120 includes an eighth transistor M8 and a ninth transistor M9.

[0111] The eighth transistor M8 is coupled between the first clock terminal CK1 to which the third n-type clock signal nCLK3 is applied and the output terminal OUT. In addition, the gate electrode of the eighth transistor M8 is coupled to the first drive node Q. The eighth transistor M8 is turned on or off according to the voltage of the first drive node Q. The third n-type clock signal nCLK3 supplied to the output terminal OUT when the eighth transistor M8 is turned on is output as a first polarity scan signal nSC(n) of the nth scan line Gn (e.g., the nth first scan line G1n and / or the nth second scan line G2n).

[0112] The ninth transistor M9 is coupled between the output terminal OUT and the second power source VGL. In addition, a gate electrode of the ninth transistor M9 is coupled to the second driving node QB. The ninth transistor M9 is turned on or off according to the voltage of the second driving node QB.

[0113] The input unit 110 controls voltages of the first node N1, the second node N2 and the second driving node QB in response to signals supplied to the first input terminal IN1, the third input terminal IN3 and the second clock terminal CK2. To this end, the input unit 110 includes a first transistor M1, a second transistor M2 and a tenth transistor M10.

[0114] The first electrode of the first transistor M1 is coupled to the first input terminal IN1 to which the scan start signal SSP or the first polarity scan signal nSC(n-2) of the n-2 first stage ST1n-2 is applied, and the second electrode of the first transistor M1 is coupled to the second drive node QB via the sixth transistor M6. The gate electrode of the first transistor M1 is coupled to the second clock terminal CK2. When the first p-type clock signal pCLK1 is supplied to the second clock terminal CK2, the first transistor M1 is turned on to electrically couple the first input terminal IN1 to the second drive node QB.

[0115] The second transistor M2 is diode-coupled between the third input terminal IN3 to which the second polarity scan signal pSC(n-1) of the n-1th second stage ST2n-1 is applied and the first node N1. The second transistor M2 may transmit the second polarity scan signal pSC(n-1) of the n-1th second stage ST2n-1 supplied to the third input terminal IN3 to the first node N1.

[0116] A first electrode of the tenth transistor M10 is coupled to the first input terminal IN1, and a second electrode of the tenth transistor M10 is coupled to the second node N2 via the eleventh transistor M11. A gate electrode of the tenth transistor M10 is coupled to the second clock terminal CK2. When the first p-type clock signal pCLK1 is supplied to the second clock terminal CK2, the tenth transistor M10 is turned on to electrically couple the first input terminal IN1 to the second node N2.

[0117] The first signal processor 130 controls the voltage of the first driving node Q in response to the voltage of the first node N1. To this end, the first signal processor 130 includes a third transistor M3.

[0118] The third transistor M3 is coupled between the first node N1 and the first driving node Q. A gate electrode of the third transistor M3 is coupled to the second input terminal IN2 to which a control signal PEN is applied. When the control signal PEN is applied, the third transistor M3 is turned on to couple the first node N1 to the first driving node Q. Therefore, the third transistor M3 can control the voltage of the first driving node Q.

[0119] The second signal processor 140 is coupled to the second driving node QB and controls the voltage of the second driving node QB in response to signals supplied to the third clock terminal CK3 and the fourth clock terminal CK4. To this end, the second signal processor 140 includes a fourth transistor M4, a fifth transistor M5, a twelfth transistor M12 and a second capacitor C2.

[0120] The fifth transistor M5 and the fourth transistor M4 are coupled in series between the first power supply terminal V1 to which the voltage of the first power supply VGH is applied and the third clock terminal CK3 to which the second p-type clock signal pCLK2 is applied. A common node of the fifth transistor M5 and the fourth transistor M4 is referred to as a third node N3.

[0121] A gate electrode of the fifth transistor M5 is coupled to a fourth clock terminal CK4 to which a fourth p-type clock signal pCLK4 is applied. The fifth transistor M5 is turned on or off according to a signal supplied to the fourth clock terminal CK4.

[0122] A gate electrode of the fourth transistor M4 is coupled to the second node N2. The fourth transistor M4 is turned on or off according to a voltage of the second node N2.

[0123] The twelfth transistor M12 is coupled between the second node N2 and the second driving node QB. The twelfth transistor M12 may electrically couple the second node N2 to the second driving node QB in response to a voltage of the second node N2.

[0124] The second capacitor C2 is coupled between the third node N3 and the second node N2. The second capacitor C2 charges a voltage corresponding to a gate-on voltage of the fourth transistor M4.

[0125] The third signal processor 150 controls the voltage of the first driving node Q. To this end, the third signal processor 150 includes a seventh transistor M7 and a first capacitor C1.

[0126] The seventh transistor M7 is coupled between the first clock terminal CK1 to which the third n-type clock signal nCLK3 is applied and the first drive node Q. The gate electrode of the seventh transistor M7 is coupled to the second drive node QB. The seventh transistor M7 is turned on or off according to the voltage of the second drive node QB. When the seventh transistor M7 is turned on, the first clock terminal CK1 and the first drive node Q can be electrically coupled to each other.

[0127] The first capacitor C1 is coupled to the first clock terminal CK1 and the first driving node Q. The first capacitor C1 charges a voltage applied to the first driving node Q. In addition, the first capacitor C1 stably maintains the voltage of the first driving node Q.

[0128] The first stabilizer 161 is coupled between the second signal processor 140 and the output unit 120. The first stabilizer 161 limits the extent of the voltage drop of the second driving node QB. To this end, the first stabilizer 161 includes a sixth transistor M6.

[0129] The sixth transistor M6 is coupled between the first transistor M1 and the second driving node QB. A gate electrode of the sixth transistor M6 is coupled to the second power terminal V2 to which the voltage of the second power source VGL is applied. The sixth transistor M6 is set to a turn-on state.

[0130] The second stabilizer 162 is coupled between the input unit 110 and the second signal processor 140. The second stabilizer 162 limits the extent of the voltage drop of the second node N2. To this end, the second stabilizer 162 includes an eleventh transistor M11.

[0131] The eleventh transistor M11 is coupled to the tenth transistor M10 and the second node N2. A gate electrode of the eleventh transistor M11 is coupled to the second power supply terminal V2. The eleventh transistor M11 is set to a turned-on state.

[0132] The transistors M1 to M12 of the first stage ST1 may be implemented with p-type transistors.

[0133] Figure 6 It is shown Figure 5 Graph of exemplary high frequency operation of the first stage shown in .

[0134] When the display device 1 is driven using a high frequency driving method, this can be represented as the display device 1 being in a first driving mode. In addition, when the display device 1 is driven using a low frequency driving method, this can be represented as the display device 1 being in a second driving mode.

[0135] The first driving mode may be a normal driving mode. That is, when a user uses the display device 1, frames may be displayed at 20 Hz or more (eg, 60 Hz).

[0136] The second driving mode may be a low power driving mode. For example, when the user is not using the display device 1, the frame may be displayed at less than 20 Hz (e.g., 1 Hz). For example, a situation where only the time and date are displayed in the "always on mode" during the normal use mode may correspond to the second driving mode.

[0137] In the first driving mode, a period may include a plurality of frames. A period is an arbitrarily defined period and is defined as a period to be compared with the second driving mode. A period may mean the same time interval in the first driving mode and the second driving mode.

[0138] In the first driving mode, each frame may include a data writing period WP and an emission period EP.

[0139] In the first driving mode, the control signal PEN may maintain a gate-on voltage that turns on the third transistor M3 during a period including a plurality of frames. Figure 5 , the third transistor M3 receiving the control signal PEN through the gate electrode of the third transistor M3 may maintain a turned-on state during one period.

[0140] Figure 7 It is shown Figure 5 For ease of description, the first stage of the high frequency operation is shown in the exemplary timing diagram. Figure 7 The operation in any one frame during a period is described in .

[0141] Reference Figure 3 , Figure 5 and Figure 7 , a timing diagram of clock signals pCLK1, pCLK2, pCLK3, pCLK4 and nCLK3, a control signal PEN and scan signals pSC(n-1), nSC(n-2), pSC(n) and nSC(n) is shown. The horizontal synchronization signal Hsync is shown as a reference signal for timing. The interval between pulses of the horizontal synchronization signal Hsync may be referred to as one horizontal period.

[0142] The first p-type clock signal pCLK1 to the fourth p-type clock signal pCLK4 are constructed with the same square wave, and each of the first p-type clock signal pCLK1 to the fourth p-type clock signal pCLK4 may be a signal whose phase is delayed by 1 / 4 cycle. The third n-type clock signal nCLK3 may be a signal having a pulse of a polarity opposite to that of the third p-type clock signal pCLK3. Each of the clock signals pCLK1, pCLK2, pCLK3, pCLK4, and nCLK3 may have a high-level portion set to be longer than a low-level portion in one cycle (for example, 4H) constructed as one square wave. Therefore, during one cycle, the high-level portions of the first p-type clock signal pCLK1 to the fourth p-type clock signal pCLK4 may overlap each other at least once.

[0143] During the high frequency driving period, the control signal PEN maintains the gate-on voltage. Therefore, the third transistor M3 maintains the on state during the high frequency driving period.

[0144] At the first time t1, the first p-type clock signal pCLK1 of a low level and the previous first polarity scan signal nSC(n-2) of a high level are supplied.

[0145] The first transistor M1 and the tenth transistor M10 are turned on by the low-level first p-type clock signal pCLK1, and the high-level previous first polarity scan signal nSC(n-2) is supplied to the second driving node QB. Therefore, the fourth transistor M4, the seventh transistor M7, and the ninth transistor M9 whose gate electrodes are coupled to the second driving node QB are turned off.

[0146] Since the second transistor M2 is in a diode-bonded state, the direction of the current does not flow from one electrode (the source electrode) of the second transistor M2 toward the other electrode (the drain electrode) of the second transistor M2. Therefore, at the first moment t1, the high-level second polarity scan signal pSC(n-1) is not transmitted to the first drive node Q. Therefore, the first drive node Q maintains the voltage of the previous period.

[0147] At the second time t2, the previous second polarity scan signal pSC(n-1) of a low level and the second p-type clock signal pCLK2 of a low level are supplied.

[0148] Therefore, according to the previous second polarity scan signal pSC(n-1) of the low level, the voltage of the first driving node Q becomes a low level and the eighth transistor M8 is turned on, and the gate electrode of the eighth transistor M8 is coupled to the first driving node Q. Therefore, the third n-type clock signal nCLK3 is output to the output terminal OUT to serve as the first polarity scan signal nSC(n) of the low level.

[0149] Due to the high level of the previous first polarity scan signal nSC(n-2) and the low level of the first p-type clock signal pCLK1, the voltage of the second driving node QB maintains a high level, and thus the ninth transistor M9 maintains a turned-off state.

[0150] At the third time t3, the third n-type clock signal nCLK3 of a high level is supplied.

[0151] The eighth transistor M8 maintains the on state, and the ninth transistor M9 maintains the off state. Therefore, the third n-type clock signal nCLK3 of a high level is output as the first polarity scan signal nSC(n) of a high level.

[0152] According to an exemplary embodiment, during a portion of the time, the gate-on voltage of the previous second polarity scan signal pSC(n-1) may overlap with the gate-on voltage of the third n-type clock signal nCLK3. The time at which the gate-on voltage of the previous second polarity scan signal pSC(n-1) is generated may precede the time at which the gate-on voltage of the third n-type clock signal nCLK3 is generated. That is, referring to Figure 7, it can be seen that the first falling pulse of the second polarity scan signal pSC(n-1) is generated at the second time t2, and the rising pulse of the third n-type clock signal nCLK3 is generated at the third time t3. That is, if the previous second polarity scan signal pSC(n-1) of the low level is not in a state of being supplied to the first drive node Q when the third n-type clock signal nCLK3 increases to a high level at the third time t3, the voltage of the first drive node Q may increase due to the combination with the first capacitor C1. Therefore, the eighth transistor M8 is turned off. Therefore, according to an exemplary embodiment, the voltage of the first drive node Q is prevented from being completely increased to the gate-on voltage at the third time t3, so that the on state of the eighth transistor M8 can be ensured.

[0153] At the fourth time t4, the third n-type clock signal nCLK3 of a low level is supplied.

[0154] The eighth transistor M8 is kept turned on, and the seventh transistor M7 is kept turned off. Therefore, the third n-type clock signal nCLK3 of low level is output to the output terminal OUT to serve as the first polarity scan signal nSC(n) of low level.

[0155] At the fourth time t4, the voltage of the first driving node Q becomes lower than a low level due to the combination with the first capacitor C1. Therefore, the eighth transistor M8 stably maintains a turned-on state, and the driving characteristics can be improved.

[0156] Although a voltage lower than the low level is applied to one electrode of the third transistor M3, the voltage of the other electrode of the third transistor M3 will not become lower than the low level. One electrode of the third transistor M3 can be connected to the first drive node Q, and the other electrode of the third transistor M3 can be connected to the first node N1. When a voltage lower than the low level is applied to one electrode of the third transistor M3 due to the combination with the first capacitor C1, the one electrode of the third transistor M3 is used as a drain electrode. Therefore, the other electrode of the third transistor M3 is used as a source electrode. In addition, since the low-level control signal PEN is applied to the gate electrode of the third transistor M3, a voltage higher than the low level will be applied to the source electrode of the third transistor M3, so that the third transistor M3 is turned on. Therefore, the third transistor M3 is turned off while the voltage of the source electrode of the third transistor M3 becomes lower than the low level.

[0157] Therefore, according to an exemplary embodiment, since the voltage of the other electrode of the third transistor M3 is maintained despite the combination with the first capacitor C1, a transient bias voltage is prevented from being applied to the second transistor M2, so that the life span of the second transistor M2 may be increased.

[0158] At the fifth time t5, the first transistor M1 and the tenth transistor M10 are turned on by the low-level first p-type clock signal pCLK1, and the low-level previous first polarity scan signal nSC(n-2) is supplied to the second driving node QB. Therefore, the fourth transistor M4, the seventh transistor M7, and the ninth transistor M9 whose gate electrodes are coupled to the second driving node QB are turned on.

[0159] When the ninth transistor M9 is turned on, the low level voltage of the second power source VGL is output to the output terminal OUT to serve as the first polarity scan signal nSC(n) of a low level.

[0160] When the seventh transistor M7 is turned on, the eighth transistor M8 is in a diode-coupled state. Therefore, the third n-type clock signal nCLK3 is not supplied to the output terminal OUT. In addition, when the fourth transistor M4 is turned on, the high level voltage of the second p-type clock signal pCLK2 is transmitted to the third node N3. In addition, the previous low level of the first polarity scan signal nSC(n-2) is supplied to the second drive node QB, and therefore, the potential difference between the two ends of the second capacitor C2 is set to a high level.

[0161] At the sixth time t6, the second p-type clock signal pCLK2 of a low level is supplied.

[0162] Since the fourth transistor M4 is in the on state, the low level voltage of the second p-type clock signal pCLK2 is supplied to one end of the second capacitor C2. One end of the second capacitor C2 can be connected to the third node N3, and the other end of the second capacitor C2 can be connected to the second node N2. Due to the combination with the second capacitor C2, the voltage of the second node N2 is reduced to a voltage lower than the low level. Therefore, the potential difference between the two ends of the second capacitor C2 can maintain a high level. Since the twelfth transistor M12 is diode-coupled due to the voltage of the second node N2, the change in the voltage of the second node N2 has no effect on the second drive node QB.

[0163] As described above, in an exemplary embodiment, the previous first polarity scan signal nSC(n-2) is supplied with a low level, and the previous second polarity scan signal pSC(n-1) is supplied with a high level, so that the potential difference between both ends of the second capacitor C2 is stably maintained while the first polarity scan signal nSC(n) is not output. Therefore, charging / discharging does not occur in the second capacitor C2, and thus, the power consumption of the display device can be reduced.

[0164] Figure 8 It is shown Figure 5 Graph of exemplary low frequency operation of the first stage shown in .

[0165] Reference Figure 2 , Figure 5 and Figure 8 In the second driving mode, the first frame in a period includes a data writing period WP and an emission period EP, and each of the other frames in a period includes a bias period BP and an emission period EP. The control signal PEN may maintain a gate-on voltage (low level) during the first frame in a period, and maintain a gate-off voltage (high level) during the other frames in the period.

[0166] In the first frame in which the control signal PEN maintains the gate-on voltage, the nth first stage ST1n may Figure 7 Therefore, the driving method in other frames will be described below.

[0167] When the control signal PEN having the gate-off voltage is supplied, the third transistor M3 of the nth first stage ST1n maintains the off state, and the first drive node Q continues to maintain the high level voltage. Therefore, the eighth transistor M8 maintains the off state, so in other frames during one period, the scan driver 30 does not output the activated first polarity scan signal nSC(n).

[0168] Therefore, the third transistor T3 and the fourth transistor T4 of the pixel PX remain in the off state in other frames during one period, so the storage capacitor Cst maintains the same data voltage during multiple frames. Specifically, the third transistor T3 and the fourth transistor T4 can be constructed with oxide semiconductor transistors, so leakage current can be minimized.

[0169] therefore, Figure 2 The pixel PX shown in FIG. 1 may display the same image during one period based on the data voltage supplied during the data writing period WP of the first frame in one period.

[0170] Fig. 9 It is shown Figure 5 FIG. 4 is a diagram of another exemplary embodiment of low frequency operation of the first stage shown in FIG.

[0171] Reference Figure 2 , Figure 5 and Fig. 9 , the control signal PEN maintains an on level during one period. The n-type clock signal nCLK outputs a pulse during a first frame in one period, and does not output a pulse in other frames in the one period.

[0172] Therefore, the third transistor M3 of the nth first stage ST1n maintains a turned-on state, and only the gate-off voltage is supplied to the eighth transistor M8 of the nth first stage ST1n. Therefore, the scan driver 30 does not output the activated first polarity scan signal nSC(n) in other frames.

[0173] Therefore, in other frames during one period, the third transistor T3 and the fourth transistor T4 of the pixel PX maintain the off state. Therefore, the pixel PX can display the same image during one period based on the data voltage supplied during the data writing period WP of the first frame in one period.

[0174] Fig.10 It is shown Figure 5 An exemplary timing diagram for low frequency operation of the first stage is shown in FIG. Fig.10 , an operation of the nth first stage ST1n in a frame including a bias period BP and an emission period EP after the first frame is shown.

[0175] Reference Fig.10 , shows an exemplary timing diagram of clock signals pCLK1, pCLK2, pCLK3, pCLK4 and nCLK3, control signal PEN, and scan signals pSC(n-1), nSC(n-2), pSC(n) and nSC(n). The horizontal synchronization signal Hsync is shown as a reference signal for timing. The interval between pulses of the horizontal synchronization signal Hsync may be referred to as one horizontal period.

[0176] The first p-type clock signal pCLK1 to the fourth p-type clock signal pCLK4 are constructed with the same square wave, and each of the first p-type clock signal pCLK1 to the fourth p-type clock signal pCLK4 may be a signal whose phase is delayed by 1 / 4 cycle. The third n-type clock signal nCLK3 may be a signal having a pulse of a polarity opposite to that of the third p-type clock signal pCLK3. Each of the clock signals pCLK1, pCLK2, pCLK3, pCLK4, and nCLK3 may have a high level portion set to be longer than a low level portion in one cycle (for example, 4H) constructed to have one square wave. Therefore, during one cycle, the high level portions of the first p-type clock signal pCLK1 to the fourth p-type clock signal pCLK4 may overlap each other at least once.

[0177] During the low frequency driving period, the control signal PEN maintains the gate cut-off voltage. Therefore, the third transistor M3 remains in the cut-off state during the low frequency driving period, and the previous second polarity scanning signal pSC(n-1) has no effect on the operation of the nth first stage ST1n. Therefore, Fig.10 The wavelength of the previous second polarity scanning signal pSC(n-1) is not shown.

[0178] At the first time t1, the previous first polarity scan signal nSC(n-2) of a high level is supplied.

[0179] The first transistor M1 and the tenth transistor M10 are turned on by the first p-type clock signal pCLK1, and the previous first polarity scan signal nSC(n-2) of a high level is supplied to the second driving node QB. Therefore, the fourth transistor M4, the seventh transistor M7, and the ninth transistor M9 whose gate electrodes are coupled to the second driving node QB are turned off.

[0180] Since the third transistor M3 is in the off state, the first drive node Q maintains the voltage of the previous period, for example, the voltage of the low level. Specifically, due to the combination with the first capacitor C1, the voltage of the first drive node Q is set to a voltage lower than the low level. When the voltage of the first drive node Q is set to a low level, the eighth transistor M8 is turned on, so that the low voltage of the third n-type clock signal nCLK3 can be output to the first polarity scan signal nSC(n).

[0181] At the first moment t1, the fifth transistor M5 is turned on by the fourth p-type clock signal pCLK4, and the high level voltage of the first power supply VGH is supplied to the third node N3. Since the tenth transistor M10 and the eleventh transistor M11 are in the on state, the previous first polarity scan signal nSC(n-2) is supplied to the second node N2, so that the second node N2 is set to a high level voltage. Therefore, the potential difference between the two ends of the second capacitor C2 is maintained at a high level.

[0182] At the second time t2, the third n-type clock signal nCLK3 of a high level is supplied.

[0183] The eighth transistor M8 remains in the on state, while the ninth transistor M9 remains in the off state. Therefore, according to the third n-type clock signal nCLK3, the first polarity scan signal nSC(n) still maintains a high level.

[0184] At the second time t2, the potential difference between both ends of the second capacitor C2 is maintained at a high level.

[0185] At the third time t3, the third n-type clock signal nCLK3 of a low level is supplied.

[0186] The eighth transistor M8 maintains the on state, and the ninth transistor M9 maintains the off state. Therefore, the third n-type clock signal nCLK3 of low level is output to the output terminal OUT to serve as the first polarity scan signal nSC(n) of low level.

[0187] At the third time t3, the voltage of the first driving node Q becomes lower than a low level due to the combination with the first capacitor C1. Therefore, the eighth transistor M8 stably maintains a turned-on state, and the driving characteristics can be improved.

[0188] At the third time t3, the potential difference between both ends of the second capacitor C2 is maintained at a high level.

[0189] At the fourth time t4, the first transistor M1 and the tenth transistor M10 are turned on by the low-level first p-type clock signal pCLK1, and the low-level previous first polarity scan signal nSC(n-2) is supplied to the second driving node QB. Therefore, the fourth transistor M4, the seventh transistor M7, and the ninth transistor M9 whose gate electrodes are coupled to the second driving node QB are turned on.

[0190] When the ninth transistor M9 is turned on, the low level voltage of the second power source VGL is output to the output terminal OUT, so that the first polarity scan signal nSC(n) maintains a low level.

[0191] When the seventh transistor M7 is turned on, the eighth transistor M8 is in a diode-coupled state. Therefore, the third n-type clock signal nCLK3 is not supplied to the output terminal OUT. In addition, when the fourth transistor M4 is turned on, the high level voltage of the second p-type clock signal pCLK2 is transmitted to the third node N3. In addition, the previous low level of the first polarity scan signal nSC(n-2) is supplied to the second drive node QB, and therefore, the potential difference between the two ends of the second capacitor C2 is maintained at a high level.

[0192] At the fifth time t5, the second p-type clock signal pCLK2 of a low level is supplied.

[0193] Since the fourth transistor M4 is in the on state, the low level voltage of the second p-type clock signal pCLK2 is supplied to one end of the second capacitor C2. Due to the combination with the second capacitor C2, the voltage of the second node N2 is reduced to a voltage lower than the low level. Therefore, the potential difference between the two ends of the second capacitor C2 can be maintained at a high level. Since the twelfth transistor M12 is diode-coupled due to the voltage of the second node N2, the change in the voltage of the second node N2 has no effect on the second driving node QB.

[0194] As described above, in the exemplary embodiment of the invention, the potential difference between both ends of the second capacitor C2 is stably maintained while the first polarity scan signal nSC(n) is not output. Therefore, charging / discharging does not occur in the second capacitor C2, and thus, the power consumption of the display device can be reduced.

[0195] Fig.11 yes Figure 3 A circuit diagram of a second exemplary embodiment of the first stage shown in FIG. Fig.11 In the drawings, the same reference numerals are used to represent Figure 5 The components are the same as those shown in , and their detailed descriptions will be omitted to avoid redundancy.

[0196] Reference Figure 3 , Figure 5 and Fig.11 , the first stage ST1a according to the second exemplary embodiment includes an input unit 111, an output unit 120, a first signal processor 130, a second signal processor 140, a third signal processor 150, and first and second stabilizers 161 and 162.

[0197] The input unit 111 controls the voltages of the first node N1, the second node N2 and the second driving node QB according to the signals supplied to the first input terminal IN1, the third input terminal IN3 and the second clock terminal CK2. To this end, the input unit 111 includes a first transistor M1, a second transistor M2, a tenth transistor M10, a thirteenth transistor M13 and a fourteenth transistor M14.

[0198] The first electrode of the first transistor M1 is coupled to the first input terminal IN1 to which the scan start signal SSP or the first polarity scan signal nSC(n-2) of the n-2 first stage ST1n-2 is applied, and the second electrode of the first transistor M1 is coupled to the second drive node QB via the sixth transistor M6. The gate electrode of the first transistor M1 is coupled to the second clock terminal CK2. When the first p-type clock signal pCLK1 is supplied to the second clock terminal CK2, the first transistor M1 is turned on to electrically couple the first input terminal IN1 to the second drive node QB.

[0199] The thirteenth transistor M13 and the fourteenth transistor M14 are coupled in series between a first power supply terminal V1 to which a voltage of the first power supply VGH is applied and a second power supply terminal V2 to which a voltage of the second power supply VGL is applied. A common node of the thirteenth transistor M13 and the fourteenth transistor M14 is referred to as a fourth node N4. The thirteenth transistor M13 is a p-type transistor, and the fourteenth transistor M14 is an n-type transistor.

[0200] The gate electrode of the thirteenth transistor M13 is coupled to the third input terminal IN3 to which the first polarity scan signal nSC(n-1) of the n-1th first stage ST1n-1 is applied. When a low voltage is supplied to the third input terminal IN3, the thirteenth transistor M13 is turned on to supply a high voltage to the fourth node N4.

[0201] A gate electrode of the fourteenth transistor M14 is coupled to the third input terminal IN3. When a high voltage is supplied to the third input terminal IN3, the fourteenth transistor M14 is turned on to supply a low voltage to the fourth node N4.

[0202] The second transistor M2 is diode-coupled between the fourth node N4 and the first node N1. The second transistor M2 may transmit a voltage of the fourth node N4 to the first driving node Q.

[0203] A first electrode of the tenth transistor M10 is coupled to the first input terminal IN1, and a second electrode of the tenth transistor M10 is coupled to the second node N2 via the eleventh transistor M11. A gate electrode of the tenth transistor M10 is coupled to the second clock terminal CK2. When a low-level first p-type clock signal pCLK1 is supplied to the second clock terminal CK2, the tenth transistor M10 is turned on to electrically couple the first input terminal IN1 to the second node N2.

[0204] As described above, in the second exemplary embodiment, the first polarity scan signal nSC(n-1) of the previous stage is inverted to be supplied to the fourth node N4 using the thirteenth transistor M13 and the fourteenth transistor M14 constituting an inverter. In addition to replacing the second polarity scan signal pSC(n-1) of the previous stage with the first polarity scan signal nSC(n-1) of the previous stage, Fig.11 The first stage ST1a shown in FIG. Figure 5 Therefore, a detailed description of the operation of the first stage ST1a will be omitted to avoid redundancy.

[0205] Fig.12 yes Figure 3 A circuit diagram of a third exemplary embodiment of the first stage shown in FIG. Fig.12 In the drawings, the same reference numerals are used to represent Figure 5 The components are the same as those shown in , and their detailed descriptions will be omitted to avoid redundancy.

[0206] Reference Figure 3 , Figure 5 and Fig.12 , the first stage ST1 b according to the third exemplary embodiment includes an input unit 110 , an output unit 120 , a first signal processor 130 , a second signal processor 140 , and a third signal processor 150 .

[0207] In the third exemplary embodiment, the first stage ST1b has the same structure as the first stabilizer 161 and the second stabilizer 162 except that the first stabilizer 161 and the second stabilizer 162 are omitted. Figure 5 Therefore, a detailed description of the operation of the first stage ST1b will be omitted to avoid redundancy.

[0208] Fig.13 yes Figure 3 A circuit diagram of a fourth exemplary embodiment of the first stage shown in FIG. Fig.13 In the drawings, the same reference numerals are used to represent Figure 5 The components are the same as those shown in , and their detailed descriptions will be omitted to avoid redundancy.

[0209] Reference Fig.13, the first stage ST1 c according to the fourth exemplary embodiment includes an input unit 110 , an output unit 120 , a second signal processor 140 , and a third signal processor 150 .

[0210] In the fourth exemplary embodiment, the first stage ST1c has the same configuration as that of the first signal processor 130, the first stabilizer 161, and the second stabilizer 162. Figure 5 The same structure as the first stage ST1n shown in FIG. Figure 5 Compared with the first stage ST1n shown in FIG. 1 , the first stage ST1c does not perform a low-frequency operation according to the control signal PEN.

[0211] Fig.14 yes Figure 3 A circuit diagram of a fifth exemplary embodiment of the first stage shown in FIG. Fig.14 In the drawings, the same reference numerals are used to represent Figure 5 The components are the same as those shown in , and their detailed descriptions will be omitted to avoid redundancy.

[0212] Reference Fig.14 The first stage ST1d according to the fifth exemplary embodiment includes an input unit 112, an output unit 121, a first signal processor 130, a second signal processor 141, a third signal processor 150, and first and second stabilizers 161 and 162.

[0213] The output unit 121 supplies the voltage of the first power source VGH or the second power source VGL to the output terminal OUT according to the voltages of the first driving node Q and the second driving node QB. To this end, the output unit 121 includes an eighth transistor M8 and a ninth transistor M9.

[0214] The eighth transistor M8 is coupled between the first clock terminal CK1 to which the second n-type clock signal nCLK2 is applied and the output terminal OUT. In addition, the gate electrode of the eighth transistor M8 is coupled to the first drive node Q. The eighth transistor M8 is turned on or off according to the voltage of the first drive node Q. When the eighth transistor M8 is turned on, the second n-type clock signal nCLK2 supplied to the output terminal OUT is output as the first polarity scan signal nSC(n) of the nth scan line Gn (e.g., the nth first scan line G1n and / or the nth second scan line G2n).

[0215] The ninth transistor M9 is coupled between the output terminal OUT and the second power source VGL. In addition, a gate electrode of the ninth transistor M9 is coupled to the second driving node QB. The ninth transistor M9 is turned on or off according to the voltage of the second driving node QB.

[0216] The input unit 112 controls voltages of the first node N1, the second node N2 and the second driving node QB in response to signals supplied to the first input terminal IN1, the third input terminal IN3 and the second clock terminal CK2. To this end, the input unit 112 includes a first transistor M1, a second transistor M2 and a tenth transistor M10.

[0217] The first electrode of the first transistor M1 is coupled to the first input terminal IN1 to which the scan start signal SSP or the first polarity scan signal nSC(n-1) of the n-1th first stage ST1n-1 is applied, and the second electrode of the first transistor M1 is coupled to the second drive node QB via the sixth transistor M6. The gate electrode of the first transistor M1 is coupled to the second clock terminal CK2. When the low-level first p-type clock signal pCLK1 is supplied to the second clock terminal CK2, the first transistor M1 is turned on to electrically couple the first input terminal IN1 to the second drive node QB.

[0218] The second transistor M2 is diode-coupled between the third input terminal IN3 to which the second polarity scan signal pSC(n) of the nth second stage ST2n is applied and the first node N1. The second transistor M2 may transmit the second polarity scan signal pSC(n) of the nth second stage ST2n supplied to the third input terminal IN3 to the first node N1.

[0219] A first electrode of the tenth transistor M10 is coupled to the first input terminal IN1, and a second electrode of the tenth transistor M10 is coupled to the second node N2 via the eleventh transistor M11. A gate electrode of the tenth transistor M10 is coupled to the second clock terminal CK2. When a low-level first p-type clock signal pCLK1 is supplied to the second clock terminal CK2, the tenth transistor M10 is turned on to electrically couple the first input terminal IN1 to the second node N2.

[0220] The second signal processor 141 is coupled to the second driving node QB and controls the voltage of the second driving node QB in response to signals supplied to the third clock terminal CK3 and the fourth clock terminal CK4. To this end, the second signal processor 141 includes a fourth transistor M4, a fifth transistor M5, a twelfth transistor M12 and a second capacitor C2.

[0221] The fifth transistor M5 and the fourth transistor M4 are coupled in series between the first power supply terminal V1 to which the voltage of the first power supply VGH is applied and the third clock terminal CK3 to which the second p-type clock signal pCLK2 is applied. A common node of the fifth transistor M5 and the fourth transistor M4 is referred to as a third node N3.

[0222] A gate electrode of the fifth transistor M5 is coupled to a fourth clock terminal CK4 to which the first p-type clock signal pCLK1 is applied. The fifth transistor M5 is turned on or off according to a signal supplied to the fourth clock terminal CK4.

[0223] A gate electrode of the fourth transistor M4 is coupled to the second node N2. The fourth transistor M4 is turned on or off according to a voltage of the second node N2.

[0224] The twelfth transistor M12 is diode-coupled between the second node N2 and the second driving node QB. The twelfth transistor M12 may electrically couple the second node N2 to the second driving node QB in response to a voltage of the second node N2.

[0225] The second capacitor C2 is coupled between the third node N3 and the second node N2. The second capacitor C2 charges a voltage corresponding to a gate-on voltage of the fourth transistor M4.

[0226] In the present embodiment, the first p-type clock signal pCLK1 and the second p-type clock signal pCLK2 may be replaced with separate signals provided from the outside.

[0227] Fig.15 It is shown Fig.14 An exemplary timing diagram of an exemplary driving method of the first stage is shown in FIG.

[0228] Reference Fig.15 , the pulse of the second n-type clock signal nCLK2 may have a polarity opposite to that of the pulse of the second p-type clock signal pCLK2. The pulse of the second n-type clock signal nCLK2 may be generated at a timing at which the pulse of the second p-type clock signal pCLK2 is generated, and the timing at which the pulse of the second n-type clock signal nCLK2 is generated may be further delayed than the timing at which the pulse of the second p-type clock signal pCLK2 is generated.

[0229] The pulse of the first p-type clock signal pCLK1 may have a polarity opposite to that of the pulse of the second n-type clock signal nCLK2. The pulse of the first p-type clock signal pCLK1 may not temporarily overlap with the pulse of the second n-type clock signal nCLK2.

[0230] The first power source VGH has a high level voltage, and the second power source VGL has a low level voltage. Therefore, in the driving method, the sixth transistor M6 having its gate electrode coupled to the second power source VGL is in a turned-on state, and therefore, description of the transistor M6 will be omitted except for special cases.

[0231] The control signal PEN maintains the gate-on voltage. Therefore, the third transistor M3 remains turned on during the high-frequency driving period.

[0232] First, at the 1b time t1b, the first polarity scan signal nSC(n-1) of the (n-1)th first stage ST1n-1 having a high level is supplied.

[0233] Since the first transistor M1 is turned on by the low level first p-type clock signal pCLK1, the high level n-1th first polarity scan signal nSC(n-1) is supplied to the second driving node QB. Therefore, the transistors M4, M9 and M12 whose gate electrodes are coupled to the second driving node QB are turned off.

[0234] Since the second transistor M2 is in a diode-connected state, the direction of the current does not flow from one electrode of the second transistor M2 (as the source electrode) toward the other electrode of the second transistor M2 (as the drain electrode). Therefore, at the 1b time t1b, the high-level second polarity scan signal pSC(n) is not transmitted to the first driving node Q. Therefore, the first driving node Q maintains the voltage of the previous period.

[0235] At the 2b time t2b, the second polarity scan signal pSC(n) of a low level and the second p-type clock signal pCLK2 of a low level are supplied.

[0236] Therefore, the voltage of the first driving node Q becomes low level according to the low level second polarity scan signal pSC(n), and the eighth transistor M8 is turned on. Therefore, the low level second n-type clock signal nCLK2 is output as the low level first polarity scan signal nSC(n).

[0237] Although the low level n-1th first polarity scan signal nSC(n-1) is supplied, the first transistor M1 is turned off by the high level first p-type clock signal pCLK1, so the voltage of the second driving node QB remains high. Therefore, the ninth transistor M9 is turned off.

[0238] At the 3b time t3b, the second n-type clock signal nCLK2 of a high level is supplied.

[0239] The eighth transistor M8 maintains the on state, and the ninth transistor M9 maintains the off state. Therefore, the high-level second n-type clock signal nCLK2 is output as the high-level first polarity scan signal nSC(n).

[0240] At the 4b time t4b, the second n-type clock signal nCLK2 of a low level is supplied.

[0241] The eighth transistor M8 is kept in the on state, and the ninth transistor M9 is kept in the off state. Therefore, the second n-type clock signal nCLK2 of the low level is output as the first polarity scan signal nSC(n) of the low level.

[0242] The voltage of the first driving node Q becomes lower than a low level due to the combination with the first capacitor C1. Therefore, the eighth transistor M8 stably maintains a turned-on state, and driving characteristics can be improved.

[0243] At the 5b time t5b, the first p-type clock signal pCLK1 of a low level is supplied.

[0244] Since the n-1th first polarity scan signal nSC(n-1) of a low level is supplied, the voltage of the second driving node QB becomes a low level. Therefore, the transistors M4, M7, and M9 whose gate electrodes are coupled to the second driving node QB are turned on.

[0245] When the ninth transistor M9 is turned on, a low-level voltage is output as the low-level first polarity scan signal nSC(n).

[0246] When the seventh transistor M7 is turned on, the eighth transistor M8 is diode-coupled. Therefore, although the second n-type clock signal nCLK2 of a high level is subsequently supplied, a voltage of a high level is not output.

[0247] When the fourth transistor M4 is turned on, the second p-type clock signal pCLK2 of a high level is applied to one electrode of the second capacitor C2.

[0248] At the sixth time t6b, the second p-type clock signal pCLK2 of a low level is supplied.

[0249] Since the fourth transistor M4 is in the on state, the second p-type clock signal pCLK2 is supplied to one electrode of the second capacitor C2, and the voltage of the second driving node QB becomes lower than the low level due to the combination with the second capacitor C2. Therefore, the ninth transistor M9 stably maintains the on state, and the driving characteristics can be improved.

[0250] In the stages and scan drivers constructed according to the principles and exemplary embodiments of the invention, the scan driver may supply a scan signal to activate an N-type transistor.

[0251] Furthermore, in the stages and scan drivers constructed according to the principles and exemplary embodiments of the invention, the stages prevent charging and discharging of capacitors provided in the stages while the scan signals maintain a low voltage, so that power consumption of the display device can be reduced.

[0252] Although specific exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements that will be apparent to those of ordinary skill in the art.

Claims

1. A stage for a scan driver of a display device, the stage comprising: an output unit that outputs a signal supplied to the first clock terminal to the output terminal according to the voltage of the first driving node or outputs a voltage of the second power supply to the output terminal according to the voltage of the second driving node; an input unit that controls the voltage of the first driving node according to a signal supplied to a first input terminal, the input unit being configured to control the voltage of the second driving node according to a signal supplied to a second input terminal and a second clock terminal; a first signal processor that controls the voltage of the second driving node according to signals supplied to a third clock terminal and a fourth clock terminal; as well as a second signal processor that controls the voltage of the first driving node according to the signal supplied to the first clock terminal, Among them, the first signal processor includes: a ninth transistor, coupled between the first power supply and the third node, the ninth transistor having a gate electrode coupled to the fourth clock terminal; a tenth transistor, coupled between the third node and the third clock terminal, the tenth transistor having a gate electrode coupled to the first node; an eleventh transistor, a diode coupled between the first node and the second driving node; and a first capacitor, coupled between the first node and the third node, the potential difference between the two ends of the first capacitor being controllable according to the signal supplied to the fourth clock terminal.

2. The stage according to claim 1, wherein: The input unit comprises: a first transistor coupled between the second input terminal and the second driving node, the first transistor having a gate electrode coupled to the second clock terminal; a second transistor diode-coupled between the first input terminal and the first drive node; and A third transistor is coupled between the second input terminal and the first signal processor, the third transistor having a gate electrode coupled to the second clock terminal. 3 . The stage of claim 2 , further comprising a third signal processor coupled between the input unit and the first driving node to control the voltage of the first driving node.

4. The stage according to claim 3, wherein: The third signal processor includes a fourth transistor coupled between the second transistor and the first driving node, the fourth transistor having a gate electrode coupled to a third input terminal operable to receive a control signal.

5. The stage according to claim 4, wherein: The control signal is supplied as a gate-on voltage of the fourth transistor during a high frequency driving mode, and is supplied as a gate-off voltage of the fourth transistor in at least one frame during a low frequency driving mode to perform biasing.

6. The stage according to claim 3, further comprising: a first stabilizer, coupled between the first signal processor and the second driving node, the first stabilizer controlling a voltage drop of the second driving node; as well as A second stabilizer is coupled between the input unit and the first signal processor, and controls a voltage drop of a first node in the first signal processor.

7. The stage according to claim 6, wherein: The first stabilizer includes a fifth transistor coupled between the first transistor and the second driving node, the fifth transistor having a gate electrode operable to receive a voltage from the second power supply.

8. The stage according to claim 6, wherein: The second stabilizer includes a sixth transistor coupled between the third transistor and the first node, the sixth transistor having a gate electrode operable to receive a voltage from the second power supply.

9. The stage of claim 1, wherein: The input unit comprises: a first transistor coupled between the second input terminal and the second driving node, the first transistor having a gate electrode coupled to the second clock terminal; a second transistor, diode-coupled between a second node and the first driving node; a third transistor coupled between the second input terminal and the first signal processor, the third transistor having a gate electrode coupled to the second clock terminal; a seventh transistor coupled between a first power source and the second node, the seventh transistor having a gate electrode coupled to the first input terminal; and an eighth transistor coupled between the second node and the second power supply, the eighth transistor having a gate electrode coupled to the first input terminal, Wherein, the seventh transistor is a p-type transistor, and the eighth transistor is an n-type transistor.

10. The stage according to claim 9, wherein: When the voltage of the second power supply is output to the output terminal, the potential difference between the two ends of the first capacitor is kept constant.

11. The stage according to claim 2, wherein: The output terminal is operable to output a scanning signal having a first polarity, The second input terminal is operable to receive a scan signal of the previous stage having the first polarity, and The first input terminal is operable to receive a scan signal of the previous stage having a second polarity, The first polarity and the second polarity are opposite to each other.

12. A scan driver including a plurality of stages for supplying scan signals to scan lines of a display device, the scan driver comprising: A first stage array having a plurality of first stages for providing a scan signal of a first polarity to the scan line; as well as A second stage array having a plurality of second stages for providing a scan signal of a second polarity to the scan line, Wherein, at least one of the plurality of first levels comprises: an output unit that outputs a signal supplied to the first clock terminal to the output terminal according to the voltage of the first driving node or outputs a voltage of the second power supply to the output terminal according to the voltage of the second driving node; an input unit that controls the voltage of the first driving node according to a signal supplied to a first input terminal, the input unit being configured to control the voltage of the second driving node according to a signal supplied to a second input terminal and a second clock terminal; a first signal processor that controls the voltage of the second driving node according to signals supplied to a third clock terminal and a fourth clock terminal; and a second signal processor that controls the voltage of the first driving node according to the signal supplied to the first clock terminal, Among them, the first signal processor includes: a ninth transistor, coupled between the first power supply and the third node, the ninth transistor having a gate electrode coupled to the fourth clock terminal; a tenth transistor, coupled between the third node and the third clock terminal, the tenth transistor having a gate electrode coupled to the first node; an eleventh transistor, a diode coupled between the first node and the second driving node; and a first capacitor, coupled between the first node and the third node, the potential difference between the two ends of the first capacitor being controllable according to the signal supplied to the fourth clock terminal.

13. The scan driver according to claim 12, wherein: The input unit comprises: a first transistor coupled between the second input terminal and the second driving node, the first transistor having a gate electrode coupled to the second clock terminal; a second transistor diode-coupled between the first input terminal and the first drive node; and A third transistor is coupled between the second input terminal and the first signal processor, the third transistor having a gate electrode coupled to the second clock terminal.

14. The scan driver according to claim 13, further comprising: A third signal processor is coupled between the input unit and the first driving node to control the voltage of the first driving node.

15. The scan driver according to claim 14, wherein: The third signal processor includes a fourth transistor coupled between the second transistor and the first driving node, the fourth transistor having a gate electrode coupled to a third input terminal operable to receive a control signal.

16. The scan driver according to claim 15, wherein: The control signal is supplied as a gate-on voltage of the fourth transistor during a high frequency driving mode, and is supplied as a gate-off voltage of the fourth transistor in at least one frame during a low frequency driving mode to perform biasing.

17. The scan driver according to claim 14, further comprising: a first stabilizer coupled between the first signal processor and the second drive node, the first stabilizer being operable to control an amount of voltage drop at the second drive node; as well as A second stabilizer is coupled between the input unit and the first signal processor, the second stabilizer being operable to control an amount of voltage drop at the first node in the first signal processor.

18. The scan driver according to claim 17, wherein: The first stabilizer includes a fifth transistor coupled between the first transistor and the second driving node, the fifth transistor having a gate electrode supplied with a voltage of the second power source, and The second stabilizer includes a sixth transistor coupled between the third transistor and the first node, the sixth transistor having a gate electrode operable to receive a voltage from the second power supply.

19. The scan driver according to claim 12, wherein: The input unit comprises: a first transistor coupled between the second input terminal and the second driving node, the first transistor having a gate electrode coupled to the second clock terminal; a second transistor, diode-coupled between a second node and the first driving node; a third transistor coupled between the second input terminal and the first signal processor, the third transistor having a gate electrode coupled to the second clock terminal; a seventh transistor coupled between a first power source and the second node, the seventh transistor having a gate electrode coupled to the first input terminal; and an eighth transistor coupled between the second node and the second power supply, the eighth transistor having a gate electrode coupled to the first input terminal, Wherein, the seventh transistor is a p-type transistor, and the eighth transistor is an n-type transistor.

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