A display device including connection wirings in a display area of the display device

Abstract

A display device including connection wirings in a display area of the display device is disclosed. The display device includes: a substrate having a display area, a peripheral area, and a pad area, the peripheral area at least partially surrounding the display area, and the pad area being within the peripheral area. A plurality of data lines are provided in the display area. A plurality of connection wirings are provided in the display area, connected to the plurality of data lines, and configured to transmit data signals from the pad area to the plurality of data lines. Each of the plurality of connection wirings includes a plurality of branches protruding from the connection wiring in a direction perpendicular to the direction along which the connection wiring mainly extends.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-0003283, filed with the Korean Intellectual Property Office on January 10, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a display device, and more particularly, to a display device including connection wirings in a display area of the display device. Background Art

[0003] As display devices have become larger, the size of the non-display area surrounding the display area has decreased. Although this has resulted in a display device with a modern appearance, there is less available space for arranging a driving circuit and wirings for driving pixels of the display device, which have conventionally been arranged along the non-display area. Summary of the Invention

[0004] A display device includes: a substrate having a display area, a peripheral area, and a pad area, the peripheral area at least partially surrounding the display area, and the pad area being within the peripheral area. A plurality of data lines are disposed in the display area. A plurality of connection wirings are disposed in the display area, connected to the plurality of data lines, and configured to transmit data signals from the pad area to the plurality of data lines. Each of the plurality of connection wirings includes a plurality of branches protruding from the connection wiring in a direction perpendicular to a direction in which the connection wiring mainly extends.

[0005] A display device includes: a substrate having a display area, a peripheral area, and a pad area, the peripheral area at least partially surrounding the display area, and the pad area being within the peripheral area. A plurality of data lines are disposed in the display area. A plurality of connection wirings are disposed in the display area, connected to the plurality of data lines, and configured to transmit data signals supplied from the pad area to the plurality of data lines. The display area includes a first area and a second area, in the first area the plurality of connection wirings extend in a first direction, and in the second area the plurality of connection wirings extend in a second direction perpendicular to the first direction. Brief Description of the Drawings

[0006] A more complete understanding of the present disclosure and many of its attendant aspects will become clear and more readily appreciated by reference to the following description of embodiments in conjunction with the accompanying drawings, in which:

[0007] Figure 1 is a plan view showing a display device according to an exemplary embodiment of the present disclosure;

[0008] Figure 2 is showing Figure 1 a first example of part A;

[0009] Figure 3 is a plan view showing a first example of part B of Figure 1 ;

[0010] Figure 4 is a plan view showing a second example of part A of Figure 1 ;

[0011] Figure 5 is a plan view showing a second example of part B of Figure 1 ;

[0012] Figure 6 is a plan view showing a third example of part A of Figure 1 ;

[0013] Figure 7 is a plan view showing a third example of part B;

[0014] Figure 8 is an equivalent circuit diagram of one pixel of a display device according to an exemplary embodiment of the present disclosure of Figure 1 ;

[0015] Figure 9 is a layout diagram showing the positions of thin film transistors (TFTs) and capacitors in a pixel included in a display device according to an exemplary embodiment of the present disclosure in Figure 1 ;

[0016] Figures 10 to 14 is a layout diagram showing components (such as Figure 9 multiple TFTs and capacitors) shown according to layers; and

[0017] Figure 15 is a cross-sectional view of a part of a display device according to an exemplary embodiment of the present disclosure of Figure 1 ; DETAILED DESCRIPTION

[0018] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals may denote like elements throughout the specification and the drawings. In this regard, the present embodiments may have forms different from those set forth herein.

[0019] It will be understood that although the terms “first,” “second,” etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another.

[0020] It will also be understood that the terms “comprising” and / or “including” used herein indicate the presence of the stated features or components, but do not preclude the presence or addition of one or more other features or components. In contrast, the phrase “consisting of” excludes the addition of unlisted features or components.

[0021] It will be understood that when a layer, region, or component is referred to as being "formed on" another layer, region, or component, the layer, region, or component may be directly or indirectly formed on the other layer, region, or component. For example, there may be an intermediate layer, region, or component.

[0022] For ease of explanation, the dimensions of elements in the drawings may be exaggerated.

[0023] Hereinafter, embodiments of the present disclosure will be described in more detail below with reference to the drawings. Regardless of the figure numbers, the same or corresponding components are given the same reference numerals.

[0024] Figure 1 is a plan view showing a display device according to an exemplary embodiment of the present disclosure.

[0025] Referring to Figure 1 , a display device 10 according to an exemplary embodiment of the present disclosure may include a display area AA in which an image is displayed and a peripheral area PA outside the display area AA and at least partially surrounding the display area AA. Accordingly, the substrate 100 has the display area AA and the peripheral area PA.

[0026] A plurality of pixels PX and wirings for applying an electrical signal to the plurality of pixels PX may be provided in the display area AA.

[0027] Each of the plurality of pixels PX may include a light-emitting device and a circuit portion for driving the light-emitting device. According to an exemplary embodiment of the present disclosure, the light-emitting device may be an organic light-emitting device, and in addition to various other supporting elements, the circuit portion may further include a plurality of transistors and capacitors.

[0028] The wirings for applying an electrical signal to the plurality of pixels PX may include a plurality of scan lines SL and a plurality of data lines DL. According to an exemplary embodiment of the present disclosure, the plurality of scan lines SL may be arranged in a plurality of rows and may transmit a scan signal to the pixels PX, the plurality of data lines DL may be arranged in a plurality of columns, and may transmit a data signal to the pixels PX. The plurality of pixels PX may be provided at portions where the plurality of scan lines SL and the plurality of data lines DL cross each other.

[0029] Connection wirings 200 for transmitting an electrical signal supplied from a pad (also referred to as a bonding pad or a solder pad) area PADA to the wirings connected to the pixels PX may be provided in the display area AA. For example, the connection wirings 200 may be connected to the data lines DL and may transmit the data signal supplied from the pad area PADA to the data lines DL.

[0030] In addition, since the length of the side of the display area AA adjacent to the pad area PADA (e.g., the horizontal side of the display area AA as shown (i.e., the side along the second direction Y)) is greater than the length of the pad area PADA (e.g., the bottom side of the pad area PADA as shown), the connection wiring 200 must be extended widely to correspond to the side of the display area AA at the position corresponding to the pad area PADA. For this purpose, as Figure 1 shown in, the connection wiring 200 can extend in the first direction X, can be bent in a direction parallel to the second direction Y perpendicular to the first direction X, can extend toward the edge of the display area AA, and then can be bent in a direction parallel to the first direction X and can extend in the first direction X. Therefore, the data signal supplied from the center of one side of the display area AA can be transmitted from the end of one side of the display area AA to the data line DL. Therefore, compared with the fan-out wiring in the peripheral area PA according to the prior art, the area of the peripheral area PA can be reduced, so that the invalid space of the display device 10 can be reduced.

[0031] In addition, the display area AA can be divided into a plurality of areas according to the extending direction of the connection wiring 200. For example, the display area AA can include a first area S1 in which the connection wiring 200 extends in a direction parallel to the first direction X, a second area S2 in which the connection wiring 200 extends in a direction parallel to the second direction Y, and a third area S3 which is the remaining area of the display area AA except for the first area S1 and the second area S2. The third area S3 can be an area in which the connection wiring 200 is not provided.

[0032] There can be a plurality of first areas S1 and a plurality of second areas S2, and each of the plurality of first areas S1 and the plurality of second areas S2 can have a substantially triangular shape. For example, in order to prevent a short circuit between the connection wirings 200, the extending length of the connection wiring 200 extending from the middle part of the center (first area S1) and in the first direction X can be greater than the extending length of the connection wiring 200 extending from the edge of the first area S1 and in the first direction X. Therefore, the entire shape of the first area S1 can be a triangular shape. In addition, since the connection wiring 200 can be bent in a direction parallel to the second direction Y and can extend from the center (first area S1), the shape of the second area S2 on both sides of the center (first area S1) can be an inverted triangular shape, and the connection wiring 200 can be bent in the X direction and can extend from the second area S2. Therefore, the first area S1 outside the second area S2 can have a triangular shape.

[0033] In the first region S1 and the second region S2, the extending directions of the connection wirings 200 are different from each other. Since the connection wirings 200 can reflect light, the reflection characteristics in the first region S1 and the second region S2 can be different from each other, and this difference can be obvious to a user who is viewing the display device 10. As a result, the division at the junction of the first region S1 and the second region S2 within the display region AA can be recognized by the user. To reduce or prevent this phenomenon, the connection wirings 200 can include a plurality of branches protruding in a direction perpendicular to the extending direction of the connection wirings 200. Therefore, the first region S1 and the second region S2 can include the same or similar patterns. Accordingly, the difference in the reflection characteristics between the first region S1 and the second region S2 can be reduced. A description will be made hereinafter with reference to Figures 2 to 7 this.

[0034] The peripheral region PA can at least partially surround the display region AA. The peripheral region PA, which is a region where no pixel PX is provided, can include a pad region PADA to which various electronic devices or a printed circuit board (PCB) is electrically attached. A voltage line for supplying power for driving the light-emitting device can also be provided in the peripheral region PA.

[0035] Figure 1 It can be understood as showing a plan view of the substrate 100 during the manufacturing process of the display device 10. In an electronic device (such as a finished display device 10 or a smart phone including the display device 10), a part of the substrate 100 can be bent backward or behind the display region AA of the electronic device so as to minimize the perceivable area of the peripheral region PA.

[0036] For example, as Figure 1 shown, the peripheral region PA can include a bending region BA, and the bending region BA can be defined between the pad region PADA and the display region AA. In this case, the substrate 100 can be bent in the bending region BA such that at least a part of the pad region PADA can at least partially overlap with the display region AA. In this case, the bending direction of the pad region PADA is set such that the pad region PADA can be behind the display region AA. Accordingly, to a user, the display region AA can seem to constitute most of the display device 10. For this purpose, the substrate 100 can include various flexible / bendable materials.

[0037] Figure 2 is a plan view showing an example of part A of Figure 1 , Figure 3 is a plan view showing an example of part B of Figure 1 . Hereinafter, exemplary embodiments of the present disclosure will be described with reference to Figures 1 to 3 this.

[0038] Referring to Figures 1 to 3, each connection wiring 200 may include a plurality of branches 211 (e.g., Figure 2 ) and 221 (e.g., Figure 3 ) that protrude in a direction perpendicular to the length direction of the connection wiring 200. Hereinafter, for ease of description, the display area will be divided into a first area S1 and a second area S2.

[0039] As Figure 2 shown, in the first area S1, the connection wiring 200 may extend in a direction parallel to the first direction X, and the first area S1 may include first branches 211 that protrude in the second direction Y.

[0040] The first branches 211 protrude symmetrically from the connection wiring 200. For example, the first branches 211 protrude from the connection wiring 200 extending in the first direction X in both side directions perpendicular to the length direction of the connection wiring 200. In addition, a pair of first branches 211 protruding toward each other from two adjacent connection wirings 200 arranged in parallel in the first area S1 may be provided in the same line. Thus, as Figure 2 shown, in the first area S1, two adjacent connection wirings 200 and the first branches 211 protruding toward each other may divide the first unit pattern A1. However, in order to prevent a short circuit between the connection wirings 200, the ends of the first branches 211 extending from two adjacent connection wirings 200 toward each other are spaced apart from each other.

[0041] In addition, as Figure 3 shown, in the second area S2, the connection wiring 200 may extend in a direction parallel to the second direction Y, and the second area S2 may include second branches 221 that protrude in the first direction X.

[0042] The second branches 221 protrude symmetrically from the connection wiring 200 extending in the second direction Y. In addition, a pair of second branches 221 protruding toward each other from two adjacent connection wirings 200 in the second area S2 may be provided in the same line. Thus, as Figure 3 shown, in the second area S2, two adjacent connection wirings 200 and the second branches 221 protruding toward each other from two adjacent connection wirings 200 may divide the second unit pattern A2. However, in order to prevent a short circuit between the connection wirings 200, the ends of the second branches 221 extending from two adjacent connection wirings 200 toward each other are spaced apart from each other.

[0043] Therefore, a first unit pattern A1 in the first region S1 and a second unit pattern A2 in the second region S2 may have similar shapes. For example, there is only such a difference: in the first unit pattern A1, a gap is formed between the first branches 211 extending towards each other, and in the second unit pattern A2, a gap is formed between the second branches 221 extending towards each other. The first unit pattern A1 and the second unit pattern A2 may have the same area, and the total length of the connection wiring 200 and the first branches 211 surrounding the first unit pattern A1 may be the same as the total length of the connection wiring 200 and the second branches 221 surrounding the second unit pattern A2.

[0044] Therefore, the light reflection characteristics in the first region S1 and the second region S2 are similar to each other. Therefore, the phenomenon in which the display region is divided into the first region S1 and the second region S2 according to the incident angle of light and is recognized can be prevented or minimized.

[0045] The third region S3 may include the first unit pattern A1 or / and the second unit pattern A2. Therefore, the phenomenon in which a viewer may be able to distinguish the third region S3 from the first region S1 and the second region S2 can be prevented. For example, since the third region S3 is in contact with and continuous with the second region S2 having an inverted triangular shape, when the third region S3 includes the second unit pattern A2, the phenomenon in which a viewer may be able to distinguish the third region S3 from the first region S1 and / or the second region S2 can be more effectively prevented.

[0046] When the third region S3 includes the first unit pattern A1 or / and the second unit pattern A2, the first unit pattern A1 and / or the second unit pattern A2 included in the third region S3 may be in a floating state.

[0047] The first dummy pattern 230 and the second dummy pattern 240 may also be provided in the first unit pattern A1 and the second unit pattern A2. The first dummy pattern 230 and the second dummy pattern 240 may be provided between two adjacent connection wirings 200 and are provided in the same layer as the layer in which the connection wiring 200 is provided. In Figure 2 and Figure 3 the first dummy pattern 230 and the second dummy pattern 240 are respectively provided in the first unit pattern A1 and the second unit pattern A2. However, the present invention is not limited thereto, and dummy patterns having various numbers and shapes can be used. The dummy patterns 230 and 240 can prevent signal interference between the circuit portion and the connection wiring 200, and can ensure the pattern density so that the device can be manufactured more easily.

[0048] Figure 4 is a plan view showing another example of part A of Figure 1 and Figure 5 is a plan view showingFigure 1 Another example of part B of the Figure 1 . Figure 4 And Figure 5 will be described below.

[0049] Referring to Figure 1 , Figure 4 and Figure 5 , each connection wiring 200 may include a plurality of branches 211 and 221 protruding in a direction perpendicular to the length direction of the connection wiring 200. As shown in Figure 4 , the connection wiring 200 extending from the first region S1 in the first direction X may include a first branch 211 protruding in the second direction Y, and as shown in Figure 5 , the connection wiring 200 extending from the second region S2 in the second direction Y may include a second branch 221 protruding in the first direction X, so that the light reflection characteristics in the first region S1 and the second region S2 may be similar to each other, and the phenomenon in which the display region is visibly divided into the first region S1 and the second region S2 can be prevented or minimized. Therefore, only the differences from the above description shown in Figure 4 and Figure 5 will be described, and it should be understood that in terms of omitting details for some elements, those elements may be at least similar to the corresponding elements that have been described. In addition, for ease of description, the display region will be divided into a first region S1 and a second region S2.

[0050] Referring to Figure 4 and Figure 5 , in the first region S1, a gap may be formed between the first branches 211 extending from two adjacent connection wirings 200 towards each other. In the second region S2, a gap may be formed between the second branches 221 extending from two adjacent connection wirings 200 towards each other. In this case, a first covering pattern 213 covering the gap between the first branches 211 may also be provided in the first region S1, and a second covering pattern 223 covering the gap between the second branches 221 may also be provided in the second region S2.

[0051] For example, the first covering pattern 213 may at least partially overlap with the ends of the first branches 211 facing each other in the first direction X (i.e., in the same direction as the extension direction of the connection wiring 200), and may be spaced apart from the ends of the first branches 211 facing each other to prevent short - circuiting of two adjacent connection wirings 200. In addition, the first covering pattern 213 may be connected to the first dummy pattern 230 or the second dummy pattern 240 to fix the position of the first covering pattern 213. In Figure 4In the drawing, based on the drawing, the first covering pattern 213 may be disposed at a position lower than the position of the first branch 211 and may be connected to the first dummy pattern 230. However, the present invention is not limited thereto. Based on the drawing, the first covering pattern 213 may be disposed at a position higher than the position of the first branch 211 and may be connected to the second dummy pattern 240.

[0052] Similarly, as Figure 5 shown in the drawing, the second covering pattern 223 may at least partially overlap with the end of the second branch 221 in the second direction Y (i.e., in the same direction as the extending direction of the connection wiring 200), and may be spaced apart from the end of the second branch 221 to prevent short - circuiting of two adjacent connection wirings 200. In addition, the second covering pattern 223 may be connected to the first dummy pattern 230 or the second dummy pattern 240 to fix the position of the second covering pattern 223.

[0053] In this way, when the first covering pattern 213 overlapping with the end of the first branch 211 is also provided in the first region S1 and the second covering pattern 223 overlapping with the end of the second branch 221 is also provided in the second region S2, the shapes of the patterns included in the first region S1 and the second region S2 may be more similar to each other. Therefore, it is possible to prevent the phenomenon that when the positions of the gaps between the first branches 211 in the first region S1 and the positions of the gaps between the second branches 221 in the second region S2 are different from each other, the reflectance of incident light at a specific angle may be different from each other. Therefore, it is possible to more effectively prevent the phenomenon in which the display region may be divided into the first region S1 and the second region S2 and recognized. The first covering pattern 213 and the second covering pattern 223 may be provided in the same layer as the layer in which the connection wiring 200 is provided.

[0054] Figure 6 is a plan view showing Figure 1 another example of part A of Figure 7 is a plan view showing another example of part B. Hereinafter, reference will be made to Figure 1 、 Figure 6 and Figure 7 to describe this.

[0055] Referring to Figure 1 、 Figure 6 and Figure 7, each connection wiring 200 may include a plurality of first branches 211 and second branches 221 protruding in a direction perpendicular to the length direction of the connection wiring 200. In addition, each connection wiring 200 may include a plurality of first slices 201 and second slices 202, as well as a plurality of bridging members 250 and 252. The plurality of first slices 201 and second slices 202 are separated from each other in a direction parallel to the extending direction of the connection wiring 200, and the plurality of bridging members 250 and 252 electrically connect the plurality of slices 201 and 202 to each other (for example, the bridging member 250 connects the slice 201 to the slice 201, and the bridging member 252 connects the slice 202 to the slice 202). In this case, the plurality of first branches 211 and second branches 221 may protrude from the plurality of slices 201 and 202, respectively. Hereinafter, for convenience of description, the display area will be divided into a first area S1 and a second area S2.

[0056] First, as Figure 6 shown, each connection wiring 200 extending in the first direction X in the first area S1 may include a plurality of first slices 201 separated from each other in the first direction X, and a plurality of first bridging members 250 electrically connecting the plurality of first slices 201. The plurality of first bridging members 250 may be disposed in a layer different from the layer in which the plurality of first slices 201 are disposed, and may be electrically connected to the first slices 201 via contact holes C.

[0057] In addition, as Figure 7 shown, each connection wiring 200 extending in the second direction Y may include a plurality of second slices 202 in the second area S2, and the plurality of second slices 202 may be electrically connected to each other via a plurality of second bridging members 252 through contact holes C.

[0058] As Figure 6 shown, a pair of first branches 211 may protrude from each of the plurality of first slices 201 in opposite directions, and a dummy bridging member may at least partially overlap with the ends of a pair of first branches 211 extending toward each other. The dummy bridging member in the first area S1 may be the same as the second bridging member 252. However, the first bridging member 250 may be electrically connected to the first slice 201 via the contact hole C, while the second bridging member 252 serving as a dummy bridging member is not connected to the first branch 211 and may be in an insulating state. For this purpose, an insulating layer may be provided between the ends of the second bridging member 252 and the ends of a pair of first branches 211. Therefore, it is possible to prevent the connection wirings 200 extending in the first direction X in the first area S1 from being short-circuited to each other via the first branches 211.

[0059] In addition, each of the plurality of second segments 202 may include a second branch 221 protruding from the second segment 202 in a direction perpendicular to the second direction Y, and a dummy bridging member may be provided at a position where the dummy bridging member overlaps with ends of a pair of second branches 221 extending toward each other. The first bridging member 250 may be the dummy bridging member in the second region S2. The first bridging member 250 as the dummy bridging member is not connected to the second branch 221 and may be in an insulating state. Accordingly, it is possible to prevent the connection wirings 200 extending in the second direction Y from being short-circuited to each other via the second branch 221.

[0060] For example, the first bridging member 250 is provided at the same position in the first region S1 and the second region S2 and the second bridging member 252 is provided at the same position in the first region S1 and the second region S2. However, in the first region S1, only the first bridging member 250 may be electrically connected to the first segment 201 via the contact hole C, and the second bridging member 252 is a dummy bridging member. On the other hand, in the second region S2, only the second bridging member 252 may be electrically connected to the second segment 202 via the contact hole C, and the first bridging member 250 is a dummy bridging member. Accordingly, the first region S1 and the second region S2 include patterns having the same shape. Accordingly, the reflection characteristics in the first region S1 and the second region S2 may be the same, and thus it is possible to prevent a phenomenon in which the display region is visibly divided into the first region S1 and the second region S2.

[0061] The first bridging member 250 and the second bridging member 252 may be provided on the connection wiring 200. The first bridging member 250 and the second bridging member 252 may be formed of a transparent material (such as indium tin oxide (ITO)) or an opaque material. According to an exemplary embodiment of the present disclosure, the first bridging member 250 and the second bridging member 252 may also be provided below the connection wiring 200. According to an exemplary embodiment of the present disclosure, the first bridging member 250 and the second bridging member 252 may be provided in the same layer in which source electrodes and drain electrodes of thin film transistors (TFTs) to be described later are provided, or in the same layer in which gate electrodes of the TFTs are provided.

[0062] A description of a third region S3 including a pattern identical to the pattern of the first region S1 or the second region S2 is the same as the above description.

[0063] Figure 8 is Figure 1 an equivalent circuit diagram of one pixel of a display device. As Figure 8As shown, a pixel PX may include a plurality of TFTs T1, T2, T3, T4, T5, T6, and T7, a capacitor Cst, and an organic light-emitting device OLED. The plurality of TFTs T1, T2, T3, T4, T5, T6, and T7 or the capacitor Cst may be included in the circuit portion of the pixel PX. The circuit portion is electrically connected to a plurality of signal lines 121, 122, 123, 124, and 171 and a power supply line 172.

[0064] The TFTs may include a driving TFT T1, a switching TFT T2, a compensating TFT T3, an initializing TFT T4, an operation control TFT T5, an emission control TFT T6, and a bypass TFT T7.

[0065] The plurality of signal lines may include a scan line 121 for transmitting a scan signal Sn, a previous scan line 122 for transmitting a previous scan signal Sn-1 to the initializing TFT T4 and the bypass TFT T7, an emission control line 123 for transmitting an emission control signal En to the operation control TFT T5 and the emission control TFT T6, a data line 171 intersecting with the scan line 121 and transmitting a data signal Dm, and an initialization voltage line 124 for transmitting an initialization voltage Vint for initializing the driving TFT T1.

[0066] The driving TFT T1 receives the data signal Dm according to the switching operation of the switching TFT T2 and supplies a driving current I OLED to the organic light-emitting device OLED. The gate electrode G1 of the driving TFT T1 may be connected to the capacitor lower electrode Cst1 of the capacitor Cst. The source electrode S1 of the driving TFT T1 may pass through the operation control TFT T5 and may be connected to the power supply line 172. The drain electrode D1 of the driving TFT T1 may pass through the emission control TFT T6 and may be electrically connected to the pixel electrode of the organic light-emitting device OLED.

[0067] The gate electrode G2 of the switching TFT T2 may be connected to the scan line 121. The source electrode S2 of the switching TFT T2 may be connected to the data line 171. The drain electrode D2 of the switching TFT T2 may be connected to the source electrode S1 of the driving TFT T1, may pass through the operation control TFT T5, and may be connected to the power supply line 172. The switching TFT T2 may be turned on according to the scan signal Sn transmitted via the scan line 121 and may perform a switching operation of transmitting the data signal Dm transmitted to the data line 171 to the source electrode S1 of the driving TFT T1.

[0068] The gate electrode G3 of the compensation TFT T3 can be connected to the scan line 121. The source electrode S3 of the compensation TFT T3 can be connected to the drain electrode D1 of the driving TFT T1, can pass through the emission control TFT T6, and can be connected to the pixel electrode of the organic light emitting device OLED. The drain electrode D3 of the compensation TFT T3 can be connected to the capacitor lower electrode Cst1 of the capacitor Cst, the drain electrode D4 of the initialization TFT T4, and the gate electrode G1 of the driving TFT T1. The compensation TFT T3 can be turned on according to the scan signal Sn transmitted via the scan line 121, and can electrically connect the gate electrode G1 of the driving TFT T1 to the drain electrode D1, so that the driving TFT T1 is diode-connected.

[0069] The gate electrode G4 of the initialization TFT T4 can be connected to the previous scan line 122. The source electrode S4 of the initialization TFT T4 can be connected to the drain electrode D7 of the bypass TFT T7 and the initialization voltage line 124. The drain electrode D4 of the initialization TFT T4 can be connected to the capacitor lower electrode Cst1 of the capacitor Cst, the drain electrode D3 of the compensation TFT T3, and the gate electrode G1 of the driving TFT T1. The initialization TFT T4 can be turned on according to the previous scan signal Sn-1 transmitted via the previous scan line 122, and can perform an initialization operation of transmitting the initialization voltage Vint to the gate electrode G1 of the driving TFT T1 and initializing the voltage of the gate electrode G1 of the driving TFT T1.

[0070] The gate electrode G5 of the operation control TFT T5 can be connected to the emission control line 123. The source electrode S5 of the operation control TFT T5 can be connected to the power supply line 172. The drain electrode D5 of the operation control TFT T5 can be connected to the source electrode S1 of the driving TFT T1 and the drain electrode D2 of the switch TFT T2.

[0071] The gate electrode G6 of the emission control TFT T6 can be connected to the emission control line 123. The source electrode S6 of the emission control TFT T6 can be connected to the drain electrode D1 of the driving TFT T1 and the source electrode S3 of the compensation TFT T3. The drain electrode D6 of the emission control TFT T6 can be electrically connected to the source electrode S7 of the bypass TFT T7 and the pixel electrode of the organic light emitting device OLED. The operation control TFT T5 and the emission control TFT T6 can be turned on simultaneously according to the emission control signal En transmitted via the emission control line 123, and can allow the driving voltage ELVDD to be transmitted to the organic light emitting device OLED, so that the driving current I OLED can flow through the organic light emitting device OLED.

[0072] The gate electrode G7 of the bypass TFT T7 can be connected to the previous scan line 122. The source electrode S7 of the bypass TFT T7 can be connected to the drain electrode D6 of the emission control TFT T6 and the pixel electrode of the organic light-emitting device OLED. The drain electrode D7 of the bypass TFT T7 can be connected to the source electrode S4 of the initialization TFT T4 and the initialization voltage line 124. The bypass TFT T7 receives a previous scan signal Sn-1 transmitted via the previous scan line 122 from the gate electrode G7. When an electrical signal with a voltage at a specific level is applied from the previous scan signal Sn-1, the bypass TFT T7 can be in an off state, such that current I d in some can be discharged as a bypass current I bp through the bypass TFT T7, where the bypass TFT T7 is cut off at the specific level.

[0073] Even when the minimum current for driving the TFT T1 to display a black image flows as a driving current and the organic light-emitting device OLED emits light, it may not be possible to correctly display the black image. Here, the minimum current of the driving TFT T1 represents a current having such a condition: under the condition, the gate-source voltage VGS of the driving TFT T1 is less than the threshold voltage Vth and the driving TFT T1 is cut off. Therefore, even when the minimum current flows as a driving current, in order to prevent the organic light-emitting device OLED from emitting light, the bypass TFT T7 can also disperse some of the current I d flowing out of the driving TFT T1 as a bypass current I bp along other current paths rather than the current path towards the organic light-emitting device OLED. Under the condition that the driving TFT T1 is cut off, a current smaller than the minimum driving current (for example, a current equal to or less than 10 pA) can be transmitted to the organic light-emitting device OLED, such that the organic light-emitting device OLED may not emit light or may minimize the degree of emission, thereby enabling a black image to be achieved.

[0074] In Figure 8 , the initialization TFT T4 and the bypass TFT T7 are connected to the previous scan line 122. However, the present invention is not limited thereto. According to an exemplary embodiment of the present disclosure, the initialization TFT T4 can be connected to the previous scan line 122 and can be driven according to the previous scan signal Sn-1, and the bypass TFT T7 can be connected to an additional wiring and can be driven according to the signal transmitted to the wiring.

[0075] The capacitor upper electrode Cst2 of the capacitor Cst can be connected to the power supply line 172, and the counter electrode of the organic light-emitting device OLED can be connected to the common voltage ELVSS. Therefore, the organic light-emitting device OLED can receive a driving current I OLED from the driving TFT T1 and can emit light.

[0076] In Figure 8 , the compensation TFT T3 and the initialization TFT T4 have dual gate electrodes. However, the present invention is not limited thereto. For example, the compensation TFT T3 and the initialization TFT T4 may have one gate electrode. In addition, various other modifications may be made to at least one of the remaining TFTs T1, T2, T5, T6, and T7.

[0077] Figure 9 is a layout diagram showing the positions of thin film transistors (TFTs) and capacitors in pixels included in the Figure 1 display device, Figures 10 to 14 is a layout diagram showing the layers of elements (such as Figure 9 multiple TFTs and capacitors), Figure 15 is a cross-sectional view showing a part of the Figure 1 display device.

[0078] Hereinafter, the detailed structure of the Figures 9 to 15 display device will be described with reference to Figure 1 .

[0079] Figure 9 shows the positions of the TFTs and capacitors in each of the first pixel PX1 in the first region (see S1 in Figure 1 ) and the second pixel PX2 in the second region (see S2 in Figure 1 ). Figures 10 to 14 Shows various elements according to layers, such as the TFTs and capacitors in each of the first pixel PX1 and the second pixel PX2. In addition, for convenience, Figure 1 as a cross-sectional view of a part of the Figure 15 display device Figure 14 shows a cross-sectional view taken along line I-I', and line I-I' passes through the opening OP indicated only in the first pixel PX1 of

[0080] As Figure 15 shown, the display device includes a substrate 100.

[0081] The substrate 100 may include various flexible or bendable materials. For example, the substrate 100 may include polymer resins such as polyethersulfone (PES), polyacrylate (PA), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate (PAR), polyimide (PI), polycarbonate (PC), and / or cellulose acetate propionate (CAP). It should be understood that the substrate 100 may be modified in various ways, such as being modified to have a multilayer structure including two layers and a barrier layer between the two layers, the two layers including such polymer resins, and the barrier layer including an inorganic material (silicon oxide (SiOx )), silicon nitride (SiN x ) and / or silicon oxynitride (SiON)).

[0082] A plurality of pixels including a first pixel PX1 and a second pixel PX2 may be disposed on a substrate 100. A buffer layer 101 may be disposed on the substrate 100. The buffer layer 101 may planarize the surface of the substrate 100 and / or may prevent impurities from penetrating into the semiconductor layer thereon. The buffer layer 101 may have a single-layer structure or a multi-layer structure including an inorganic insulating material (such as SiO x , SiN x and / or SiON).

[0083] The semiconductor layer may be disposed on the buffer layer 101. The semiconductor layer may have various curved shapes. As shown in Figure 10 , the first pixel PX1 and the second pixel PX2 may have semiconductor layers with the same shape. Hereinafter, unless otherwise specified, it may be assumed that the layers of each of the first pixel PX1 and the second pixel PX2 have the same shape.

[0084] The semiconductor layer may include a driving channel region 131a corresponding to the driving TFT T1, a switching channel region 131b corresponding to the switching TFT T2, compensation channel regions 131c1, 131c2, and 131c3 corresponding to the compensation TFT T3, initialization channel regions 131d1, 131d2, and 131d3 corresponding to the initialization TFT T4, an operation control channel region 131e corresponding to the operation control TFT T5, an emission control channel region 131f corresponding to the emission control TFT T6, and a bypass channel region 131g corresponding to the bypass TFT T7. For example, the driving channel region 131a, the switching channel region 131b, the compensation channel regions 131c1, 131c2, and 131c3, the initialization channel regions 131d1, 131d2, and 131d3, the operation control channel region 131e, the emission control channel region 131f, and the bypass channel region 131g may be Figure 10 some of the regions of the semiconductor layer shown in

[0085] The semiconductor layer may include polysilicon. The semiconductor layer may include source regions and drain regions formed by doping impurities on both sides of the channel region. Here, the impurities may vary according to the type of TFT and may include N-type impurities or P-type impurities. The channel region, the source region on one side of the channel region, and the drain region on the other side of the channel region may be collectively referred to as the active layer. For example, the TFT may have an active layer, and the active layer may include a channel region, a source region, and a drain region.

[0086] The source region or drain region formed by doping may be interpreted as the source electrode or drain electrode of the TFT. For example, the driving source electrode may correspond to the one in Figure 10The driving source region 176a doped with impurities near the driving channel region 131a in the semiconductor layer shown in Figure 10 The driving drain region 177a doped with impurities near the driving channel region 131a in the semiconductor layer shown in. In addition to the driving source region 176a and the driving drain region 177a, Figure 9 and Figure 10 also show the source regions 176b, 176c, 176d, 176e, 176f and 176g and the drain regions 177b, 177c, 177d, 177e, 177f and 177g of the TFTs T2 to T7.

[0087] The gate insulating layer 320 formed of an inorganic insulating material (such as SiO x , SiN x or SiON) may be provided on the semiconductor layer.

[0088] A conductive layer such as the gate electrode 125a is provided on the gate insulating layer 320. Various other conductive layers may be provided on the gate insulating layer 320. In this way, the various conductive layers provided on the gate insulating layer 320 may be referred to as gate wirings. As Figure 11 shown in, the gate wiring may include a scan line 121, a previous scan line 122, an emission control line 123, and a capacitor lower electrode.

[0089] The capacitor Cst may at least partially overlap with the driving TFT T1. In this case, the capacitor lower electrode may be the gate electrode 125a of the driving TFT T1. Therefore, the areas of the capacitor Cst and the driving TFT T1 can be increased, and high-quality images can be provided. However, the present invention is not limited thereto. According to an exemplary embodiment of the present disclosure, the capacitor Cst may not overlap with the driving TFT T1, and the capacitor lower electrode may be an independent element separate from the gate electrode 125a of the driving TFT T1.

[0090] As Figure 11 shown in, the switch gate electrode 125b and the compensation gate electrodes 125c1 and 125c2 (collectively referred to as the compensation gate electrode 125c) may be a portion of the scan line 121 that intersects the semiconductor layer or a portion protruding from the scan line 121, the initialization gate electrodes 125d1 and 125d2 (collectively referred to as the initialization gate electrode 125d) and the bypass gate electrode 125g may be a portion of the previous scan line 122 that intersects the semiconductor layer or a portion protruding from the previous scan line 122, and the operation control gate electrode 125e and the emission control gate electrode 125f may be a portion of the emission control line 123 that intersects the semiconductor layer or a portion protruding from the emission control line 123.

[0091] The first interlayer insulating layer 331 may cover the gate wiring. The first interlayer insulating layer 331 may be formed of an inorganic insulating material (such as SiN x , SiO x and / or SiON).

[0092] The capacitor upper electrode 127 may be disposed on the first interlayer insulating layer 331. However, the initialization voltage line 124 may be disposed in the same layer as the layer in which the capacitor upper electrode 127 is disposed.

[0093] As Figure 12 shown, the opening 27 may be formed in the capacitor upper electrode 127. Accordingly, the capacitor lower electrode and the compensation drain region 177c of the compensation TFT T3 may be electrically connected to each other using the connection member 174 described later.

[0094] The second interlayer insulating layer 332 is disposed on the capacitor upper electrode 127. The second interlayer insulating layer 332 may be formed of an inorganic insulating material (such as SiN x , SiO x and / or SiON).

[0095] The power supply line 172 may be disposed on the second interlayer insulating layer 332. The power supply line 172 may be connected to the capacitor upper electrode 127 via the contact hole 168 formed in the second interlayer insulating layer 332, and may be connected to the semiconductor layer therebelow via the contact holes 165 and 169 formed in the gate insulating layer 320, the first interlayer insulating layer 331, and the second interlayer insulating layer 332.

[0096] Various conductive layers other than the power supply line 172 may be disposed on the second interlayer insulating layer 332. For example, as Figure 13 shown, the data line 171, the initialization connection line 173, the connection member 174, and the drain electrode 175 may be formed on the second interlayer insulating layer 332.

[0097] The data line 171 may be connected to the switch source region 176b via the contact hole 164 formed in the gate insulating layer 320, the first interlayer insulating layer 331, and the second interlayer insulating layer 332.

[0098] One end of the initialization connection line 173 may be connected to the initialization voltage line 124 via the contact hole 161 formed in the second interlayer insulating layer 332. The other end of the initialization connection line 173 may be connected to the initialization source region 176d via the contact holes 162 formed in the gate insulating layer 320, the first interlayer insulating layer 331, and the second interlayer insulating layer 332. The initialization drain region 177d may be a portion of the semiconductor layer in which impurities are doped on the opposite side of the initialization source region 176d based on the initialization channel regions 131d1, 131d2, and 131d3.

[0099] One end of the connection member 174 may be connected to the compensation drain region 177c and the initialization drain region 177d via contact holes 166 formed in the gate insulating layer 320, the first interlayer insulating layer 331, and the second interlayer insulating layer 332. The other end of the connection member 174 may be connected to the capacitor lower electrode via contact hole 167 formed in the first interlayer insulating layer 331 and the second interlayer insulating layer 332. In this case, the other end of the connection member 174 may be connected to the capacitor lower electrode via an opening 27 formed in the capacitor upper electrode 127.

[0100] The drain electrode 175 may be connected to the emission control drain region 177f via contact holes 163 formed in the gate insulating layer 320, the first interlayer insulating layer 331, and the second interlayer insulating layer 332. The drain electrode 175 may be electrically connected to the pixel electrode 410. Source electrodes other than the drain electrode 175 may be disposed on the second interlayer insulating layer 332.

[0101] The first organic insulating layer 341 may be disposed on the power line 172 and the drain electrode 175. As Figure 14 shown, the connection wiring 200 and the dummy patterns 230 and 240 may be formed on the first organic insulating layer 341. In addition, the second organic insulating layer 342 may be disposed on the connection wiring 200 and the dummy patterns 230 and 240.

[0102] Each of the first organic insulating layer 341 and the second organic insulating layer 342 may include imide-based polymers, general polymers (such as polymethyl methacrylate (PMMA) or polystyrene (PS)), polymer derivatives having a phenol group, acrylic polymers, aryl ether polymers, amide polymers, fluorine (F)-based polymers, parylene-based polymers, vinyl alcohol polymers, and mixtures thereof.

[0103] The connection wiring 200 and the dummy patterns 230 and 240 may have a single-layer structure or a multi-layer structure including aluminum (Al), copper (Cu), titanium (Ti), and / or their alloys.

[0104] In the first pixel PX1, the connection wiring 200 extends in a direction parallel to the first direction X. For example, the connection wiring 200 may at least partially overlap with the power line 172. In one example, the first branch 211 protruding from the connection wiring 200 in a direction perpendicular to the length direction of the connection wiring 200 may at least partially overlap with the initialization voltage line 124.

[0105] In the second pixel PX2, the connection wiring 200 may extend in a direction parallel to the second direction Y, and the second branch 221 may protrude from the connection wiring 200. For example, in the second pixel PX2, the connection wiring 200 may at least partially overlap with the initialization voltage line 124, and the second branch 221 may at least partially overlap with the power supply line 172.

[0106] Accordingly, the pattern formed by the connection wiring 200 and the first branch 211 in the first pixel PX1 and the pattern formed by the connection wiring 200 and the second branch 221 in the second pixel PX2 are similar to each other. Accordingly, it is possible to prevent or minimize a phenomenon in which the display area may be divided into a first area S1 and a second area S2 according to the incident angle of light and recognized.

[0107] As described above, the first dummy pattern 230 and the second dummy pattern 240 may prevent signal interference between the circuit portion and the connection wiring 200 and ensure the pattern density, thereby providing a simplified manufacturing process.

[0108] In Figure 14 reference is made to Figure 2 and Figure 3 the connection wiring 200 and related structures described. However, the display device may include the connection wiring 200 and related structures described with reference to Figures 4 to 7 reference is made to

[0109] The light-emitting device 400 may be disposed on the second organic insulating layer 342, wherein the light-emitting device 400 may include a pixel electrode 410, a common electrode 430, and an intermediate layer 420 disposed between the pixel electrode 410 and the common electrode 430 and including an emission layer. For example, the light-emitting device 400 may be an organic light-emitting device.

[0110] The pixel electrode 410 may be a (semi) transparent electrode (i.e., a transparent electrode or a semi-transparent electrode) or a reflective electrode. For example, when the pixel electrode 410 is a (semi) transparent electrode, the pixel electrode 410 may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and / or AZO. When the pixel electrode 410 is a reflective electrode, the pixel electrode 410 may include a reflective layer and a layer formed of ITO, IZO, ZnO, In2O3, IGO, or AZO, the reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and / or a compound thereof. The present invention is not limited thereto, and the pixel electrode 410 may include various materials, and the pixel electrode 410 may be differently modified, such as being modified to have a single-layer structure or a multi-layer structure.

[0111] The pixel defining layer 350 for covering the edge of the pixel electrode 410 may be disposed on the second organic insulating layer 342. The pixel defining layer 350 may have an opening OP corresponding to each pixel (i.e., an opening OP through which at least the center of the pixel electrode 410 is exposed), thereby defining the pixel. In addition, the pixel defining layer 350 increases the distance between the edge of the pixel electrode 410 and the common electrode 430, thereby preventing arcing between them. The pixel defining layer 350 may be formed of an organic material such as polyimide or hexamethyldisiloxane (HMDSO).

[0112] The intermediate layer 420 may be formed on the pixel electrode 410 exposed through the opening OP of the pixel defining layer 350. The intermediate layer 420 may include a small molecular weight material or a polymer material. When the intermediate layer 420 includes a small molecular weight material, the intermediate layer 420 may have a structure in which a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL) are stacked in a single or composite structure. The intermediate layer 420 may include various organic materials including copper phthalocyanine (CuPc), N,N'-bis(naphthalen-1-yl)-N,N'-diphenyl-benzidine (NPB), and tris(8-hydroxyquinoline) aluminum (Alq3). These layers may be formed by a method such as vacuum deposition.

[0113] When the intermediate layer 420 includes a polymer material, the intermediate layer 420 may have a structure mainly including an HTL and an EML. In this case, the HTL may include poly(3,4-ethylenedioxythiophene) (PEDOT), and the EML may include a poly(phenylene vinylene) (PPV) - type polymer material and a polyfluorene - type polymer material. The structure of the intermediate layer 420 is not limited to the above description, and the intermediate layer 420 may have various different structures. For example, the intermediate layer 420 may include a layer formed integrally on a plurality of pixel electrodes 410, or may include a patterned layer corresponding to each of the plurality of pixel electrodes 410.

[0114] The common electrode 430 may cover the display area (see Figure 1AA). For example, the common electrode 430 may be formed as a single body to cover a plurality of light emitting devices 400. The common electrode 430 may be a (semi)transparent electrode or a reflective electrode. When the common electrode 430 is a (semi)transparent electrode, the common electrode 430 may have a layer formed of a metal having a small work function (e.g., Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg) (or another material having a work function within the range established by the above materials) and / or its compound, and a (semi)transparent conductive layer (such as ITO, IZO, ZnO, or In2O3). When the common electrode 430 is a reflective electrode, the common electrode 430 may have a layer formed of Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, and / or its compound. The configuration and material of the common electrode 430 are not limited thereto, and various modifications can be made.

[0115] As described above, since the connection wiring for transmitting data signals to the data lines is provided within the display area, the ineffective space of the display device can be reduced. In addition, the light reflection characteristics are the same or similar throughout the display area. Therefore, the phenomenon in which the area where the connection wiring is provided becomes visible can be prevented.

[0116] Although various exemplary embodiments of the present disclosure have been described herein with reference to the accompanying drawings, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure.

Claims

1. A display device, the display device comprising: a substrate including a display area, a peripheral area, and a pad area, the peripheral area at least partially surrounding the display area, the pad area being within the peripheral area; a plurality of data lines disposed in the display area; and a plurality of connection wirings disposed in the display area, connected to the plurality of data lines, and configured to transmit data signals from the pad area to the plurality of data lines, wherein each of the plurality of connection wirings includes a plurality of branches protruding from the plurality of connection wirings in a direction perpendicular to a direction along which the plurality of connection wirings mainly extend, and wherein the display area includes a first area and a second area, in the first area the plurality of connection wirings extend in a first direction, and in the second area the plurality of connection wirings extend in a second direction perpendicular to the first direction.

2. The display device according to claim 1, wherein, The plurality of connection wirings are arranged parallel to each other, a pair of branches protruding from two adjacent connection wirings among the plurality of connection wirings protrude toward each other and are located in the same line, and ends of the pair of branches are separated from each other.

3. The display device according to claim 2, wherein the display device further includes a covering pattern that at least partially overlaps with the ends of the pair of branches in a direction that is the same as the direction of the main extension of the plurality of connection wirings, where The covering pattern is separated from the ends of the pair of branches in the same direction as the direction along which the plurality of connection wirings mainly extend, and is located in the same layer as the layer in which the plurality of connection wirings are disposed.

4. The display device according to claim 3, the display device further comprising a dummy pattern, the dummy pattern being disposed between two adjacent connection wirings among the plurality of connection wirings in the same layer as the layer in which the plurality of connection wirings are disposed.

5. The display device according to claim 4, wherein, The covering pattern is connected to the dummy pattern.

6. The display device according to claim 2, wherein, Each of the plurality of connection wirings includes a plurality of segments and a plurality of bridge members, the plurality of segments being separated from each other in the direction along which the plurality of connection wirings mainly extend, the plurality of bridge members electrically connecting each of the plurality of segments to each other.

7. The display device according to claim 6, wherein, The plurality of branches protrude from the plurality of segments, the display device further comprising a dummy bridge member, the dummy bridge member at least partially overlapping with the ends of the pair of branches in a direction perpendicular to a direction along which the ends of the pair of branches mainly extend.

8. The display device according to claim 7, wherein, An insulating layer is disposed between the dummy bridge member and the ends of the pair of branches.

9. The display device according to claim 1, wherein, The display area further includes a third area, the third area being a remaining area of the display area other than the first area and the second area.

10. The display device according to claim 9, wherein, Two adjacent connection wirings among the plurality of connection wirings and the plurality of branches extending toward each other from the two adjacent connection wirings define a first unit pattern in the first area, two adjacent connection wirings among the plurality of connection wirings and the plurality of branches extending toward each other from the two adjacent connection wirings define a second unit pattern in the second area, the second unit pattern having the same area as the first unit pattern, the third area includes the first unit pattern or the second unit pattern, and the first unit pattern or the second unit pattern included in the third area is in a floating state.

11. A display device, the display device comprising: a substrate including a display area, a peripheral area, and a pad area, the peripheral area at least partially surrounding the display area, the pad area being within the peripheral area; a plurality of data lines disposed in the display area; and a plurality of connection wirings disposed in the display area, connected to the plurality of data lines, and configured to transmit data signals supplied from the pad area to the plurality of data lines, wherein the display area includes a first area and a second area, in the first area the plurality of connection wirings extend in a first direction, in the second area the plurality of connection wirings extend in a second direction perpendicular to the first direction, and each of the plurality of connection wirings extends in a positive direction of the first direction and bends in the second direction, and each of the plurality of connection wirings that bends in the second direction extends in a negative direction of the first direction.

12. The display device according to claim 11, wherein, In the first area, each of the plurality of connection wirings includes a plurality of first branches extending from the plurality of connection wirings in the second direction, in the second area, each of the plurality of connection wirings includes a plurality of second branches extending from the plurality of connection wirings in the first direction.

13. The display device according to claim 12, wherein, The plurality of first branches extending toward each other from two adjacent connection wirings among the plurality of connection wirings are disposed in the same line in the first area, the plurality of second branches extending toward each other from two adjacent connection wirings among the plurality of connection wirings are disposed in the same line in the second area.

14. The display device according to claim 13, wherein, The two adjacent connection wirings and the plurality of first branches extending toward each other from the two adjacent connection wirings define a first unit pattern in the first area, the two adjacent connection wirings and the plurality of second branches extending toward each other from the two adjacent connection wirings define a second unit pattern in the second area, and each of the first unit patterns and each of the second unit patterns have equal areas.

15. The display device according to claim 14, wherein, The display area further includes a third area, the third area being a remaining area of the display area other than the first area and the second area, wherein the third area includes the first unit pattern or the second unit pattern, and the first unit pattern or the second unit pattern included in the third area is in a floating state.

16. The display device according to claim 13, wherein, The first area further includes a first covering pattern, the first covering pattern at least partially overlapping with ends of the plurality of first branches extending toward each other in the first direction, the second area further includes a second covering pattern, the second covering pattern overlapping with ends of the plurality of second branches protruding toward each other in the second direction.

17. The display device according to claim 13, wherein, In the first area, each of the plurality of connection wirings includes a plurality of first segments and a plurality of bridge members, the plurality of first segments being spaced apart from each other in the first direction, the plurality of bridge members electrically connecting the plurality of first segments to each other.

18. The display device according to claim 17, wherein, The plurality of first branches protrude from the plurality of first segments, and the display device further includes dummy bridge members that at least partially overlap the ends of the plurality of first branches in a direction perpendicular to the main extending direction of the ends of the plurality of first branches.

19. The display device according to claim 13, wherein, In the second region, each of the plurality of connection wirings includes a plurality of second segments and a plurality of bridge members, the plurality of second segments are spaced apart from each other in the second direction, and the plurality of bridge members electrically connect the plurality of second segments to each other.

20. The display device according to claim 19, wherein, The plurality of second branches protrude from the plurality of second segments, and the display device further includes dummy bridge members that overlap the ends of the plurality of second branches in a direction perpendicular to the main extending direction of the ends of the plurality of second branches.

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