Display device

Abstract

A display device may include: a substrate in which an opening is defined; a first disconnection line disposed on the substrate, the first disconnection line extending along a first direction and including a first disconnection portion and a second disconnection portion, and the first disconnection portion and the second disconnection portion being disconnected from each other by the opening; and a first bypass line disposed in a layer different from the first disconnection line on the substrate, the first bypass line bypassing the opening and connecting the first disconnection portion and the second disconnection portion to each other.

Description

Technical Field

[0001] Embodiments relate to a display device. More particularly, embodiments relate to a display device having an aperture defined within a display area. Background Art

[0002] Display devices generally include, for example, liquid crystal displays (LCDs), plasma display panels (PDPs), organic light emitting diode (OLED) devices, field emission displays (FEDs), and electrophoretic display devices.

[0003] OLED devices generally include two electrodes and an organic emission layer disposed therebetween. In the organic emission layer, electrons injected from one electrode and holes injected from the other electrode recombine to form excitons, and the excitons emit light through energy emission.

[0004] OLED devices have a self-emitting characteristic and may not include discrete light sources typically included in LCDs, such that the thickness and weight of OLED devices may be less than those of LCDs. In addition, due to desirable characteristics of OLED devices, such as low power consumption, high brightness, and high response speed, OLED devices have drawn attention as next-generation display devices.

[0005] Recently, display devices having a wider display area and a narrow bezel area that is outside the display area have been developed. Summary of the Invention

[0006] Embodiments provide a display device that reduces a dead zone.

[0007] Embodiments of a display device include: a substrate having an aperture defined therein; a first disconnection line disposed on the substrate, the first disconnection line extending along a first direction and including a first disconnection portion and a second disconnection portion, and the first disconnection portion and the second disconnection portion being disconnected from each other by the aperture; and a first bypass line disposed in a layer different from the first disconnection line on the substrate, the first bypass line bypassing the aperture and connecting the first disconnection portion and the second disconnection portion to each other.

[0008] In an embodiment, the first bypass line may include: a first bypass portion extending along a second direction that intersects the first direction, the first bypass portion being connected to the first disconnection portion; a second bypass portion extending along the second direction, the second bypass portion being connected to the second disconnection portion; and a third bypass portion extending along the first direction, the third bypass portion connecting the first bypass portion and the second bypass portion.

[0009] In an embodiment, the display device may further include: a connection line disposed in the same layer as the first disconnection line on the substrate, the connection line extending along a first direction and not being disconnected by an opening. In this embodiment, the third bypass portion may overlap with the connection line.

[0010] In an embodiment, the connection line may transmit a DC voltage.

[0011] In an embodiment, the first disconnection line may be a scan line, an emission control line, or an initialization voltage line.

[0012] In an embodiment, the display device may further include: a second disconnection line disposed in a layer different from the first disconnection line on the substrate, the second disconnection line extending along a second direction intersecting the first direction and including a third disconnection portion and a fourth disconnection portion, and the third disconnection portion and the fourth disconnection portion being disconnected from each other by an opening; and a second bypass line disposed in a layer different from the second disconnection line on the substrate, the second bypass line bypassing the opening and connecting the third disconnection portion and the fourth disconnection portion to each other.

[0013] In an embodiment, the second bypass line may include: a fourth bypass portion extending along the first direction, the fourth bypass portion being connected to the third disconnection portion; a fifth bypass portion extending along the first direction, the fifth bypass portion being connected to the fourth disconnection portion; and a sixth bypass portion extending along the second direction, the sixth bypass portion connecting the fourth bypass portion and the fifth bypass portion to each other.

[0014] In an embodiment, the display device may further include: a connection line disposed in the same layer as the second disconnection line on the substrate, the connection line extending along the second direction and not being disconnected by an opening. In this embodiment, the sixth bypass portion may overlap with the connection line.

[0015] In an embodiment, the connection line may transmit a DC voltage.

[0016] In an embodiment, the second disconnection line may be a data line or a driving voltage line.

[0017] In an embodiment, the second bypass line may be disposed in the same layer as the first bypass line on the substrate.

[0018] In an embodiment, the length of the second bypass line may be greater than the length of the first bypass line.

[0019] In an embodiment, the display device may further include: a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, and a third conductive layer sequentially stacked one on top of another on the substrate. In this embodiment, the first conductive layer may include the first disconnection line, and the third conductive layer may include the first bypass line.

[0020] In an embodiment, the second conductive layer may include a second disconnection line, and the third conductive layer may further include a second bypass line.

[0021] An embodiment of a display device includes: a substrate in which an opening is defined; a first line disposed on the substrate, the first line extending along a first direction and including a first disconnection line and a first connection line, the first disconnection line being disconnected by the opening, and the first connection line not being disconnected by the opening; and a first bypass line disposed in a layer different from the first line on the substrate, the first bypass line bypassing the opening and connecting the first disconnection line.

[0022] In an embodiment, the first disconnection line may include a first disconnection portion and a second disconnection portion spaced apart from each other, the opening being between the first disconnection portion and the second disconnection portion, and the first bypass line may include: a first bypass portion extending along a second direction intersecting the first direction, the first bypass portion being connected to the first disconnection portion; a second bypass portion extending along the second direction, the second bypass portion being connected to the second disconnection portion; and a third bypass portion extending along the first direction, the third bypass portion connecting the first bypass portion and the second bypass portion to each other.

[0023] In an embodiment, the third bypass portion may overlap with the first connection line.

[0024] In an embodiment, the display device may further include: a second line disposed in a layer different from the first line on the substrate, the second line extending along a second direction intersecting the first direction and including a second disconnection line and a second connection line, the second disconnection line being disconnected by the opening, and the second connection line not being disconnected by the opening; and a second bypass line disposed in a layer different from the second line on the substrate, the second bypass line bypassing the opening and connecting the second disconnection line.

[0025] In an embodiment, the second disconnection line may include a third disconnection portion and a fourth disconnection portion spaced apart from each other, the opening being between the third disconnection portion and the fourth disconnection portion, and the second bypass line may include: a fourth bypass portion extending along the first direction, the fourth bypass portion being connected to the third disconnection portion; a fifth bypass portion extending along the first direction, the fifth bypass portion being connected to the fourth disconnection portion; and a sixth bypass portion extending along the second direction, the sixth bypass portion connecting the fourth bypass portion and the fifth bypass portion to each other.

[0026] In an embodiment, the sixth bypass portion may overlap with the second connection line.

[0027] In an embodiment, the display device may further include: a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, and a third conductive layer that are sequentially stacked one on top of another on a substrate. In this embodiment, the first conductive layer may include a first line, and the third conductive layer may include a first bypass line.

[0028] In an embodiment, the second conductive layer may include a second line, and the third conductive layer may further include a second bypass line.

[0029] In these embodiments of the display device according to the present invention, a first disconnection line disconnected by an opening may be connected to each other through a first bypass line disposed in a layer different from the first disconnection line on the substrate and bypassing the opening. Accordingly, a dead zone caused by the first bypass line around the opening may be reduced.

[0030] In these embodiments, the first bypass line may overlap with a first connection line disposed in the same layer as the first disconnection line on the substrate, not disconnected by the opening, and transmitting a DC voltage. Accordingly, electrical coupling between the first bypass line and the first connection line may be effectively prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other features of the present invention will become more apparent by describing exemplary embodiments of the present invention in further detail with reference to the accompanying drawings, in which:

[0032] Figure 1 is a block diagram illustrating a display device according to an embodiment;

[0033] Figure 2 is an illustration Figure 1 of a circuit diagram of a pixel of the display device in;

[0034] Figure 3 is a plan view illustrating a display device according to an embodiment;

[0035] Figure 4 is an illustration Figure 3 of a cross-sectional view of the display device in;

[0036] Figure 5 is an illustration Figure 3 of an enlarged plan view of region V in;

[0037] Figure 6 is an illustration Figure 5 of a plan view of the first line in;

[0038] Figure 7 is a cross-sectional view taken along Figure 6 line VII-VII' in;

[0039] Figure 8 is an illustration Figure 5The plan view of the second line in;

[0040] Figure 9 is a sectional view taken along Figure 8 the line IX-IX' in; and

[0041] Figure 10 and Figure 11 is a plan view showing a display device according to an alternative embodiment. Detailed Description

[0042] Now, the present invention will be described more fully hereinafter with reference to the accompanying drawings in which various embodiments are shown. However, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the text, the same reference numerals refer to the same elements.

[0043] It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element, or intervening elements may be present between the element and the other element. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements.

[0044] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, the first element, component, region, layer, or section discussed below may be referred to as the second element, component, region, layer, or section without departing from the teachings herein.

[0045] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting. As used herein, the singular forms "a" and "the" are intended to include the plural forms, including "at least one", unless the context clearly dictates otherwise. "Or" means "and / or". "At least one of A and B" means "A and / or B". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be further understood that when used in this specification, the terms "comprises" and / or "comprising" specify the presence of the stated features, regions, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components, and / or groups thereof.

[0046] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another as illustrated in the figures. It will be understood that the relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is flipped, an element described as on the "lower" side of another element will then be oriented on the "upper" side of the other element. Thus, the exemplary term "lower" can include both the "lower" and "upper" orientations depending on the specific orientation of the figure. Similarly, if the device in one of the figures is flipped, an element described as "beneath" or "below" another element will then be oriented "above" the other element. Thus, the exemplary terms "beneath" or "below" can include both the above and below orientations.

[0047] When considering the measurements discussed and the errors associated with the measurements of a particular quantity (i.e., the limitations of the measurement system), "about" or "approximate" as used herein includes the recited value and means within an acceptable deviation range of the particular value as determined by one of ordinary skill in the art.

[0048] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0049] Exemplary embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. Accordingly, variations in the illustrated shapes as a result, for example, of manufacturing techniques and / or tolerances are to be expected. Thus, the embodiments described herein should not be construed as limited to the particular shapes of regions illustrated herein but are to include, for example, shape deviations resulting from manufacturing. For example, regions illustrated or described as flat may typically have rough and / or non-linear features. Additionally, the sharp corners illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the exact shape of a region and are not intended to limit the scope of the claims.

[0050] Hereinafter, embodiments of a display device according to the present invention will be described in detail with reference to the accompanying drawings.

[0051] Figure 1 is a block diagram illustrating a display device according to an embodiment.

[0052] Referring to Figure 1 , embodiments of the display device may include a display unit 10, a scan driver 20, a data driver 30, an emission control driver 40, and a controller 50.

[0053] The display unit 10 may be disposed in the display area and may include a plurality of pixels PX at intersections of a plurality of scan lines SL1 to SLn, a plurality of data lines DTL1 to DTLm, and a plurality of emission control lines EL1 to ELn. The pixels PX may be arranged in a substantially matrix form. The scan lines SL1 to SLn, the emission control lines EL1 to ELn, and the initialization voltage line IL may extend along a first direction DR1 which is the row direction of the pixels PX, and the data lines DTL1 to DTLm and the driving voltage line ELVDDL may extend along a second direction DR2 which is the column direction of the pixels PX.

[0054] Each pixel PX may be connected to at least one corresponding scan line among the scan lines SL1 to SLn. The scan driver 20 may transmit scan signals to each pixel PX via the scan lines SL1 to SLn.

[0055] Each pixel PX may be connected to a corresponding data line (e.g., a single data line) among the data lines DTL1 to DTLm. The data driver 30 may transmit data signals to each pixel PX via the data lines DTL1 to DTLm. When the scan signals are provided to the scan lines SL1 to SLn, the data signals may be provided to the pixels PX selected by the scan signals.

[0056] Each pixel PX may be connected to a corresponding emission control line (e.g., a single emission control line) among the emission control lines EL1 to ELn. The emission control driver 40 may transmit emission control signals to each pixel PX via the emission control lines EL1 to ELn. The emission control signals may control the emission timing or emission period of each pixel PX. Alternatively, the emission control driver 40 may be omitted according to the internal structure of the pixel PX.

[0057] The controller 50 can convert multiple externally received image signals IR, IG, and IB into multiple image data signals DR, DG, and DB, and can transmit the image data signals DR, DG, and DB to the data driver 30. The controller 50 can receive a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a clock signal MCLK. The controller 50 can generate control signals for controlling the scan driver 20, the data driver 30, and the emission control driver 40 respectively, and can transmit the generated control signals to the scan driver 20, the data driver 30, and the emission control driver 40 respectively. In one embodiment, for example, the controller 50 can generate a scan drive control signal SCS for controlling the scan driver 20, a data drive control signal DCS for controlling the data driver 30, and an emission drive control signal ECS for controlling the emission control driver 40, and can transmit the scan drive control signal SCS, the data drive control signal DCS, and the emission drive control signal ECS to the scan driver 20, the data driver 30, and the emission control driver 40 respectively.

[0058] Each pixel PX can receive a driving voltage ELVDD and a common voltage ELVSS from the outside. The driving voltage ELVDD can be a predetermined high-level voltage. The common voltage ELVSS can be a voltage lower than the driving voltage ELVDD or can be a ground voltage. The driving voltage ELVDD can be supplied to each pixel PX via a driving voltage line ELVDDL. The initialization voltage line IL can receive an initialization voltage VINT from an external power source and can supply the initialization voltage VINT to each pixel PX.

[0059] Each pixel PX can emit light having a brightness corresponding to a driving current supplied to a corresponding display element based on data signals received via data lines DTL1 to DTLm. Hereinafter, for convenience of description, an embodiment in which the display device includes an organic light-emitting element as a display element will be described. However, embodiments of the present invention are not limited thereto, and these embodiments can be applied to various types of display devices such as liquid crystal display devices, electrophoretic display devices, and the like.

[0060] Figure 2 is a diagram Figure 1 of a circuit diagram of an embodiment of a pixel PX of the display device in

[0061] Refer to Figure 2, each pixel PX of the display device may include a plurality of transistors T1, T2, T3, T4, T5, T6, and T7, a storage capacitor Cst, an organic light-emitting element OLED, and a plurality of signal lines 131, 132, 133, 134, 151, and 152 connected to the transistors T1, T2, T3, T4, T5, T6, and T7, the storage capacitor Cst, and the organic light-emitting element OLED.

[0062] The transistors T1, T2, T3, T4, T5, T6, and T7 may include a driving transistor T1, a switching transistor T2, a compensating transistor T3, a first initialization transistor T4, an operation control transistor T5, an emission control transistor T6, and a second initialization transistor T7.

[0063] The signal lines 131, 132, 133, 134, 151, and 152 may include a scan line 131 for transmitting a scan signal Sn, a previous scan line 132 for transmitting a previous scan signal Sn-1, an emission control line 133 for transmitting an emission control signal En, an initialization voltage line 134 for transmitting an initialization voltage VINT to initialize the driving transistor T1 and the anode of the organic light-emitting element OLED, a data line 151 for transmitting a data signal Dm, and a driving voltage line 152 for transmitting a driving voltage ELVDD. The previous scan line 132 may be parallel to the scan line 131, the emission control line 133 may be parallel to the previous scan line 132, the initialization voltage line 134 may be parallel to the emission control line 133, the data line 151 may cross the scan line 131, and the driving voltage line 152 may be parallel to the data line 151.

[0064] The driving gate electrode G1 of the driving transistor T1 may be connected to the first electrode Cst1 of the storage capacitor Cst, the driving source electrode S1 of the driving transistor T1 may be connected to the driving voltage line 152 via the operation control transistor T5, and the driving drain electrode D1 of the driving transistor T1 may be electrically connected to the anode of the organic light-emitting element OLED via the emission control transistor T6. The driving transistor T1 may receive the data signal Dm based on the switching operation of the switching transistor T2, and may provide a driving current I OLED to the organic light-emitting element OLED.

[0065] The switching gate electrode G2 of the switching transistor T2 can be connected to the scan line 131, the switching source electrode S2 of the switching transistor T2 can be connected to the data line 151, and the switching drain electrode D2 of the switching transistor T2 can be connected to the driving source electrode S1 of the driving transistor T1 and connected to the driving voltage line 152 via the operation control transistor T5. The switching transistor T2 can be turned on according to the scan signal Sn received through the scan line 131, and can perform a switching operation for transmitting the data signal Dm applied to the switching transistor T2 through the data line 151 to the driving source electrode S1 of the driving transistor T1.

[0066] The compensation gate electrode G3 of the compensation transistor T3 can be connected to the scan line 131, the compensation source electrode S3 of the compensation transistor T3 can be connected to the driving drain electrode D1 of the driving transistor T1 and connected to the anode of the organic light emitting element OLED via the emission control transistor T6, and the compensation drain electrode D3 of the compensation transistor T3 can be connected to the first electrode Cst1 of the storage capacitor Cst, the first initialization source electrode S4 of the first initialization transistor T4, and the driving gate electrode G1 of the driving transistor T1. The compensation transistor T3 can be turned on in response to the scan signal Sn applied to the compensation transistor T3 through the scan line 131, and can diode-connect the driving transistor T1 by electrically connecting the driving gate electrode G1 and the driving drain electrode D1 of the driving transistor T1.

[0067] The first initialization gate electrode G4 of the first initialization transistor T4 can be connected to the previous scan line 132, the first initialization drain electrode D4 of the first initialization transistor T4 can be connected to the second initialization drain electrode D7 of the second initialization transistor T7 and the initialization voltage line 134, and the first initialization source electrode S4 of the first initialization transistor T4 can be connected to the first electrode Cst1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation transistor T3, and the driving gate electrode G1 of the driving transistor T1. The first initialization transistor T4 can be turned on in response to the previous scan signal Sn-1 applied to the first initialization transistor T4 through the previous scan line 132, and can perform an initialization operation for initializing the voltage of the driving gate electrode G1 of the driving transistor T1 by transmitting the initialization voltage VINT to the driving gate electrode G1 of the driving transistor T1.

[0068] The operation control gate electrode G5 of the operation control transistor T5 can be connected to the emission control line 133, the operation control source electrode S5 of the operation control transistor T5 can be connected to the driving voltage line 152, and the operation control drain electrode D5 of the operation control transistor T5 can be connected to the driving source electrode S1 of the driving transistor T1 and the switching drain electrode D2 of the switching transistor T2.

[0069] The emission control gate electrode G6 of the emission control transistor T6 can be connected to the emission control line 133, the emission control source electrode S6 of the emission control transistor T6 can be connected to the drive drain electrode D1 of the drive transistor T1 and the compensation source electrode S3 of the compensation transistor T3, and the emission control drain electrode D6 of the emission control transistor T6 can be connected to the second initialization source electrode S7 of the second initialization transistor T7 and the anode of the organic light-emitting element OLED.

[0070] The operation control transistor T5 and the emission control transistor T6 can be simultaneously turned on in response to an emission control signal En applied to the operation control transistor T5 and the emission control transistor T6 through the emission control line 133. Accordingly, the drive voltage ELVDD can be transmitted to the organic light-emitting element OLED, and the drive current I OLED can flow through the organic light-emitting element OLED.

[0071] The second initialization gate electrode G7 of the second initialization transistor T7 can be connected to the previous scan line 132, the second initialization source electrode S7 of the second initialization transistor T7 can be connected to the emission control drain electrode D6 of the emission control transistor T6 and the anode of the organic light-emitting element OLED, and the second initialization drain electrode D7 of the second initialization transistor T7 can be connected to the first initialization drain electrode D4 of the first initialization transistor T4 and the initialization voltage line 134. The second initialization transistor T7 can be turned on in response to a previous scan signal Sn-1 applied to the second initialization transistor T7 through the previous scan line 132, and can initialize the anode of the organic light-emitting element OLED.

[0072] The operation of each pixel PX will be described in detail below.

[0073] During the initialization period, when the previous scan signal Sn-1 is supplied through the previous scan line 132, the first initialization transistor T4 can be turned on in response to the previous scan signal Sn-1, and the drive transistor T1 can be initialized with an initialization voltage VINT supplied from the initialization voltage line 134.

[0074] During the data programming period, when the scan signal Sn is supplied through the scan line 131, the switch transistor T2 and the compensation transistor T3 can be turned on in response to the scan signal Sn. The drive transistor T1 can be diode-connected and forward-biased through the turned-on compensation transistor T3.

[0075] Subsequently, a compensation voltage Dm + Vth obtained by subtracting the threshold voltage -Vth of the driving transistor T1 (here, the threshold voltage has a negative value) from the data signal Dm supplied from the data line 151 can be applied to the driving gate electrode G1 of the driving transistor T1. In this case, the driving voltage ELVDD and the compensation voltage Dm + Vth can be applied to opposite ends (or the first electrode Cst1 and the second electrode Cst2) of the storage capacitor Cst, such that charges corresponding to the voltage difference between the opposite ends of the storage capacitor Cst are stored in the storage capacitor Cst.

[0076] During the emission period, the operation control transistor T5 and the emission control transistor T6 can be turned on in response to the emission control signal En supplied from the emission control line 133. A driving current I based on the voltage difference between the voltage of the driving gate electrode G1 of the driving transistor T1 and the driving voltage ELVDD can be generated OLED and the driving current I OLED can be supplied to the organic light-emitting element OLED through the emission control transistor T6.

[0077] Figure 3 is a plan view illustrating a display device according to an embodiment.

[0078] Referring to Figure 3 , an embodiment of the display device may include: a display area DA and a peripheral area PA outside the display area DA. Figure 1 Multiple pixels PX in Figure 1 and multiple lines SL1 to SLn, DTL1 to DTLm, EL1 to ELn, ELVDDL, and IL for transmitting electrical signals to the pixels PX can be arranged in the display area DA, and each pixel PX includes a display element such as an organic light-emitting element OLED.

[0079] The substrate 100 may include an opening OP defined in the display area DA. In an embodiment, the opening OP may have a substantially circular shape. However, the present disclosure is not limited thereto, and in an alternative embodiment, the opening OP may have, for example, a polygonal shape or an elliptical shape. In an embodiment, an optical device such as a camera may be arranged in the opening OP.

[0080] Figure 4 is an illustration Figure 3 of the cross-sectional view of the display device in Figure 4 Specifically, Figure 3 can illustrate a part of one pixel PX located in the display area DA of the display device in

[0081] Referring toFigure 4 ,a transistor TR, signal lines 131, 133, 134, 151, and 152, insulating layers 105, 120, 140, 160, 180, and 210, an organic light-emitting element OLED, and a packaging layer 240 may be disposed on a substrate 100.

[0082] The substrate 100 may include glass, metal, or plastic. In an embodiment, the substrate 100 may include a material having a flexible property or a bendable property. In an embodiment where the substrate 100 has a flexible property or a bendable property, the substrate 100 may include, for example, a polymer resin such as polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), or cellulose acetate phthalate (CAP). The substrate 100 may have a single-layer structure, or may have a multi-layer structure including an inorganic layer and a layer including at least one of the above materials. In an embodiment, the substrate 100 may have a structure including a first organic layer, an inorganic layer, and a second organic layer stacked on one another.

[0083] A buffer layer 105 may be disposed on the substrate 100. The buffer layer 105 may include: an inorganic material including an oxide or a nitride. The buffer layer 105 may provide a flat surface on the substrate 100 and may include an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0084] A semiconductor layer 110 may be disposed on the buffer layer 105. The semiconductor layer 110 may include, for example, polysilicon, amorphous silicon, or an oxide semiconductor or may be formed of polysilicon, amorphous silicon, or an oxide semiconductor.

[0085] The semiconductor layer 110 may include a channel region and a source region and a drain region disposed on respective opposite sides of the channel region. In an embodiment, the source region and the drain region may be impurity-doped, and the impurity may include an N-type impurity or a P-type impurity.

[0086] A gate insulating layer 120 may be disposed on the semiconductor layer 110. The gate insulating layer 120 may include: an inorganic material including an oxide or a nitride or an organic material. In one embodiment, for example, the gate insulating layer 120 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, or zinc oxide, and may have a single-layer structure or a multi-layer structure.

[0087] The first conductive layer 130 including the scan line 131, the emission control line 133, the initialization voltage line 134, and the gate electrode 135 may be disposed on the gate insulating layer 120. In an embodiment, the scan line 131, the emission control line 133, the initialization voltage line 134, and the gate electrode 135 may be disposed in the same layer as each other and may include the same material as each other. In one embodiment, for example, the first conductive layer 130 may include molybdenum (Mo), copper (Cu), or titanium (Ti), and may have a single-layer structure or a multi-layer structure.

[0088] The first insulating layer 140 may be disposed on the first conductive layer 130. The first insulating layer 140 may include: an inorganic material including an oxide or a nitride or an organic material. In one embodiment, for example, the first insulating layer 140 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, or zinc oxide, and may have a single-layer structure or a multi-layer structure.

[0089] The second conductive layer 150 including the data line 151, the driving voltage line 152, the source electrode 153, and the drain electrode 154 may be disposed on the first insulating layer 140. In an embodiment, the data line 151, the driving voltage line 152, the source electrode 153, and the drain electrode 154 may be disposed in the same layer as each other and may include the same material as each other. In one embodiment, for example, the second conductive layer 150 may include aluminum (Al), copper (Cu), or titanium (Ti), and may have a single-layer structure or a multi-layer structure.

[0090] The semiconductor layer 110, the gate electrode 135, the source electrode 153, and the drain electrode 154 may jointly define a transistor TR. Figure 4 The transistor TR illustrated in may correspond to any one of the driving transistor T1, the switching transistor T2, the compensation transistor T3, the first initialization transistor T4, the operation control transistor T5, the emission control transistor T6, and the second initialization transistor T7.

[0091] The second insulating layer 160 may be disposed on the second conductive layer 150. The second insulating layer 160 may include: an inorganic material including an oxide or a nitride or an organic material. In one embodiment, for example, the second insulating layer 160 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, or zinc oxide, and may have a single-layer structure or a multi-layer structure.

[0092] The planarization layer 180 may be disposed on the second insulating layer 160. The planarization layer 180 may include, for example, an organic material such as acrylate, benzocyclobutene (BCB), PI, or hexamethyldisiloxane (HMDSO). The planarization layer 180 may be used to substantially planarize a portion above the transistor TR (or provide a flat surface on a portion above the transistor TR). The planarization layer 180 may have a single-layer structure or a multi-layer structure.

[0093] The organic light-emitting element OLED including the pixel electrode 190, the counter electrode 230, and the intermediate layer 220 inserted between the pixel electrode 190 and the counter electrode 230 may be disposed on the planarization layer 180. The intermediate layer 220 may include an emission layer.

[0094] The pixel electrode 190 may be connected to the emission control drain electrode D6 of the emission control transistor T6 in Figure 2 through the contact hole defined in the planarization layer 180 and the second insulating layer 160.

[0095] The pixel defining layer 210 may be disposed on the planarization layer 180. In an embodiment, the opening portion corresponding to each pixel (i.e., the opening portion exposing the central portion of the pixel electrode 190) may be defined by the pixel defining layer 210 to define a pixel. In this embodiment, the pixel defining layer 210 may increase the distance between the edge of the pixel electrode 190 and the counter electrode 230, thereby effectively preventing an arc or the like from occurring between the edge of the pixel electrode 190 and the counter electrode 230. In one embodiment, for example, the pixel defining layer 210 may include an organic material such as PI or HMDSO.

[0096] The intermediate layer 220 of the organic light-emitting element OLED may include a low-molecular material or a polymer material. In an embodiment where the intermediate layer 220 includes a low-molecular material, the intermediate layer 220 may have a stacked structure including a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). Each of HIL, HTL, EML, ETL, and EIL may have a single-layer structure or a multi-layer structure. The intermediate layer 220 may include at least one of various organic materials such as copper phthalocyanine (CuPc), N,N'-bis(naphthalen-1-yl)-N,N'-diphenylbenzidine (NPB), or tris(8-hydroxyquinoline)aluminum (Alq3), for example.

[0097] In embodiments where the intermediate layer 220 comprises a polymeric material, the intermediate layer 220 may include an HTL and an EML. In this embodiment, the HTL may include PEDOT, and the EML may include polymers such as polyphenylene vinylene (PPV) and polyfluorene. The intermediate layer 220 may include a common layer over the plurality of pixel electrodes 190, or may include a patterned layer corresponding to each of the pixel electrodes 190.

[0098] The counter electrode 230 may be disposed over the display area DA. In an embodiment, the counter electrode 230 may be a common layer covering the plurality of organic light-emitting elements OLED, and may correspond to the plurality of pixel electrodes 190.

[0099] In an embodiment, the pixel electrode 190 and the counter electrode 230 may be the anode and the cathode of the organic light-emitting element OLED, respectively. However, the present disclosure is not limited thereto, and in alternative embodiments, the pixel electrode 190 and the counter electrode 230 may be the cathode and the anode of the organic light-emitting element OLED, respectively.

[0100] The encapsulation layer 240 may be disposed over the organic light-emitting element OLED. Since the organic light-emitting element OLED may be vulnerable to damage from moisture or oxygen from the outside, the organic light-emitting element OLED may be covered by the encapsulation layer 240. The encapsulation layer 240 may cover the display area DA, and a portion of the encapsulation layer 240 may extend outside the display area DA. The encapsulation layer 240 may include a first inorganic encapsulation layer 241, an organic encapsulation layer 242, and a second inorganic encapsulation layer 243.

[0101] The first inorganic encapsulation layer 241 may cover the counter electrode 230, and may include ceramics, metal oxides, metal nitrides, metal carbides, indium oxide, tin oxide, indium tin oxide (ITO), silicon oxide, silicon nitride, and / or silicon oxynitride. Although not shown, in alternative embodiments, other layers such as a cover layer may be inserted between the first inorganic encapsulation layer 241 and the counter electrode 230. Since the shape of the first inorganic encapsulation layer 241 conforms to the underlying structure of the first inorganic encapsulation layer 241, the first inorganic encapsulation layer 241 may not have a flat upper surface.

[0102] The organic encapsulation layer 242 may cover the first inorganic encapsulation layer 241, and the upper surface of the organic encapsulation layer 242 may be substantially planarized. Specifically, the upper surface of the organic encapsulation layer 242 may have at least a flat portion corresponding to the display area DA. The organic encapsulation layer 242 may include at least one material selected from methacrylate, polyester, polyethylene, polypropylene, PET, PEN, PC, PI, polyvinyl sulfonate, polyoxymethylene, polyarylate, and HMDSO.

[0103] The second inorganic encapsulation layer 243 may cover the organic encapsulation layer 242 and may include ceramics, metal oxides, metal nitrides, metal carbides, indium oxide, tin oxide, ITO, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0104] In an embodiment, as described above, since the encapsulation layer 240 has a multi-layer structure including the first inorganic encapsulation layer 241, the organic encapsulation layer 242, and the second inorganic encapsulation layer 243, even if cracks are generated inside the encapsulation layer 240, the cracks may not be connected between the first inorganic encapsulation layer 241 and the organic encapsulation layer 242 or may not be connected between the organic encapsulation layer 242 and the second inorganic encapsulation layer 243. Therefore, the formation of paths through which moisture, oxygen, etc. penetrate from the outside into the display area DA can be effectively prevented or minimized.

[0105] Figure 5 is a magnified plan view of region V in Figure 3 . Specifically, Figure 5 illustrates the opening OP of the substrate 100 and the peripheral region of the opening OP. Figure 6 is a plan view of the first line L1 in Figure 5 . Figure 7 is a cross-sectional view taken along line VII-VII’ in Figure 6 . Figure 8 is a plan view of the second line L2 in Figure 5 . Figure 9 is a cross-sectional view taken along line IX-IX’ in Figure 8 .

[0106] Referring to Figure 5 , Figure 6 , Figure 7 , Figure 8 and Figure 9 , an embodiment of the display device may include a substrate 100 in which an opening OP is defined and a plurality of first lines L1 and a plurality of second lines L2 disposed on the substrate 100.

[0107] The opening OP may be defined through the substrate 100, and the first lines L1 and the second lines L2 may not be disposed in the opening OP. In an embodiment, the opening OP may have a substantially circular shape, and the circular shape may have a diameter ranging from about 4.6 millimeters (mm) to about 4.8 mm. In one embodiment, for example, the inside of the display area DA of the substrate 100 may be cut into a circular shape to form the opening OP.

[0108] A peripheral portion PP around the opening OP can be formed at the periphery of the opening OP. The peripheral portion PP can include a cutting edge for cutting the substrate 100 to form the opening OP. In an embodiment, the peripheral portion PP can have a substantially circular ring shape with a width ranging from about 0.3 mm to about 0.4 mm.

[0109] The first line L1 can extend along the first direction DR1. In an embodiment, each of the first lines L1 can be Figure 4 a scanning line 131 in Figure 4 the emission control line 133 in or Figure 4 the initialization voltage line 134 in. In this embodiment, the first line L1 can be disposed on the gate insulating layer 120.

[0110] In an embodiment where the opening OP is defined or formed inside the display area DA, some of the first lines L1 extending along the first direction DR1 can be disconnected by the opening OP. Thus, the first line L1 can include a plurality of first disconnection lines DL1 disconnected by the opening OP and a plurality of first connection lines CL1 not disconnected by the opening OP. In this embodiment, the first disconnection lines DL1 disconnected by the opening OP can be connected to each other through first bypass lines BL1 that bypass the opening OP respectively.

[0111] In an embodiment, as Figure 6 shown in, each of the first disconnection lines DL1 can include a first disconnection portion DP1 and a second disconnection portion DP2 disconnected by the opening OP (see Figure 5 ). The first disconnection portion DP1 and the second disconnection portion DP2 can be spaced apart in the first direction DR1, and the opening OP is disposed between the first disconnection portion DP1 and the second disconnection portion DP2.

[0112] The first bypass line BL1 can connect the first disconnection portion DP1 and the second disconnection portion DP2 while bypassing the opening OP. The first bypass line BL1 can include a first bypass portion BP1 extending along the second direction DR2 and connected to the first disconnection portion DP1, a second bypass portion BP2 extending along the second direction DR2 and connected to the second disconnection portion DP2, and a third bypass portion BP3 extending along the first direction DR1 and connecting the first bypass portion BP1 and the second bypass portion BP2 to each other. In one embodiment, for example, the first bypass line BL1 can have a "U-shaped" shape.

[0113] The first bypass line BL1 may be disposed in a layer different from the first disconnection line DL1. In an embodiment, the first bypass line BL1 may be disposed on the second insulating layer 160. In this embodiment, the first bypass line BL1 may be electrically connected to the first disconnection line DL1 via connection patterns CP1 and CP2 disposed on the first insulating layer 140.

[0114] In an embodiment, as Figure 7 shown, the first connection pattern CP1 may contact the first disconnection portion DP1 by being disposed inside (e.g., filling) the first contact hole CH1 defined in the first insulating layer 140, and the second connection pattern CP2 may contact the second disconnection portion DP2 by being disposed inside (e.g., filling) the second contact hole CH2 defined in the first insulating layer 140. The first bypass portion BP1 may contact the first connection pattern CP1 by being disposed inside (e.g., filling) the third contact hole CH3 defined in the second insulating layer 160, and the second bypass portion BP2 may contact the second connection pattern CP2 by being disposed inside (e.g., filling) the fourth contact hole CH4 defined in the second insulating layer 160. Accordingly, the first bypass portion BP1 and the second bypass portion BP2 may be electrically connected to the first disconnection portion DP1 and the second disconnection portion DP2, respectively, and the first disconnection line DL1 may be connected to each other through the first bypass line BL1.

[0115] In an embodiment, the third bypass portion BP3 of the first bypass line BL1 may overlap one of the first connection lines CL1. In this embodiment, the first connection line CL1 overlapping with the third bypass portion BP3 may transmit a DC voltage. In one embodiment, for example, the third bypass portion BP3 may overlap the first connection line CL1 corresponding to the initialization voltage line 134 that transmits an initialization voltage (i.e., a DC voltage). If the first bypass line BL1 overlaps a scan line 131 or an emission control line 133 that transmits an AC voltage such as a scan signal or an emission control signal, the first bypass line BL1 may be electrically coupled to the scan line 131 or the emission control line 133. In an embodiment according to the present invention, the third bypass portion BP3 of the first bypass line BL1 may overlap the first connection line CL1 for transmitting a DC voltage, thereby effectively preventing the first bypass line BL1 from being electrically coupled to the first connection line CL1 located under the first bypass line BL1.

[0116] In a case where the first bypass line BL1 is located in the same layer as the layer of the first disconnection line DL1, pixels PX may not be disposed in the region where the first bypass line BL1 is disposed to prevent the first bypass line BL1 from Figure 4The scan line 131, emission control line 133, initialization voltage line 134, and gate electrode 135 disposed on the gate insulating layer 120 overlap. Accordingly, a dead zone in which the pixel PX is not located may be formed around the opening OP. In an embodiment according to the present invention, the first bypass line BL1 may be disposed on a second insulating layer 160 different from the gate insulating layer 120 on which the first disconnection line DL1 is disposed, such that the pixel PX may be disposed in the region where the first bypass line BL1 is disposed. Accordingly, in this embodiment, the dead zone caused by the first bypass line BL1 around the opening OP may be reduced or substantially not formed.

[0117] The second line L2 may extend along a second direction DR2 while being insulated from the first line L1. In an embodiment, each of the second lines L2 may be Figure 4 the data line 151 in Figure 4 or the driving voltage line 152 in. In this embodiment, the second line L2 may be disposed on the first insulating layer 140.

[0118] In an embodiment in which the opening OP is defined or formed inside the display area DA, some of the second lines L2 extending along the second direction DR2 may be disconnected by the opening OP. Accordingly, the second line L2 may include a plurality of second disconnection lines DL2 disconnected by the opening OP and a plurality of second connection lines CL2 not disconnected by the opening OP. The second disconnection lines DL2 disconnected by the opening OP may be connected to each other by second bypass lines BL2 that bypass the opening OP, respectively.

[0119] Each of the second disconnection lines DL2 may include a third disconnection portion DP3 and a fourth disconnection portion DP4 disconnected from each other by the opening OP. The third disconnection portion DP3 and the fourth disconnection portion DP4 may be spaced apart in the second direction DR2, and the opening OP is disposed between the third disconnection portion DP3 and the fourth disconnection portion DP4.

[0120] The second bypass line BL2 may connect the third disconnection portion DP3 and the fourth disconnection portion DP4 to each other while bypassing the opening OP. The second bypass line BL2 may include a fourth bypass portion BP4 extending along the first direction DR1 and connected to the third disconnection portion DP3, a fifth bypass portion BP5 extending along the first direction DR1 and connected to the fourth disconnection portion DP4, and a sixth bypass portion BP6 extending along the second direction DR2 and connecting the fourth bypass portion BP4 and the fifth bypass portion BP5 to each other. In one embodiment, for example, the second bypass line BL2 may have a "U" shape.

[0121] The second bypass line BL2 may be disposed in a layer different from the second disconnection line DL2. In an embodiment, the second bypass line BL2 may be disposed on the second insulating layer 160. The fourth bypass portion BP4 may be in contact with the third disconnection portion DP3 by being disposed inside (e.g., filling) a fifth contact hole CH5 defined in the second insulating layer 160, and the fifth bypass portion BP5 may be in contact with the fourth disconnection portion DP4 by being disposed inside (e.g., filling) a sixth contact hole CH6 defined in the second insulating layer 160. Accordingly, the second disconnection lines DL2 may be connected to each other through the second bypass line BL2.

[0122] In an embodiment, the second bypass line BL2 may be disposed in the same layer as the layer of the first bypass line BL1 on the substrate 100. In one embodiment, for example, the first bypass line BL1 and the second bypass line BL2 may be disposed on the second insulating layer 160. In this embodiment, the first bypass line BL1 and the second bypass line BL2 may be spaced apart from each other to prevent the first bypass line BL1 and the second bypass line BL2 disposed in the same layer from being electrically connected to each other. In an embodiment, the second bypass line BL2 may be located outside the first bypass line BL1. In this embodiment, the second bypass line BL2 may surround a part of the first bypass line BL1. Accordingly, the length of the second bypass line BL2 may be greater than the length of the first bypass line BL1.

[0123] In an embodiment, the sixth bypass portion BP6 of the second bypass line BL2 may overlap with one of the second connection lines CL2. In this embodiment, the second connection line CL2 overlapping with the sixth bypass portion BP6 may transmit a DC voltage. In one embodiment, for example, the sixth bypass portion BP6 may overlap with the second connection line CL2, and the second connection line CL2 corresponds to a drive voltage line 152 for applying a drive voltage (i.e., a DC voltage). If the second bypass line BL2 overlaps with a data line 151 that transmits an AC voltage such as a data signal, the second bypass line BL2 may be electrically coupled to the data line 151. In an embodiment of the present invention, the sixth bypass portion BP6 of the second bypass line BL2 may overlap with the second connection line CL2 that transmits a DC voltage, thereby effectively preventing the second bypass line BL2 from being electrically coupled to the second connection line CL2 located under the second bypass line BL2.

[0124] In a case where the second bypass line BL2 is located in the same layer as the layer of the second disconnection line DL2, the pixel PX may not be disposed in the region where the second bypass line BL2 is disposed to prevent the second bypass line BL2 from overlapping with the data line 151, the driving voltage line 152, the source electrode 153, and the drain electrode 154 disposed on the first insulating layer 140. Accordingly, a dead zone where the pixel PX is not located may be formed around the opening OP. In an embodiment according to the present invention, the second bypass line BL2 may be disposed on a second insulating layer 160 different from the first insulating layer 140 on which the second disconnection line DL2 is disposed, such that the pixel PX may be disposed in the region where the second bypass line BL2 is disposed. Accordingly, the dead zone caused by the second bypass line BL2 around the opening OP may be reduced or substantially not formed.

[0125] Figure 10 and Figure 11 is a plan view illustrating a display device according to an alternative embodiment.

[0126] Referring to Figure 10 , in an alternative embodiment, the opening OP defined inside the display area DA may have a quadrilateral shape with rounded corners. In this embodiment, a sound device (e.g., a speaker) may be disposed in the opening OP. In this embodiment, the first disconnection line may be disconnected by the opening OP and may be connected to each other through a first bypass line disposed in a layer different from the first disconnection line. In this embodiment, the second disconnection line may be disconnected by the opening OP and may be connected to each other through a second bypass line disposed in a layer different from the second disconnection line.

[0127] Referring to Figure 11 , in another alternative embodiment, the opening OP may be defined at a side portion of the substrate 100. In one embodiment, for example, the opening OP may have a recessed shape in which the opening OP is recessed from the side portion of the substrate 100 toward the inside of the substrate 100. In this embodiment, the opening OP may be defined outside the display area DA. In this embodiment, a device (e.g., a camera or a speaker) may be disposed in the opening OP. In this embodiment, the first disconnection line may be disconnected by the opening OP and may be connected to each other through a first bypass line disposed in a layer different from the first disconnection line.

[0128] These embodiments of the display device may be applied to display devices included in a computer, a notebook computer, a mobile phone, a smart phone, a smart tablet, a portable media player (PMP), a personal digital assistant (PDA), an MP3 player, and the like.

[0129] The present invention should not be construed as limited to the exemplary embodiments set forth herein. On the contrary, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

[0130] Although the present invention has been specifically shown and described with reference to exemplary embodiments thereof, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit or scope of the invention as defined by the following claims.

Claims

1. A display device, comprising: a substrate, an opening being defined in the substrate; a first disconnection line disposed on the substrate, the first disconnection line extending along a first direction and including a first disconnection portion and a second disconnection portion, and the first disconnection portion and the second disconnection portion being disconnected from each other by the opening; a first bypass line disposed in a layer different from the first disconnection line on the substrate, the first bypass line bypassing the opening and connecting the first disconnection portion and the second disconnection portion to each other; and a connection line disposed on the substrate in the same layer as the first disconnection line, the connection line extending along the first direction and not being disconnected by the opening, wherein the first bypass line includes: a first bypass portion extending along a second direction intersecting the first direction; a second bypass portion extending along the second direction; and a third bypass portion extending along the first direction, the third bypass portion connecting the first bypass portion and the second bypass portion, wherein the third bypass portion of the first bypass line overlaps with the connection line, and wherein the connection line transmits a DC voltage.

2. The display device according to claim 1, wherein: the first bypass portion is connected to the first disconnection portion, and the second bypass portion is connected to the second disconnection portion.

3. The display device according to claim 1, wherein, The first disconnection line is a scan line, an emission control line, or an initialization voltage line.

4. The display device according to claim 1, further comprising: a second disconnection line disposed in a layer different from the first disconnection line on the substrate, the second disconnection line extending along the second direction and including a third disconnection portion and a fourth disconnection portion, and the third disconnection portion and the fourth disconnection portion being disconnected from each other by the opening; and a second bypass line disposed in a layer different from the second disconnection line on the substrate, the second bypass line bypassing the opening and connecting the third disconnection portion and the fourth disconnection portion to each other.

5. The display device according to claim 4, wherein, The second bypass line includes: a fourth bypass portion extending along the first direction, the fourth bypass portion being connected to the third disconnection portion; a fifth bypass portion extending along the first direction, the fifth bypass portion being connected to the fourth disconnection portion; and a sixth bypass portion extending along the second direction, the sixth bypass portion connecting the fourth bypass portion and the fifth bypass portion to each other.

6. The display device according to claim 5, further comprising: a connection line disposed on the substrate in the same layer as the second disconnection line, the connection line extending along the second direction and not being disconnected by the opening, wherein the sixth bypass portion overlaps with the connection line.

7. The display device according to claim 6, wherein, The connection line transmits a DC voltage.

8. The display device according to claim 4, wherein, The second disconnection line is a data line or a driving voltage line.

9. The display device according to claim 4, wherein, The second bypass line is disposed on the substrate in the same layer as the first bypass line.

10. The display device according to claim 4, wherein, The length of the second bypass line is greater than the length of the first bypass line.

11. The display device according to claim 4, further comprising: A first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, and a third conductive layer sequentially stacked one on top of another on the substrate, wherein: the first conductive layer includes the first disconnection line, and the third conductive layer includes the first bypass line.

12. The display device according to claim 11, wherein: the second conductive layer includes the second disconnection line; and the third conductive layer further includes the second bypass line.

13. A display device, comprising: a substrate, an opening being defined in the substrate; a first line disposed on the substrate, the first line extending along a first direction and including a first disconnection line and a first connection line, the first disconnection line being disconnected by the opening, and the first connection line not being disconnected by the opening; and a first bypass line disposed in a layer different from the first line on the substrate, the first bypass line bypassing the opening and connecting the first disconnection line, wherein the first bypass line includes: a first bypass portion extending along a second direction intersecting the first direction; a second bypass portion extending along the second direction; and a third bypass portion extending along the first direction, the third bypass portion connecting the first bypass portion and the second bypass portion to each other, wherein the third bypass portion of the first bypass line overlaps with the first connection line, and wherein the first connection line transmits a DC voltage.

14. The display device according to claim 13, wherein: the first disconnection line includes a first disconnection part and a second disconnection part spaced apart from each other, the opening being between the first disconnection part and the second disconnection part, the first bypass portion is connected to the first disconnection part, and the second bypass portion is connected to the second disconnection part.

15. The display device according to claim 13, further comprising: a second line disposed in a layer different from the first line on the substrate, the second line extending along the second direction and including a second disconnection line and a second connection line, the second disconnection line being disconnected by the opening, and the second connection line not being disconnected by the opening; and a second bypass line disposed in a layer different from the second line on the substrate, the second bypass line bypassing the opening and connecting the second disconnection line.

16. The display device according to claim 15, wherein: the second disconnection line includes a third disconnection part and a fourth disconnection part spaced apart from each other, the opening being between the third disconnection part and the fourth disconnection part, and the second bypass line includes: a fourth bypass portion extending along the first direction, the fourth bypass portion being connected to the third disconnection part; a fifth bypass portion extending along the first direction, the fifth bypass portion being connected to the fourth disconnection part; and a sixth bypass portion extending along the second direction, the sixth bypass portion connecting the fourth bypass portion and the fifth bypass portion to each other.

17. The display device according to claim 16, wherein, The sixth bypass portion overlaps with the second connection line.

18. The display device according to claim 15, further comprising: a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, and a third conductive layer sequentially stacked one on top of another on the substrate, wherein: the first conductive layer includes the first line, and the third conductive layer includes the first bypass line.

19. The display device according to claim 18, wherein the second conductive layer includes the second line, and the third conductive layer further includes the second bypass line.

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