Light emitting element and method for manufacturing the same

Abstract

A light emitting element and a manufacturing method thereof are disclosed. The light emitting element comprises: a substrate comprising an upper surface; a first light emitting unit and a second light emitting unit respectively located on the upper surface, wherein the first light emitting unit and the second light emitting unit respectively comprise a lower semiconductor layer and an upper semiconductor layer; and a conductive structure electrically connecting the first light emitting unit and the second light emitting unit; wherein the lower semiconductor layer of the first light emitting unit comprises: a first upper surface not covered by the upper semiconductor layer, and a first sidewall; wherein the first sidewall comprises a first sub-sidewall and a second sub-sidewall, an inner angle between the first sub-sidewall and the first upper surface is an obtuse angle, and an inner angle between the second sub-sidewall and the upper surface is an obtuse angle.

Description

TECHNICAL FIELD

[0001] The present invention relates to a light emitting element, and more particularly, to a light emitting element with improved light emitting efficiency. BACKGROUND

[0002] Light emitting diodes (LEDs) in solid state light emitting elements have been widely used in household appliances, lighting devices, indicator lights, and optoelectronic products, etc. due to their low power consumption, low heat generation, long lifetime, small size, fast response, and good optoelectronic properties, such as stable light emitting wavelength. With the development of optoelectronic technology, solid state light emitting elements have made considerable progress in light emitting efficiency, operating lifetime, and brightness.

[0003] A conventional LED chip includes a substrate, an n-type semiconductor layer, an active layer, and a p-type semiconductor layer formed on the substrate, and p- and n-electrodes formed on the p- and n-type semiconductor layers, respectively. When the LED chip is energized through the electrodes and a certain forward bias voltage is applied, holes from the p-type semiconductor layer and electrons from the n-type semiconductor layer combine in the active layer to emit light.

[0004] A high voltage LED chip is formed by dividing the area of a single LED chip into a plurality of light emitting units and connecting the light emitting units in series. Compared with a conventional single LED chip, the high voltage LED chip can operate at a low current and a high voltage and has a large output power under the same chip size. The number and size of the light emitting units of the high voltage LED chip can be determined according to the requirement of different input voltages, and each light emitting unit can be optimized. The high voltage LED chip has the advantages of operating at a high voltage, small size, and excellent flexibility in packaging and optical design. However, in the prior art, the light emitted by the plurality of light emitting units on the single substrate can be absorbed by the materials arranged between the adjacent light emitting units or the layers therebetween, resulting in poor light emitting efficiency. SUMMARY

[0005] A light emitting element is disclosed. The light emitting element includes a substrate including an upper surface, a first light emitting unit and a second light emitting unit located on the upper surface, respectively, wherein the first light emitting unit and the second light emitting unit each include a lower semiconductor layer and an upper semiconductor layer, and a conductive structure electrically connecting the first light emitting unit and the second light emitting unit, wherein the lower semiconductor layer of the first light emitting unit includes a first upper surface not covered by the upper semiconductor layer and a first sidewall, wherein the first sidewall includes a first sub-sidewall and a second sub-sidewall, an inner angle between the first sub-sidewall and the first upper surface is an obtuse angle, and an inner angle between the second sub-sidewall and the upper surface is an obtuse angle.

[0006] A light emitting element includes a substrate including an upper surface, a first light emitting unit and a second light emitting unit located on the upper surface, wherein the first light emitting unit and the second light emitting unit each include a lower semiconductor layer and an upper semiconductor layer, and a conductive structure electrically connecting the first light emitting unit and the second light emitting unit, wherein the lower semiconductor layer of the first light emitting unit includes a first sidewall located in a peripheral region of the light emitting element, wherein the first sidewall and the upper surface form an obtuse angle, and the first sidewall is a parallelogram from a side view, and the parallelogram includes a pair of opposite angles, wherein the pair of opposite angles include a first acute angle and a second acute angle. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 A top view of a light emitting element 1 according to an embodiment of the present application;

[0008] Figures 2A to 2C A cross-sectional view of the light emitting element 1 according to an embodiment of the present application;

[0009] Figure 2D A partial top view of the light emitting element 1 according to an embodiment of the present application;

[0010] Figure 3 A Scanning Electron Microscope (SEM) image of the light emitting element 1 according to an embodiment of the present application;

[0011] Figure 4 A partial cross-sectional view of the light emitting element according to an embodiment of the present application;

[0012] Figure 5A A partial perspective view of the light emitting element 1 according to an embodiment of the present application;

[0013] Figure 5B A partial perspective view of the light emitting element according to an embodiment of the present application;

[0014] Figures 6A to 6H A schematic view of a manufacturing method of the light emitting element according to an embodiment of the present application;

[0015] Figure 7 A schematic view of a manufacturing method of the light emitting element according to another embodiment of the present application;

[0016] Figure 8 A top view of a light emitting element 3 according to an embodiment of the present application;

[0017] Figures 9A to 9B A cross-sectional view of the light emitting element 3 according to an embodiment of the present application;

[0018] Figures 10A to 10CFIG. 1 is a schematic view of a manufacturing method of a light emitting element 3 according to an embodiment of the present application.

[0019] Explanation of symbols

[0020] 1, 3 light emitting element

[0021] 8 protective layer

[0022] 10 substrate

[0023] 10a upper surface

[0024] 12 semiconductor stack

[0025] 12a upper semiconductor layer

[0026] 12b lower semiconductor layer

[0027] 121 first semiconductor layer

[0028] 121a upper surface

[0029] 122 second semiconductor layer

[0030] 123 active layer

[0031] 13 scribe line

[0032] 17 laser

[0033] 18 transparent conductive layer

[0034] 20 first electrode

[0035] 201 first pad electrode

[0036] 202 first extension electrode

[0037] 22, 22a-22f light emitting unit

[0038] 23 insulating layer

[0039] 23a intermediate portion

[0040] 23b island portion

[0041] 23c extension portion

[0042] 27 laser

[0043] 28 platform region

[0044] 30 second electrode

[0045] 301 second pad electrode

[0046] 302 second extension electrode

[0047] 36 trench

[0048] 230a first insulating portion

[0049] 230b second insulating portion

[0050] 60 connecting electrode

[0051] E1 first lower edge

[0052] E2 second lower edge

[0053] E1' first upper edge

[0054] E2' second upper edge

[0055] Eax, Eay, Ebx, Eby, Ecx, Edx, Eex, Eey, Efx, Efy peripheral edge

[0056] L extension line

[0057] P patterned structure

[0058] S1 first sidewall

[0059] S11 first sub-sidewall

[0060] S12 second sub-sidewall

[0061] S2 second sidewall

[0062] SU upper sidewall

[0063] SX sandwich surface

[0064] θ1-θ3 included angle DETAILED DESCRIPTION

[0065] Embodiments of the present application will be described in detail, and drawings will be drawn, and the same or similar parts will be illustrated with the same reference numerals in each drawing.

[0066] Some embodiments of the present application can be accompanied by Figure 1 It is to be understood that the drawings of the embodiments of the present application are also considered to be a part of the description of the embodiments of the present application. It is to be understood that the drawings of the embodiments of the present application are not drawn to scale of actual devices and elements. The shapes and thicknesses of the embodiments can be exaggerated in the drawings for the purpose of clarity in illustrating the features of the embodiments of the present application. In addition, the structures and devices in the drawings are illustrated in a schematic manner for the purpose of clarity in illustrating the features of the embodiments of the present application.

[0067] Figure 1 is a light emitting element 1 disclosed in a first embodiment of the present application; Figure 2A is Figure 1 is a cross-sectional view along the line A-A' in FIG. 1; Figure 2BFig. 1 is a schematic cross-sectional view of a light emitting element according to an embodiment of the present application; Figure 1 Fig. 2 is a schematic cross-sectional view of the light emitting element of Fig. 1 along the line B-B'; Figure 2C Fig. 3 is a schematic cross-sectional view of the light emitting element of Fig. 1 along the line C-C'; Figure 1 Fig. 4 is a schematic cross-sectional view of the light emitting element of Fig. 1 along the line D-D'; Figure 2D Fig. 5 is a schematic cross-sectional view of the light emitting element of Fig. 1 along the line E-E'; Figure 1 Fig. 6 is a schematic cross-sectional view of the light emitting element of Fig. 1 along the line F-F';

[0068] The light emitting element 1 includes a substrate 10 and a plurality of light emitting units 22 (22a-22f) disposed on the upper surface 10a of the substrate 10, separated from each other by trenches 36, and each including a semiconductor stack 12. Conductive structures are formed between adjacent light emitting units 22 and on each light emitting unit 22, and electrically connect the light emitting units 22 to form a series array of light emitting units.

[0069] The substrate 10 can be a growth substrate, including a gallium arsenide (GaAs) substrate for growing gallium indium phosphide (AlGaInP) and a gallium phosphide (GaP) substrate, or a sapphire (Al2O3) substrate for growing indium gallium nitride (InGaN) or aluminum gallium nitride (AlGaN), a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, and an aluminum nitride (AlN) substrate. The substrate 10 includes an upper surface 10a parallel to the xy plane in Fig. 1. Figure 1 The substrate 10 can be a patterned substrate, i.e., the substrate 10 has a patterned structure P on the upper surface 10a thereof. In one embodiment, the patterned structure P is formed by partially etching the upper surface of the substrate 10 by mechanical grinding, dry etching, or wet etching. In another embodiment, the patterned structure P is formed by forming a layer of a material different from the substrate 10 on the upper surface 10a of the substrate 10, and patterning the layer. The patterned structure P can include a platform structure or a pyramidal structure with a triangular (or polygonal) base, a hemispherical structure, a conical structure, or a polygonal structure. Light emitted from the semiconductor stack 12 can be refracted by the patterned structure P of the substrate 10, thereby improving the brightness of the light emitting element. In addition, the patterned structure P slows down or suppresses the misfit dislocation between the substrate 10 and the semiconductor stack 12 due to lattice mismatch, thereby improving the epitaxial quality of the semiconductor stack 12. In another embodiment, the patterned structure P is a recessed structure (not shown) extending into the substrate from the upper surface 10a of the substrate 10, and the pattern of the recessed structure can be pyramidal, hemispherical, conical, or polygonal.

[0070] In one embodiment of the present application, the semiconductor stack 12 can be formed on the substrate 10 by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), or ion plating, such as sputtering or evaporation.

[0071] The semiconductor stack 12 includes, in sequence, a buffer structure (not shown), a first semiconductor layer 121, an active layer 123, and a second semiconductor layer 122 formed on the substrate 10. The buffer structure can reduce the lattice mismatch and inhibit dislocations, thereby improving the epitaxial quality. The material of the buffer layer includes GaN, AlGaN, or AlN. In one embodiment, the buffer structure includes a plurality of sub-layers (not shown). The sub-layers include the same material or different materials. In one embodiment, the buffer structure includes two sub-layers, wherein the first sub-layer is grown by sputtering and the second sub-layer is grown by MOCVD. In one embodiment, the buffer layer further includes a third sub-layer. The third sub-layer is grown by MOCVD, and the growth temperature of the second sub-layer is higher or lower than that of the third sub-layer. In one embodiment, the first, second, and third sub-layers include the same material, such as AlN. In one embodiment of the present application, the first semiconductor layer 121 and the second semiconductor layer 122, such as cladding layers or confinement layers, have different conductive types, electrical properties, polarities, or doping elements for providing electrons or holes. For example, the first semiconductor layer 121 is an n-type semiconductor, and the second semiconductor layer 122 is a p-type semiconductor. The active layer 123 is formed between the first semiconductor layer 121 and the second semiconductor layer 122. Electrons and holes combine in the active layer 123 under the drive of current, converting electrical energy into optical energy to emit light. The wavelength of the light emitted by the light emitting element 1 or the semiconductor stack 12 can be adjusted by changing the physical properties and chemical compositions of one or more layers in the semiconductor stack 12.

[0072] The material of the semiconductor stack 12 includes Al x In y Ga (1-x-y) N or Al x In y Ga (1-x-y)P is a III-V semiconductor material, where 0≤x, y≤1; x+y≤1. Depending on the material of the active layer, when the material of the semiconductor stack 12 is of the AlInGaP family, red light with a wavelength between 610 nm and 650 nm or yellow light with a wavelength between 550 nm and 570 nm can be emitted. When the material of the semiconductor stack 12 is of the InGaN family, blue or deep blue light with a wavelength between 400 nm and 490 nm or green light with a wavelength between 490 nm and 550 nm can be emitted. When the material of the semiconductor stack 12 is of the AlGaN family, UV light with a wavelength between 400 nm and 250 nm can be emitted. The active layer 123 can be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), a multi-quantum well (MQW). The material of the active layer 123 can be an i-type, p-type or n-type semiconductor.

[0073] The semiconductor stack 12 of each light emitting unit comprises a mesa region 28 formed by removing portions of the second semiconductor layer 122 and the active layer 123 from the upper surface of the semiconductor stack 12 down to the upper surface 121a of the first semiconductor layer 121. In a subsequent fabrication process, an electrically conductive structure will be formed on the mesa region 28. The semiconductor stack 12 above the extension line L (and extension plane) of the mesa region 28 is referred to as an upper semiconductor layer 12a and the semiconductor stack 12 below the extension line L is referred to as a lower semiconductor layer 12b, as seen in a side view. The upper semiconductor layer 12a comprises the second semiconductor layer 122 and the active layer 123. In an embodiment, the upper semiconductor layer 12a further comprises portions of the first semiconductor layer 121. The lower semiconductor layer 12b comprises all or another portion of the first semiconductor layer 121 and the buffer structure. In an embodiment, portions of the mesa region 28 in each light emitting unit 22 surround the second semiconductor layer 122 and the active layer 123 thereof.

[0074] The trench 36 is located between any two adjacent light emitting units 22, the bottom of which is the upper surface 10a of the substrate 10 and the sidewall of which is the sidewall of the semiconductor stack 12 of the two adjacent light emitting units 22. In an embodiment, when the substrate 10 is a patterned substrate, the patterned structure P is located at the bottom of the trench 10; in an embodiment, when the substrate 10 is a patterned substrate, the patterned structure P surrounds the periphery of all light emitting units 22.

[0075] An insulating layer 23 is disposed on each light-emitting unit 22 and within the trench 36, covering the upper surface 10a and patterned structure P of the substrate 10, and extending to the sidewalls and upper surface of the semiconductor stack 12 of the light-emitting unit 22. In this embodiment, the insulating layer 23 includes a first insulating portion 230a on the platform region 28 of the end light-emitting unit 22f in the series array, a second insulating portion 230b on the second semiconductor layer 122 of the starting light-emitting unit 22a, a middle portion 23a, an island portion 23b, and an extension portion 23c on the trench 36. In one embodiment, as... Figure 2A As shown, the middle portion 23a covers the sidewall S2 of the lower semiconductor layer 12b of the light-emitting unit 22a, the upper surface 10a of the substrate 10, and the sidewall S2 of the semiconductor stack 12 of the light-emitting unit 22b. In another embodiment, the middle portion 23a covers a portion of the trench 36, and the middle portion 23a does not cover the sidewall S2 of the lower semiconductor layer 12b of the light-emitting unit 22a, or only covers a portion of the sidewall S2 of the lower semiconductor layer 12b of the light-emitting unit 22a. An island-shaped portion 23b is formed on the upper surface 121a (i.e., the platform region 28) of the first semiconductor layer 121 in the light-emitting unit 22a, and an extension portion 23c is formed on the upper surface of the second semiconductor layer 122 in the light-emitting unit 22b. Figure 1 As shown, the island portion 23b may comprise one or more islands; the extension portion 23c extends from the intermediate portion 23a. In another embodiment, the insulating layer 23 does not have the island portion 23b. In another embodiment, the insulating layer 23 does not have the extension portion 23c. In another embodiment, the first insulating portion 230a may be omitted.

[0076] The insulating layer 23 is made of a transparent insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, titanium oxide, aluminum oxide, or a combination or stack of the above materials. The insulating layer 23 can be a single layer or a stack of multiple layers; in one embodiment, the insulating layer 23 comprises a stack of one or more insulating layer pairs, each insulating layer pair comprising two sublayers made of two different insulating materials, and the insulating layer 23 is a distributed Bragg reflector (DBR).

[0077] In one embodiment, the first insulating portion 230a, the second insulating portion 230b, the intermediate portion 23a, the island portion 23b, and the extension portion 23c are formed in the same fabrication process. For example, a transparent insulating material is formed on the upper surface of the light emitting element 1, and then patterned, for example, by developing and etching, to form the first insulating portion 230a, the second insulating portion 230b, the intermediate portion 23a, the island portion 23b, and the extension portion 23c. In one embodiment, the first insulating portion 230a, the second insulating portion 230b, the intermediate portion 23a, the island portion 23b, and the extension portion 23c have the same material and / or substantially the same thickness. In one embodiment, the first insulating portion 230a, the second insulating portion 230b, the intermediate portion 23a, the island portion 23b, and the extension portion 23c are formed in different fabrication processes. For example, the first insulating portion 230a and the second insulating portion 230b are formed in the same fabrication process, and the intermediate portion 23a, the island portion 23b, and the extension portion 23c are formed in another fabrication process. In one embodiment, the first insulating portion 230a, the second insulating portion 230b, the intermediate portion 23a, the island portion 23b, and the extension portion 23c have different materials. For example, the first insulating portion 230a and the second insulating portion 230b have the same material, and the intermediate portion 23a, the island portion 23b, and the extension portion 23c have another same material. In one embodiment, the first insulating portion 230a, the second insulating portion 230b, the intermediate portion 23a, the island portion 23b, and the extension portion 23c have different layer structures. For example, the first insulating portion 230a and the second insulating portion 230b are formed as a stack of multiple layers, and the intermediate portion 23a, the island portion 23b, and the extension portion 23c have a single layer structure.

[0078] In one embodiment, the second insulating portion 230b includes an opening exposing the upper surface of the second semiconductor layer 122 of the light emitting unit 22a. In another embodiment, the second insulating portion 230b includes a plurality of separate island structures (not shown) on the second semiconductor layer 122 of the light emitting unit 22a, and the upper surface of the second semiconductor layer 122 of the light emitting unit 22a is between the separate island structures.

[0079] The transparent conductive layer 18 covers the upper surface of the second semiconductor layer 122 of each light emitting unit 22 and is in electrical contact with the second semiconductor layer 122. In this embodiment, the transparent conductive layer 18 also covers the extension portion 23c of the insulating layer 23 and the second insulating portion 230b. The transparent conductive layer 18 can be a metal or a transparent conductive material, where the metal can be a thin metal layer having light transmission, and the transparent conductive material is transparent to the light emitted by the active layer 123, including materials such as indium tin oxide (ITO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), or indium zinc oxide (IZO). In one embodiment, the transparent conductive layer 18 also has an opening corresponding to the opening of the second insulating portion 230b.

[0080] A conductive structure is formed on the light-emitting unit 22 and the trench 36. The conductive structure includes a first electrode 20, a second electrode 30 on the light-emitting unit, and a connecting electrode 60 formed between two adjacent light-emitting units 22 (e.g., 22a and 22b, 22b and 22c, 22c and 22d, 22d and 22e, 22e and 22f). The material of the conductive structure includes metals such as chromium (Cr), titanium (Ti), gold (Au), aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), rhodium (Rh), or platinum (Pt), or alloys or stacks of the above materials.

[0081] Reference Figure 1 and Figure 2B In the light-emitting unit 22f, a first electrode 20 is formed on its first semiconductor layer 121, including a first pad electrode 201 and a first extension electrode 202 extending from the first pad electrode 201. The first electrode 20 is electrically connected to the first semiconductor layer 121 and is located on the first insulating portion 230a. In each of the other light-emitting units, a first extension electrode 202 is also provided and electrically connected to its first semiconductor layer 121. In the light-emitting unit 22a, a second electrode 30 is formed on the transparent conductive layer 18 and electrically connected to the transparent conductive layer 18 and the second semiconductor layer 122, including a second pad electrode 301 and a second extension electrode 302 extending from the second pad electrode 301. In each of the other light-emitting units, a second extension electrode 202 is also provided and electrically connected to its second semiconductor layer 122. In this embodiment, the position of the second pad electrode 301 corresponds to the opening of the second insulating portion 230b and the opening of the transparent conductive layer 18, and contacts the second semiconductor layer 122 through these openings. A connecting electrode 60 is formed on the middle portion 23a of the insulating layer 23, connecting a first extended electrode 202 on one light-emitting unit and a second extended electrode 302 on an adjacent light-emitting unit, thereby forming a series-connected light-emitting unit array of the light-emitting units 22. In this embodiment, viewed from above, the maximum width of the connecting electrode 60 is larger than the width of the first extended electrode 202 and the second extended electrode 302. At the portion of the connecting electrode 60 that connects to the first extended electrode 202 and the second extended electrode 302, the width of the connecting electrode 60 within the trench 36 tapers in the direction from the trench 36 toward the semiconductor stack 12, relative to the width of the connecting electrode 60 within the trench 36.

[0082] In another embodiment, the connecting electrode 60 is connected to the first extended electrode 202 on two adjacent light-emitting units 22, and / or the connecting electrode 60 is connected to the second extended electrode 302 on two adjacent light-emitting units 22, so that the light-emitting units 22 form different light-emitting unit arrays such as parallel, series, or series-parallel connection.

[0083] The second pad electrode 301 on the light-emitting unit 22a and the first pad electrode 201 on the light-emitting unit 22f are used for wire bonding during the operation of the light-emitting element 1 to form an electrical connection with external electronic components or a power supply. The aforementioned first insulating portion 230a and second insulating portion 230b serve to prevent current from flowing directly into the semiconductor stack 12 through the pad electrodes, instead allowing the current to diffuse through the extended electrodes 202 and 302 and the transparent conductive layer 18 above them. Similarly, the extension portion 23c of the insulating layer 23 is disposed along the second extended electrode 302 and located below the second extended electrode 302, preventing the current conducted through the second extended electrode 302 from flowing directly into the semiconductor stack 12, instead allowing it to diffuse through the transparent conductive layer 18 above the insulating layer 23. Therefore, in this embodiment, the extension portion 23c of the insulating layer 23 also serves as a current blocking function. The island-shaped portions 23b of the insulating layer 23 are disposed at intervals below the first extended electrode 202 along the first extended electrode 202, which also has the function of blocking current. Therefore, the first extended electrode 202 contacts the first semiconductor layer 121 at intervals through the gaps between the island-shaped portions 23b, so that the current is evenly distributed.

[0084] like Figures 2A to 2C As shown, the lower semiconductor layer 12b of each light-emitting unit 22 includes a first sidewall S1 not covered by the connecting electrode 60 and the insulating layer 23, and a second sidewall S2 below the middle portion 23a of the connecting electrode 60 and the insulating layer 23. The sidewall of the upper semiconductor layer 12a of each light-emitting unit 22 is designated as the upper sidewall SU. In the light-emitting element 1 with a series-connected light-emitting unit array, two adjacent light-emitting units 22 are electrically separated by a trench 36, and then electrically connected by a conductive structure spanning the trench 36. However, due to the high aspect ratio of the trench 36, the conductive structure is not easily uniformly covered on the trench 36 during manufacturing, and is prone to breakage and damage. Therefore, to ensure the reliability of the electrical connection between adjacent light-emitting units 22, the connecting electrode 60 and the middle portion 23a of the insulating layer must be well attached to and cover the sidewalls of the semiconductor stack 12; therefore, the inner angle θ2 between the second sidewall S2 and the upper surface 10a of the substrate 10 is an acute angle, and the inner angle (not shown) between the upper sidewall SU and the upper surface 10a of the substrate 10 is an acute angle. In one embodiment, θ2 is less than 80 degrees; in another embodiment, θ2 is between 20 and 80 degrees. Furthermore, as... Figures 2A to 2C As shown, the first sidewall S1 in each light-emitting unit 22 forms an obtuse angle θ1 with the inner surface 10a of the substrate 10. In one embodiment, θ1 is between 100 and 160 degrees.

[0085] like Figure 1 , Figures 2A to 2DAs shown, each light emitting unit 22 has a rectangular shape in a top view and has four edges, wherein a plurality of first side walls S1 and at least one second side wall S2 are located on the four edges. In one embodiment, one of the first side walls S1 and the second side wall S2 are located on the same edge of one light emitting unit 22, and the other or more first side walls S1 are located on edges other than the edge on which the second side wall S2 is located. In another embodiment, in a top view, the length of the second side wall S2 extending along the edge on which it is located is substantially equal to the length of the edge on which it is located, and the first side wall S1 is located only on edges other than the edge on which the second side wall S2 is located.

[0086] In one embodiment, the length of the second side wall S2 extending along the edge on which it is located is greater than or equal to 10 μm. Figure 1 and Figure 2D In a top view, the length of the second side wall S2 extending along the edge on which it is located is greater than or equal to the length of the intermediate portion 23a of the insulating layer 23 extending along the edge on which the light emitting unit 22 is located, for example, greater than 10 μm. In this way, it can be ensured that the insulating layer 23 is conformally attached to and covers the side wall of the semiconductor stack 12.

[0087] Figure 3 A scanning electron microscope (SEM) image of the side wall of the semiconductor stack 12 in the first embodiment is shown. The entire surface of the first side wall S1 is uneven on the upper surface 10a of the substrate 10. In more detail, the first side wall S1 has unevenness in the form of concave and convex.

[0088] Figure 4 A partial enlarged view of a cross section of the side wall of the semiconductor stack 12 in the light emitting element of the second embodiment is shown. The light emitting element of the second embodiment is similar to the light emitting element 1 of the first embodiment, and the difference is that the first side wall S1 includes a first sub-side wall S11 connected to the upper surface 121a of the first semiconductor layer 121 and a second sub-side wall S12 located between the first sub-side wall S11 and the substrate 10. The included angle θ3 between the first sub-side wall S11 and the upper surface 121a of the first semiconductor layer 121 is an obtuse angle, and the included angle θ1 between the second sub-side wall S12 and the upper surface 10a of the substrate 10 is an obtuse angle. In the second embodiment, the first side wall S1 having a plurality of sub-side walls allows light to be extracted from the first side wall S1 after being refracted and / or reflected.

[0089] In one embodiment, the included angle (not shown) between the first sub-side wall S11 and the second sub-side wall S12 is greater than or equal to 90 degrees.

[0090] In one embodiment, θ3 is greater than or equal to 90 degrees; in one embodiment, θ3 is between 100 and 160 degrees. In this embodiment, in a side view, the length of the second sub-side wall S12 is greater than the length of the first sub-side wall S11.

[0091] In one embodiment, when the upper surface 10a of the substrate has a patterned structure P, the overall surface of the second sub-sidewall S12 is uneven. More specifically, the second sub-sidewall S12 has an uneven, undulating shape. In one embodiment, when the upper surface 10a of the substrate has a patterned structure P, the overall surface of the second sub-sidewall S12 is uneven while the overall surface of the first sub-sidewall S11 is smooth. In one embodiment, the surface roughness of the second sub-sidewall S12 is greater than the surface roughness of the first sub-sidewall S11.

[0092] To clearly illustrate the relative relationship of the semiconductor stack 12 between two adjacent light-emitting units 22, Figure 5A For the reason Figure 1 A schematic diagram of the three-dimensional structure shown in the X1 direction. Figure 5A In this figure, only the semiconductor stack 12 of the light-emitting units 22e and 22f is shown; the patterned structure P, insulating layer 23, connecting electrode 60, first extended electrode 202, second extended electrode 302, and transparent conductive layer 18 are omitted. Figure 5A As shown, light-emitting units 22e and 22f are adjacent and separated by a groove 36. On their facing edges, they each have a first sidewall S1 and a second sidewall S2. The first sidewall S1 and the second sidewall S2 each have a first lower edge E1 and a second lower edge E2; wherein the second lower edge E2 is closer to its adjacent light-emitting unit than the first lower edge E1. When viewed from above, as... Figure 2D As shown, the bottom width W2 of the trench 36 below the insulating layer 23 is the distance between the second lower edges E2 of the second sidewalls S2 of two adjacent light-emitting units 22. Figure 5A The bottom width W1 of the other parts of the groove 36 shown is the distance between the first lower edges E1 of the first sidewalls S1 of two adjacent light-emitting units 22; wherein the bottom width W2 is smaller than the bottom width W1. Furthermore, Figure 5A The first upper edge E1' of the first sidewall S1 and the second upper edge E2' of the second sidewall S2 are connected and form a straight line. In another embodiment, they are not connected in a straight line, that is, the two upper edges are not aligned with the same plane, and the second upper edge E2' protrudes outward in the y-axis direction and is closer to its adjacent light-emitting unit than the first upper edge E1'.

[0093] Furthermore, the patterned structure P located between two adjacent second sidewalls S2 has different dimensions and / or different morphologies than the patterned structures P in other areas of the substrate 10. For example, the patterned structure P located between two adjacent second sidewalls S2 or directly below the middle portion 23a of the insulating layer 23 is conical or hemispherical, while the patterned structures P in other areas, such as the patterned structure P located between two adjacent first sidewalls S1 of the light-emitting unit, is pyramidal, polygonal, tetrahedral, or a platform structure with a polygonal base.

[0094] In addition, the sidewall of the lower semiconductor layer 12b comprises a sandwich surface Sx located below the first sidewall S1 and the second sidewall S2. The sandwich surface Sx is a triangle in a side view, and the base of the triangle is connected to the upper surface 10a of the substrate. The second sidewall S2, which forms an acute angle with the upper surface 10a of the substrate, can ensure the reliability of the electrical connection between adjacent light emitting units 22; the first sidewall S1, which forms an obtuse angle with the upper surface 10a of the substrate, can reduce the internal total reflection of light in the semiconductor stack, which is conducive to extracting light from the semiconductor stack 12 and improving the light extraction efficiency of the light emitting element 1. When the connecting electrode 60 is a light shielding material, such as a non-transparent metal, the light blocked by the connecting electrode 60 on the second sidewall S2 can be extracted from the sandwich surface Sx through reflection and / or refraction, thereby increasing the light extraction efficiency of the light emitting element 1.

[0095] When the distance between multiple light emitting units is too close, the light emitted by the semiconductor stack 12 can be absorbed by the layers arranged between adjacent light emitting units or between them, resulting in poor light extraction efficiency. Therefore, in an embodiment, the minimum bottom width of the trench 36 is greater than 5 μm; more specifically, the distance W2 between the second lower edges E2 of the two second sidewalls S2 of two adjacent light emitting units facing each other should be greater than 5 μm.

[0096] Similarly, Figure 5B In the light emitting element of the second embodiment, a schematic diagram of the three-dimensional structure shown in the X1 direction is shown. The difference between Figure 5A is that, Figure 5B In the first embodiment, the first sidewall S1 comprises a first sub-sidewall S11 connected to the upper surface 121a of the first semiconductor layer 121, and a second sub-sidewall S12 located between the first sub-sidewall S11 and the substrate 10.

[0097] The above embodiments are described with Figure 1 A-A' section, B-B' section and C-C' section in the second embodiment; however, those skilled in the art can understand the sidewall structure of the semiconductor stack of each light emitting unit 22 through the disclosure of the present application. For example, the semiconductor stack sidewall between the light emitting units 22c and 22f, and the semiconductor stack sidewall between the light emitting units 22a and 22d, as there is no insulation layer 23 and connecting electrode 60 arranged, the two adjacent semiconductor stack sidewalls should be formed with the first sidewall S1 as shown in Figure 2C For example, the semiconductor stack sidewall of each light emitting unit 22 close to the periphery of the light emitting element 1 should be formed with the first sidewall S1 as shown in the leftmost and rightmost semiconductor stack sidewalls in the second embodiment. Figure 2C For example, the semiconductor stack sidewall of each light emitting unit 22 close to the periphery of the light emitting element 1 should be formed with the first sidewall S1 as shown in the leftmost and rightmost semiconductor stack sidewalls in the second embodiment.

[0098] Figures 6A to 6H A method for manufacturing a light emitting element according to an embodiment of the present application is shown. First, as shown inFigure 6A As shown, a semiconductor stack 12 is formed on a substrate 10. In this embodiment, the substrate in the manufacturing process and the substrate of the final light emitting device are both denoted by the same reference numeral for the sake of convenience. The substrate 10 in this manufacturing process comprises a wafer or a carrier having a sufficient area for the subsequent manufacturing processes to be performed. The substrate 10 and the semiconductor stack 12 formed thereon constitute a semiconductor wafer. Next, as shown in Figure 6B As shown, portions of the semiconductor stack 12 are removed until the upper surface 10a of the substrate 10 is exposed, forming trenches 36, and portions of the semiconductor stack 12 are removed until the upper surface 121a of the first semiconductor layer 121 is exposed, forming platform regions 28. The trenches 36 divide the semiconductor stack 12 into a plurality of regions, defining a plurality of light emitting units 22. Next, a protective layer 8 is formed on all of the light emitting units 22, the trenches 36, and the upper surface 10a of the substrate. In one embodiment, the thickness of the protective layer 8 is about 1000 nm. The material of the protective layer 8 can be selected from silicon oxide, silicon nitride, or a combination thereof. The protective layer 8 can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or spin-coating. As shown, a semiconductor stack 12 is formed on a substrate 10. In this embodiment, the substrate in the manufacturing process and the substrate of the final light emitting device are both denoted by the same reference numeral for the sake of convenience. The substrate 10 in this manufacturing process comprises a wafer or a carrier having a sufficient area for the subsequent manufacturing processes to be performed. The substrate 10 and the semiconductor stack 12 formed thereon constitute a semiconductor wafer. Next, as shown in

[0099] Next, as shown in Figure 6C and Figure 6D the intermediate manufacturing process steps are shown in cross-section along B-B’ and C-C’, respectively. The protective layer openings are disposed along the edges of each light emitting unit 22 and the trenches 36, except for the portions of the edges of the light emitting units 22 where the connecting electrodes 60 and the insulating layer 23 are to be formed. That is, the portions of the edges of the light emitting units 22 where the connecting electrodes 60 and the insulating layer 23 are to be formed do not have protective layer openings. Figure 6C Figure 6D the intermediate manufacturing process steps are shown in cross-section along B-B’ and C-C’, respectively. The protective layer openings are disposed along the edges of each light emitting unit 22 and the trenches 36, except for the portions of the edges of the light emitting units 22 where the connecting electrodes 60 and the insulating layer 23 are to be formed. That is, the portions of the edges of the light emitting units 22 where the connecting electrodes 60 and the insulating layer 23 are to be formed do not have protective layer openings. Figure 1 Next, as shown in

[0100] and Figure 6E the intermediate manufacturing process steps are shown in cross-section along B-B’ and C-C’, respectively. The protective layer openings are disposed along the edges of each light emitting unit 22 and the trenches 36, except for the portions of the edges of the light emitting units 22 where the connecting electrodes 60 and the insulating layer 23 are to be formed. That is, the portions of the edges of the light emitting units 22 where the connecting electrodes 60 and the insulating layer 23 are to be formed do not have protective layer openings. Figure 6F Figure 6E the intermediate manufacturing process steps are shown in cross-section along B-B’ and C-C’, respectively. The protective layer openings are disposed along the edges of each light emitting unit 22 and the trenches 36, except for the portions of the edges of the light emitting units 22 where the connecting electrodes 60 and the insulating layer 23 are to be formed. That is, the portions of the edges of the light emitting units 22 where the connecting electrodes 60 and the insulating layer 23 are to be formed do not have protective layer openings. Figure 6F Figure 1 ​​​Intermediate fabrication process steps for the B-B' and C-C' sections. In one embodiment, the etching step employs wet etching to remove a portion of the lower semiconductor layer 12b in the protective layer opening, forming the first sidewall S1. In another embodiment, the etching step further includes etching the patterned structure P of the upper surface 10a of the substrate in the protective layer opening. In one embodiment, the etching solution may be selected from sulfuric acid, phosphoric acid, hydrochloric acid, hydrofluoric acid, or combinations thereof. In one embodiment, after the formation of the first sidewall S1, a roughening step may be performed on the first sidewall S1. For example, the first sidewall S1 may be etched with potassium hydroxide to form a roughened structure. In one embodiment, after etching, the patterned structure P covered by the protective layer 8 and the patterned structure P not covered by the protective layer 8 have different sizes and / or different morphologies. For example, the patterned structure P covered by the protective layer 8 is conical or hemispherical; while after etching, the patterned structure P not covered by the protective layer 8 has a pyramidal, polygonal, tetrahedral, or platform structure with a polygonal base, etc. The angle θ1 between the first sidewall S1 and the upper surface 10a of the substrate can be controlled by the composition of the etching solution, the etching time, and the temperature.

[0101] Next, as Figure 6G and Figure 6H As shown, remove the protective layer 8. Figure 6G and Figure 6H Display respectively Figure 1 Intermediate fabrication steps for the B-B' and C-C' cross sections. After the protective layer 8 is removed, the fabrication steps for the insulating layer, transparent conductive layer, and conductive structure are performed (not shown). Finally, the light-emitting elements are separated, and each light-emitting element contains multiple light-emitting units 22 connected in series. For example, the back side of the substrate 10 is irradiated with a laser 17 to form a modified region inside the substrate 10 (not shown), and then cracks are formed along the crystal plane of the substrate from the modified region to separate the light-emitting elements. The lower semiconductor layer 12b of each light-emitting unit 22 includes a first sidewall S1 and a second sidewall S2 on which the connecting electrode 60 and the insulating layer 23 will be formed in subsequent fabrication processes.

[0102] In one embodiment, such as Figure 7 As shown, the protective layer 8 is not completely removed, but is retained and subjected to photolithography and etching processes to pattern it and form an insulating layer 23, followed by the fabrication of a transparent conductive layer, conductive structure and other steps (not shown in the figure).

[0103] In one embodiment, by adjusting the width of the protective layer opening and / or the width of the pre-etching trench 36, and in combination with the aforementioned different etching conditions, a first sidewall S1 as in the first embodiment or a first sidewall S1 having multiple sub-sidewalls as in the second embodiment can be obtained.

[0104] Figure 8It is a light-emitting element 3 disclosed in the third embodiment of the present invention; Figure 9A for Figure 8 Cross-sectional view along line segment A-A'; Figure 9B for Figure 8 A cross-sectional view along line segment B-B' or line segment C-C'.

[0105] The structure of the light-emitting element 3 in the third embodiment is similar to that of the light-emitting element 1 in the first embodiment, except that the first sidewall S1, which has an obtuse angle with the inner surface 10a of the substrate, is only disposed on the sidewall of the semiconductor stack 12 surrounding the light-emitting element 3. More specifically, the first sidewall S1 is only disposed on the outer edges of the light-emitting units 22 arranged on the periphery of the light-emitting element 3, and not on the adjacent edges between any two adjacent light-emitting units 22. In this embodiment, the light-emitting units 22 of the light-emitting element 3 are arranged in a 3×2 two-dimensional matrix, and the light-emitting units 22a-22f are all peripheral light-emitting units. The first sidewall S1 is disposed on the outer edges Eax, Edx, Eex, Eey, Efy, Efx, Ecx, Ebx, Eby and Eay of the light-emitting units 22a-22f; the second sidewall S2, which has an acute angle with the inner surface 10a of the substrate, is disposed on the adjacent edges between any two adjacent light-emitting units 22 (22a-22f).

[0106] Depend on Figure 9A and Figure 9B It can be seen that the cross-sectional structure of light-emitting unit 22a and light-emitting unit 22e along A-A' is either composed of... Figure 8 When viewed along the Y2 direction, the lower semiconductor layer 12b appears as a parallelogram-like shape. This parallelogram-like shape consists of a pair of parallel opposite sides and a pair of acute opposite angles with unequal angles. These two acute opposite angles cause the other pair of opposite sides of the parallelogram-like shape to be non-parallel. For example... Figure 9A As shown, in the light-emitting element 22a: the first sidewall S1 located at the outer edge Eay has an obtuse angle θ1 with the inner angle θ1 of the upper surface 10a of the substrate and an acute angle θ3 with the inner angle θ3 of the upper surface of the lower semiconductor layer 12b; the first sidewall S1 located at the outer edge Eax has an obtuse angle θ1 with the inner angle θ1 of the upper surface 10a of the substrate, and when viewed from the Y2 direction, the first sidewall S1 is a parallelogram-like or parallelogram-like shape; and the second sidewall S2 of the lower semiconductor layer 12b facing the light-emitting units 22d and 22b is an acute angle with the inner angle θ2 of the upper surface 10a of the substrate. That is, the first sidewall S1 is disposed on the two outer edges Eax and Eay of the light-emitting unit 22a, and the second sidewall S2 is disposed on the other two edges of the light-emitting unit 22a.

[0107] Depend on Figure 8Viewed from the Y2 direction, when θ3 and θ2 are substantially equal, the lower semiconductor layer 12b of the light-emitting unit 22a is a parallelogram. When θ3 and θ2 are not equal, the lower semiconductor layer 12b of the light-emitting unit 22a is a near-parallelogram. In one embodiment, the difference between θ3 and θ2 is less than 40 degrees. The lower semiconductor layer 12b of the light-emitting unit 22e has the same structure as the lower semiconductor layer 12b of the light-emitting unit 22a.

[0108] like Figure 9A As shown, in the light-emitting element 22d, the sidewall of the lower semiconductor layer 12b facing the light-emitting units 22a, 22c, and 22e is a second sidewall S2 with an acute angle to the inner surface of the upper surface 10a of the substrate. The light-emitting unit 22d has a cross-sectional structure along A-A', or is composed of... Figure 8 When viewed from the Y2 direction, the lower semiconductor layer 12b is trapezoidal. The angles of the two base angles of the trapezoid, i.e., the two θ2 angles in the light-emitting unit 22d, can be equal or unequal. The first sidewall S1 on the outer edge Edx of the light-emitting unit 22d forms an obtuse angle with the inner angle of the upper surface 10a of the substrate, and when viewed from the Y2 direction, the first sidewall S1 is trapezoidal. That is, the first sidewall S1 is disposed on the outer edge Edx of the light-emitting unit 22d, and the second sidewall S2 is disposed on the other three edges of the light-emitting unit 22d.

[0109] Figure 9B show Figure 8 A cross-sectional view along line segment B-B' or C-C'. (From...) Figure 9B It can be seen that the cross-sectional structure of light-emitting unit 22f and light-emitting unit 22e along B-B' is either... Figure 8 When viewed in the X1 direction, the lower semiconductor layer 12 of the light-emitting unit 22f and the light-emitting unit 22e are approximately parallelogram-shaped or parallelogram-shaped. In the light-emitting element 22f: the first sidewall S1 located at the outer edge Efx has an obtuse angle θ1 with the inner angle θ1 of the upper surface 10a of the substrate and an acute angle θ3 with the inner angle θ3 of the upper surface of the lower semiconductor layer 12b; and the second sidewall S2 adjacent to the light-emitting unit 22e has an acute angle θ2 with the inner angle θ2 of the upper surface 10a of the substrate.

[0110] Depend on Figure 8 Viewed from the X1 direction, when θ3 and θ2 are substantially equal, the lower semiconductor layer 12b of the light-emitting units 22e and 22f is a parallelogram. When θ3 and θ2 are not equal, the lower semiconductor layer 12b of the light-emitting units 22e and 22f is a near-parallelogram. In one embodiment, the difference between θ3 and θ2 is less than 40 degrees. Similarly, when viewed from the opposite X1 direction, the light-emitting units 22a and 22b also have the same structure as described above, and therefore will not be repeated.

[0111] The lower semiconductor layer 12b of the light emitting unit 22c has the same structure as the light emitting unit 22d, and the lower semiconductor layer 12b of the light emitting unit 22b has the same structure as the light emitting unit 22a.

[0112] In one embodiment, the surface of the first side wall S1 is uneven, as in the aforementioned light emitting element 1.

[0113] In each light emitting unit 22 of the light emitting element 3, the side wall of the lower semiconductor layer 12b facing the adjacent light emitting unit 22 is a second side wall S2 forming an acute internal angle with the upper surface 10a of the substrate, and the connecting electrode 60 is disposed on the second side wall S2, so that the reliability of the electrical connection between the adjacent light emitting units 22 can be ensured; the side wall of the lower semiconductor layer 12b at the peripheral edge of the light emitting element 3 is a first side wall S1 forming an obtuse internal angle with the upper surface 10a of the substrate, so that the internal total reflection of light in the semiconductor stack can be reduced, which is beneficial to extracting light from the semiconductor stack 12 and improving the light extraction efficiency of the light emitting element 3.

[0114] In the present embodiment, the arrangement manner and number of the light emitting units 22 in the light emitting element 3 are not limited to a two-dimensional matrix arrangement of 3x2. The light emitting element 3 can include a single row of light emitting unit string, a 2x2 light emitting unit matrix, or a light emitting unit matrix of 3x2 or more. In addition, the number of light emitting units in each row or the number of light emitting units in each column can be equal or unequal. In one embodiment, when the light emitting element 3 is a single row of light emitting unit string, and each light emitting unit is rectangular, in the light emitting units at the beginning and end of the string, the first side wall S1 forming an obtuse internal angle with the upper surface 10a of the substrate is disposed on three edges of the light emitting unit; the second side wall S2 forming an acute internal angle with the upper surface 10a of the substrate is disposed on the remaining one edge of the light emitting unit. In another embodiment, when the light emitting element 3 includes a light emitting unit matrix of 3x3 or more, and each light emitting unit is rectangular, at least one light emitting unit has four edges, each of which is a second side wall S2 forming an acute internal angle with the upper surface 10a of the substrate.

[0115] In the present embodiment, the first side wall S1 can also include a first sub-side wall S11 connected to the upper surface 121a of the first semiconductor layer 121, and a second sub-side wall S12 between the first sub-side wall S11 and the substrate 10, as shown in FIG. 6. Figure 4 The internal angle θ3 between the first sub-side wall S11 and the upper surface 121a of the first semiconductor layer 121 is an obtuse angle, and the internal angle θ1 between the second sub-side wall S12 and the upper surface 10a of the substrate is an obtuse angle.

[0116] Figures 10A to 10C A manufacturing method of the light emitting element 3 according to an embodiment of the present application is shown. Figure 10A A manufacturing method of the light emitting element 3 according to an embodiment of the present application is shown. Figure 8Intermediate fabrication process step of cross-section A-A'. First, as shown in Figure 10A the first embodiment, a semiconductor stack 12 is formed on the substrate 10 to form a semiconductor wafer; then, portions of the semiconductor stack 12 are removed until the substrate upper surface 10a is exposed to form the trenches 36, and portions of the semiconductor stack 12 are removed until the upper surface 121a of the first semiconductor layer 121 is exposed to form the mesa regions 28. The trenches 36 divide the semiconductor stack 12 into a plurality of regions, defining a plurality of light emitting elements 3. In this step, the lower semiconductor layers 12b of adjacent light emitting elements 3 in the semiconductor wafer are connected. Then, a passivation layer 8 is formed on all the light emitting elements 22, the trenches 36 and the substrate upper surface 10a. In one embodiment, the passivation layer 8 has a thickness of about 1 μm to about 5 μm. The material of the passivation layer 8 can be selected from silicon oxide, silicon nitride or a combination thereof. The passivation layer 8 can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD) or spin-coating.

[0117] Then, a dicing line 13 formation step is performed. As shown in Figure 10B a laser 27 is irradiated from the upper surface of the passivation layer 8. The laser 27 scribes the semiconductor stack 12 downward from the upper surface of the passivation layer 8 to form the dicing line 13. As viewed from the side, the dicing line 13 extends downward to a depth in the lower semiconductor layer 12b, or to a depth in the substrate 10, or to the substrate upper surface 10a. At the same time, the dicing line 13 defines a plurality of light emitting elements 3 in the semiconductor wafer. That is, the dicing line 13 defines the periphery of each light emitting element 3. In one embodiment, the laser 27 scribes the semiconductor stack 12 downward from the upper surface of the passivation layer 8 to a depth in the substrate 10, forming a roughened region (not shown) in the substrate 10. In one embodiment, a dry etching step, such as an inductively coupled plasma (ICP) etching, is performed from the upper surface of the passivation layer 8 to etch the semiconductor stack 12 downward to a depth to form the dicing line 13.

[0118] Then, as shown in Figure 10C ​As shown, an etching step is performed on the semiconductor stack 12. In one embodiment, the etching step employs a wet etching to remove a portion of the lower semiconductor layer 12b in the gap formed by the scribe line 13 to form the first side wall S1. In another embodiment, the etching step also includes etching the patterned structure P on the upper surface 10a of the substrate 10 under the scribe line 13. In one embodiment, the etching solution includes sulfuric acid, phosphoric acid, hydrochloric acid, hydrofluoric acid or a combination thereof. In one embodiment, after the first side wall S1 is formed, a roughening step can be performed on the first side wall S1. For example, the first side wall S1 is etched with potassium hydroxide to form a rough structure (not shown) on the first side wall S1. In one embodiment, after the etching, the patterned structure P covered by the protective layer 8 and the patterned structure P not covered by the protective layer 8 have different dimensions and / or different topographies. For example, the patterned structure P covered by the protective layer 8 is conical or hemispherical, while the patterned structure P not covered by the protective layer 8 has an angular pyramid, a polygon, a tetrahedron or a platform structure with a polygonal base after the etching. The angle of the inner angle θ1 between the first side wall S1 and the upper surface 10a of the substrate 10 can be controlled by the composition of the etching solution, the etching time and the temperature.

[0119] Next, the protective layer 8 is removed. After the protective layer 8 is removed, the fabrication steps of the insulating layer, the transparent conductive layer, the conductive structure and the like are performed (not shown). In one embodiment, the protective layer 8 is not completely removed, but is retained and patterned by photolithography or etching to form the insulating layer 23, and then the fabrication steps of the transparent conductive layer, the conductive structure and the like are performed (not shown).

[0120] Finally, the semiconductor wafer is divided along the scribe line 13, i.e. around the light emitting element 3, to form a plurality of light emitting elements 3. The division method is the same as the fabrication method of the light emitting element 1 described above, and is not described again.

[0121] In one embodiment, in the scribe line 13 forming step, when the laser 27 cuts the semiconductor stack 12 to a depth inside the substrate 10 and forms a rough region (not shown) inside the substrate 10, after the semiconductor wafer is divided to form a plurality of light emitting elements 3, a rough region is formed on the side wall of the substrate 10 corresponding to the rough region, connected to the upper surface 10a of the substrate 10.

[0122] In another embodiment of the method of manufacturing the light emitting element 3, there is no step of forming the dicing lines 13, but the trenches 36 are used to define the light emitting elements 3 as in the method of manufacturing the light emitting element 1 described above. For example, the semiconductor stack 12 is etched down to the substrate upper surface 10a by dry etching. Then, the protective layer 8 is formed on the light emitting units 22, the trenches 36 and the substrate upper surface 10a. Then, the protective layer openings are formed by photolithography and etching. Unlike the method of manufacturing the light emitting element 1, the protective layer openings are only located around the light emitting elements 3, but not along the edges of the light emitting units and the trenches 36 as in the method of manufacturing the light emitting element 1 described above. Similarly, the etching step is performed by wet etching to remove a portion of the lower semiconductor layer 12b in the protective layer openings to form the first side walls S1 around the light emitting elements 3.

[0123] The above embodiments are only illustrative of the principles and effects of the present application, and are not intended to limit the present application. Any person skilled in the art can modify and change the above embodiments without departing from the technical principles and spirit of the present application. Therefore, the scope of protection of the present application should be subject to the appended claims.

Claims

1. A light emitting element characterized by comprising: A light emitting element comprising: a substrate comprising an upper surface; a first light emitting unit and a second light emitting unit respectively located on the upper surface, wherein the first light emitting unit and the second light emitting unit respectively comprise a lower semiconductor layer and an upper semiconductor layer; and a conductive structure located on the first light emitting unit and the second light emitting unit, electrically connecting the first light emitting unit and the second light emitting unit; wherein the lower semiconductor layer of the first light emitting unit and the second light emitting unit respectively comprises: a first upper surface not covered by the upper semiconductor layer; a first sidewall; and a second sidewall located below the conductive structure, wherein the inner angle between the second sidewall and the upper surface is an acute angle; wherein the first light emitting unit and the second light emitting unit have a shortest distance between them, the shortest distance being located between the second sidewalls.

2. The light emitting element of claim 1, wherein the first sidewall of the first light emitting unit comprises a first sub-sidewall and a second sub-sidewall, the inner angle between the first sub-sidewall and the first upper surface is an obtuse angle, and the inner angle between the second sub-sidewall and the first upper surface is an obtuse angle.

3. The light emitting element of claim 2, wherein the first sub-sidewall is connected to the second sub-sidewall.

4. The light emitting element of claim 2, wherein the first sub-sidewall is connected to the second sidewall.

5. The light emitting element of claim 1, wherein the first sidewall and the second sidewall of the first light emitting unit both face the second light emitting unit, the first sidewall and the second sidewall of the first light emitting unit respectively comprise an upper edge, and the upper edge of the second sidewall is closer to the second light emitting unit than the upper edge of the first sidewall.

6. The light emitting element of claim 1, wherein the lower semiconductor layer of the first light emitting unit comprises a facet located between the first sidewall and the second sidewall of the first light emitting unit, the facet is a triangle shape as viewed from the side, and a base of the triangle is connected to the upper surface of the substrate.

7. The light emitting element of claim 1, further comprising an insulating layer located below the conductive structure.

8. The light emitting element of claim 7, wherein: the upper surface of the substrate comprises a plurality of patterned structures; and a portion of the plurality of patterned structures is covered by the insulating layer, and another portion of the plurality of patterned structures is not covered by the insulating layer; wherein the portion of the plurality of patterned structures and the another portion of the plurality of patterned structures have different sizes and / or different topographies. A light emitting element comprising:

9. A light emitting element characterized by comprising: a substrate comprising an upper surface; a first light emitting unit and a second light emitting unit respectively located on the upper surface, wherein the first light emitting unit and the second light emitting unit respectively comprise a lower semiconductor layer and an upper semiconductor layer; and a conductive structure located on the first light emitting unit and the second light emitting unit, electrically connecting the first light emitting unit and the second light emitting unit; wherein the lower semiconductor layer of the first light emitting unit comprises: a first edge; a first sidewall located at a peripheral region of the light emitting element; and a second sidewall facing the second light emitting unit and extending along the first edge, the inner angle between the second sidewall and the upper surface is an acute angle. ​ ​ wherein the first sidewall and the upper surface form an obtuse angle, and the first sidewall is a parallelogram-like shape from a normal direction of the first sidewall, the parallelogram-like shape including a pair of opposite angles, wherein the pair of opposite angles includes a first acute angle and a second acute angle; wherein the second sidewall extends along a length of the first edge substantially equal to a length of the first edge.

10. The light emitting element of claim 9, wherein the second sidewall is not located in the peripheral region of the light emitting element.

11. The light emitting element of claim 10, wherein the conductive structure is located on the second sidewall.

12. The light emitting element of claim 9, wherein an angle difference between the first acute angle and the second acute angle is less than 40 degrees.

13. The light emitting element of claim 9, wherein the lower semiconductor layer of the second light emitting unit includes a third sidewall located in the peripheral region of the light emitting element, wherein the third sidewall and the upper surface form an obtuse angle, and the third sidewall is a right trapezoid from a side view.

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