Organic light emitting diode display device

Abstract

An organic light emitting diode display device is provided, the organic light emitting diode display device comprising a substrate, a light emitting layer, a first power supply wiring, a second power supply wiring, a connection pattern and an upper electrode. The substrate has a display area, a peripheral area and a pad area, the peripheral area surrounds the display area and includes a first peripheral area, a second peripheral area and a third peripheral area, and the pad area is arranged on one side of the peripheral area. The light emitting layer is arranged in the display area on the substrate. The first power supply wiring is arranged in a part of the first peripheral area, the second peripheral area and the third peripheral area on the substrate. The second power supply wiring is arranged in the display area, the first peripheral area and the third peripheral area on the substrate and is not arranged in the second peripheral area, and is positioned inside the first power supply wiring.

Description

Technical Field

[0001] Exemplary embodiments of the invention relate generally to an organic light emitting diode display device, and more particularly, to an organic light emitting diode display device including a low power wiring and a high power wiring. Background Art

[0002] Flat panel display devices are used as display devices instead of cathode ray tube display devices due to their light weight and thinness. As representative examples of such flat panel display devices, there are liquid crystal display devices and organic light emitting diode display devices.

[0003] An organic light emitting diode display device may include a display area, a peripheral area surrounding the display area, and a pad area on one side of the peripheral area. A plurality of pixel circuits and a plurality of organic light emitting diodes may be arranged in the display area, and a first power wiring and a second power wiring may be arranged in the peripheral area. In addition, a plurality of pad electrodes may be arranged in the pad area. For example, a low power supply voltage and a high power supply voltage may be generated from an external device, and the voltages may be provided to the first power wiring and the second power wiring, respectively, through the pad electrodes. In addition, the low power supply voltage applied to the first power wiring may be provided to the cathode electrode of the organic light emitting diode, and the high power supply voltage applied to the second power wiring may be provided to the anode electrode of the organic light emitting diode. In other words, the first power wiring and the second power wiring are arranged together in the peripheral area, so that the width of the first power wiring may be relatively small. The above information disclosed in this background technology section is only used for understanding the background of the inventive concept, and therefore, the information may contain information that does not constitute prior art. Summary of the invention

[0004] The applicant has found that when an organic light emitting diode display device having a first power wiring and a second power wiring is driven at high brightness, current is concentrated in the first power wiring disposed in a peripheral region (e.g., both lower side ends of the peripheral region) adjacent to the pad region, thereby increasing the temperature. In this case, the first power wiring may be short-circuited, or an insulating layer positioned around the first power wiring may be deformed due to heat generation.

[0005] A display device constructed according to an exemplary embodiment of the invention prevents a short circuit and thermal damage by reducing heat generated in a power wiring in a portion of a peripheral area.

[0006] For example, the first power wiring and the connection pattern of the display may have a relatively wide width so that heat generated in the first power wiring positioned in a portion of the peripheral area of ​​the display may be reduced compared to a conventional display.

[0007] In addition, a relatively larger number of openings can be provided so that the connection pattern is in direct contact with the first power wiring provided in a portion of the peripheral region. In other words, in the display device, the heat generated in the first power wiring in the peripheral region can be further reduced. Therefore, compared with the conventional design, defects in the display device caused by heat generation in the peripheral region of the first power wiring can be reduced.

[0008] Additional features of the inventive concepts will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the inventive concepts.

[0009] According to some exemplary embodiments, an organic light emitting diode display device includes a substrate, a light emitting layer, a first power wiring, a second power wiring, a connection pattern and an upper electrode. The substrate has a display area, a peripheral area and a pad area, the peripheral area at least partially surrounds the display area and includes a first peripheral area, a second peripheral area and a third peripheral area, and the pad area is arranged on one side of the peripheral area. The light emitting layer is arranged on the substrate in the display area. The first power wiring is arranged on the substrate in a part of the first peripheral area, the second peripheral area and the third peripheral area. The second power wiring is arranged on the substrate in the display area, the first peripheral area and the third peripheral area and is not arranged in the second peripheral area, and is at least partially surrounded by the first power wiring. The conductive pattern overlaps with the first power wiring in a part of the first peripheral area, the second peripheral area and the third peripheral area on the first power wiring, and is electrically connected to the first power wiring. The upper electrode is arranged on the conductive pattern and the light emitting layer in a part of the peripheral area and the display area, and partially overlaps with the first power wiring and the conductive pattern. The upper electrode is electrically connected to the conductive pattern.

[0010] The organic light emitting diode display device may further include a plurality of pad electrodes disposed in a first portion of the pad region. The first peripheral region may be adjacent to the first portion of the pad region where the pad electrodes are disposed, and the second peripheral region may be located on an opposite side of the first peripheral region while being adjacent to a second portion of the pad region where no pad electrodes are disposed.

[0011] The first power wiring includes a wiring that may be electrically connected to the pad electrode in the first peripheral region.

[0012] At least one of the conductive pattern and the upper electrode may have a wavy shape in the first peripheral region.

[0013] A low power supply voltage may be applied to the first power supply wiring, and a high power supply voltage may be applied to the second power supply wiring.

[0014] The second power wiring includes a wiring that may include a first portion, a second portion, and a third portion, the first portion being disposed in the first peripheral region, the second portion being disposed in the display region and having a grid shape, and the third portion being disposed in a portion of the third peripheral region to at least partially surround the second portion. The first portion, the second portion, and the third portion of the second power wiring may be formed integrally with each other.

[0015] The first and second portions of the second power wiring may be connected to each other in the first peripheral region adjacent to a portion of the boundary between the display area and the peripheral region, and the second and third portions of the second power wiring may be connected to each other in the third peripheral region adjacent to another portion of the boundary between the display area and the peripheral region.

[0016] A third portion of the second power wiring may be spaced apart from an inner side of the first power wiring.

[0017] The third portion of the second power wiring may not be provided in the second peripheral region.

[0018] The second portion of the second power wiring may have a lattice shape in a portion of the display area, and may have a stripe shape in another portion of the display area.

[0019] The display area may be in a rectangular shape with curved corners. The curved corners of the display area may include: a first corner adjacent to the pad area; and a second corner facing the first corner.

[0020] The first corner may be adjacent to the second peripheral region, and the second corner may be adjacent to the third peripheral region.

[0021] The first power wiring may have a first width in the second peripheral region, and may have a second width in the third peripheral region, the second width being smaller than the first width.

[0022] The organic light emitting diode display device may further include a protective insulating layer, a first planarization layer, and a second planarization layer. The protective insulating layer may be disposed between the substrate and the light emitting layer in the display region and the peripheral region, and may define an opening in the second peripheral region. The first planarization layer may be disposed on the protective insulating layer in a portion of the peripheral region and the display region to expose the opening of the protective insulating layer. The second planarization layer may be disposed on the first planarization layer in a portion of the peripheral region and the display region, and may have a plurality of openings in the second peripheral region that expose the first power wiring.

[0023] The second planarization layer positioned in the first peripheral region may not form a plurality of openings exposing the first power wirings.

[0024] The second planarization layer positioned in the first peripheral region may have a wavy shape.

[0025] The organic light emitting diode display device may further include a plurality of concavo-convex patterns disposed between the first planarization layer and the second planarization layer.

[0026] The light emitting layer may extend from the display region to the peripheral region, and the light emitting layer positioned in the peripheral region may not overlap with the plurality of openings of the second planarization layer in the second peripheral region.

[0027] The organic light emitting diode display device may further include a lower electrode disposed in the display region on the second planarization layer. The upper electrode may be disposed on the lower electrode, and the upper electrode extends from the display region to the peripheral region.

[0028] The upper electrode may directly contact the conductive pattern in the second peripheral region.

[0029] The upper electrode may have a wavy shape in the first peripheral region, and the upper electrode may be in direct contact with the conductive pattern in the first peripheral region.

[0030] The lower electrode may be positioned on the same layer as the conductive pattern.

[0031] The first power wiring may include a first sub-power wiring and a second sub-power wiring. The first sub-power wiring may be disposed between the substrate and the protective insulating layer, and may be exposed by an opening of the protective insulating layer. The second sub-power wiring may be disposed between the first planarization layer and the second planarization layer, and may be in direct contact with the first sub-power wiring through the opening of the protective insulating layer. The second sub-power wiring may be exposed by an opening of the second planarization layer.

[0032] The conductive pattern includes a connection pattern that can directly contact the second sub power wiring through the plurality of openings of the second planarization layer.

[0033] The organic light emitting diode display device may further include: a semiconductor element disposed in the display region between the substrate and the protective insulating layer; and a wiring pattern and a connection electrode disposed in the display region between the first planarization layer and the second planarization layer.

[0034] The wiring pattern and the connection electrode may be positioned on the same layer as the second sub power supply wiring.

[0035] The semiconductor element may include: an active layer, which is arranged in a display area on a substrate; a gate insulating layer, which is arranged on the active layer; a gate electrode, which is arranged on the gate insulating layer; an interlayer insulating layer, which is arranged on the gate electrode; and a source electrode and a drain electrode, which are arranged on the interlayer insulating layer.

[0036] The source electrode and the drain electrode may be positioned on the same layer as the first sub power wiring.

[0037] According to some exemplary embodiments, an organic light emitting diode display device includes a substrate, a light emitting layer, a first power wiring, a second power wiring, a planarization layer, a connection pattern, and an upper electrode. The substrate has a display area, a peripheral area, and a pad area, the peripheral area at least partially surrounds the display area and includes a first peripheral area, a second peripheral area, and a third peripheral area, and the pad area is arranged on one side of the peripheral area. The light emitting layer is arranged on the substrate in the display area. The first power wiring is arranged on the substrate in a part of the first peripheral area, the second peripheral area, and the third peripheral area. The second power wiring is arranged on the substrate in the display area, the first peripheral area, and the third peripheral area and is not arranged in the second peripheral area, and is at least partially surrounded by the first power wiring. The planarization layer is arranged on the first power wiring and the second power wiring in a part of the peripheral area and the display area, and has a wavy shape in at least one of the first peripheral area, the second peripheral area, and the third peripheral area. The connection pattern partially overlaps with the first power wiring in a part of the first peripheral area, the second peripheral area, and the third peripheral area on the planarization layer, and is electrically connected to the first power wiring. The connection pattern has a wavy shape in at least one of the first peripheral area, the second peripheral area, and the third peripheral area. The upper electrode is arranged in a portion of the peripheral region and the display region on the connection pattern and the light emitting layer, and partially overlaps the first power wiring and the connection pattern. The upper electrode is electrically connected to the connection pattern and has a wavy shape in at least one of the first peripheral region, the second peripheral region, and the third peripheral region.

[0038] The organic light emitting diode display device may further include a plurality of concavo-convex patterns disposed between the planarization layer and the first power wiring.

[0039] The second power wiring includes a wiring that may include a first portion, a second portion, and a third portion, the first portion being disposed in the first peripheral region, the second portion being disposed in the display region and having a grid shape, and the third portion being disposed in a portion of the third peripheral region to at least partially surround the second portion. The first portion, the second portion, and the third portion of the second power wiring may be formed integrally with each other.

[0040] The second portion of the second power wiring may have a lattice shape in a portion of the display area, and may have a stripe shape in another portion of the display area.

[0041] According to some exemplary embodiments, a method for driving a display device is provided, the display device having: a substrate including a display area, a peripheral area and a pad area, the peripheral area at least partially surrounding the display area and including a first peripheral area, a second peripheral area and a third peripheral area; a light-emitting layer arranged on the substrate in the display area; a first power wiring arranged in at least two areas of the first peripheral area, the second peripheral area and the third peripheral area; and a second power wiring arranged in only two areas of the first peripheral area, the second peripheral area and the third peripheral area and the display area, the method comprising the following steps: applying a low power voltage to the first power wiring, and applying a high power voltage to the second power wiring.

[0042] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings illustrate exemplary embodiments of the invention and together with the description serve to explain the inventive concept, wherein the accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, in which:

[0044] Figure 1 is a plan view showing an organic light emitting diode display device constructed according to an exemplary embodiment of the invention;

[0045] Figure 2A It is shown that the Figure 1 A plan view of a first power wiring and a second power wiring in an organic light emitting diode display device;

[0046] Figure 2B is shown with included Figure 2A A plan view of an exemplary embodiment of a second power wiring in an organic light emitting diode display device;

[0047] Figure 2C is shown with included Figure 2A A plan view of another exemplary embodiment of a second power wiring in an organic light emitting diode display device;

[0048] Figure 2D is shown with included Figure 2A A plan view of yet another exemplary embodiment of a second power wiring in an organic light emitting diode display device;

[0049] Figure 3A It shows that the setting Figure 2A a plan view of a connection pattern on a first power wiring;

[0050] Figure 3Bis a plan view showing a conventional organic light emitting diode display device;

[0051] Figure 4 is shown electrically connected to Figure 1 A schematic block diagram of external devices of an organic light emitting diode display device;

[0052] Figure 5 It shows that the setting Figure 1 A circuit diagram of a representative sub-pixel circuit in a sub-pixel circuit region and an exemplary embodiment of an organic light emitting diode OLED disposed on the sub-pixel circuit;

[0053] Figure 6 is along Figure 3A A cross-sectional view taken along line II';

[0054] Figure 7 is along Figure 3A A cross-sectional view taken along line II-II';

[0055] Figures 8 to 26 is a cross-sectional view illustrating a method of manufacturing an organic light emitting diode display device according to an exemplary embodiment of the invention;

[0056] Fig. 27 and Fig.28 is a cross-sectional view showing an organic light emitting diode display device according to an exemplary embodiment of the invention; and

[0057] Fig.29 and Fig.30 is a cross-sectional view showing an organic light emitting diode display device constructed according to an exemplary embodiment of the invention. DETAILED DESCRIPTION

[0058] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of various exemplary embodiments or implementations of the invention. "Embodiment" and "implementation" as used herein are interchangeable words and are non-limiting examples of devices or methods using one or more of the inventive concepts disclosed herein. However, it is apparent that various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other cases, in order to avoid making various exemplary embodiments unnecessarily obscure, known structures and devices are shown in block diagram form. In addition, various exemplary embodiments may be different, but need not be exclusive. For example, without departing from the inventive concept, the specific shape, configuration and features of the exemplary embodiment may be used or implemented in another exemplary embodiment.

[0059] Unless otherwise specified, the exemplary embodiments shown will be understood as providing exemplary features of various details that can actually implement some ways of the inventive concept. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter, individually or collectively referred to as "elements") of the various embodiments may be further combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0060] The use of cross hatching and / or shading is usually provided in the drawings to make the boundaries between adjacent elements clear. Thus, unless otherwise specified, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for the specific material, material properties, size, ratio, commonality between the elements shown and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for clarity and / or descriptive purposes. When the exemplary embodiments may be implemented differently, the specific process sequence may be performed in a different order than described. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described order. In addition, the same reference numerals represent the same elements.

[0061] When an element or layer is referred to as being "on" another element or layer, "connected to" or "bonded to" another element or layer, the element or layer may be directly on, directly connected to or directly bonded to the other element or layer, or there may be an intermediate element or intermediate layer. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly bonded to" another element or layer, there is no intermediate element or intermediate layer. For this reason, the term "connection" may refer to physical connection, electrical connection and / or fluid connection with or without intermediate elements. In addition, the D1 axis, the D2 axis and the D3 axis are not limited to the three axes of a rectangular coordinate system (such as an x-axis, a y-axis and a z-axis), and may be interpreted in a broader sense. For example, the D1 axis, the D2 axis and the D3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as any combination of only X, only Y, only Z, or two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0062] Although the terms "first", "second", etc. can be used here to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, the first element discussed below can be named as the second element without departing from the disclosed teachings.

[0063] For descriptive purposes, spatially relative terms such as "under," "below," "below," "down," "above," "upper," "above," "higher," "side" (e.g., as in "sidewall"), etc., may be used herein to describe the relationship of one element to another (other) element as shown in the accompanying drawings. Spatially relative terms are intended to include different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, an element described as "under" or "beneath" other elements or features will subsequently be positioned as "above" the other elements or features. Thus, the exemplary term "under" can include both above and below orientations. In addition, the device can be positioned otherwise (e.g., rotated 90 degrees or at other orientations), and as such, the spatially relative descriptors used herein are interpreted accordingly.

[0064] The terms used here are for the purpose of describing specific embodiments, and are not intended to be limited. As used here, unless the context clearly indicates otherwise, the singular forms "one", "one (kind / person)" and "said (the)" are also intended to include plural forms. In addition, when the terms "comprise", "include" and / or their variations are used in this specification, it is explained that there are stated features, integral bodies, steps, operations, elements, components and / or their groups, but it is not excluded that there are or add one or more other features, integral bodies, steps, operations, elements, components and / or their groups. It should also be noted that, as used here, the terms "substantially", "approximately" and other similar terms are used as approximate terms rather than as terms of degree, so that they are used to explain the inherent deviations in measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0065] Various exemplary embodiments are described herein with reference to cross-sectional views and / or exploded illustrations as schematic diagrams of idealized exemplary embodiments and / or intermediate structures. As such, variations in the shapes of the illustrations, such as those caused by manufacturing techniques and / or tolerances, will be expected. Therefore, the exemplary embodiments disclosed herein should not necessarily be interpreted as being limited to the specific illustrated shapes of the regions, but will include deviations in shape caused by, for example, manufacturing. In this way, the regions shown in the drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and as such, no limitation is necessarily intended.

[0066] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this disclosure is a part. Terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless explicitly so defined herein.

[0067] Hereinafter, exemplary embodiments will be explained in detail with reference to the accompanying drawings.

[0068] Figure 1 is a plan view showing an organic light emitting diode display device according to an exemplary embodiment of the invention, Figure 2A It is used to describe the Figure 1 A plan view of a first power supply wiring and a second power supply wiring which may be in the form of wiring in an organic light emitting diode display device, Figure 2B It is used to describe the Figure 2A A plan view of an example of a second power supply wiring in an organic light emitting diode display device, Figure 2C It is shown that the Figure 2A A plan view of another example of a second power supply wiring in an organic light emitting diode display device, Figure 2D It is shown that the Figure 2A A plan view of yet another example of a second power supply wiring in an organic light emitting diode display device of Figure 3A It is used to describe the settings Figure 2A a plan view of a connection pattern on a first power supply wiring, Figure 3B is a plan view showing a conventional organic light emitting diode display device, and Figure 4 is used to illustrate the electrical connection to Figure 1 A block diagram of external devices of an organic light emitting diode display device.

[0069] Reference Figure 1 , Figure 2A , Figure 3A and Figure 4, an organic light emitting diode ("OLED") display device 100 may include a first power wiring 350, a second power wiring 390, a conductive pattern (which may be in the form of a connection pattern 295), a pad (or "pad") electrode 470, etc., and may include a display area 10, a peripheral area 20, and a pad area 60. In this case, the peripheral area 20 may substantially surround the display area 10, and the pad area 60 may be positioned on one side of the peripheral area 20. In addition, the display area 10 may include a plurality of sub-pixel circuit areas 30. In some exemplary embodiments, the display area 10 may be in a rectangular shape with curved corners when viewed from the top, and the OLED display device 100 (or Figure 6 and Figure 7 The substrate 110 of the display area 10 may also be in a rectangular shape with curved corners when viewed in a plane. For example, the display area 10 may include a first corner 11 adjacent to the pad area 60 and a second opposite corner 12 facing the first corner 11.

[0070] The peripheral region 20 may include a first peripheral region 21, a second peripheral region 22, and a third peripheral region 23. For example, the first peripheral region 21 of the peripheral region 20 may be adjacent to the pad electrode 470 provided in the pad region 60 (or may be positioned to correspond to the first portion of the pad region 60 provided with the pad electrode 470), the second peripheral region 22 may be positioned on both sides of the first peripheral region 21 (or both lower side ends of the peripheral region 20), and the third peripheral region 23 may correspond to the remaining portion of the peripheral region 20 except the first peripheral region 21 and the second peripheral region 22. In other words, the second peripheral region 22 may be positioned to correspond to the second portion of the pad region 60 where the pad electrode 470 is not provided. In this case, the second portion may be positioned on both sides of the first portion of the pad region 60. In addition, the second peripheral region 22 may be adjacent to the first corner 11 of the display region 10. In other words, the first peripheral region 21, the second peripheral region 22, and the third peripheral region 23 may be different from each other and may not overlap each other. In some exemplary embodiments, the second peripheral region 22 may not overlap the pad electrode 470 in a longitudinal direction (e.g., a first direction D1 or a second direction D2 opposite to the first direction D1) in a plan view of the OLED display device 100, and may be located at both lower side ends of the peripheral region 20. For example, the peripheral region 20 may have a ring or annular shape similar to a racetrack with a hollow center when viewed in a plane.

[0071] The sub-pixel circuit region 30 may be arranged in the display region 10. For example, Figure 5 A representative sub-pixel circuit SPC (for example, Figure 6 and Figure 7The semiconductor element 250 of FIG. 1 may be disposed in each sub-pixel circuit region 30 , and the organic light emitting diode OLED (eg, Figure 6 and Figure 7 The sub-pixel structure 200 may be disposed on the sub-pixel circuit SPC. An image may be displayed in the display area 10 through the sub-pixel circuit SPC and the organic light emitting diode OLED.

[0072] For example, a first sub-pixel circuit, a second sub-pixel circuit, and a third sub-pixel circuit may be disposed in the sub-pixel circuit region 30. The first sub-pixel circuit may be connected to a first organic light emitting diode for emitting red light, the second sub-pixel circuit may be connected to a second organic light emitting diode for emitting green light, and the third sub-pixel circuit may be connected to a third organic light emitting diode for emitting blue light.

[0073] In some exemplary embodiments, the first organic light emitting diode may overlap with the first sub-pixel circuit, the second organic light emitting diode may overlap with the second sub-pixel circuit, and the third organic light emitting diode may overlap with the third sub-pixel circuit. Optionally, the first organic light emitting diode may overlap with a portion of the first sub-pixel circuit and a portion of other sub-pixel circuits different from the first sub-pixel circuit, the second organic light emitting diode may overlap with a portion of the second sub-pixel circuit and a portion of other sub-pixel circuits different from the second sub-pixel circuit, and the third organic light emitting diode may overlap with a portion of the third sub-pixel circuit and a portion of other sub-pixel circuits different from the third sub-pixel circuit. For example, the first to third organic light emitting diodes may be arranged by using the following schemes, etc.: an RGB stripe scheme in which rectangles having the same size are arranged in sequence; an S stripe scheme in which the S stripe scheme includes a blue organic light emitting diode having a relatively large area; a WRGB scheme in which the WRGB scheme also includes a white organic light emitting diode; a PenTile scheme in which an RG-GB pattern is repeatedly arranged.

[0074] In addition, at least one driving transistor, at least one switching transistor, and at least one capacitor may be disposed in each sub-pixel circuit region 30. In some exemplary embodiments, a driving transistor (e.g., Figure 5 The first transistor TR1) and six switch transistors (eg, Figure 5 The second to seventh transistors TR2, TR3, TR4, TR5, TR6 and TR7) and a storage capacitor (eg, Figure 5 A storage capacitor CST) or the like may be provided in each sub-pixel circuit region 30.

[0075] Although the inventive OLED display device 100 has been described as having a rounded rectangular shape when viewed in a plane, the shape is not limited thereto. For example, when viewed in a plane, the OLED display device 100 may have a rectangular shape, a triangular shape, a diamond shape, a polygonal shape, a circular shape, an elliptical shape, or other shapes known in the art.

[0076] A plurality of wirings may be provided in the peripheral region 20. For example, the wirings may include data signal wirings, gate signal wirings, light emission control signal wirings, gate initialization signal wirings, initialization voltage wirings, power supply wirings, etc. The wirings may extend from the peripheral region 20 to the display region 10 and may be electrically connected to the sub-pixel circuit SPC and the organic light emitting diode OLED. In addition, a gate driver and a data driver, etc. may be provided in the peripheral region 20.

[0077] like Figure 2A and Figure 3A As shown in , the first power wiring 350 may be disposed in a portion of the peripheral region 20. In other words, the first power wiring 350 may be disposed in a portion of the first peripheral region 21, the second peripheral region 22, and the third peripheral region 23. The first power wiring 350 may have a generally hook shape (a ring shape with a lower opening). In some exemplary embodiments, the first power wiring 350 may have a first width W1 in the second peripheral region 22, and may have a second width W2 that is smaller than the first width W1 in the third peripheral region 23. The first power wiring 350 may be electrically connected to the pad electrode 470 in the first peripheral region 21. For example, the first power wiring 350 may be electrically connected to the outermost pad electrode 470 among the pad electrodes 470. A low power supply voltage may be applied to the first power wiring 350, and the low power supply voltage may be provided to the cathode electrode (e.g., Figure 6 and Figure 7 upper electrode 340).

[0078] Although for convenience Figure 2A 3 shows the first power wiring 350 as a single wiring, but the first power wiring 350 may be at least two wirings stacked on each other. In other words, the first power wiring 350 may have a structure in which at least two wirings (eg, Figure 6 and Figure 7 The structure of the first sub power supply wiring 351 and the second sub power supply wiring 352).

[0079] In addition, the second power wiring 390 may be provided in a portion of the peripheral region 20 and the display region 10. In other words, the second power wiring 390 may be provided in a portion of the third peripheral region 23, the display region 10, and the first peripheral region 21. The second power wiring 390 may be provided between the ends of the first power wiring 350 in the first peripheral region 21 to be electrically connected to the pad electrode 470, may have a lattice shape in the display region 10, and may be separated from the inner side of the first power wiring 350 in the third peripheral region 23. In this case, a portion of the second power wiring 390 provided in the first peripheral region 21 is defined as a first portion, a portion of the second power wiring 390 provided in the display region 10 is defined as a second portion, and a portion of the second power wiring 390 surrounding the second portion is defined as a third portion. The first portion, the second portion, and the third portion may be formed integrally with each other. The first and second portions of the second power wiring 390 may be connected to each other in the first peripheral region 21 adjacent to the boundary between the display region 10 and the peripheral region 20, and the second and third portions of the second power wiring 390 may be connected to each other in the third peripheral region 23 adjacent to the boundary between the display region 10 and the peripheral region 20. In some exemplary embodiments, the third portion of the second power wiring 390 may not be disposed in the second peripheral region 22. In other words, the third portion of the second power wiring 390 is not disposed in the second peripheral region 22, so that the second portion of the second power wiring 390 positioned at the lower end of the display region 10 may not be connected to the third portion of the second power wiring 390. Therefore, the second power wiring 390 is not disposed in the second peripheral region 22, so that the first power wiring 350 may be disposed in the second peripheral region 22 with a relatively wide first width W1. The second power wiring 390 may be electrically connected to the pad electrode 470 in the first peripheral region 21. For example, the second power wiring 390 may be electrically connected to the pad electrode 470 located inside the pad electrode 470 connected to the first power wiring 350 among the pad electrodes 470. A high power voltage may be applied to the second power wiring 390, and the high power voltage may be provided to the anode electrode (e.g., Figure 6 and Figure 7 of the lower electrode 290).

[0080] Although for convenience Figure 2A 2 and 3. The second power wiring 390 is shown as a single wiring, but the second power wiring 390 may be at least two wirings stacked on each other. In other words, the second power wiring 390 may have a structure in which at least two wirings are stacked.

[0081] In another exemplary embodiment, Figure 2BAs shown in , the second power wiring 390 may be provided in a portion of the peripheral region 20 and the display region 10. In other words, the second power wiring 390 may be provided in a portion of the third peripheral region 23, the first peripheral region 21, and the display region 10. The second power wiring 390 may be provided between the ends of the first power wiring 350 in the first peripheral region 21 to be electrically connected to the pad electrode 470, may have a lattice shape in a portion of the display region 10, and may be separated from the inner side of the first power wiring 350 in the third peripheral region 23. In this case, a portion of the second power wiring 390 provided in the first peripheral region 21 is defined as a first portion, a portion of the second power wiring 390 provided in the display region 10 is defined as a second portion, and a portion of the second power wiring 390 surrounding the second portion is defined as a third portion. The first portion, the second portion, and the third portion may be formed integrally with each other. In some exemplary embodiments, the second portion positioned at one portion of the display region 10 (e.g., the lower end of the display region 10) may have a lattice shape, and the second portion positioned at the remaining portion of the display region 10 (the center and the upper end of the display region 10) may have a shape characterized by longitudinal strips that are spaced apart from each other in the first direction D1 and extend along the third direction D3 when viewed in a plane. The first portion and the second portion of the second power wiring 390 may be connected to each other adjacent to the boundary between the display region 10 and the peripheral region 20 in the first peripheral region 21, and the second portion and the third portion of the second power wiring 390 may be connected to each other adjacent to the boundary between the display region 10 and the peripheral region 20 in the third peripheral region 23. In some exemplary embodiments, the third portion of the second power wiring 390 may not be disposed in the second peripheral region 22. In other words, the third portion of the second power wiring 390 is not disposed in the second peripheral region 22, so that the second portion of the second power wiring 390 positioned at the lower end of the display region 10 may not be connected to the third portion of the second power wiring 390.

[0082] Although for convenience Figure 2B 2 and 3. The second power wiring 390 is shown as a single wiring, but the second power wiring 390 may be at least two wirings stacked on each other. In other words, the second power wiring 390 may have a structure in which at least two wirings are stacked.

[0083] In yet another exemplary embodiment, Figure 2C As shown in Figure 2A compared to, Figure 2CThe second power wiring 390 may be disposed at the first corner 11. The second power wiring 390 positioned at the first corner 11 may be disposed along the boundary between the display area 10 and the second peripheral area 22. In other words, the second power wiring 390 may be disposed in a portion of the display area 10 and a portion of the second peripheral area 22. For example, in the display area 10 positioned adjacent to the first corner 11, since the first corner 11 has a curved shape, the sub-pixel circuit area 30 (or sub-pixel) may be arranged in a step shape, and an empty space may be formed between the boundary between the display area 10 and the second peripheral area 22 and the sub-pixel circuit area 30. In other words, the second power wiring 390 may be disposed in the empty space and may be separated from the first power wiring 350 inwardly (e.g., in a direction from the peripheral area 20 to the display area 10) in the second peripheral area 22.

[0084] In yet another exemplary embodiment, Figure 2D As shown in Figure 2B compared to, Figure 2D The second power wiring 390 may be disposed at the first corner 11. The second power wiring 390 positioned at the first corner 11 may be disposed along the boundary between the display area 10 and the second peripheral area 22. In other words, the second power wiring 390 may be disposed in a portion of the display area 10 and a portion of the second peripheral area 22. For example, in the display area 10 positioned adjacent to the first corner 11, since the first corner 11 has a curved shape, the sub-pixel circuit area 30 (or sub-pixel) may be arranged in a step shape, and an empty space may be formed between the boundary between the display area 10 and the second peripheral area 22 and the sub-pixel circuit area 30. In other words, the second power wiring 390 may be disposed in the empty space and may be separated from the first power wiring 350 inwardly (e.g., in a direction from the peripheral area 20 to the display area 10) in the second peripheral area 22.

[0085] Refer again Figure 2A and Figure 3A, the connection pattern 295 may be disposed on the first power wiring 350 in a portion of the first peripheral region 21, the second peripheral region 22, and the third peripheral region 23. In some exemplary embodiments, the connection pattern 295 may overlap with the first power wiring 350 disposed in the first peripheral region 21. The connection pattern 295 may be in a ring shape with a lower opening. In other words, the end of the first power wiring 350 may be aligned with the end of the connection pattern 295. In addition, the connection pattern 295 may overlap with the first power wiring 350 in the second peripheral region 22 and have a width smaller than the width of the first power wiring 350, and may overlap with the third portion of the second power wiring 390 and the first power wiring 350 in the third peripheral region 23. Alternatively, the width of the connection pattern 295 may be equal to or greater than the width of the first power wiring 350 in the second peripheral region 22, and the connection pattern 295 may not overlap with the third portion of the second power wiring 390 in the third peripheral region 23 and have a width equal to or greater than the width of the first power wiring 350. The low power voltage may be applied from the first power wiring 350 to the connection pattern 295, and the low power voltage may be provided to the cathode electrode (eg, Figure 6 and Figure 7 upper electrode 340).

[0086] For example, in Figure 3B In the conventional organic light emitting diode display device shown in , the first power wiring 1350 and the second power wiring 1390 are disposed together in the peripheral region 20. In other words, the third portion of the second power wiring 1390 is disposed in a portion of the first peripheral region 21 in addition to being disposed in the second peripheral region 22. Therefore, the first power wiring 1350 has a relatively reduced width in a portion of the first peripheral region 21 and the second peripheral region 22. In other words, the first power wiring 1350 has substantially the same width (e.g., the second width W2) in the peripheral region 20. When the conventional organic light emitting diode display device is driven at high brightness, current is concentrated on the first power wiring 1350 disposed in a portion of the first peripheral region 21 and the second peripheral region 22, thereby increasing the temperature (e.g., heat generation). In this case, due to the heat generation, the first power wiring 1350 may be short-circuited, or the insulating layer positioned around the first power wiring 1350 may be deformed. In other words, due to the heat generation of the first power wiring 1350 in a portion of the first peripheral region 21 and the second peripheral region 22, the conventional OLED display device may become defective.

[0087] In some exemplary embodiments of the invention, the first power wiring 350 and the connection pattern 295 have a relatively wide width in a portion of the first peripheral region 21 and the second peripheral region 22, so that in the OLED display device 100, heat generated in the first power wiring 350 positioned in a portion of the first peripheral region 21 and the second peripheral region 22 can be relatively reduced. For example, when the area of ​​the portion where heat is generated increases, the temperature of the generated heat can be relatively reduced because the generated heat is spread over a larger area.

[0088] Refer again Figure 1 , FIG. 2A to FIG. 2D , Figure 3A and Figure 4 , a pad electrode 470 electrically connected to the external device 101 may be provided in the pad region 60. In addition, a connection electrode may be provided between the pad electrode 470 and the first power wiring 350 and between the pad electrode 470 and the second power wiring 390. For example, the connection electrode may electrically connect the pad electrode 470 to each of the first power wiring 350 and the second power wiring 390. Alternatively, an end of each of the first power wiring 350 and the second power wiring 390 may be directly connected to the pad electrode 470.

[0089] like Figure 4 As schematically shown in FIG. 1 , the external device 101 may be electrically connected to the OLED display device 100 through a flexible printed circuit board or a printed circuit board. For example, one side of the flexible printed circuit board may be in direct contact with the pad electrode 470, and the opposite side of the flexible printed circuit board may be in direct contact with the external device 101. The external device 101 may provide a data signal, a gate signal, a light emitting control signal, a gate initialization signal, an initialization voltage, a high power supply voltage, a low power supply voltage, etc. to the OLED display device 100. In some exemplary embodiments, the low power supply voltage (e.g., Figure 5 The low power voltage ELVSS) may be generated from the external device 101, and the low power voltage may be provided to the first power wiring 350 through the flexible printed circuit board, the pad electrode 470, and the connection electrode. Figure 5 A high power supply voltage ELVDD) may be generated from an external device 101, and the high power supply voltage may be provided to the second power supply wiring 390 through the flexible printed circuit board, the pad electrode 470, and the connection electrode. In addition, a driving integrated circuit may be mounted on the flexible printed circuit board. In other exemplary embodiments, the driving integrated circuit may be mounted on the OLED display device 100 adjacent to the pad electrode 470.

[0090] Figure 5 It shows that the setting Figure 1A circuit diagram of a sub-pixel circuit in a sub-pixel circuit area and an organic light emitting diode OLED arranged on the sub-pixel circuit.

[0091] Reference Figure 5 , a sub-pixel circuit SPC and an organic light emitting diode OLED (eg, Figure 6 and Figure 7 The sub-pixel structure 200 may be disposed in each sub-pixel circuit region 30 of the OLED display device 100, and one sub-pixel circuit SPC may include first to seventh transistors TR1, TR2, TR3, TR4, TR5, TR6, and TR7 (eg, Figure 6 and Figure 7 The semiconductor element 250 of FIG. 1 ), the storage capacitor CST, the wiring for the high power supply voltage ELVDD (eg, FIG. 2A to FIG. 2D and Figure 3A A second power supply wiring 390 for the low power supply voltage ELVSS (eg, FIG. 2A to FIG. 2D and Figure 3A The first power wiring 350 of the embodiment of the present invention may include a first power wiring 350 for initialization voltage VINT, a wiring for data signal DATA, a wiring for gate signal GW, a wiring for gate initialization signal GI, a wiring for light emission control signal EM, a wiring for diode initialization signal GB, etc. As described above, the first transistor TR1 may correspond to a driving transistor, and the second to seventh transistors TR2, TR3, TR4, TR5, TR6, and TR7 may correspond to switching transistors. Each of the first to seventh transistors TR1, TR2, TR3, TR4, TR5, TR6, and TR7 may include a first terminal, a second terminal, a channel, and a gate terminal. In some exemplary embodiments, the first terminal may be a source terminal, and the second terminal may be a drain terminal. Alternatively, the first terminal may be a drain terminal, and the second terminal may be a source terminal.

[0092] The organic light emitting diode OLED may output light based on the driving current ID. The organic light emitting diode OLED may include a first terminal and a second terminal. In some exemplary embodiments, the second terminal of the organic light emitting diode OLED may be supplied with a low power supply voltage ELVSS, and the first terminal of the organic light emitting diode OLED may be supplied with a high power supply voltage ELVDD. For example, the first terminal of the organic light emitting diode OLED may be an anode terminal, and the second terminal of the organic light emitting diode OLED may be a cathode terminal. Alternatively, the first terminal of the organic light emitting diode OLED may be a cathode terminal, and the second terminal of the organic light emitting diode OLED may be an anode terminal. In some exemplary embodiments, the anode terminal of the organic light emitting diode OLED may correspond to Figure 6The lower electrode 290 of the organic light emitting diode OLED may correspond to the cathode terminal of the organic light emitting diode OLED. Figure 6 The upper electrode 340 is provided.

[0093] The first transistor TR1 may generate a driving current ID. In some exemplary embodiments, the first transistor TR1 may operate in a saturation region. In this case, the first transistor TR1 may generate a driving current ID based on a voltage difference between a gate terminal and a source terminal. In addition, a grayscale may be represented based on the magnitude of the driving current ID supplied to the organic light emitting diode OLED. Alternatively, the first transistor TR1 may operate in a linear region. In this case, a grayscale may be represented based on the sum of the time during which the driving current is supplied to the organic light emitting diode OLED within one frame.

[0094] The gate terminal of the second transistor TR2 may be supplied with a gate signal GW. The first terminal of the second transistor TR2 may be supplied with a data signal DATA. The second terminal of the second transistor TR2 may be connected to the first terminal of the first transistor TR1. For example, the gate signal GW may be provided from a gate driver, and the gate signal GW may be applied to the gate terminal of the second transistor TR2 through wiring for the gate signal GW. The second transistor TR2 may supply the data signal DATA to the first terminal of the first transistor TR1 during the activation period of the gate signal GW. In this case, the second transistor TR2 may operate in a linear region.

[0095] The gate terminal of the third transistor TR3 may be supplied with a gate signal GW. The first terminal of the third transistor TR3 may be connected to the gate terminal of the first transistor TR1. The second terminal of the third transistor TR3 may be connected to the second terminal of the first transistor TR1. For example, the gate signal GW may be provided from a gate driver, and the gate signal GW may be applied to the gate terminal of the third transistor TR3 through wiring for the gate signal GW. The third transistor TR3 may connect the gate terminal of the first transistor TR1 to the second terminal of the first transistor TR1 during the activation period of the gate signal GW. In this case, the third transistor TR3 may operate in a linear region. In other words, the third transistor TR3 may diode-connect the first transistor TR1 during the activation period of the gate signal GW. Because the first transistor TR1 is diode-connected, the voltage difference between the first terminal of the first transistor TR1 and the gate terminal of the first transistor TR1 may be almost as large as the threshold voltage of the first transistor TR1. As a result, a voltage obtained by adding the voltage difference (i.e., the threshold voltage) to the voltage of the data signal DATA supplied to the first terminal of the first transistor TR1 may be supplied to the gate terminal of the first transistor TR1 during the activation period of the gate signal GW. In other words, the data signal DATA can be compensated to be almost as large as the threshold voltage of the first transistor TR1, and the compensated data signal DATA can be supplied to the gate terminal of the first transistor TR1. Since the threshold voltage compensation is performed, the problem of non-uniform driving current caused by the threshold voltage deviation of the first transistor TR1 can be solved.

[0096] An output terminal of the initialization voltage wiring provided with the initialization voltage VINT can be connected to the first terminal of the fourth transistor TR4 and the first terminal of the seventh transistor TR7, and an input terminal of the initialization voltage wiring can be provided with the initialization voltage VINT, and a second terminal of the fourth transistor TR4 can be connected to the first terminal of the storage capacitor CST.

[0097] A gate terminal of the fourth transistor TR4 may be supplied with a gate initialization signal GI. A first terminal of the fourth transistor TR4 may be supplied with an initialization voltage VINT. A second terminal of the fourth transistor TR4 may be connected to a gate terminal of the first transistor TR1.

[0098] The fourth transistor TR4 may supply the initialization voltage VINT to the gate terminal of the first transistor TR1 during the activation period of the gate initialization signal GI. In this case, the fourth transistor TR4 may operate in a linear region. In other words, the fourth transistor TR4 may initialize the gate terminal of the first transistor TR1 to the initialization voltage VINT during the activation period of the gate initialization signal GI. In some exemplary embodiments, the initialization voltage VINT may have a voltage level sufficiently lower than the voltage level of the data signal DATA held by the storage capacitor CST in the previous frame, and the initialization voltage VINT may be supplied to the gate terminal of the first transistor TR1. In other exemplary embodiments, the initialization voltage may have a voltage level sufficiently higher than the voltage level of the data signal held by the storage capacitor in the previous frame, and the initialization voltage may be supplied to the gate terminal of the first transistor TR1.

[0099] In some exemplary embodiments, the gate initialization signal GI may be a signal substantially identical to the gate signal GW transmitted one horizontal time before. For example, the gate initialization signal GI supplied to the sub-pixel circuit in the nth row (where n is an integer of 2 or greater) of the sub-pixel circuit SPC included in the OLED display device 100 may be a signal substantially identical to the gate signal GW supplied to the sub-pixel circuit in the (n-1)th row of the sub-pixel circuit SPC. In other words, the activated gate initialization signal GI may be supplied to the sub-pixel circuit in the nth row of the sub-pixel circuit SPC by supplying the activated gate signal GW to the sub-pixel circuit in the (n-1)th row of the sub-pixel circuit SPC. As a result, when the gate terminal of the first transistor TR1 in the sub-pixel circuit in the nth row of the sub-pixel circuit SPC is initialized to the initialization voltage VINT, the data signal DATA may be supplied to the sub-pixel circuit in the (n-1)th row of the sub-pixel circuit SPC.

[0100] The gate terminal of the fifth transistor TR5 may be supplied with a light emitting control signal EM. The first terminal of the fifth transistor TR5 may be connected to a wiring for a high power supply voltage ELVDD. The second terminal of the fifth transistor TR5 may be connected to a first terminal of the first transistor TR1. For example, a light emitting control signal EM may be provided from a light emitting control driver, and the light emitting control signal EM may be applied to the gate terminal of the fifth transistor TR5 through a wiring for the light emitting control signal EM. The fifth transistor TR5 may supply the high power supply voltage ELVDD to the first terminal of the first transistor TR1 during the activation period of the light emitting control signal EM. Conversely, the fifth transistor TR5 may cut off the supply of the high power supply voltage ELVDD during the deactivation period of the light emitting control signal EM. In this case, the fifth transistor TR5 may operate in a linear region. The fifth transistor TR5 supplies the high power supply voltage ELVDD to the first terminal of the first transistor TR1 during the activation period of the light emitting control signal EM, so that the first transistor TR1 may generate a driving current ID. In addition, the fifth transistor TR5 cuts off the supply of the high power supply voltage ELVDD during the deactivation period of the light emitting control signal EM, so that the data signal DATA supplied to the first terminal of the first transistor TR1 may be supplied to the gate terminal of the first transistor TR1.

[0101] The sixth transistor TR6 (eg, Figure 6 The gate terminal of the semiconductor element 250 of the sixth transistor TR6 may be supplied with the light emitting control signal EM. The first terminal of the sixth transistor TR6 may be connected to the second terminal of the first transistor TR1. The second terminal of the sixth transistor TR6 may be connected to the first terminal of the organic light emitting diode OLED. The sixth transistor TR6 may supply the driving current ID generated by the first transistor TR1 to the organic light emitting diode OLED during the activation period of the light emitting control signal EM. In this case, the sixth transistor TR6 may operate in a linear region. In other words, the sixth transistor TR6 supplies the driving current ID generated by the first transistor TR1 to the organic light emitting diode OLED during the activation period of the light emitting control signal EM, so that the organic light emitting diode OLED may output light. In addition, the sixth transistor TR6 electrically separates the first transistor TR1 from the organic light emitting diode OLED during the deactivation period of the light emitting control signal EM, so that the data signal DATA supplied to the second terminal of the first transistor TR1 (more accurately, the data signal that has been subjected to threshold voltage compensation) may be supplied to the gate terminal of the first transistor TR1.

[0102] The gate terminal of the seventh transistor TR7 may be supplied with a diode initialization signal GB. The first terminal of the seventh transistor TR7 may be supplied with an initialization voltage VINT. The second terminal of the seventh transistor TR7 may be connected to the first terminal of the organic light emitting diode OLED. The seventh transistor TR7 may supply the initialization voltage VINT to the first terminal of the organic light emitting diode OLED during the activation period of the diode initialization signal GB. In this case, the seventh transistor TR7 may operate in a linear region. In other words, the seventh transistor TR7 may initialize the first terminal of the organic light emitting diode OLED to the initialization voltage VINT during the activation period of the diode initialization signal GB.

[0103] Alternatively, the gate initialization signal GI and the diode initialization signal GB may be signals that are substantially identical to each other. The operation of initializing the gate terminal of the first transistor TR1 and the operation of initializing the first terminal of the organic light emitting diode OLED do not affect each other. In other words, the operation of initializing the gate terminal of the first transistor TR1 and the operation of initializing the first terminal of the organic light emitting diode OLED may be independent of each other. Therefore, the diode initialization signal GB is not generated separately, so that the economic efficiency of the process can be improved.

[0104] The storage capacitor CST may include a first terminal and a second terminal. The storage capacitor CST may be connected between the wiring for the high power supply voltage ELVDD and the gate terminal of the first transistor TR1. For example, the first terminal of the storage capacitor CST may be connected to the gate terminal of the first transistor TR1, and the second terminal of the storage capacitor CST may be connected to the wiring for the high power supply voltage ELVDD. The storage capacitor CST may maintain the voltage level of the gate terminal of the first transistor TR1 during the deactivation period of the gate signal GW. The deactivation period of the gate signal GW may include the activation period of the light emitting control signal EM, and the drive current ID generated by the first transistor TR1 may be supplied to the organic light emitting diode OLED during the activation period of the light emitting control signal EM. Therefore, based on the voltage level maintained by the storage capacitor CST, the drive current ID generated by the first transistor TR1 may be supplied to the organic light emitting diode OLED.

[0105] Although the sub-pixel circuit SPC has been described as including seven transistors and one capacitor, the configuration of the exemplary embodiment of the invention is not limited thereto. For example, the sub-pixel circuit SPC may have a configuration including at least one transistor and at least one storage capacitor.

[0106] Figure 6 is along Figure 3A A cross-sectional view taken along line II' of Figure 7 is along Figure 3AA cross-sectional view taken along line II-II'.

[0107] Reference Figure 6 and Figure 7 , the OLED display device 100 may include a substrate 110, a buffer layer 115, a semiconductor element 250, a protective insulating layer 400, a first power wiring 350, a first planarization layer 270, a wiring pattern 215, a connection electrode 235, a second planarization layer 275, a pixel defining layer 310, a sub-pixel structure 200, a capping layer 345, a blocking structure 370, a thin film encapsulation structure 450, etc. In this case, the semiconductor element 250 may include an active layer 130, a gate insulating layer 150, a first gate electrode 170, a first interlayer insulating layer 190, a second gate electrode 175, a second interlayer insulating layer 195, a source electrode 210, and a drain electrode 230, and the first power wiring 350 may include a first sub-power wiring 351 and a second sub-power wiring 352. In addition, the blocking structure 370 may include a first blocking pattern 371 and a second blocking pattern 372, and the sub-pixel structure 200 may include a lower electrode 290, a light emitting layer 330, and an upper electrode 340. In addition, the thin film encapsulation structure 450 may include a first thin film encapsulation layer 451 , a second thin film encapsulation layer 452 , and a third thin film encapsulation layer 453 .

[0108] A substrate 110 including a transparent material or an opaque material may be provided. The substrate 110 may be formed by using a flexible transparent resin substrate. In some exemplary embodiments, the substrate 110 may have a structure in which a first organic layer, a first barrier layer, a second organic layer, and a second barrier layer are sequentially stacked. The first barrier layer and the second barrier layer may include an inorganic material such as silicon oxide, and may block moisture and / or water from penetrating through the first organic layer and the second organic layer. In addition, the first organic layer and the second organic layer may include an organic material such as a polyimide resin, and may have flexibility.

[0109] Because the substrate 110 is thin and flexible, the substrate 110 can be formed on a rigid glass substrate to support the formation of the semiconductor element 250 and the sub-pixel structure 200. For example, after the buffer layer 115 is disposed on the second barrier layer, the semiconductor element 250 and the sub-pixel structure 200 can be formed on the buffer layer 115. After the semiconductor element 250 and the sub-pixel structure 200 are formed, the glass substrate can be removed. In other words, due to the flexible physical properties of the substrate 110, it may be difficult to directly form the semiconductor element 250 and the sub-pixel structure 200 on the substrate 110. In view of the above point of view, the glass substrate is removed after the semiconductor element 250 and the sub-pixel structure 200 are formed using a rigid glass substrate, so that the first organic layer, the first barrier layer, the second organic layer, and the second barrier layer can be used as the substrate 110.

[0110] like Figure 6 and Figure 7 As shown in FIG. 1 , since the OLED display device 100 includes a display area 10, a peripheral area 20 having a first peripheral area 21, a second peripheral area 22, and a third peripheral area 23, and a pad area 60, the substrate 110 may also be divided into the display area 10, the first peripheral area 21, and the second peripheral area 22 (see FIG. 1 ). Figure 1 ).

[0111] Alternatively, the substrate 110 may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate (F-doped quartz substrate), a soda-lime glass substrate, an alkali-free glass substrate, or the like.

[0112] Although the substrate 110 is described as having four layers, the configuration of the exemplary embodiment is not limited thereto. For example, in other exemplary embodiments, the substrate 110 may include a single layer or multiple layers.

[0113] The buffer layer 115 may be disposed on the substrate 110. In some exemplary embodiments, the buffer layer 115 may be disposed in the display region 10 and the peripheral region 20 (e.g., the second peripheral region 22) over the entire substrate 110. The buffer layer 115 may prevent metal atoms or impurities from diffusing from the substrate 110 into the semiconductor element 250, and may control the heat transfer rate during the crystallization process for forming the active layer 130 to obtain a substantially uniform active layer 130. In addition, when the surface of the substrate 110 is uneven, the buffer layer 115 may be used to improve the flatness of the surface of the substrate 110. Depending on the type of the substrate 110, at least two buffer layers 115 may be disposed on the substrate 110, or no buffer layer 115 may be disposed on the substrate 110. The buffer layer 115 may include a silicon compound, a metal oxide, or the like. For example, the buffer layer 115 may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), Silicon Oxycarbide (SiO x C y ), Silicon Carbonitride (SiC x N y ), aluminum oxide (AlO x ), aluminum nitride (AlN x ), tantalum oxide (TaO x ), hafnium oxide (HfO x )、ZrO x ), titanium oxide (TiO x )wait.

[0114] The active layer 130 may be disposed on the buffer layer 115 in the display region 10. The active layer 130 may include an oxide semiconductor, an inorganic semiconductor (eg, amorphous silicon or polycrystalline silicon), an organic semiconductor, etc. The active layer 130 may have a source region, a drain region, and a channel region positioned between the source region and the drain region.

[0115] The gate insulating layer 150 may be disposed on the active layer 130. The gate insulating layer 150 may cover the active layer 130 in the display region 10 on the buffer layer 115, and may extend in a direction from the display region 10 to the peripheral region 20. For example, the gate insulating layer 150 may fully cover the active layer 130 on the buffer layer 115, and may have a substantially flat top surface without causing steps around the active layer 130. Alternatively, the gate insulating layer 150 may cover the active layer 130 on the buffer layer 115 while being disposed with a uniform thickness along the contour of the active layer 130, or may be disposed in the display region 10 and the second peripheral region 22 over the entire buffer layer 115. The gate insulating layer 150 may include a silicon compound, a metal oxide, or the like. In other exemplary embodiments, the gate insulating layer 150 may have a multilayer structure having a plurality of insulating layers including materials different from each other.

[0116] The first gate electrode 170 may be disposed on the gate insulating layer 150 in the display region 10. The first gate electrode 170 may be disposed on a portion of the gate insulating layer 150 under which the active layer 130 is positioned (e.g., to overlap the channel region of the active layer 130). The first gate electrode 170 may include a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These materials may be used alone or in combination with each other. In other exemplary embodiments, the first gate electrode 170 may have a multilayer structure including a plurality of layers.

[0117] The first interlayer insulating layer 190 may be disposed on the first gate electrode 170. The first interlayer insulating layer 190 may cover the first gate electrode 170 in the display region 10 on the gate insulating layer 150, and may extend in a direction from the display region 10 to the peripheral region 20. For example, the first interlayer insulating layer 190 may fully cover the first gate electrode 170 on the gate insulating layer 150, and may have a substantially flat top surface without causing steps around the first gate electrode 170. Alternatively, the first interlayer insulating layer 190 may cover the first gate electrode 170 on the gate insulating layer 150, and may be disposed with a uniform thickness along the contour of the first gate electrode 170. The first interlayer insulating layer 190 may include a silicon compound, a metal oxide, and the like. In other exemplary embodiments, the first interlayer insulating layer 190 may have a multilayer structure having a plurality of insulating layers including materials different from each other.

[0118] The second gate electrode 175 may be disposed in the display region 10 on the first interlayer insulating layer 190. The second gate electrode 175 may be disposed on a portion of the first interlayer insulating layer 190 under which the first gate electrode 170 is located. Alternatively, the first gate electrode 170 and the second gate electrode 175 may be used as Figure 5 The storage capacitor CST of the second gate electrode 175 may include a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These materials may be used alone or in combination with each other. In other exemplary embodiments, the second gate electrode 175 may have a multilayer structure including a plurality of layers.

[0119] The second interlayer insulating layer 195 may be disposed on the second gate electrode 175. The second interlayer insulating layer 195 may cover the second gate electrode 175 in the display region 10 on the first interlayer insulating layer 190, and may extend in a direction from the display region 10 to the peripheral region 20. For example, the second interlayer insulating layer 195 may fully cover the second gate electrode 175 on the first interlayer insulating layer 190, and may have a substantially flat top surface without causing steps around the second gate electrode 175. Alternatively, the second interlayer insulating layer 195 may cover the second gate electrode 175 on the first interlayer insulating layer 190, and may be disposed with a uniform thickness along the contour of the second gate electrode 175. The second interlayer insulating layer 195 may include a silicon compound, a metal oxide, and the like. In other exemplary embodiments, the second interlayer insulating layer 195 may have a multilayer structure having a plurality of insulating layers including materials different from each other.

[0120] The source electrode 210 and the drain electrode 230 may be disposed in the display region 10 on the second interlayer insulating layer 195. The source electrode 210 may be connected to the source region of the active layer 130 through a contact hole formed by removing the first portion of the gate insulating layer 150, the first portion of the first interlayer insulating layer 190, and the first portion of the second interlayer insulating layer 195, and the drain electrode 230 may be connected to the drain region of the active layer 130 through a contact hole formed by removing the second portion of the gate insulating layer 150, the second portion of the first interlayer insulating layer 190, and the second portion of the second interlayer insulating layer 195. Each of the source electrode 210 and the drain electrode 230 may include a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These materials may be used alone or in combination with each other. In other exemplary embodiments, each of the source electrode 210 and the drain electrode 230 may have a multilayer structure including a plurality of layers.

[0121] Therefore, the semiconductor element 250 including the active layer 130 , the gate insulating layer 150 , the first gate electrode 170 , the first interlayer insulating layer 190 , the second gate electrode 175 , the second interlayer insulating layer 195 , the source electrode 210 , and the drain electrode 230 may be provided in the above configuration.

[0122] Although the semiconductor element 250 has been described as having a top gate structure, the configuration of the exemplary embodiment is not limited thereto. For example, the semiconductor element 250 may have a bottom gate structure.

[0123] In addition, although the OLED display device 100 has been described as including one semiconductor element, the configuration of the exemplary embodiment is not limited thereto. For example, the OLED display device 100 may include at least one semiconductor element and at least one storage capacitor.

[0124] Although Figure 6 The semiconductor element 250 and Figure 7 The semiconductor elements 250 are assumed to have the same reference numerals for convenience of explanation, but Figure 6 The semiconductor element 250 and Figure 7 The semiconductor elements 250 may be different semiconductor elements from each other. In other words, Figure 6 The semiconductor element 250 may be a semiconductor element disposed in the display region 10 adjacent to the second peripheral region 22, and Figure 7 The semiconductor element 250 may be a semiconductor element provided in the display region 10 adjacent to the first peripheral region 21 .

[0125] The first sub power wiring 351 may be provided on the second interlayer insulating layer 195 in a portion of the first peripheral region 21, the second peripheral region 22, and the third peripheral region 23 (eg, see FIG. 2A to FIG. 2D The first power sub-wiring 350 in the first peripheral region 21 is provided. The first sub-power wiring 351 may have a substantially annular shape and have a lower opening. In some exemplary embodiments, the first sub-power wiring 351 may have a first width W1 in a portion of the first peripheral region 21 and the second peripheral region 22, and may have a second width W2 less than the first width W1 in the third peripheral region 23. In other words, the first sub-power wiring 351 may have different widths in the first peripheral region 21, the second peripheral region 22, and the third peripheral region 23.

[0126] The first sub power supply wiring 351 may be electrically connected to the first peripheral region 21. FIG. 2A to FIG. 2D For example, the first sub power wiring 351 may be electrically connected to the outermost pad electrode 470 among the pad electrodes 470 . Figure 5The low power voltage ELVSS may be applied to the first sub power wiring 351, and the low power voltage ELVSS may be provided to the upper electrode 340 through the connection pattern 295. The first sub power wiring 351 may include a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. For example, the first sub power wiring 351 may include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), aluminum alloy, aluminum nitride (AlN), etc. x ), silver-containing alloys, tungsten nitride (WN x ), copper-containing alloys, molybdenum-containing alloys, titanium nitride (TiN x ), chromium nitride (CrN x ), Tantalum Nitride (TaN x ), strontium ruthenium oxide (SrRu x O y ), zinc oxide (ZnO x )、Indium Tin Oxide (ITO), Tin Oxide (SnO x ), indium oxide (InO x ), gallium oxide (GaO x ), indium zinc oxide (IZO), etc. These materials may be used alone or in combination with each other. Optionally, the first sub-power wiring 351 may have a multilayer structure including a plurality of layers. In some exemplary embodiments, the source electrode 210, the drain electrode 230, and the first sub-power wiring 351 may be positioned on the same layer as each other.

[0127] The protective insulating layer 400 may be disposed on the second interlayer insulating layer 195, the source electrode 210 and the drain electrode 230, and the first sub power wiring 351. The protective insulating layer 400 may cover the source electrode 210 and the drain electrode 230 in the display region 10 on the second interlayer insulating layer 195, and may cover the first sub power wiring 351 in the second peripheral region 22 on the second interlayer insulating layer 195. In some exemplary embodiments, the protective insulating layer 400 may have a first opening 401 and a second opening 402 for exposing a portion of the first sub power wiring 351 in the peripheral region 20 (or the first peripheral region 21 and the second peripheral region 22). The second sub power wiring 352 may be connected to the first sub power wiring 351 through the first opening 401 and the second opening 402. In addition, the protective insulating layer 400 may have an opening for exposing a portion of the drain electrode 230 in the display region 10. The connection electrode 235 may be connected to the drain electrode 230 through the opening positioned in the display region 10. For example, the protective insulating layer 400 may sufficiently cover the source electrode 210 and the drain electrode 230 and the first sub-power wiring 351 on the second interlayer insulating layer 195, and may have a substantially flat top surface without causing steps around the source electrode 210 and the drain electrode 230 and the first sub-power wiring 351. Alternatively, the protective insulating layer 400 may cover the source electrode 210 and the drain electrode 230 and the first sub-power wiring 351 on the second interlayer insulating layer 195, and may be set to a substantially uniform thickness along the contours of the source electrode 210 and the drain electrode 230 and the first sub-power wiring 351. The protective insulating layer 400 may include a silicon compound, a metal oxide, etc. In other exemplary embodiments, the protective insulating layer 400 may have a multilayer structure having a plurality of insulating layers including materials different from each other.

[0128] The first planarization layer 270 may be disposed on the protective insulating layer 400. The first planarization layer 270 may be disposed on the protective insulating layer 400 in a portion of the peripheral region 20 (e.g., a portion of the first peripheral region 21 and a portion of the second peripheral region 22) and the display region 10. In other words, the first planarization layer 270 may cover the protective insulating layer 400 in the display region 10 while extending in a direction from the display region 10 to the peripheral region 20, and may expose the first opening 401 and the second opening 402 of the protective insulating layer 400 in the peripheral region 20. In other words, the first planarization layer 270 may extend from the display region 10 to the peripheral region 20 to cover at least a portion of the first opening 401. For example, the first planarization layer 270 may have a relatively thick thickness, in which case the first planarization layer 270 may have a substantially flat top surface. In order to achieve such a flat top surface of the first planarization layer 270, a planarization process may be additionally performed on the first planarization layer 270. Optionally, the first planarization layer 270 may be disposed on the protective insulating layer 400 along the contour of the protective insulating layer 400 with a uniform thickness. The first planarization layer 270 may be formed of an organic material or an inorganic material. In some exemplary embodiments, the first planarization layer 270 may include an organic material. For example, the first planarization layer 270 may include a photoresist, a polyacrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, an acrylic resin, an epoxy resin, etc.

[0129] The wiring pattern 215 and the connection electrode 235 may be disposed in the display area 10 on the first planarization layer 270. The wiring pattern 215 may transmit a gate signal, a data signal, a light emitting signal, an initialization signal, a power supply voltage, etc. The connection electrode 235 may be separated from the wiring pattern 215 in the display area 10 on the first planarization layer 270. The connection electrode 235 may be connected to the drain electrode 230 through a contact hole formed by removing a portion of the first planarization layer 270 positioned in the display area 10, and the connection electrode 235 may electrically connect the lower electrode 290 to the drain electrode 230. Alternatively, the connection electrode 235 may not be connected to the drain electrode 230, but may electrically connect the semiconductor element 250 to another semiconductor element through a contact hole in another cross-sectional view of the OLED display device 100. Each of the wiring pattern 215 and the connection electrode 235 may include a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These materials may be used alone or in combination with each other. In other exemplary embodiments, each of the wiring pattern 215 and the connection electrode 235 may have a multi-layer structure including a plurality of layers.

[0130] The second sub power wiring 352 may be disposed in the peripheral region 20 on the first planarization layer 270. The second sub power wiring 352 may have a lower open ring shape. In some exemplary embodiments, the second sub power wiring 352 may have a first width W1 in a portion of the first peripheral region 21 and the second peripheral region 22, and may have a second width W2 smaller than the first width W1 in the third peripheral region 23. In other words, the second sub power wiring 352 may have different widths in the first peripheral region 21, the second peripheral region 22, and the third peripheral region 23.

[0131] The second sub power wiring 352 may be in direct contact with the first sub power wiring 351 through the first opening 401 in the first peripheral region 21 and the second peripheral region 22, and may be in direct contact with the first sub power wiring 351 through the second opening 402. In addition, the second sub power wiring 352 may have an opening for exposing the top surface of the protective insulating layer 400 between the first opening 401 and the second opening 402 in the first peripheral region 21 and the second peripheral region 22 (see Fig.12 Alternatively, the second sub power supply wiring 352 may be continuously provided without openings in the first peripheral region 21 and the second peripheral region 22 .

[0132] The second sub power supply wiring 352 may be electrically connected to the first peripheral region 21. FIG. 2A to FIG. 2D The pad electrode 470 of the second sub-power wiring 352. For example, the second sub-power wiring 352 may be electrically connected to the outermost pad electrode 470 among the pad electrodes 470. The low power voltage ELVSS may be applied to the second sub-power wiring 352 through the first sub-power wiring 351, and the low power voltage ELVSS may be provided to the upper electrode 340 through the connection pattern 295. The second sub-power wiring 352 may include a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These materials may be used alone or in combination with each other. Optionally, the second sub-power wiring 352 may have a multilayer structure including a plurality of layers. In some exemplary embodiments, the wiring pattern 215, the connection electrode 235, and the second sub-power wiring 352 may be positioned on the same layer as each other.

[0133] Therefore, the first power supply wiring 350 including the first sub power supply wiring 351 and the second sub power supply wiring 352 may be provided in the above configuration.

[0134] Although the first power wiring 350 has been described as including the first sub-power wiring 351 and the second sub-power wiring 352, the configuration of the exemplary embodiment is not limited thereto. For example, the first power wiring 350 may have a configuration including only the first sub-power wiring 351, a configuration including only the second sub-power wiring 352, or a configuration including the first sub-power wiring 351, the second sub-power wiring 352, and another wiring.

[0135] In addition, although the first sub-power wiring 351 and the second sub-power wiring 352 have been described as having the first width W1 in the first peripheral region 21 and the second peripheral region 22 and having the second width W2 in the third peripheral region 23, the configuration of the exemplary embodiment is not limited thereto. For example, in other exemplary embodiments, only one of the first sub-power wiring 351 and the second sub-power wiring 352 may have the first width W1 in the second peripheral region 22.

[0136] The second planarization layer 275 may be disposed on the wiring pattern 215, the connection electrode 235, the second sub power wiring 352, and the first planarization layer 270. The second planarization layer 275 may cover the wiring pattern 215 and the connection electrode 235 in the display region 10 on the first planarization layer 270 while extending in a direction from the display region 10 to the peripheral region 20, and may cover the second sub power wiring 352 in the peripheral region 20. In some exemplary embodiments, as shown in FIG. Figure 6 As shown in , the second planarization layer 275 may have a plurality of openings 490 for exposing the top surface of the second sub power wiring 352 in the second peripheral region 22. The connection pattern 295 may be in direct contact with the second sub power wiring 352 through the openings 490 of the second planarization layer 275. In addition, the openings 490 may be formed in a portion where the first power wiring 350 and the connection pattern 295 overlap each other in the third peripheral region 23. In other words, the openings 490 may be formed in the second planarization layer 275 so as not to overlap with the light emitting layer 330 in the second peripheral region 22 and the third peripheral region 23 on the first planarization layer 270. Optionally, as Figure 7 , the second planarization layer 275 is configured without an opening for exposing the top surface of the second sub power wiring 352 in the first peripheral region 21. In other words, the second planarization layer 275 positioned in the first peripheral region 21 may cover the second sub power wiring 352 adjacent to the display region 10.

[0137] Furthermore, the second planarization layer 275 may cover the end portion of the second sub power supply wiring 352 disposed in the first opening 401 in the peripheral region 20 .

[0138] For example, in Figure 3BIn the conventional organic light emitting diode display device shown in FIG. 1 , the first power wiring 1350 and the second power wiring 1390 may be disposed together in the peripheral region 20. In other words, the third portion of the second power wiring 1390 may be disposed in a portion of the first peripheral region 21 and the second peripheral region 22. Therefore, the first power wiring 1350 may have a relatively reduced width in a portion of the first peripheral region 21 and the second peripheral region 22. In other words, the first power wiring 1350 may have substantially the same width in the peripheral region 20. In this case, the width of the portion where the first power wiring 1350 and the connection pattern 1295 overlap each other may be relatively reduced in a portion of the first peripheral region 21 and the second peripheral region 22. As a result, the number of openings in the second planarization layer 275 formed in the second peripheral region 22 may be relatively small. When the conventional organic light emitting diode display device is driven at high brightness, current may be concentrated on the first power wiring 1350 disposed in a portion of the first peripheral region 21 and the second peripheral region 22, thereby increasing temperature (e.g., heat generation). In this case, due to heat generation, the first power wiring 1350 may be short-circuited or an insulating layer positioned around the first power wiring 1350 may be deformed. In other words, due to heat generation occurring in a portion of the first peripheral region 21 and the second peripheral region 22 by the first power wiring 1350, the conventional OLED display device may become defective.

[0139] In some exemplary embodiments of the invention, the first power wiring 350 and the connection pattern 295 have relatively wide widths in a portion of the first peripheral region 21 and the second peripheral region 22, so that a relatively larger number of openings 490 for directly contacting the connection pattern 295 with the first power wiring 350 in the second peripheral region 22 can be formed. Therefore, in the OLED display device 100, heat generated in the first power wiring 350 positioned in a portion of the first peripheral region 21 and the second peripheral region 22 can be relatively reduced. For example, the opening 490 can cause the connection pattern 295 to have a stepped portion connected to the second sub-power wiring 352, and the surface area of ​​the connection pattern 295 can be relatively increased.

[0140] Refer again Figure 6, the second planarization layer 275 may have a relatively thick thickness to fully cover the wiring pattern 215, the connecting electrode 235, and the second sub-power wiring 352, and in this case, the second planarization layer 275 may have a substantially flat top surface. In order to achieve such a flat top surface of the second planarization layer 275, a planarization process may be additionally performed on the second planarization layer 275. Optionally, the second planarization layer 275 may cover the wiring pattern 215, the connecting electrode 235, and the second sub-power wiring 352, and may be arranged with a uniform thickness along the contours of the wiring pattern 215, the connecting electrode 235, and the second sub-power wiring 352. The second planarization layer 275 may be formed of an organic material or an inorganic material. In some exemplary embodiments, the second planarization layer 275 may include an organic material.

[0141] The first barrier pattern 371 may be disposed in the peripheral region 20 on the protective insulating layer 400 and the second sub-power wiring 352. The first barrier pattern 371 may be separated from the second planarization layer 275 in the direction from the display region 10 to the peripheral region 20, and may cover the first end of the second sub-power wiring 352 disposed in the second opening 402. For example, the first barrier pattern 371 may be disposed along the contour of the peripheral edge of the display region 10. In other words, the first barrier pattern 371 may surround the display region 10 in the first peripheral region 21, the second peripheral region 22, and the third peripheral region 23. In some exemplary embodiments, the first barrier pattern 371 may be used to block leakage of the second thin film encapsulation layer 452. The first barrier pattern 371 may include an organic material or an inorganic material. In some exemplary embodiments, the first barrier pattern 371 may include an organic material. In addition, the top surface of the second planarization layer 275 and the top surface of the first barrier pattern 371 may be at the same level.

[0142] The lower electrode 290 may be disposed in the display region 10 on the second planarization layer 275. The lower electrode 290 may be connected to the connection electrode 235 through a contact hole formed by removing a portion of the second planarization layer 275, and the lower electrode 290 may be electrically connected to the semiconductor element 250. The lower electrode 290 may include a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These materials may be used alone or in combination with each other. In other exemplary embodiments, the lower electrode 290 may have a multilayer structure including a plurality of layers.

[0143] The connection pattern 295 may be disposed in the peripheral region 20 on the second planarization layer 275, the protective insulation layer 400, the first barrier pattern 371, and the second sub power wiring 352. The connection pattern 295 may have a lower open ring shape. Figure 6, the second planarization layer 275 shown in the figure is disposed on the inner side of the opening 490, the protective insulating layer 400, the first barrier pattern 371, and the second sub-power wiring 352 disposed in the second opening 402, and may extend in the direction from the display area 10 to the peripheral area 20. In other words, the connection pattern 295 may be disposed above the second planarization layer 275, the first barrier pattern 371, and the second sub-power wiring 352 also located above the protective insulating layer 400. In some exemplary embodiments, the connection pattern 295 may overlap with the first power wiring 350 in a portion of the first peripheral area 21, and the end of the first power wiring 350 may be aligned with the end of the connection pattern 295. The connection pattern 295 may include a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These materials may be used alone or in combination with each other. In other exemplary embodiments, the connection pattern 295 may have a multilayer structure including a plurality of layers. In some exemplary embodiments, the top surface of the lower electrode 290 and the uppermost surface of the connection pattern 295 may be at the same level.

[0144] The pixel defining layer 310 may be disposed in the display region 10 and the peripheral region 20 on the second planarization layer 275. In some exemplary embodiments, as shown in FIG. Figure 6 As shown in , the pixel defining layer 310 may extend in a direction from the display region 10 to the peripheral region 20 while exposing a portion of the lower electrode 290 in the display region 10, and the pixel defining layer 310 may be disposed on the connection pattern 295 while exposing the connection pattern 295 disposed in the opening 490 in the second peripheral region 22. Optionally, as Figure 7 As shown in , the pixel defining layer 310 may expose a portion of the lower electrode 290 in the display region 10 while extending in a direction from the display region 10 to the peripheral region 20, and the pixel defining layer 310 may be disposed on the connection pattern 295 while exposing the connection pattern 295 disposed on the second planarization layer 275 in the first peripheral region 21. The pixel defining layer 310 may be formed of an organic material or an inorganic material. In some exemplary embodiments, the pixel defining layer 310 may include an organic material.

[0145] The second barrier pattern 372 may be disposed in the peripheral region 20 on the connection pattern 295. The second barrier pattern 372 may be spaced apart from the pixel defining layer 310 in the direction from the display region 10 to the peripheral region 20, and may cover the connection pattern 295 disposed on the first barrier pattern 371. For example, the second barrier pattern 372 may be disposed along the outline of the display region 10. In other words, the second barrier pattern 372 may surround the display region 10 in the first peripheral region 21, the second peripheral region 22, and the third peripheral region 23. In some exemplary embodiments, the second barrier pattern 372 may be used together with the first barrier pattern 371 to block leakage of the second thin film encapsulation layer 452. The second barrier pattern 372 may include an organic material or an inorganic material. In some exemplary embodiments, the second barrier pattern 372 may include an organic material. In addition, the top surface of the pixel defining layer 310 and the top surface of the second barrier pattern 372 may be at the same level.

[0146] Therefore, the barrier structure 370 including the first barrier pattern 371 and the second barrier pattern 372 may be provided in the above configuration.

[0147] Although the OLED display device 100 has been described as including one blocking structure 370, the configuration of the exemplary embodiment is not limited thereto. For example, in other exemplary embodiments, at least one blocking structure may be further provided while being spaced apart from the blocking structure 370 in the direction from the display region 10 to the peripheral region 20. In other words, the OLED display device 100 may include at least two blocking structures.

[0148] The portion formed between the pixel defining layer 310 and the blocking structure 370 may be defined as a first blocking region. The first blocking region may be positioned parallel to the blocking structure 370, and the first planarization layer 270, the second planarization layer 275, and the pixel defining layer 310 may not be disposed in the first blocking region. For example, in order to prevent moisture and / or water from penetrating into the display region 10 through the first planarization layer 270, the second planarization layer 275, and the pixel defining layer 310 disposed in the peripheral region 20, the first planarization layer 270, the second planarization layer 275, and the pixel defining layer 310 may not be disposed in the first blocking region. In other exemplary embodiments, when the OLED display device 100 further includes an additional blocking structure, the second blocking region may be additionally formed between the blocking structure 370 and the additional blocking structure.

[0149] The light emitting layer 330 may be disposed on the substrate 110 in a portion of the peripheral region 20 and in the display region 10 (see Fig.21). For example, the light emitting layer 330 may be disposed on the pixel defining layer 310 and the lower electrode 290 in the display region 10 while extending in a direction from the display region 10 to the peripheral region 20, and may be disposed on a portion of the pixel defining layer 310 in the peripheral region 20. In other words, the light emitting layer 330 may be disposed over the pixel defining layer 310 and the lower electrode 290. In some exemplary embodiments, the light emitting layer 330 may not overlap the connection pattern 295 positioned in the opening 490 in the second peripheral region 22 and the connection pattern 295 exposed by the pixel defining layer 310 positioned in the first peripheral region 21.

[0150] The light emitting layer 330 may have a multi-layer structure including an organic light emitting layer ("EML"), a hole injection layer ("HIL"), a hole transport layer ("HTL"), an electron transport layer ("ETL"), an electron injection layer ("EIL"), etc. In some exemplary embodiments, the EML, the HIL, the HTL, the ETL, and the EIL may be disposed in the peripheral region 20. In other exemplary embodiments, the HIL, the HTL, the ETL, and the EIL may be disposed in the peripheral region 20 in addition to the EML.

[0151] The EML of the light emitting layer 330 may be formed using at least one of the light emitting materials for emitting different colors of light (i.e., red light, green light, blue light, etc.) according to the sub-pixel. Alternatively, the EML of the light emitting layer 330 may be formed by stacking a plurality of light emitting materials for emitting different colors of light such as red light, green light, or blue light to emit white light as a whole. In this case, a color filter may be provided on the light emitting layer 330 provided on the lower electrode 290. The color filter may include at least one of a red color filter, a green color filter, and a blue color filter. Alternatively, the color filter may include a yellow color filter, a cyan color filter, and a magenta color filter. The color filter may include a photosensitive resin or a color photoresist.

[0152] The upper electrode 340 may be disposed on the substrate 110 in a portion of the peripheral region 20 and in the display region 10 (see Fig.23 For example, the upper electrode 340 may be disposed on the light emitting layer 330 in the display region 10 while extending in a direction from the display region 10 to the peripheral region 20, and may be disposed on the light emitting layer 330, a portion of the pixel defining layer 310, and the peripheral region 20. Figure 6 The connection pattern 295 provided in the opening 490 shown in FIG. Figure 7 In other words, the upper electrode 340 may be disposed above the light emitting layer 330, the pixel defining layer 310, and the connection pattern 295. In some exemplary embodiments, the upper electrode 340 may be disposed above the light emitting layer 330, the pixel defining layer 310, and the connection pattern 295. Figure 6The connection pattern 295 and the opening 490 are provided in the Figure 7 The upper electrode 340 is directly in contact with the connection pattern 295 exposed by the pixel defining layer 310 as shown in FIG, and can receive the low power supply voltage ELVSS from the connection pattern 295. The upper electrode 340 may include a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These materials may be used alone or in combination with each other. In other exemplary embodiments, the upper electrode 340 may have a multilayer structure including a plurality of layers.

[0153] Thus, a sub-pixel structure 200 including a lower electrode 290 , a light emitting layer 330 , and an upper electrode 340 may be provided.

[0154] Although Figure 6 The sub-pixel structure 200 and Figure 7 The sub-pixel structures 200 are assumed to have the same reference numerals for convenience of explanation, but Figure 6 The sub-pixel structure 200 and Figure 7 The sub-pixel structures 200 may be different from each other. In other words, Figure 6 The sub-pixel structure 200 may be a sub-pixel structure disposed in the display region 10 adjacent to the second peripheral region 22. Figure 7 The sub-pixel structure 200 may be a sub-pixel structure disposed in the display region 10 adjacent to the first peripheral region 21 .

[0155] The capping layer 345 may be disposed on the substrate 110 in a portion of the first peripheral region 21, a portion of the second peripheral region 22, and the display region 10. For example, the capping layer 345 may be disposed on the upper electrode 340 in the display region 10 while extending in a direction from the display region 10 to the peripheral region 20, and may be disposed on the upper electrode 340 in the peripheral region 20. In other words, the capping layer 345 may be disposed above the upper electrode 340 in the display region 10 and the peripheral region 20. In some exemplary embodiments, the capping layer 345 may overlap the upper electrode 340 in the peripheral region 20. The capping layer 345 may protect the sub-pixel structure 200, and may include an organic material or an inorganic material. In some exemplary embodiments, the capping layer 345 may include a triamine derivative, an arylenediamine derivative, 4,4'-N,N'-dicarbazole-biphenyl (4,4'-bis(N-carbazolyl)-1,1'-biphenyl) (CBP), tri-8-hydroxyquinoline aluminum (Alq 3 )wait.

[0156] The first thin film encapsulation layer 451 may be disposed in the display region 10 and the peripheral region 20 on the substrate 110. For example, the first thin film encapsulation layer 451 may be disposed on the cover layer 345 in the display region 10 while extending in a direction from the display region 10 to the peripheral region 20, and may be disposed on the cover layer 345, the pixel defining layer 310, the blocking structure 370, and the connection pattern 295 in the peripheral region 20. In other words, the first thin film encapsulation layer 451 may be disposed over the cover layer 345, the pixel defining layer 310, the blocking structure 370, and the connection pattern 295. In some exemplary embodiments, the first thin film encapsulation layer 451 may be in direct contact with the cover layer 345 in the opening 490, and may be in direct contact with the connection pattern 295 in the blocking region (e.g., a portion positioned between the pixel defining layer 310 and the blocking structure 370 in the second peripheral region 22). The first thin film encapsulation layer 451 may prevent the sub-pixel structure 200 from being degraded due to the penetration of moisture, oxygen, and the like. In addition, the first thin film encapsulation layer 451 may be used to protect the sub-pixel structure 200 from external impact. The first thin film encapsulation layer 451 may include a flexible inorganic material.

[0157] The second thin film encapsulation layer 452 may be disposed on the first thin film encapsulation layer 451 in a portion of the peripheral region 20 and the display region 10. The second thin film encapsulation layer 452 may overlap a portion of the sidewall of the blocking structure 370. Alternatively, the second thin film encapsulation layer 452 may not overlap the blocking structure 370, or may cover the blocking structure 370 while extending in a direction from the display region 10 to the peripheral region 20. The second thin film encapsulation layer 452 may improve the flatness of the OLED display device 100, and may protect the sub-pixel structure 200. The second thin film encapsulation layer 452 may include a flexible organic material.

[0158] The third thin film encapsulation layer 453 may be disposed on the second thin film encapsulation layer 452 and the first thin film encapsulation layer 451. The third thin film encapsulation layer 453 may cover the second thin film encapsulation layer 452 in the display area 10 while being disposed with a uniform thickness along the contour of the second thin film encapsulation layer 452, and may extend to the peripheral area 20. The third thin film encapsulation layer 453 may be disposed along a portion of the second thin film encapsulation layer 452 and the contour of the first thin film encapsulation layer 451 in the peripheral area 20. The third thin film encapsulation layer 453 may, together with the first thin film encapsulation layer 451, prevent the sub-pixel structure 200 from being degraded due to the penetration of moisture, oxygen, etc. In addition, the third thin film encapsulation layer 453 may be used together with the first thin film encapsulation layer 451 and the second thin film encapsulation layer 452 to protect the sub-pixel structure 200 from external impact. The third thin film encapsulation layer 453 may include a flexible inorganic material.

[0159] Therefore, a thin film encapsulation structure 450 including a first thin film encapsulation layer 451, a second thin film encapsulation layer 452, and a third thin film encapsulation layer 453 may be provided. Alternatively, the thin film encapsulation structure 450 may have a five-layer structure formed by stacking the first to fifth thin film encapsulation layers or a seven-layer structure formed by stacking the first to seventh thin film encapsulation layers.

[0160] As mentioned above, the above configuration can be set Figure 6 and Figure 7 The OLED display device 100 shown in FIG.

[0161] The OLED display device 100 according to some exemplary embodiments of the present invention includes the first power wiring 350 and the connection pattern 295 having a relatively wide width, so that in the OLED display device 100, heat generated in the first power wiring 350 positioned in a portion of the first peripheral area 21 and the second peripheral area 22 can be relatively reduced.

[0162] In addition, the OLED display device 100 includes the first power wiring 350 and the connection pattern 295 having a relatively wide width, so that in the OLED display device 100, a relatively larger number of openings 490 for directly contacting the connection pattern 295 with the first power wiring 350 in the second peripheral region 22 can be formed. In other words, in the OLED display device 100, heat generated in the first power wiring 350 positioned in a portion of the first peripheral region 21 and the second peripheral region 22 can be further reduced. Therefore, defects of the OLED display device 100 due to heat generation occurring in the first power wiring 350 in a portion of the first peripheral region 21 and the second peripheral region 22 can be relatively reduced.

[0163] Figures 8 to 26 is a cross-sectional view showing a method of manufacturing an organic light emitting diode display device according to an exemplary embodiment of the invention. Figures 8 to 20 , Fig. 22 , Fig.23 , Fig.25 and Fig.26 is a cross-sectional view showing a method of manufacturing an organic light emitting diode display device, Fig.21 is a plan view showing a light emitting layer included in an organic light emitting diode display device, and Fig.24 is a plan view showing an upper electrode included in an organic light emitting diode display device.

[0164] Reference Figure 8, a rigid glass substrate 105 may be provided. A substrate 110 including a transparent material or an opaque material may be formed on the rigid glass substrate 105. The substrate 110 may be formed by using a flexible transparent resin substrate. In some exemplary embodiments, the substrate 110 may have a configuration in which a first organic layer, a first barrier layer, a second organic layer, and a second barrier layer are sequentially stacked. The first barrier layer and the second barrier layer may include an inorganic material such as silicon oxide. In addition, the first organic layer and the second organic layer may include an organic material such as a polyimide resin. In this case, each of the first barrier layer and the second barrier layer may block moisture that penetrates the first organic layer and the second organic layer.

[0165] The buffer layer 115 may be formed on the substrate 110. In some exemplary embodiments, the buffer layer 115 may be formed in the display region 10 and the second peripheral region 22 on the entire substrate 110. Depending on the type of the substrate 110, at least two buffer layers 115 may be provided on the substrate 110, or the buffer layer 115 may not be provided on the substrate 110. The buffer layer 115 may be formed using a silicon compound, a metal oxide, or the like. For example, the buffer layer 115 may include SiO x 、SiN x 、SiO x N y 、SiO x C y 、SiC x N y 、AlO x 、AlN x 、TaO x , HfO x 、ZrO x 、TiO x wait.

[0166] An active layer 130 may be formed in the display region 10 on the buffer layer 115. The active layer 130 may be formed using an oxide semiconductor, an inorganic semiconductor, an organic semiconductor, etc. The active layer 130 may have a source region, a drain region, and a channel region positioned between the source region and the drain region.

[0167] The gate insulating layer 150 may be formed on the active layer 130. The gate insulating layer 150 may cover the active layer 130 in the display region 10 on the buffer layer 115, and may extend in a direction from the display region 10 to the peripheral region 20. For example, the gate insulating layer 150 may fully cover the active layer 130 on the buffer layer 115, and may have a substantially flat top surface without causing steps around the active layer 130. Alternatively, the gate insulating layer 150 may cover the active layer 130 on the buffer layer 115 while being formed with a uniform thickness along the contour of the active layer 130, or may be formed in the display region 10 and the second peripheral region 22 on the entire buffer layer 115. The gate insulating layer 150 may be formed using a silicon compound, a metal oxide, or the like. In other exemplary embodiments, the gate insulating layer 150 may have a multilayer structure having a plurality of insulating layers including materials different from each other.

[0168] The first gate electrode 170 may be formed on the gate insulating layer 150 in the display region 10. The first gate electrode 170 may be formed on a portion of the gate insulating layer 150 under which the active layer 130 is positioned. The first gate electrode 170 may be formed using a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These materials may be used alone or in combination with one another. In other exemplary embodiments, the first gate electrode 170 may have a multilayer structure including a plurality of layers.

[0169] A first interlayer insulating layer 190 may be formed on the first gate electrode 170. The first interlayer insulating layer 190 may cover the first gate electrode 170 in the display region 10 on the gate insulating layer 150, and may extend in a direction from the display region 10 to the peripheral region 20. For example, the first interlayer insulating layer 190 may fully cover the first gate electrode 170 on the gate insulating layer 150, and may have a substantially flat top surface without causing steps around the first gate electrode 170. Alternatively, the first interlayer insulating layer 190 may cover the first gate electrode 170 on the gate insulating layer 150, and may be formed with a uniform thickness along the contour of the first gate electrode 170. The first interlayer insulating layer 190 may be formed using a silicon compound, a metal oxide, or the like. In other exemplary embodiments, the first interlayer insulating layer 190 may have a multilayer structure having a plurality of insulating layers including materials different from each other.

[0170] The second gate electrode 175 may be formed in the display region 10 on the first interlayer insulating layer 190. The second gate electrode 175 may be formed on a portion of the first interlayer insulating layer 190 under which the first gate electrode 170 is positioned. The second gate electrode 175 may be formed using a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These materials may be used alone or in combination with one another. In other exemplary embodiments, the second gate electrode 175 may have a multilayer structure including a plurality of layers.

[0171] A second interlayer insulating layer 195 may be formed on the second gate electrode 175. The second interlayer insulating layer 195 may cover the second gate electrode 175 in the display region 10 on the first interlayer insulating layer 190, and may extend in a direction from the display region 10 to the peripheral region 20. For example, the second interlayer insulating layer 195 may fully cover the second gate electrode 175 on the first interlayer insulating layer 190, and may have a substantially flat top surface without causing a step around the second gate electrode 175. Alternatively, the second interlayer insulating layer 195 may cover the second gate electrode 175 on the first interlayer insulating layer 190, and may be formed with a uniform thickness along the contour of the second gate electrode 175. The second interlayer insulating layer 195 may be formed using a silicon compound, a metal oxide, or the like. In other exemplary embodiments, the second interlayer insulating layer 195 may have a multilayer structure having a plurality of insulating layers including materials different from each other.

[0172] Reference Fig. 9 , a source electrode 210 and a drain electrode 230 may be formed in the display area 10 on the second interlayer insulating layer 195. The source electrode 210 may be connected to the source region of the active layer 130 through a contact hole formed by removing a first portion of the gate insulating layer 150, a first portion of the first interlayer insulating layer 190, and a first portion of the second interlayer insulating layer 195, and the drain electrode 230 may be connected to the drain region of the active layer 130 through a contact hole formed by removing a second portion of the gate insulating layer 150, a second portion of the first interlayer insulating layer 190, and a second portion of the interlayer insulating layer 195. Each of the source electrode 210 and the drain electrode 230 may be formed using a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These materials may be used alone or in combination with each other. In other exemplary embodiments, each of the source electrode 210 and the drain electrode 230 may have a multilayer structure including a plurality of layers.

[0173] Thus, the semiconductor element 250 including the active layer 130 , the gate insulating layer 150 , the first gate electrode 170 , the first interlayer insulating layer 190 , the second gate electrode 175 , the second interlayer insulating layer 195 , the source electrode 210 , and the drain electrode 230 may be formed.

[0174] The first sub power wiring 351 may be formed in a portion of the first peripheral region 21, the second peripheral region 22, and the third peripheral region 23 on the second interlayer insulating layer 195 (eg, see FIG. 2A to FIG. 2D In some exemplary embodiments, the first sub-power wiring 351 may have a first width W1 in a portion of the first peripheral region 21 and the second peripheral region 22, and may have a second width W2 less than the first width W1 in the third peripheral region 23. In other words, the first sub-power wiring 351 may have different widths in the first peripheral region 21, the second peripheral region 22, and the third peripheral region 23. The first sub-power wiring 351 may be formed using a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. For example, Au, Ag, Al, Pt, Ni, Ti, Pd, Mg, Ca, Li, Cr, Ta, W, Cu, Mo, Sc, Nd, Ir, an aluminum alloy, AlN x , silver alloy, WN x , copper alloy, molybdenum alloy, TiN x CrN x 、TaN x 、SrRu x O y 、ZnO x 、ITO、SnO x 、InO x 、GaO x , IZO, etc. to form the first sub-power wiring 351. These materials may be used alone or in combination with each other. Optionally, the first sub-power wiring 351 may have a multilayer structure including a plurality of layers. In some exemplary embodiments, the source electrode 210, the drain electrode 230, and the first sub-power wiring 351 may be formed simultaneously on the same layer using the same material.

[0175] For example, after forming a preliminary first electrode layer on the second interlayer insulating layer 195 , the preliminary first electrode layer may be partially etched to simultaneously form the source electrode 210 , the drain electrode 230 , and the first sub power wiring 351 .

[0176] Reference Fig.10, a protective insulating layer 400 may be formed on the second interlayer insulating layer 195, the source electrode 210 and the drain electrode 230, and the first sub power wiring 351. The protective insulating layer 400 may cover the source electrode 210 and the drain electrode 230 in the display region 10 on the second interlayer insulating layer 195, and may cover the first sub power wiring 351 in the second peripheral region 22 on the second interlayer insulating layer 195. In some exemplary embodiments, the protective insulating layer 400 may have a first opening 401 and a second opening 402 for exposing a portion of the first sub power wiring 351 in the peripheral region 20 (or the first peripheral region 21 and the second peripheral region 22). In addition, the protective insulating layer 400 may have an opening for exposing a portion of the drain electrode 230 in the display region 10. For example, the protective insulating layer 400 may sufficiently cover the source electrode 210 and the drain electrode 230 and the first sub-power wiring 351 on the second interlayer insulating layer 195, and may have a substantially flat top surface without causing steps around the source electrode 210 and the drain electrode 230 and the first sub-power wiring 351. Alternatively, the protective insulating layer 400 may cover the source electrode 210 and the drain electrode 230 and the first sub-power wiring 351 on the second interlayer insulating layer 195, and may be formed to a substantially uniform thickness along the contours of the source electrode 210 and the drain electrode 230 and the first sub-power wiring 351. The protective insulating layer 400 may be formed using silicon compounds, metal oxides, etc. In other exemplary embodiments, the protective insulating layer 400 may have a multilayer structure having a plurality of insulating layers including materials different from each other.

[0177] Reference Fig.11, a first planarization layer 270 may be formed on the protective insulating layer 400. The first planarization layer 270 may be formed on the protective insulating layer 400 in a portion of the peripheral region 20 (e.g., a portion of the first peripheral region 21 and a portion of the second peripheral region 22) and the display region 10. In other words, the first planarization layer 270 may cover the protective insulating layer 400 in the display region 10 while extending in a direction from the display region 10 to the peripheral region 20, and may expose the first opening 401 and the second opening 402 of the protective insulating layer 400 in the peripheral region 20. In other words, the first planarization layer 270 may extend from the display region 10 to the peripheral region 20 to cover at least a portion of the first opening 401. In addition, the first planarization layer 270 may have a contact hole for exposing a portion of the drain electrode 230. For example, the first planarization layer 270 may have a relatively thick thickness, and in this case, the first planarization layer 270 may have a substantially flat top surface. In order to realize such a flat top surface of the first planarization layer 270, a planarization process may be additionally performed on the first planarization layer 270. Alternatively, the first planarization layer 270 may be formed with a uniform thickness along the contour of the protective insulation layer 400 on the protective insulation layer 400. An organic material may be used to form the first planarization layer 270. For example, the first planarization layer 270 may include a photoresist, a polyacrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, an acrylic resin, an epoxy resin, etc.

[0178] Reference Fig.12 , a wiring pattern 215 and a connecting electrode 235 may be formed in the display area 10 on the first planarization layer 270. The connecting electrode 235 may be separated from the wiring pattern 215 in the display area 10 on the first planarization layer 270. The connecting electrode 235 may be connected to the drain electrode 230 through a contact hole of the first planarization layer 270 positioned in the display area 10. Each of the wiring pattern 215 and the connecting electrode 235 may be formed using a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These materials may be used alone or in combination with each other. In other exemplary embodiments, each of the wiring pattern 215 and the connecting electrode 235 may have a multilayer structure including a plurality of layers.

[0179] A second sub power wiring 352 (eg, see FIG. 2 ) may be formed in the peripheral region 20 on the first planarization layer 270. FIG. 2A to FIG. 2DIn some exemplary embodiments, the second sub-power wiring 352 may have a first width W1 in a portion of the first peripheral region 21 and the second peripheral region 22, and may have a second width W2 that is smaller than the first width W1 in the third peripheral region 23. In other words, the second sub-power wiring 352 may have different widths in the second peripheral region 22 and the third peripheral region 23. The second sub-power wiring 352 may be in direct contact with the first sub-power wiring 351 through the first opening 401 in the first peripheral region 21 and the second peripheral region 22, and may be in direct contact with the first sub-power wiring 351 through the second opening 402. In addition, the second sub-power wiring 352 may have an opening for exposing the top surface of the protective insulating layer 400 between the first opening 401 and the second opening 402 in the first peripheral region 21 and the second peripheral region 22. Alternatively, the second sub-power wiring 352 may be continuously formed without openings in the first peripheral region 21 and the second peripheral region 22. The second sub-power wiring 352 may be formed using a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These materials may be used alone or in combination with each other. Alternatively, the second sub-power wiring 352 may have a multilayer structure including a plurality of layers. In some exemplary embodiments, the wiring pattern 215, the connection electrode 235, and the second sub-power wiring 352 may be formed simultaneously on the same layer using the same material.

[0180] For example, after forming a preliminary second electrode layer on the first planarization layer 270 , the first sub power wiring 351 , and the protective insulating layer 400 , the preliminary second electrode layer may be partially etched to simultaneously form the wiring pattern 215 , the connection electrode 235 , and the second sub power wiring 352 .

[0181] Reference Fig.13 and Fig.14 , a second planarization layer 275 may be formed on the wiring pattern 215, the connection electrode 235, the second sub power wiring 352, and the first planarization layer 270. The second planarization layer 275 may cover the wiring pattern 215 and the connection electrode 235 in the display region 10 on the first planarization layer 270 while extending in a direction from the display region 10 to the peripheral region 20, and may cover the second sub power wiring 352 in the peripheral region 20. In some exemplary embodiments, as Fig.13 As shown in , the second planarization layer 275 may have a plurality of openings 490 for exposing the top surface of the second sub power wiring 352 in the second peripheral region 22. In addition, the openings 490 may be formed in a portion where the first power wiring 350 and the connection pattern 295 overlap each other in the third peripheral region 23. Fig.14, the second planarization layer 275 is configured without an opening for exposing the top surface of the second sub power wiring 352 in the first peripheral region 21. In other words, the second planarization layer 275 positioned in the first peripheral region 21 may cover the second sub power wiring 352 adjacent to the display region 10.

[0182] In addition, the second planarization layer 275 may cover the end of the second sub-power wiring 352 formed in the first opening 401 in the peripheral area 20, and may have a contact hole for exposing the connection electrode 235 in the display area 10. The second planarization layer 275 may have a relatively thick thickness to fully cover the wiring pattern 215, the connection electrode 235, and the second sub-power wiring 352, and in this case, the second planarization layer 275 may have a substantially flat top surface. In order to achieve such a flat top surface of the second planarization layer 275, a planarization process may be additionally performed on the second planarization layer 275. Optionally, the second planarization layer 275 may cover the wiring pattern 215, the connection electrode 235, and the second sub-power wiring 352, and may be formed with a uniform thickness along the contours of the wiring pattern 215, the connection electrode 235, and the second sub-power wiring 352. The second planarization layer 275 may be formed using an organic material.

[0183] A first barrier pattern 371 may be formed in the peripheral region 20 on the protective insulating layer 400 and the second sub power wiring 352. The first barrier pattern 371 may be spaced apart from the second planarization layer 275 in a direction from the display region 10 to the peripheral region 20, and may cover a first end of the second sub power wiring 352 formed in the second opening 402. For example, the first barrier pattern 371 may be formed along the contour of the peripheral edge of the display region 10. In other words, the first barrier pattern 371 may surround the display region 10 in the first peripheral region 21, the second peripheral region 22, and the third peripheral region 23. In some exemplary embodiments, the second planarization layer 275 and the first barrier pattern 371 may be formed simultaneously using the same material.

[0184] Reference Fig.15 and Fig.16 , a lower electrode 290 may be formed in the display area 10 on the second planarization layer 275. The lower electrode 290 may be connected to the connection electrode 235 through a contact hole formed by removing a portion of the second planarization layer 275. The lower electrode 290 may be formed using a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These materials may be used alone or in combination with one another. In other exemplary embodiments, the lower electrode 290 may have a multilayer structure including a plurality of layers.

[0185] A connection pattern 295 may be formed in the peripheral region 20 on the second planarization layer 275, the protective insulation layer 400, the first barrier pattern 371, and the second sub power wiring 352. Fig.15 The connection pattern 295 is formed on the inner side of the opening 490 of the second planarization layer 275 shown in FIG, the protective insulating layer 400 positioned between the second planarization layer 275 and the first barrier pattern 371, the first barrier pattern 371, and the second sub-power wiring 352 formed in the second opening 402, and the connection pattern 295 can be extended in the direction from the display area 10 to the peripheral area 20. In other words, the connection pattern 295 can be formed along the contours of the second planarization layer 275, the protective insulating layer 400, the first barrier pattern 371, and the second sub-power wiring 352. The connection pattern 295 can be formed using a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These materials can be used alone or in combination with each other. In other exemplary embodiments, the connection pattern 295 may have a multilayer structure including a plurality of layers. In some exemplary embodiments, the lower electrode 290 and the connection pattern 295 can be formed simultaneously using the same material.

[0186] For example, after forming a preliminary third electrode layer on the second planarization layer 275 , the second sub power wiring 352 , and the protective insulating layer 400 , the preliminary third electrode layer may be partially etched to simultaneously form the lower electrode 290 and the connection pattern 295 .

[0187] Reference Fig.17 and Fig.18 , a pixel defining layer 310 may be formed in the display region 10 and the peripheral region 20 on the second planarization layer 275. In some exemplary embodiments, as Fig.17 As shown in , the pixel defining layer 310 may extend in a direction from the display region 10 to the peripheral region 20 while exposing a portion of the lower electrode 290 in the display region 10, and the pixel defining layer 310 may be formed on the connection pattern 295 while exposing the connection pattern 295 in the opening 490 formed in the second peripheral region 22. Alternatively, as Fig.18 As shown in , the pixel defining layer 310 may expose a portion of the lower electrode 290 in the display region 10 while extending in a direction from the display region 10 to the peripheral region 20, and the pixel defining layer 310 may be formed on the connection pattern 295 while exposing the connection pattern 295 formed on the second planarization layer 275 in the first peripheral region 21. The pixel defining layer 310 may be formed using an organic material.

[0188] A second barrier pattern 372 may be formed in the peripheral region 20 on the connection pattern 295. The second barrier pattern 372 may be spaced apart from the pixel defining layer 310 in a direction from the display region 10 to the peripheral region 20, and may cover the connection pattern 295 formed on the first barrier pattern 371. For example, the second barrier pattern 372 may be formed along the contour of the peripheral edge of the display region 10. In other words, the second barrier pattern 372 may surround the display region 10 in the first peripheral region 21, the second peripheral region 22, and the third peripheral region 23. The second barrier pattern 372 may be formed using an organic material. In addition, the pixel defining layer 310 and the second barrier pattern 372 may be formed simultaneously using the same material.

[0189] Thus, a barrier structure 370 including a first barrier pattern 371 and a second barrier pattern 372 may be formed.

[0190] Reference Fig.19 , Fig. 20 and Fig.21 , the light emitting layer 330 may be formed in a portion of the peripheral region 20 and the display region 10 on the substrate 110. For example, the light emitting layer 330 may be formed on the pixel defining layer 310 and the lower electrode 290 in the display region 10 while extending in a direction from the display region 10 to the peripheral region 20, and may be formed on a portion of the pixel defining layer 310 in the peripheral region 20. In other words, the light emitting layer 330 may be formed along the contours of the pixel defining layer 310 and the lower electrode 290. In some exemplary embodiments, the light emitting layer 330 may not overlap the connection pattern 295 positioned in the opening 490 in the second peripheral region 22 and the connection pattern 295 exposed by the pixel defining layer 310 positioned in the first peripheral region 21. The light emitting layer 330 may have a multilayer structure including an EML, a HIL, a HTL, an ETL, an EIL, and the like. The EML of the light emitting layer 330 may be formed using at least one of the light emitting materials for emitting light of different colors according to the sub-pixels. Alternatively, the EML of the light emitting layer 330 may be formed by stacking a plurality of light emitting materials for emitting different colors of light such as red light, green light, or blue light to emit white light as a whole. In this case, a color filter may be formed on the light emitting layer 330 formed on the lower electrode 290. The color filter may include at least one of a red color filter, a green color filter, and a blue color filter. Alternatively, the color filter may include a yellow color filter, a cyan color filter, and a magenta color filter. The color filter may be formed using a photosensitive resin or a color photoresist.

[0191] Reference Fig. 22 , Fig.23 and Fig.24, the upper electrode 340 may be formed on the substrate 110 in a portion of the peripheral region 20 and the display region 10. For example, the upper electrode 340 may be formed on the light emitting layer 330 in the display region 10 while extending in a direction from the display region 10 to the peripheral region 20, and may be formed on the light emitting layer 330, a portion of the pixel defining layer 310, and the peripheral region 20. Fig. 22 The connection pattern 295 formed in the opening 490 shown in FIG. Fig.23 In other words, the upper electrode 340 may be formed along the contours of the light emitting layer 330, the pixel defining layer 310, and the connecting pattern 295. In some exemplary embodiments, the upper electrode 340 may be formed at the same Fig. 22 The connection pattern 295 and the opening 490 shown in FIG. Fig.23 The upper electrode 340 is directly in contact with the connection pattern 295 exposed by the pixel defining layer 310 as shown in FIG. The upper electrode 340 may be formed using a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These materials may be used alone or in combination with each other. In other exemplary embodiments, the upper electrode 340 may have a multilayer structure including a plurality of layers.

[0192] Thus, the sub-pixel structure 200 including the lower electrode 290 , the light emitting layer 330 , and the upper electrode 340 may be formed.

[0193] like Fig. 22 , Fig.23 and Fig.24 As shown in , the upper electrode 340 may protrude from the light emitting layer 330 by a first distance d1 in a direction from the display region 10 to the peripheral region 20. In other words, the area of ​​the upper electrode 340 may be larger than the area of ​​the light emitting layer 330. In addition, when viewed in a plane, the display region 10 may have a rectangular shape with curved corners, and when viewed in a plane, the light emitting layer 330 and the upper electrode 340 may also have a rectangular shape with curved corners.

[0194] Due to the rectangular shape having curved corners when viewed in a plane, the distances by which the upper electrode 340 protrudes from the light emitting layer 330 in the direction from the display area 10 to the peripheral area 20 may be different from each other in the first peripheral area 21, the second peripheral area 22, and the third peripheral area 23. For example, the second distance d2 by which the upper electrode 340 protrudes from the light emitting layer 330 in the area A may be relatively smaller than the distances by which the upper electrode 340 protrudes from the light emitting layer 330 in other areas. In this case, because the second distance d2 is too small in the area A, it may be difficult to form an opening in the second planarizing layer 275 for exposing the second sub power wiring 352. Therefore, the opening 490 is not formed in the second planarizing layer 275 in the area A (see FIG. 4 ). Fig.23 ).

[0195] Refer again Fig. 22 and Fig.23 , a capping layer 345 may be formed on the substrate 110 in a portion of the first peripheral region 21, a portion of the second peripheral region 22, and the display region 10. For example, the capping layer 345 may be formed on the upper electrode 340 in the display region 10 while extending in a direction from the display region 10 to the peripheral region 20, and may be formed on the upper electrode 340 in the peripheral region 20. In other words, the capping layer 345 may be formed along the contour of the upper electrode 340 in the display region 10 and the peripheral region 20. In some exemplary embodiments, the capping layer 345 may overlap with the upper electrode 340 in the peripheral region 20. Triamine derivatives, arylenediamine derivatives, 4,4'-N,N'-dicarbazole-biphenyl (CBP), Alq 3 etc. to form a capping layer 345 .

[0196] Reference Fig.25 and Fig.26 , a first thin film encapsulation layer 451 may be formed on the substrate 110 in the display region 10 and the peripheral region 20. For example, the first thin film encapsulation layer 451 may be formed on the cover layer 345 in the display region 10 while extending in a direction from the display region 10 to the peripheral region 20, and may be formed on the cover layer 345, the pixel defining layer 310, the blocking structure 370, and the connection pattern 295 in the peripheral region 20. In other words, the first thin film encapsulation layer 451 may be formed along the contours of the cover layer 345, the pixel defining layer 310, the blocking structure 370, and the connection pattern 295. In some exemplary embodiments, the first thin film encapsulation layer 451 may be in direct contact with the cover layer 345 in the opening 490, and may be in direct contact with the connection pattern 295 in a portion positioned between the pixel defining layer 310 and the blocking structure 370 in the second peripheral region 22. The first thin film encapsulation layer 451 may be formed using a flexible inorganic material.

[0197] A second thin film encapsulation layer 452 may be formed on the first thin film encapsulation layer 451 in a portion of the peripheral region 20 and the display region 10. The second thin film encapsulation layer 452 may overlap a portion of the sidewall of the blocking structure 370. Alternatively, the second thin film encapsulation layer 452 may not overlap the blocking structure 370, or may cover the blocking structure 370 while extending in a direction from the display region 10 to the peripheral region 20. The second thin film encapsulation layer 452 may be formed using a flexible organic material.

[0198] A third thin film encapsulation layer 453 may be formed on the second thin film encapsulation layer 452 and the first thin film encapsulation layer 451. The third thin film encapsulation layer 453 may cover the second thin film encapsulation layer 452 in the display region 10 while being formed with a uniform thickness along the contour of the second thin film encapsulation layer 452, and may extend to the peripheral region 20. The third thin film encapsulation layer 453 may be formed along a portion of the second thin film encapsulation layer 452 and the contour of the first thin film encapsulation layer 451 in the peripheral region 20. The third thin film encapsulation layer 453 may be formed using a flexible inorganic material.

[0199] Thus, a thin film encapsulation structure 450 including a first thin film encapsulation layer 451, a second thin film encapsulation layer 452, and a third thin film encapsulation layer 453 may be formed. Alternatively, the thin film encapsulation structure 450 may have a five-layer structure formed by stacking the first to fifth thin film encapsulation layers or a seven-layer structure formed by stacking the first to seventh thin film encapsulation layers.

[0200] After forming the thin film encapsulation structure 450, the glass substrate 105 may be removed from the substrate 110. Figure 6 and Figure 7 The OLED display device 100 shown in FIG.

[0201] Fig. 27 and Fig.28 is a cross-sectional view showing an organic light emitting diode display device according to an exemplary embodiment of the invention. For example, Fig. 27 is along Figure 3A A cross-sectional view taken along line II' of Fig.28 is along Figure 3A In addition to the second planarization layer 1275 having a wavy (eg, undulating) shape as shown in the figure, Fig. 27 and Fig.28 The organic light emitting diode display device 500 shown in FIG. Figures 1 to 3A as well as Figures 4 to 7 The OLED display device 100 described above has substantially the same or similar structure. Fig. 27 and Fig.28 In order to avoid redundancy, the reference to Figures 1 to 3A as well as Figures 4 to 7 Redundant description of elements where the elements described are substantially the same or similar.

[0202] Reference Fig. 27 and Fig.28, the OLED display device 500 may include a substrate 110, a buffer layer 115, a semiconductor element 250, a protective insulating layer 400, a first power wiring 350, a first planarization layer 270, a wiring pattern 215, a connection electrode 235, a second planarization layer 1275, a pixel defining layer 310, a sub-pixel structure 200, a capping layer 345, a blocking structure 370, a thin film encapsulation structure 450, etc. In this case, the first power wiring 350 may include a first sub-power wiring 351 and a second sub-power wiring 352, and the sub-pixel structure 200 may include a lower electrode 290, a light emitting layer 330, and an upper electrode 340. In addition, the thin film encapsulation structure 450 may include a first thin film encapsulation layer 451, a second thin film encapsulation layer 452, and a third thin film encapsulation layer 453.

[0203] The second planarization layer 1275 may be disposed on the wiring pattern 215, the connection electrode 235, the second sub power wiring 352, and the first planarization layer 270. The second planarization layer 1275 may cover the wiring pattern 215 and the connection electrode 235 in the display area 10 on the first planarization layer 270 while extending in a direction from the display area 10 to the peripheral area 20, and may cover the second sub power wiring 352 in the peripheral area 20. In some exemplary embodiments, the second planarization layer 1275 is configured to have no opening for exposing the top surface of the second sub power wiring 352 in the first peripheral area 21 and the second peripheral area 22. In other words, the second planarization layer 1275 positioned in the first peripheral area 21 and the second peripheral area 22 may cover the second sub power wiring 352 adjacent to the display area 10. In addition, the second planarization layer 1275 may have an undulating shape in the first peripheral area 21 and the second peripheral area 22. The second planarization layer 1275 has an undulating shape in the first peripheral region 21 and the second peripheral region 22, so that the connection pattern 295, the upper electrode 340, the cap layer 345 and the first thin film encapsulation layer 451 arranged in the first peripheral region 21 and the second peripheral region 22 on the second planarization layer 1275 may also have an undulating shape. In this case, the area of ​​the connection pattern 295 arranged in the first peripheral region 21 and the second peripheral region 22 and the area of ​​the upper electrode 340 directly contacting the connection pattern 295 can be relatively increased. Optionally, the second planarization layer 1275 may have an undulating shape in the first peripheral region 21 or the second peripheral region 22. In other exemplary embodiments, the first planarization layer 270 may have an undulating shape. In addition, the second planarization layer 1275 and / or the first planarization layer 270 arranged in the third peripheral region 23 may have an undulating shape.

[0204] In some exemplary embodiments of the invention, the second planarization layer 1275 has an undulating shape in the first peripheral region 21 and the second peripheral region 22, so that the areas of the connection pattern 295 and the upper electrode 340 disposed in the first peripheral region 21 and the second peripheral region 22 can be relatively increased. Therefore, in the OLED display device 500, the heat generated in the first power wiring 350 positioned in a portion of the first peripheral region 21 and the second peripheral region 22 can be relatively reduced.

[0205] Fig.29 and Fig.30 is a cross-sectional view showing an organic light emitting diode display device according to an exemplary embodiment of the invention. For example, Fig.29 is along Figure 3A A cross-sectional view taken along line II' of Fig.30 is along Figure 3A In addition to the concave-convex pattern 510, Fig.29 and Fig.30 The OLED display device 600 shown in FIG. Fig. 27 and Fig.28 The OLED display device 500 described above has substantially the same or similar structure. Fig.29 and Fig.30 In order to avoid redundancy, the reference to Fig. 27 and Fig.28 Redundant description of elements where the elements described are substantially the same or similar.

[0206] Reference Fig.29 and Fig.30 , the OLED display device 600 may include a substrate 110, a buffer layer 115, a semiconductor element 250, a protective insulating layer 400, a first power wiring 350, a first planarization layer 270, a wiring pattern 215, a connection electrode 235, a concave-convex pattern 510, a second planarization layer 1275, a pixel defining layer 310, a sub-pixel structure 200, a capping layer 345, a blocking structure 370, a thin film encapsulation structure 450, etc. In this case, the first power wiring 350 may include a first sub-power wiring 351 and a second sub-power wiring 352.

[0207] A plurality of concavo-convex patterns 510 may be provided in the first peripheral region 21 and the second peripheral region 22 on the second sub power wiring 352. The concavo-convex pattern 510 may help the second planarization layer 1275 to easily have an undulating shape. For example, the concavo-convex pattern 510 may include an organic material. Alternatively, the concavo-convex pattern 510 may be provided in the first peripheral region 21 or the second peripheral region 22 on the second sub power wiring 352.

[0208] In other exemplary embodiments, the concavo-convex pattern 510 may be disposed in the first peripheral region 21 and the second peripheral region 22 on the second planarization layer 275. In this case, the connection pattern 295 may be disposed along the contour of the concavo-convex pattern 510 in the first peripheral region 21 and the second peripheral region 22, and the connection pattern 295 may have an undulating shape. In addition, the upper electrode 340 disposed on the connection pattern 295 may have an undulating shape.

[0209] The principles of the invention can be applied to various display devices including OLED display devices. For example, embodiments of the invention can be in the form of vehicle display devices, ship display devices, aircraft display devices, portable communication devices, display devices for display or for information transmission, medical display devices, etc.

[0210] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, as will be apparent to one of ordinary skill in the art, the inventive concept is not limited to such embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements.

Claims

1. An organic light emitting diode display device, comprising: a substrate having a display area, a peripheral area and a pad area, the peripheral area at least partially surrounding the display area and including a first peripheral area, a second peripheral area and a third peripheral area, the pad area being disposed on one side of the peripheral area; A light-emitting layer, disposed on the substrate in the display area; a first power supply wiring provided on the substrate in a portion of the first peripheral region, the second peripheral region, and the third peripheral region; a second power wiring disposed in the display region, the first peripheral region, and the third peripheral region on the substrate and not disposed in the second peripheral region, and at least partially surrounded by the first power wiring; a conductive pattern partially overlapping the first power wiring in the portion of the first peripheral region, the second peripheral region, and the third peripheral region on the first power wiring and electrically connected to the first power wiring; as well as an upper electrode disposed in a portion of the peripheral region and the display region on the conductive pattern and the light emitting layer, partially overlapping the first power wiring and the conductive pattern, and electrically connected to the conductive pattern, The first power wiring has a first width in the second peripheral region and a second width in the third peripheral region, and the second width is smaller than the first width.

2. The organic light emitting diode display device according to claim 1, further comprising a plurality of pad electrodes disposed in the first portion of the pad region, in, The first peripheral region is adjacent to the first portion of the pad region where the plurality of pad electrodes are disposed, and The second peripheral region is located on an opposite side of the first peripheral region while being adjacent to a second portion of the pad region where the plurality of pad electrodes are not disposed, and Herein, the first power wiring includes a wiring electrically connected to the plurality of pad electrodes in the first peripheral region.

3. The organic light emitting diode display device according to claim 1, wherein: At least one of the conductive pattern and the upper electrode has a wavy shape in the first peripheral region.

4. The organic light emitting diode display device according to claim 1, wherein: A low power supply voltage is applied to the first power supply wiring, and A high power supply voltage is applied to the second power supply wiring.

5. The organic light emitting diode display device according to claim 1, wherein: the second power wiring includes a wiring having a first portion, a second portion, and a third portion, the first portion being disposed in the first peripheral region, the second portion being disposed in the display region and having a grid shape, and the third portion being disposed in a portion of the third peripheral region to at least partially surround the second portion, and The first portion, the second portion, and the third portion of the second power wiring are formed integrally with each other.

6. The organic light emitting diode display device according to claim 5, wherein: A portion of the first portion and the second portion of the second power wiring adjacent to a boundary between the display area and the peripheral area is connected to each other in the first peripheral area, and Another portion of the second portion and the third portion of the second power wiring adjacent to the boundary between the display area and the peripheral area is connected to each other in the third peripheral area, wherein the third portion of the second power wiring is separated from the inner side of the first power wiring, wherein the third portion of the second power wiring is not provided in the second peripheral area, and The second portion of the second power wiring has a lattice shape in a portion of the display area, and has a stripe shape in another portion of the display area.

7. The organic light emitting diode display device according to claim 1, wherein: The display area is in a rectangular shape with curved corners, and The curved corner of the display area includes: a first corner adjacent the pad region; and a second corner, facing the first corner, and wherein the first corner is adjacent to the second peripheral area, and The second corner is adjacent to the third peripheral area.

8. The organic light emitting diode display device according to claim 1, further comprising: a protective insulating layer disposed between the substrate and the light emitting layer in the display region and the peripheral region and defining an opening in the second peripheral region; a first planarization layer disposed on the protective insulating layer in a portion of the peripheral region and the display region to expose the opening of the protective insulating layer; as well as a second planarization layer provided on the first planarization layer in a part of the peripheral region and the display region and having a plurality of openings exposing the first power wiring in the second peripheral region, wherein the second planarization layer positioned in the first peripheral region does not form the plurality of openings exposing the first power wirings, and wherein the light emitting layer extends from the display area to the peripheral area, and The light emitting layer positioned in the peripheral region does not overlap the plurality of openings of the second planarization layer in the second peripheral region.

9. The organic light emitting diode display device according to claim 8, wherein: The second planarization layer positioned in the first peripheral region has a wavy shape. 10 . The organic light emitting diode display device according to claim 8 , further comprising a plurality of concavo-convex patterns disposed between the first planarization layer and the second planarization layer.

11. The organic light emitting diode display device according to claim 8, further comprising a lower electrode disposed in the display area on the second planarization layer, in, The upper electrode is disposed on the lower electrode, and the upper electrode extends from the display area to the peripheral area, and Wherein, the lower electrode and the conductive pattern are positioned on the same layer.

12. The organic light emitting diode display device according to claim 11, wherein: The upper electrode is in direct contact with the conductive pattern in the second peripheral region.

13. The organic light emitting diode display device according to claim 11, wherein: The upper electrode has a wavy shape in the first peripheral region, and The upper electrode is in direct contact with the conductive pattern in the first peripheral region.

14. The organic light emitting diode display device according to claim 8, wherein: The first power wiring comprises: a first sub-power supply wiring line provided between the substrate and the protective insulating layer and exposed by the opening of the protective insulating layer; and a second sub power wiring, provided between the first planarization layer and the second planarization layer, in direct contact with the first sub power wiring through the opening of the protective insulating layer, and exposed by the plurality of openings of the second planarization layer, and The conductive pattern includes a connection pattern, and the connection pattern is in direct contact with the second sub-power wiring through the plurality of openings of the second planarization layer.

15. The organic light emitting diode display device according to claim 14, further comprising: A semiconductor element is disposed in the display area between the substrate and the protective insulating layer; as well as A wiring pattern and a connection electrode are provided in the display area between the first planarization layer and the second planarization layer, The wiring pattern and the connection electrode are located on the same layer as the second sub-power wiring.

16. The organic light emitting diode display device according to claim 15, wherein: The semiconductor element comprises: An active layer, disposed on the substrate in the display area; A gate insulating layer, disposed on the active layer; A gate electrode, disposed on the gate insulating layer; an interlayer insulating layer, disposed on the gate electrode; and A source electrode and a drain electrode are disposed on the interlayer insulating layer, and The source electrode and the drain electrode are located on the same layer as the first sub-power wiring.

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