Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a manufacturing method are provided. The semiconductor device includes a first semiconductor die, a second semiconductor die, a dielectric layer, a first redistribution layer, and a second redistribution layer. The first semiconductor die includes a first bonding pad and a second bonding pad. The second semiconductor die includes a third bonding pad and a fourth bonding pad. The dielectric layer covers the first semiconductor die and the second semiconductor die, and defines a first opening exposing the first bonding pad and the second bonding pad, and a second opening exposing the third bonding pad and the fourth bonding pad. The first redistribution layer is on the dielectric layer, and electrically connects the first bonding pad and the third bonding pad. The second redistribution layer is on the dielectric layer, and electrically connects the second bonding pad and the fourth bonding pad.

Description

Technical Field

[0001] This invention relates to semiconductor devices and manufacturing methods, and specifically to semiconductor devices comprising a dielectric layer defining openings that expose a plurality of bonding pads, and a method thereof for manufacturing the same. Background Technology

[0002] Conventionally, a fan-out wafer-level packaging structure includes multiple semiconductor dies, an encapsulant surrounding the semiconductor dies, and at least one redistribution layer electrically connecting the semiconductor dies, wherein the redistribution layer is disposed on a dielectric layer on the semiconductor dies and the encapsulant. The dielectric layer may define an opening for at least one bonding pad exposing the die, and the redistribution layer may extend into the opening to contact the bonding pad. However, short circuits between redistribution layers on the sidewalls of the openings in the dielectric layer are not directly detectable. Summary of the Invention

[0003] In some embodiments, a semiconductor device includes a first semiconductor die, a second semiconductor die, a dielectric layer, a first redistribution layer, and a second redistribution layer. The first semiconductor die includes a first bonding pad and a second bonding pad. The second semiconductor die includes a third bonding pad and a fourth bonding pad. The dielectric layer covers the first semiconductor die and the second semiconductor die, and defines a first opening exposing the first bonding pad and the second bonding pad, and a second opening exposing the third bonding pad and the fourth bonding pad. The first redistribution layer is located on the dielectric layer and electrically connects the first bonding pad and the third bonding pad. The second redistribution layer is located on the dielectric layer and electrically connects the second bonding pad and the fourth bonding pad.

[0004] In some embodiments, a semiconductor device includes a semiconductor die and a dielectric layer. The semiconductor die has a surface and includes a first bonding pad, a second bonding pad, and a first passivation layer. The first bonding pad is adjacent to the surface of the semiconductor die. The second bonding pad is adjacent to the surface of the semiconductor die. The first passivation layer is adjacent to the surface of the semiconductor die. The first passivation layer surrounds and exposes the first bonding pad and the second bonding pad. The dielectric layer covers the semiconductor die and defines a first opening exposing the first bonding pad and the second bonding pad, and a measurement opening in a non-bonding pad region.

[0005] In some embodiments, a method for manufacturing a semiconductor device includes: (a) providing a first semiconductor die including a first bonding pad and a second bonding pad; (b) disposing a second semiconductor die adjacent to the first semiconductor die, wherein the second semiconductor die includes a third bonding pad and a fourth bonding pad; (c) forming a dielectric layer to cover the first semiconductor die and the second semiconductor die; and (d) forming a first opening, a second opening, and a measurement opening in the dielectric layer, wherein the first opening exposes the first bonding pad and the second bonding pad, the second opening exposes the third bonding pad and the fourth bonding pad, and the measurement opening is in a non-bonding pad region. Attached Figure Description

[0006] Some aspects of embodiments of the invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that various structures may not be drawn to scale, and the dimensions of various structures may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 A top view illustrating a semiconductor device according to some embodiments of the present invention.

[0008] Figure 2 illustrate Figure 1 The enlarged view of area "A" shown in the image.

[0009] Figure 3 illustrate Figure 2 An enlarged view of area "B" shown in the image.

[0010] Figure 4 illustrate Figure 3 A three-dimensional image.

[0011] Figure 5 Explanation along Figure 1 The image shows a cross-sectional view of the semiconductor device shown in line 5-5.

[0012] Figure 6 illustrate Figure 1 A three-dimensional magnified view of the measurement circuit of a semiconductor device.

[0013] Figure 7 A top view illustrating a semiconductor device according to some embodiments of the present invention.

[0014] Figure 8 A top view illustrating a semiconductor device according to some embodiments of the present invention.

[0015] Figure 9 A top view illustrating a semiconductor device according to some embodiments of the present invention.

[0016] Figure 10 Explanation along Figure 9 The image shows a cross-sectional view of the semiconductor device shown by line 10-10.

[0017] Figure 11 Cross-sectional views of a semiconductor device according to some embodiments of the present invention are shown.

[0018] Figure 12 Cross-sectional views illustrating semiconductor package structures according to some embodiments of the present invention are shown.

[0019] Figure 13 This describes one or more stages of an example of a method for manufacturing a semiconductor device according to some embodiments of the present invention.

[0020] Figure 14 This describes one or more stages of an example of a method for manufacturing a semiconductor device according to some embodiments of the present invention.

[0021] Figure 15 This describes one or more stages of an example of a method for manufacturing a semiconductor device according to some embodiments of the present invention.

[0022] Figure 16 This describes one or more stages of an example of a method for manufacturing a semiconductor device according to some embodiments of the present invention.

[0023] Figure 17 This describes one or more stages of an example of a method for manufacturing a semiconductor device according to some embodiments of the present invention.

[0024] Figure 18 This describes one or more stages of an example of a method for manufacturing a semiconductor device according to some embodiments of the present invention.

[0025] Figure 19 illustrate Figure 18 Top view.

[0026] Figure 20 This describes one or more stages of an example of a method for manufacturing a semiconductor device according to some embodiments of the present invention.

[0027] Figure 21 This describes one or more stages of an example of a method for manufacturing a semiconductor device according to some embodiments of the present invention.

[0028] Figure 22 illustrate Figure 21 Top view. Detailed Implementation

[0029] Common reference numerals are used throughout the accompanying drawings and detailed embodiments to indicate the same or similar components. Embodiments of the invention will be readily understood from the following detailed description, taken in conjunction with the accompanying drawings.

[0030] The following disclosure provides numerous different embodiments or instances of various features for implementing the provided subject matter. Specific examples of components and arrangements are described below to illustrate specific aspects of the invention. Of course, these components and arrangements are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed or disposed in direct contact, and may also include embodiments where additional features may be formed or disposed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of the invention. This repetition is for the purposes of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0031] A fan-out wafer-level package structure may include multiple semiconductor dies, a package body surrounding the semiconductor dies, and at least one redistribution layer electrically connecting the semiconductor dies. Each of the semiconductor dies may include multiple bonding pads and a passivation layer. The passivation layer may define multiple openings corresponding to corresponding bonding pads to expose the corresponding bonding pads. In a comparative embodiment, the fan-out wafer-level package structure may further include a dielectric layer covering the passivation layer of the semiconductor dies and the package body. The redistribution layer may be disposed on the dielectric layer. The dielectric layer may define multiple openings to expose at least one bonding pad of each of the semiconductor dies, and the redistribution layer may extend into the openings of the dielectric layer to contact the bonding pads. In one example, the width of the opening in the dielectric layer may be smaller than the width of the opening in the passivation layer, and the opening in the dielectric layer may be located within the opening in the passivation layer. Therefore, some portions of the dielectric layer may extend into the opening in the passivation layer. However, in another example, the width of the opening in the passivation layer can be reduced to a relatively small value (e.g., less than 30 micrometers), while the opening in the dielectric layer does not need to be reduced to this small value. Therefore, the width of the opening in the dielectric layer can be greater than the width of the opening in the passivation layer, and the dielectric layer does not need to extend into the opening in the passivation layer.

[0032] However, the increased density of the bonding pads reduces the pitch between them (i.e., the spacing between the openings in the passivation layer). The redistributed layers struggle to hold firmly in place between two bonding pads (i.e., between the two openings in the passivation layer). Furthermore, the redistributed layers can be formed via the following steps: An entire metal layer can be formed on the top surface of the dielectric layer and in the openings of the dielectric layer. Then, portions of the metal layer can be etched away to form a patterned circuit layer comprising multiple redistributed layers. However, during the etching process, portions of the metal layer to be etched may not be completely removed. That is, some portions of the metal layer to be etched may remain. Therefore, residual metal can cause short circuits between the redistributed layers on the top surface of the dielectric layer and the redistributed layers on the sidewalls of the openings in the dielectric layer, potentially leading to failure in fan-out wafer-level packages. However, this short circuit is typically not directly detected by applying a probe to the redistributed layer using a test device, as the redistributed layer is damaged upon contact with the probe.

[0033] At least some embodiments of the present invention provide a semiconductor device including a dielectric layer comprising a plurality of openings defining a plurality of bonding pads exposing a semiconductor die. In some embodiments, the dielectric layer may further define measurement openings in non-bonding pad regions for housing measurement circuitry. Current leakage measurement can be performed on the measurement circuitry to simulate the case of a redistribution layer. At least some embodiments of the present invention further provide techniques for manufacturing semiconductor devices.

[0034] Figure 1 A top view illustrating a semiconductor device 1 according to some embodiments of the present invention. Figure 2 illustrate Figure 1 The enlarged view of area "A" shown in the image. Figure 3 illustrate Figure 2 The enlarged view of area "B" shown in the image. Figure 4 illustrate Figure 3 A three-dimensional image. Figure 5 Explanation along Figure 1 The image shows a cross-sectional view of the semiconductor device 1 taken by line 5-5. The semiconductor device 1 includes a first semiconductor die 2, a second semiconductor die 3, a first dielectric layer 12, a patterned circuit layer 13, and a package 18.

[0035] like Figure 1 and Figure 5As shown, the first semiconductor die 2 includes a first body 20, a plurality of bonding pads (including, for example, first bonding pad 22 and second bonding pad 24), and a first passivation layer 23. The material of the first body 20 may include silicon. The first body 20 has a top surface 201 and a bottom surface 202 opposite to the top surface 201. The top surface 201 of the first body 20 may be an active surface, and the bottom surface 202 of the first body 20 may be a backside surface. The material of the bonding pads (including, for example, first bonding pad 22 and second bonding pad 24) may be a conductive metal such as gold, aluminum, or copper. The bonding pads (including, for example, first bonding pad 22 and second bonding pad 24) are disposed adjacent to the top surface 201 of the first body 20. The material of the first passivation layer 23 may include silicon nitride or silicon oxide. A first passivation layer 23 is formed or disposed adjacent to the top surface 201 of the first body 20 to cover a portion of the bonding pads (including, for example, first bonding pad 22 and second bonding pad 24). The first passivation layer 23 defines a plurality of openings 231 to expose corresponding ones of the bonding pads (including, for example, first bonding pad 22 and second bonding pad 24). That is, the first passivation layer 23 surrounds and exposes the bonding pads (including, for example, first bonding pad 22 and second bonding pad 24).

[0036] The size of the second semiconductor die 3 may be the same as or different from the size of the first semiconductor die 2. The second semiconductor die 3 includes a second body 30, a plurality of bonding pads (including, for example, a third bonding pad 32 and a fourth bonding pad 34), and a second passivation layer 33. The material of the second body 30 may include silicon. The second body 30 has a top surface 301 and a bottom surface 302 opposite to the top surface 301. The top surface 301 of the second body 30 may be an active surface, and the bottom surface 302 of the second body 30 may be a back surface. The material of the bonding pads (including, for example, a third bonding pad 32 and a fourth bonding pad 34) may be a conductive metal such as gold, aluminum, or copper. The bonding pads (including, for example, a third bonding pad 32 and a fourth bonding pad 34) are disposed adjacent to the top surface 301 of the second body 30. The material of the second passivation layer 33 may include silicon nitride or silicon oxide. A second passivation layer 33 is formed or disposed adjacent to the top surface 301 of the second body 30 to cover portions of the bonding pads (including, for example, third bonding pad 32 and fourth bonding pad 34). The second passivation layer 33 defines a plurality of openings 331 to expose corresponding ones of the bonding pads (including, for example, third bonding pad 32 and fourth bonding pad 34). That is, the second passivation layer 33 surrounds and exposes the bonding pads (including, for example, third bonding pad 32 and fourth bonding pad 34). In one embodiment, the top surface of the second passivation layer 33 of the second semiconductor die 3 may be substantially coplanar with the top surface of the first passivation layer 23 of the first semiconductor die 2.

[0037] Package 18 (e.g., molding compound) covers at least a portion of the first semiconductor die 2, at least a portion of the second semiconductor die 3, and at least a portion of the first dielectric layer 12. Package 18 has a top surface 181 and a bottom surface 182 opposite to the top surface 181. Figure 5 As shown, the top surface 181 of the package 18 is not coplanar with the top surface of the first passivation layer 23 of the first semiconductor die 2 and the top surface of the second passivation layer 33 of the second semiconductor die 3. The top surface 181 of the package 18 is lower than the top surface of the first passivation layer 23 of the first semiconductor die 2 and the top surface of the second passivation layer 33 of the second semiconductor die 3. The bottom surface 182 of the package 18 is lower than the bottom surface 202 of the first body 20 of the first semiconductor die 2 and the bottom surface 302 of the second body 30 of the second semiconductor die 3. Therefore, the package 18 covers the bottom portion of the first semiconductor die 2 and the bottom portion of the second semiconductor die 3.

[0038] A first dielectric layer 12 is formed or located on the first passivation layer 23 of the first semiconductor die 2, the second passivation layer 33 of the second semiconductor die 3, and the package 18, so as to cover and contact the first passivation layer 23 of the first semiconductor die 2, the second passivation layer 33 of the second semiconductor die 3, and the package 18. The material of the first dielectric layer 12 may include a curable photoimageable dielectric (PID) material, such as epoxy resin or polyimide (PI) including a photoinitiator or another resin material. The first dielectric layer 12 may define a plurality of openings (including, for example, a first opening 122, a second opening 124, a third opening 126, and a measurement opening 128). Figure 2 , Figure 3 and Figure 5 As shown, the first opening 122 exposes a plurality of bonding pads (including, for example, first bonding pad 22 and second bonding pad 24) of the first semiconductor die 2, a plurality of openings 231 of the first passivation layer 23, and a portion of the first passivation layer 23. That is, the plurality of bonding pads (including, for example, first bonding pad 22 and second bonding pad 24) of the first semiconductor die 2, the plurality of openings 231 of the first passivation layer 23, and a portion of the first passivation layer 23 are located within the first opening 122 of the first dielectric layer 12. The size (e.g., width) of the first opening 122 of the first dielectric layer 12 is larger than the size of the opening 231 of the first passivation layer 23. The first dielectric layer 12 does not extend into the opening 231 of the first passivation layer 23 to contact the bonding pads (including, for example, first bonding pad 22 and second bonding pad 24) of the first semiconductor die 2.

[0039] like Figure 2As shown, the second opening 124 exposes a plurality of bonding pads (including, for example, third bonding pads 32 and fourth bonding pads 34) of the second semiconductor die 3, a plurality of openings 331 of the second passivation layer 33, and a portion of the second passivation layer 33. That is, the plurality of bonding pads (including, for example, third bonding pads 32 and fourth bonding pads 34) of the second semiconductor die 3, the plurality of openings 331 of the second passivation layer 33, and a portion of the second passivation layer 33 are located within the second opening 124 of the first dielectric layer 12. The size (e.g., width) of the second opening 124 of the first dielectric layer 12 is larger than the size of the opening 331 of the second passivation layer 33. The first dielectric layer 12 does not extend into the opening 331 of the second passivation layer 33 to contact the bonding pads (including, for example, third bonding pads 32 and fourth bonding pads 34) of the second semiconductor die 3. In one embodiment, the size (e.g., width and depth) of the second opening 124 may be substantially equal to the size of the first opening 122.

[0040] like Figure 2 As shown, the third opening 126 is positioned adjacent to the first opening 122 and the second opening 124. Figure 2 and Figure 5 As shown, the third opening 126 exposes a plurality of bonding pads (including, for example, third bonding pad 32a and fourth bonding pad 34a) of the second semiconductor die 3, a plurality of openings 331 of the second passivation layer 33, and a portion of the second passivation layer 33. That is, the plurality of bonding pads (including, for example, third bonding pad 32a and fourth bonding pad 34a) of the second semiconductor die 3, the plurality of openings 331 of the second passivation layer 33, and a portion of the second passivation layer 33 are located within the third opening 126 of the first dielectric layer 12. The size (e.g., width) of the third opening 126 of the first dielectric layer 12 is larger than the size of the opening 331 of the second passivation layer 33. The first dielectric layer 12 does not extend into the opening 331 of the second passivation layer 33 to contact the bonding pads (including, for example, third bonding pad 32a and fourth bonding pad 34a) of the second semiconductor die 3. In one embodiment, the size (e.g., width and depth) of the third opening 126 may be substantially equal to the size of the second opening 124.

[0041] like Figure 1As shown, the first opening 122, the second opening 124, and the third opening 126 are located in the bonding pad region. That is, bonding pads are present within or corresponding to the first opening 122, the second opening 124, and the third opening 126. In contrast, the measurement opening 128 is located in the non-bonding pad region. That is, there is no bonding pad present or corresponding to the measurement opening 128. In one embodiment, the measurement opening 128 is located at a position corresponding to the exterior of the first semiconductor die 2 and the second semiconductor die 3. Therefore, the measurement opening 128 may expose a portion of the first dielectric layer 12 or a portion of the package 18. In one embodiment, the size (e.g., width and depth) of the measurement opening 128 may be approximately equal to the size of the first opening 122.

[0042] like Figure 1 and Figure 5 As shown, a patterned circuit layer 13 is located on a first dielectric layer 12. The material of the patterned circuit layer 13 may be copper. The patterned circuit layer 13 includes multiple overlay layers (including, for example, a first overlay layer 14 and a second overlay layer 16) and measurement circuitry 19. In one embodiment, the overlay layers (including, for example, a first overlay layer 14 and a second overlay layer 16) and the measurement circuitry 19 may be formed on the same layer and simultaneously. The first overlay layer 14 is located on the first dielectric layer 12 and electrically connects a first bonding pad 22 in a first opening 122 and a third bonding pad 32 in a second opening 124. The first overlay layer 14 may include a trace portion and a pad portion. Figure 1 As shown, one end of the first repetitive layer 14 extends downward into the first opening 122 to cover and contact the first bonding pad 22, and the other end of the first repetitive layer 14 extends upward into the second opening 124 to cover and contact the third bonding pad 32. Therefore, the two ends of the first repetitive layer 14 extend in different directions. Similarly, the second repetitive layer 16 is located on the first dielectric layer 12 and electrically connects the second bonding pad 24 in the first opening 122 and the fourth bonding pad 34 in the second opening 124. The second repetitive layer 16 may include trace portions and pad portions. Figure 1As shown, one end of the second repetitive layer 16 extends downward into the first opening 122 to cover and contact the second bonding pad 24, and the other end of the second repetitive layer 16 extends upward into the second opening 124 to cover and contact the fourth bonding pad 34. Therefore, the two ends of the second repetitive layer 16 extend in different directions. In one embodiment, the second repetitive layer 16 is substantially parallel to the first repetitive layer 14, and the length of the second repetitive layer 16 is substantially equal to the length of the first repetitive layer 14. Additionally, the measurement circuit 19 is located on the first dielectric layer 12 and extends into the measurement opening 128.

[0043] like Figure 3 and Figure 4 As shown, the first re-layer 14 includes a first portion 141, a second portion 142, and a third portion 143. The first portion 141 is located on the first dielectric layer 12. The second portion 142 is located in the first opening 122 and contacts the first bonding pad 22 and the first passivation layer 23. The third portion 143 connects the first portion 141 and the second portion 142. The third portion 143 is located on the top surface of the first dielectric layer 12 and the sidewall 1221 of the first opening 122 and contacts the top surface of the first dielectric layer 12 and the sidewall 1221 of the first opening 122. The first portion 141 can be defined as a trace portion. The second portion 142 and the third portion 143 can be defined as pad portions. Similarly, the second re-layer 16 includes a first portion 161, a second portion 162, and a third portion 163. The first portion 161 is located on the first dielectric layer 12. The second portion 162 is located in the first opening 122 and contacts the second bonding pad 24 and the first passivation layer 23. The third portion 163 connects the first portion 161 and the second portion 162. The third portion 163 is located on the top surface of the first dielectric layer 12 and on the sidewall 1221 of the first opening 122, and contacts the top surface of the first dielectric layer 12 and the sidewall 1221 of the first opening 122. The first portion 161 can be defined as a trace portion. The second portion 162 and the third portion 163 can be defined as pad portions. The first portion 141 of the first layer 14 and the first portion 161 of the second layer 16 are located on portions of the first dielectric layer 12 between the first opening 122 and the second opening 124, or between the second opening 124 and the third opening 126.

[0044] Figure 6 illustrate Figure 1An enlarged perspective view of the measurement circuit 19 of the semiconductor device 1. The measurement circuit 19 is located on a first dielectric layer 12 and in a measurement opening 128. The measurement opening 128 may have a first sidewall 1281, a second sidewall 1282 opposite to the first sidewall 1281, and a bottom surface 1283. In one embodiment, the measurement circuit 19 may include an interdigitated structure comprising a first comb circuit 19a and a second comb circuit 19b facing the first comb circuit 19a. The first comb circuit 19a includes a plurality of first conductive segments 191, a first connecting segment 193, a first testing pad 195, and a third testing pad 197. Each of the first conductive segments 191 is located on the first dielectric layer 12 and extends into the measurement opening 128. That is, each of the first conductive segments 191 is located on and in contact with the top surface of the first dielectric layer 12, the first sidewall 1281 of the measurement opening 128, the bottom surface 1283 of the measurement opening 128, and the second sidewall 1282 of the measurement opening 128. The first connecting segment 193 is located only on the top surface of the first dielectric layer 12. All the first conductive segments 191 are connected to the first connecting segment 193. The first test pad 195 and the third test pad 197 are respectively connected to the two ends of the first connecting segment 193. Similarly, the second comb circuit 19b includes a plurality of second conductive segments 192, second connecting segments 194, second test pads 196, and a fourth test pad 198. Each of the second conductive segments 192 is located on the first dielectric layer 12 and extends into the measurement opening 128. That is, each of the second conductive segments 192 is located on and in contact with the top surface of the first dielectric layer 12, the first sidewall 1281 of the measurement opening 128, the bottom surface 1283 of the measurement opening 128, and the second sidewall 1282 of the measurement opening 128. The second connecting segment 194 is located only on the top surface of the first dielectric layer 12. All second conductive segments 192 are connected to the second connecting segment 194. The second test pad 196 and the fourth test pad 198 are respectively connected to the two ends of the second connecting segment 194.

[0045] like Figure 6As shown, the first conductive segment 191 and the second conductive segment 192 are staggered and isolated from each other. That is, the first conductive segment 191 is not connected to the second comb circuit 19b, and the second conductive segment 192 is not connected to the first comb circuit 19a. Therefore, the first comb circuit 19a and the second comb circuit 19b are isolated from each other. In one embodiment, the linewidth of the first conductive segment 191 and the second conductive segment 192 of the measuring circuit 19 may be approximately equal to the linewidth of the first portion 141 of the first redistribution layer 14 or the first portion 161 of the second redistribution layer 16. In addition, the gap (i.e., linespacing) between the first conductive segment 191 and the second conductive segment 192 of the measuring circuit 19 may be approximately equal to or less than the gap between the first portion 141 of the first redistribution layer 14 and the first portion 161 of the second redistribution layer 16 on the first dielectric layer 12.

[0046] exist Figures 1 to 6In the embodiments described herein, the first opening 122, the second opening 124, the third opening 126, and the measurement opening 128 are formed simultaneously; and the measurement circuit 19 and the redistribution layers (including, for example, the first redistribution layer 14 and the second redistribution layer 16) are formed simultaneously. Therefore, the surface conditions of the sidewalls 1221 of the first opening 122, the sidewalls of the second opening 124, and the sidewalls of the third opening 126 can be substantially the same as the surface condition of the measurement opening 128. The measurement circuit 19 can simulate the state of the redistribution layers (including, for example, the first redistribution layer 14 and the second redistribution layer 16) after the etching process. In a worse case, during the etching process, portions of the sputtered metal layer to be etched may not be completely removed; that is, some portions of the sputtered metal layer to be etched may remain. Therefore, residual metal may cause short circuits between the top surface of the first dielectric layer 12 and the redistribution layers (including, for example, the first redistribution layer 14 and the second redistribution layer 16) on the sidewalls of the openings of the first dielectric layer 12 (including, for example, the sidewall 1221 of the first opening 122, the sidewall of the second opening 124, and the sidewall of the third opening 126). This could potentially lead to malfunction or failure of the semiconductor device 1. However, this short circuit can be detected by applying probes of a test apparatus to the measurement circuit 19, as described below. The first, second, third, and fourth probes of the test apparatus are applied or provided to contact the first test pad 195, the second test pad 196, the third test pad 197, and the fourth test pad 198, respectively. If the current between the first and second probes is greater than or equal to a predetermined value (e.g., 900 picoamperes, PA), this indicates that a short circuit occurs between the first comb circuit 19a and the second comb circuit 19b. That is, residual metal may remain on the top surface of the first dielectric layer 12 adjacent to the measurement opening 128, the first sidewall 1281 of the measurement opening 128, the bottom surface 1283 of the measurement opening 128, and / or the second sidewall 1282 of the measurement opening 128 in the non-bonding pad region. Meanwhile, it can be assumed that residual metal remains on the top surface of the first dielectric layer 12 adjacent to the openings in the bonding pad region (including, for example, the first opening 122, the second opening 124, and the third opening 126), and / or on the sidewalls of the openings in the bonding pad region of the first dielectric layer 12 (including, for example, the sidewall 1221 of the first opening 122, the sidewall of the second opening 124, and the sidewall of the third opening 126). Therefore, it can be assumed that the short circuit occurs between the re-layers (including, for example, the first re-layer 14 and the second re-layer 16), and the quality of the etching process of the re-layers (including, for example, the first re-layer 14 and the second re-layer 16) is determined to be unqualified or abnormal. Then, a compensation process is implemented by another etching process or other suitable process.

[0047] If the current between the first probe and the second probe is less than a predetermined value (e.g., 900 picoamperes (PA)), this means that an open circuit occurs between the first comb circuit 19a and the second comb circuit 19b. That is, no residual metal remains on the top surface of the first dielectric layer 12 adjacent to the measurement opening 128, the first sidewall 1281 of the measurement opening 128, the bottom surface 1283 of the measurement opening 128, and / or the second sidewall 1282 of the measurement opening 128 in the non-bonding pad area. Simultaneously, it can be presumed that no residual metal remains on the top surface of the first dielectric layer 12 adjacent to the openings (including, for example, the first opening 122, the second opening 124, and the third opening 126) in the bonding pad area of ​​the first dielectric layer 12, or on the sidewalls of the openings (including, for example, the sidewall 1221 of the first opening 122, the sidewall of the second opening 124, and the sidewall of the third opening 126) in the bonding pad area of ​​the first dielectric layer 12. Therefore, it can be presumed that the open circuit occurred between the overlay layers (including, for example, the first overlay layer 14 and the second overlay layer 16), and the quality of the etching process of the overlay layers (including, for example, the first overlay layer 14 and the second overlay layer 16) was determined to be qualified or normal.

[0048] Similarly, the currents between the first and fourth probes, the second and third probes, and the second and fourth probes can be used to estimate the quality of the etching process of the re-layers (including, for example, the first re-layer 14 and the second re-layer 16) by the methods described above. Therefore, the quality of the re-layers (including, for example, the first re-layer 14 and the second re-layer 16) can be ensured or improved after the etching process. It should be noted that the probes of the test equipment (the first, second, third, and fourth probes) do not directly contact the re-layers (including, for example, the first re-layer 14 and the second re-layer 16), and therefore, the re-layers (including, for example, the first re-layer 14 and the second re-layer 16) are not damaged.

[0049] Figure 7 A top view illustrating a semiconductor device 1a according to some embodiments of the present invention is shown. Except for the layout of the patterned circuit layer 13a, the semiconductor device 1a is similar to... Figure 1 The semiconductor device 1 shown in the figure. Except for the orientation of the redistribution layers (including, for example, the first redistribution layer 14a and the second redistribution layer 16a), the patterned circuit layer 13a is similar to Figure 1 The patterned circuit layer 13 is shown in the diagram. A first overlay layer 14a is located on the first dielectric layer 12 and electrically connects the first bonding pad 22 in the first opening 122 and the third bonding pad 32' in the second opening 124a. (See diagram for details.) Figure 7As shown, one end of the first repetitive layer 14a extends downward into the first opening 122 to cover and contact the first bonding pad 22, and the other end of the first repetitive layer 14a extends upward into the second opening 124a to cover and contact the third bonding pad 32'. Therefore, the two ends of the first repetitive layer 14a extend in the same direction. The first repetitive layer 14a is generally inverted "U" shaped. Similarly, the second repetitive layer 16a is located on the first dielectric layer 12 and electrically connects the second bonding pad 24 in the first opening 122 and the fourth bonding pad 34' in the second opening 124a. Figure 7 As shown, one end of the second repetitive fabric layer 16a extends downward into the first opening 122 to cover and contact the second bonding pad 24, and the other end of the second repetitive fabric layer 16a extends downward into the second opening 124a to cover and contact the fourth bonding pad 34'. Therefore, the two ends of the second repetitive fabric layer 16a extend in the same direction. Thus, the length of the second repetitive fabric layer 16a is greater than the length of the first repetitive fabric layer 14a.

[0050] Figure 8 A top view illustrating a semiconductor device 1b according to some embodiments of the present invention. Except for the location of the measuring opening 128 and the measuring circuit 19, the semiconductor device 1b is similar to... Figure 1 The semiconductor device 1 shown in the figure. The measurement opening 128 is located at a position corresponding to the interior of the second semiconductor die 3. That is, the measurement opening 128, viewed in cross-section, is located directly above the second semiconductor die 3. Therefore, the measurement opening 128 can expose a portion of the second passivation layer 33 or a portion of the first dielectric layer 12 on the top surface 301 of the second body 30 of the second semiconductor die 3. The measurement circuit 19 is located on the first dielectric layer 12 and within the measurement opening 128. In one embodiment, the measurement opening 128 can be located at a position corresponding to the interior of the first semiconductor die 2. That is, the measurement opening 128, viewed in cross-section, can be located directly above the first semiconductor die 2. Therefore, the measurement opening 128 can expose a portion of the first passivation layer 23 or a portion of the first dielectric layer 12 on the top surface 201 of the first body 20 of the first semiconductor die 2.

[0051] Figure 9 A top view illustrating a semiconductor device 1c according to some embodiments of the present invention. Figure 10 Explanation along Figure 9 The image shows a cross-sectional view of the semiconductor device 1c taken along line 10-10. Except for the additional second dielectric layer 15 and upper patterned circuit layer 13c, the semiconductor device 1c is similar to... Figures 1 to 5The semiconductor device 1 shown in the figure. The material of the second dielectric layer 15 may be the same as or different from the material of the first dielectric layer 12. The second dielectric layer 15 is formed on or located in the first dielectric layer 12 and in the openings of the first dielectric layer 12 (including, for example, the first opening 122, the second opening 124, the third opening 126, and the measurement opening 128). Thus, the second dielectric layer 15 covers and contacts the top surface of the first dielectric layer 12, the patterned circuit layer 13, a portion of the first passivation layer 23, and a portion of the second passivation layer 33. In addition, the second dielectric layer 15 defines a plurality of openings (including, for example, the first opening 152, the second opening 154, and the measurement opening 158) to expose a portion of the first dielectric layer 12 and a portion of the patterned circuit layer 13.

[0052] An upper patterned circuit layer 13c is located on the second dielectric layer 15. The upper patterned circuit layer 13c may be made of copper. The upper patterned circuit layer 13c includes multiple overlay layers (including, for example, a first overlay layer 14c and a second overlay layer 16c) and measurement circuitry 19c. In one embodiment, the overlay layers (including, for example, a first overlay layer 14c and a second overlay layer 16c) and measurement circuitry 19c may be formed on the same layer and simultaneously. A portion of the first overlay layer 14c is located on the second dielectric layer 15. One end of the first overlay layer 14c extends into a first opening 152 to cover and contact a portion of the patterned circuit layer 13 in the first opening 152. The first overlay layer 14c may include trace portions and pad portions. Similarly, a portion of the second overlay layer 16c is located on the second dielectric layer 15. One end of the second overlay layer 16c extends into the first opening 152 to cover and contact a portion of the patterned circuit layer 13 in the first opening 152. The second layer 16c may include trace portions and pad portions. Additionally, the measurement circuit 19c is similar to the measurement circuit 19 and is located on the second dielectric layer 15, extending into the measurement opening 158.

[0053] Figure 11 A cross-sectional view of a semiconductor device 1d according to some embodiments of the present invention is shown. Except for additionally including a protective layer 17, a plurality of under-bump metal (UBM) 191, and a plurality of connection bumps 19, the semiconductor device 1d is similar to... Figure 10The semiconductor device 1c shown in the figure. The material of the protective layer 17 may be the same as or different from the material of the second dielectric layer 15. The protective layer 17 is formed on or located in the second dielectric layer 15 and in the openings of the second dielectric layer 15 (including, for example, the first opening 152, the second opening 154, and the measurement opening 158). Thus, the protective layer 17 covers and contacts the top surface of the second dielectric layer 15 and the upper patterned circuit layer 13c. In addition, the protective layer 17 defines a plurality of openings 171 to expose portions of the upper patterned circuit layer 13c. UBM 191 is located on the protective layer 17 and in corresponding locations of the openings 171 of the protective layer 17 to contact the exposed portions of the upper patterned circuit layer 13c. Connection bumps 19 (e.g., solder balls or solder bumps) are located on corresponding locations of the UBM 191.

[0054] Figure 12 A cross-sectional view of a semiconductor package structure 4 according to some embodiments of the present invention is shown. The semiconductor package structure 4 includes a semiconductor device 1d, a substrate 42, an underfill 44, and a plurality of external connection devices 46. The semiconductor device 1d can be connected to... Figure 11 The semiconductor device 1d shown is identical to that of the semiconductor device 1d and may include a plurality of connection bumps 19. The semiconductor device 1d is bonded to and electrically connected to the top surface of the substrate 42 via the connection bumps 19. An underfill 44 is located between the semiconductor device 1d and the top surface of the substrate 42 to cover and protect the connection bumps 19. External connection devices 46 (e.g., solder balls or solder bumps) are located on the bottom surface of the substrate 42 for external connection. In one embodiment, the semiconductor package structure 4 may be electrically connected and bonded to a motherboard, such as a printed circuit board (PCB), via the external connection devices 46.

[0055] Figures 13 to 22 This invention describes a method for manufacturing a semiconductor device according to some embodiments of the present invention. In some embodiments, the method is used for manufacturing... Figures 1 to 6 Semiconductor device 1 shown in the figure and Figure 11 The semiconductor device 1d shown in the figure.

[0056] See Figure 13 A carrier 52 is provided. The carrier 52 can be a panel type or a wafer type. The carrier 52 has a first surface 521 and a second surface 522 opposite to the first surface 521. In addition, an adhesion layer 54 is disposed adjacent to the second surface 522 of the carrier 52.

[0057] See Figure 14A first semiconductor die 2 and a second semiconductor die 3 are disposed adjacent to the bonding layer 54. The first semiconductor die 2 is disposed side-by-side adjacent to the second semiconductor die 3. The first semiconductor die 2 includes a first body 20, a plurality of bonding pads (including, for example, first bonding pad 22 and second bonding pad 24), and a first passivation layer 23. The first body 20 has a top surface 201 and a bottom surface 202 opposite to the top surface 201. The top surface 201 of the first body 20 may be an active surface, and the bottom surface 202 of the first body 20 may be a back surface. The bonding pads (including, for example, first bonding pad 22 and second bonding pad 24) are adjacent to the top surface 201 of the first body 20. The first passivation layer 23 is formed or disposed adjacent to the top surface 201 of the first body 20 to cover portions of the bonding pads (including, for example, first bonding pad 22 and second bonding pad 24). The first passivation layer 23 defines a plurality of openings 231 to expose corresponding ones of the bonding pads (including, for example, first bonding pad 22 and second bonding pad 24). The second semiconductor die 3 includes a second body 30, a plurality of bonding pads (including, for example, third bonding pad 32 and fourth bonding pad 34), and the second passivation layer 33. The second body 30 has a top surface 301 and a bottom surface 302 opposite to the top surface 301. The top surface 301 of the second body 30 may be an active surface, and the bottom surface 302 of the second body 30 may be a back surface. The bonding pads (including, for example, third bonding pad 32 and fourth bonding pad 34) are adjacent to the top surface 301 of the second body 30. The second passivation layer 33 is formed or disposed adjacent to the top surface 301 of the second body 30 to cover portions of the bonding pads (including, for example, third bonding pad 32 and fourth bonding pad 34). The second passivation layer 33 defines a plurality of openings 331 to expose corresponding ones in the bonding pads (including, for example, the third bonding pad 32 and the fourth bonding pad 34).

[0058] The top surfaces of the first semiconductor die 2 and the second semiconductor die 3 are generally upward-facing the bonding layer 54. The first semiconductor die 2 and the second semiconductor die 3 are recessed into the bonding layer 54. Therefore, a portion of the first semiconductor die 2 and a portion of the second semiconductor die 3 can be embedded in the bonding layer 54. In the illustrated embodiment, the top surfaces of the first semiconductor die 2 and the second semiconductor die 3 may be higher than the bottom surface of the bonding layer 54.

[0059] See Figure 15 An encapsulation 18 is applied to cover the bottom surfaces of the first semiconductor die 2, the second semiconductor die 3, and the bonding layer 54. Therefore, the encapsulation 18 surrounds at least a portion of the first semiconductor die 2 and at least a portion of the second semiconductor die 3 and fills at least a portion of the space between the first semiconductor die 2 and the second semiconductor die 3.

[0060] See Figure 16 The carrier 52 is removed by thermal processing or other suitable processes.

[0061] See Figure 17 The adhesive layer 54 is removed by thermal processing or other suitable processes.

[0062] See Figure 18 and Figure 19 ,in Figure 19 illustrate Figure 18 In a top view, a first dielectric layer 12 is formed or located on the first passivation layer 23 of the first semiconductor die 2, the second passivation layer 33 of the second semiconductor die 3, and the package 18, so as to cover and contact the first passivation layer 23 of the first semiconductor die 2, the second passivation layer 33 of the second semiconductor die 3, and the package 18. Next, a plurality of openings (including, for example, a first opening 122, a second opening 124, a third opening 126, and a measurement opening 128) are formed in the first dielectric layer 12 through an exposure and development process. The first opening 122 exposes a plurality of bonding pads of the first semiconductor die 2 (including, for example, first bonding pad 22 and second bonding pad 24), a plurality of openings 231 of the first passivation layer 23, and a portion of the first passivation layer 23. The second opening 124 exposes a plurality of bonding pads of the second semiconductor die 3 (including, for example, third bonding pad 32 and fourth bonding pad 34), a plurality of openings 331 of the second passivation layer 33, and a portion of the second passivation layer 33. The third opening 126 is adjacent to the first opening 122 and the second opening 124. The third opening 126 exposes a plurality of bonding pads of the second semiconductor die 3 (including, for example, third bonding pad 32a and fourth bonding pad 34a), a plurality of openings 331 of the second passivation layer 33, and a portion of the second passivation layer 33. Figure 19 As shown, the first opening 122, the second opening 124, and the third opening 126 are located in the bonding pad area. Conversely, the measurement opening 128 is located in the non-bonding pad area. The first opening 122, the second opening 124, the third opening 126, and the measurement opening 128 can be formed simultaneously. In one embodiment, the first dielectric layer 12 has a plurality of dicing lines 56 to define a plurality of cells 58. The measurement opening 128 can be located within the cell 58; therefore, the position of the measurement opening 128 corresponds to the first semiconductor die 2 or the second semiconductor die 3. Thus, the measurement opening 128 can remain in the final product (i.e., semiconductor device 1) after the single-cut process. Figure 1 In another embodiment, however, the measurement opening 128 may be located outside the cell 58; therefore, the measurement opening 128 is located away from the first semiconductor die 2 or the second semiconductor die 3. Thus, the measurement opening 128 may not remain in the final product (i.e., the semiconductor device 1). Figure 1 ))middle.

[0063] See Figure 20The metal layer 60 is formed or disposed on the first dielectric layer 12 and in the openings of the first dielectric layer 12 (including, for example, the first opening 122, the second opening 124, the third opening 126 and the measuring opening 128) by sputtering or other suitable processes to cover and contact the bonding pads (including, for example, the first bonding pad 22, the second bonding pad 24, the third bonding pad, the fourth bonding pad 34, the third bonding pad 32a and the fourth bonding pad 34a).

[0064] See Figure 21 and Figure 22 ,in Figure 22 for Figure 21 A top view shows that a portion of the metal layer 60 is removed by selective etching or other suitable processes to form a patterned circuit layer 13 on the first dielectric layer 12. The patterned circuit layer 13 includes multiple redistribution layers (including, for example, a first redistribution layer 14 and a second redistribution layer 16) and measurement circuitry 19. In one embodiment, the redistribution layers (including, for example, a first redistribution layer 14 and a second redistribution layer 16) and measurement circuitry 19 may be formed on the same layer and simultaneously. The first redistribution layer 14 extends into a first opening 122 to electrically connect a first bonding pad 22 and extends into a second opening 124 to electrically connect a third bonding pad 32. The second redistribution layer 16 extends into the first opening 122 to electrically connect a second bonding pad 24 and extends into the second opening 124 to electrically connect a fourth bonding pad 34. Measurement circuitry 19 is located on the first dielectric layer 12 and extends into a measurement opening 128. A perspective view of a portion of the first redistribution layer 14 and the second redistribution layer 16 is shown below. Figure 4 The three-dimensional diagram of the measurement circuit 19 shown is as follows: Figure 6 As shown.

[0065] Next, regarding the measurement circuit 19 ( Figure 6Current leakage measurement is performed as follows. Since the first opening 122, the second opening 124, the third opening 126, and the measurement opening 128 are formed simultaneously, the surface conditions of the sidewalls 1221 of the first opening 122, the sidewalls of the second opening 124, and the sidewalls of the third opening 126 can be substantially the same as the surface condition of the measurement opening 128. Furthermore, since the measurement circuit 19 and the redistribution layers (including, for example, the first redistribution layer 14 and the second redistribution layer 16) are formed simultaneously, the measurement circuit 19 can simulate the state of the redistribution layers (including, for example, the first redistribution layer 14 and the second redistribution layer 16) after the etching process. The first probe, second probe, third probe, and fourth probe of the test equipment are implemented or provided to contact the first test pad 195, the second test pad 196, the third test pad 197, and the fourth test pad 198, respectively. If the current between the first and second probes is greater than or equal to a predetermined value (e.g., 900 picoamperes (PA)), this means a short circuit occurs between the first comb circuit 19a and the second comb circuit 19b. Therefore, it can be presumed that the short circuit occurs between the re-layers (including, for example, the first re-layer 14 and the second re-layer 16), and the quality of the etching process for the re-layers (including, for example, the first re-layer 14 and the second re-layer 16) is determined to be unacceptable or abnormal. A compensation process is then implemented using another etching process or other suitable process.

[0066] If the current between the first and second probes is less than a predetermined value (e.g., 900 picoamperes (PA)), this means that an open circuit occurs between the first comb circuit 19a and the second comb circuit 19b. Therefore, it can be presumed that an open circuit occurs between the relay layers (including, for example, the first relay layer 14 and the second relay layer 16), and the quality of the etching process for the relay layers (including, for example, the first relay layer 14 and the second relay layer 16) is determined to be acceptable or normal. Similarly, the current between the first and fourth probes, the current between the second and third probes, and the current between the second and fourth probes can be used to presumably determine the quality of the etching process for the relay layers (including, for example, the first relay layer 14 and the second relay layer 16) by the method described above. Therefore, the quality of the relay layers (including, for example, the first relay layer 14 and the second relay layer 16) of the patterned circuit layer 13 after the etching process can be ensured or improved.

[0067] Next, a single-cut process is performed along cutting line 56 to obtain Figures 1 to 6 Semiconductor device 1.

[0068] In one embodiment, prior to the single-cutting process, an additional first dielectric layer 12 (such as...) can be applied. Figure 11A second dielectric layer 15, an upper patterned circuit layer 13c, a protective layer 17, a plurality of under-bump metal (UBM) 191, and a plurality of connection bumps 19 are formed or disposed on the first dielectric layer 12. The second dielectric layer 15 is formed or disposed on the first dielectric layer 12 and in openings of the first dielectric layer 12 (including, for example, a first opening 122, a second opening 124, a third opening 126, and a measurement opening 128). Then, a plurality of openings (including, for example, a first opening 152, a second opening 154, and a measurement opening 158) are formed in the second dielectric layer 15 to expose a portion of the first dielectric layer 12 and a portion of the patterned circuit layer 13. The upper patterned circuit layer 13c is located on the second dielectric layer 15. The upper patterned circuit layer 13c includes a plurality of redistribution layers (including, for example, a first redistribution layer 14c and a second redistribution layer 16c) and measurement circuitry 19c. Next, current leakage is measured for the measurement circuit 19c to ensure or improve the etching quality of the overlay layers (including, for example, the first overlay layer 14c and the second overlay layer 16c) of the upper patterned circuit layer 13c.

[0069] Next, a protective layer 17 is formed or disposed on the second dielectric layer 15 and in openings of the second dielectric layer 15 (including, for example, the first opening 152, the second opening 154, and the measurement opening 158). Next, a plurality of openings 171 are formed in the protective layer 17 to expose portions of the upper patterned circuit layer 13c. Next, UBMs 191 are formed or disposed on the protective layer 17 and in corresponding openings 171 of the protective layer 17 to contact the exposed portions of the upper patterned circuit layer 13c. Next, connection bumps 19 (e.g., solder balls or solder bumps) are disposed on corresponding UBMs 191. Next, a single-cut process is performed along the dicing line 56 to obtain... Figure 11 Semiconductor device 1d.

[0070] Unless otherwise specified, spatial descriptions such as "above," "below," "upward," "left," "right," "downward," "top," "bottom," "vertical," "horizontal," "side," "higher," "lower," "upper," "above," and "below" are used to indicate orientations relative to those shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein can be arranged in space in any orientation or manner, provided that the advantages of the embodiments of the invention are not deviated from by such arrangement.

[0071] As used herein, the terms “approximately,” “generally,” “roughly,” and “about” are used to describe and account for small variations. When used in conjunction with an event or situation, the term may refer to examples in which the event or situation clearly occurred and examples in which the event or situation is very close to occurring. For example, when used in conjunction with numerical values, the term may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two numerical values ​​is less than or equal to ±10% of the average of the values, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the two numerical values ​​can be considered “approximately” the same.

[0072] If the displacement between two surfaces is no greater than 5 micrometers, no greater than 2 micrometers, no greater than 1 micrometer, or no greater than 0.5 micrometers, then the two surfaces can be considered coplanar or approximately coplanar.

[0073] Unless the context clearly specifies otherwise, as used herein, the singular terms “a” and “the” may include multiple indicators.

[0074] As used herein, the terms “conductive,” “electrically conductive,” and “conductivity” refer to the ability to conduct electric current. Conductive materials typically indicate those that exhibit minimal or zero resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Generally, conductive materials have a conductivity greater than approximately 10. 4 S / m (e.g., at least 10) 5 S / m or at least 10 6 A material is defined as having an electrical conductivity of S / m. The electrical conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of a material is measured at room temperature.

[0075] Additionally, quantities, ratios, and other values ​​are sometimes presented in range format in this document. It should be understood that such range format is for convenience and brevity, and should be flexibly interpreted to include not only values ​​explicitly specified as range limits, but also all individual values ​​or subranges covered within the range, as if each value and subrange were explicitly specified.

[0076] While the invention has been described and illustrated with respect to specific embodiments thereof, such descriptions and illustrations are not restrictive. Those skilled in the art will understand that various changes and substitutions may be made without departing from the true spirit and scope of the invention as defined by the appended claims. Illustrations may not be drawn to scale. Due to manufacturing processes and limitations, there may be differences between process reproductions in the invention and actual equipment. Other embodiments of the invention may exist that are not specifically described. This specification and the accompanying drawings should be considered illustrative rather than restrictive. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of the invention. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with respect to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the invention. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of the invention.

Claims

1. A semiconductor device comprising: The first semiconductor die includes a first bonding pad, a second bonding pad, and a first passivation layer. The second semiconductor die includes a third bonding pad and a fourth bonding pad; A first dielectric layer covers the first semiconductor die and the second semiconductor die, and defines a first opening exposing the first bonding pad and the second bonding pad and a second opening exposing the third bonding pad and the fourth bonding pad, wherein the first bonding pad and the second bonding pad are exposed in the same first opening and the third bonding pad and the fourth bonding pad are exposed in the same second opening; A first layer of fabric, located on the first dielectric layer, electrically connects the first bonding pad and the third bonding pad; and A second layer, located on the first dielectric layer, electrically connects the second bonding pad and the fourth bonding pad. The first and second folded fabric layers are formed on the same layer and simultaneously. The first and second folded fabric layers are substantially parallel. The two ends of the first folded fabric layer extend in different directions from each other. The two ends of the second folded fabric layer extend in different directions from each other. The length of the second folded fabric layer is approximately equal to the length of the first folded fabric layer.

2. The semiconductor device of claim 1, wherein the first redistribution layer contacts the first dielectric layer, and the second redistribution layer contacts the first dielectric layer.

3. The semiconductor device of claim 2, wherein the first redistribution layer comprises a first portion and a second portion, the first portion of the first redistribution layer being located on the first dielectric layer, and the second portion of the first redistribution layer being located in the first opening and contacting the first bonding pad and the first passivation layer, the second redistribution layer comprising a first portion and a second portion, the first portion of the second redistribution layer being located on the first dielectric layer, and the second portion of the second redistribution layer being located in the first opening and contacting the second bonding pad and the first passivation layer, wherein the first dielectric layer does not extend between the second portion of the first redistribution layer and the second portion of the second redistribution layer.

4. The semiconductor device of claim 3, wherein, in a top view, the first opening and the second opening do not overlap along the long side and short side of the first opening, and the first opening and the second opening are respectively located on both sides of the first portion of the first overlapping layer.

5. The semiconductor device of claim 4, wherein the first redistribution layer further comprises a third portion connecting the first portion and the second portion, the third portion being perpendicular to the first portion, the maximum width of the third portion being equal to the maximum width of the second portion and greater than the maximum width of the first portion, and the maximum width of the second portion being greater than the maximum width of the first bonding pad.

6. The semiconductor device of claim 4, further comprising: A second dielectric layer is located on the first dielectric layer and in the first and second openings of the first dielectric layer. The second dielectric layer covers the first and second redistributed layers. The second dielectric layer defines a plurality of openings to expose a portion of the first dielectric layer, a portion of the first redistributed layer, and a portion of the second redistributed layer. The plurality of openings of the second dielectric layer do not perpendicularly overlap the first and second openings of the first dielectric layer. An upper patterned circuit layer is located on the second dielectric layer. The upper patterned circuit layer includes multiple redistribution layers. The upper patterned circuit layer contacts the exposed portions of the first redistribution layer and the exposed portions of the second redistribution layer. and A protective layer is located on the second dielectric layer and in a plurality of openings in the second dielectric layer, the protective layer defining the plurality of openings to expose portions of the upper patterned circuit layer.

7. A semiconductor device comprising: A semiconductor die having a surface and comprising: A first bonding pad is located adjacent to the surface of the semiconductor die; A second bonding pad is located adjacent to the surface of the semiconductor die; A first passivation layer is adjacent to the surface of the semiconductor die and surrounds and exposes the first bonding pad and the second bonding pad; A first dielectric layer covers the semiconductor die and defines a first opening and a first measurement opening. The first opening exposes the first bonding pad and the second bonding pad. The first measurement opening is located in a non-bonding pad area. The first bonding pad and the second bonding pad are exposed in the same first opening. The depth of the first measurement opening is approximately equal to the depth of the first opening. The surface condition of the sidewall of the first measurement opening is approximately the same as the surface condition of the sidewall of the first opening. The first opening and the first measurement opening are formed simultaneously. and A first fabric layer is located on the dielectric layer and extends into the first opening to electrically connect the first bonding pad. A second fabric layer is located on the dielectric layer and extends into the first opening to electrically connect the second bonding pad. and A first measurement circuit is located on the dielectric layer and extends into the measurement opening. The first redistribution layer, the second redistribution layer, and the first measurement circuit are formed on the same layer and simultaneously. The first measurement circuit includes at least two conductive segments, and the gap between the conductive segments is approximately equal to or smaller than the gap between the first redistribution layer and the second redistribution layer on the dielectric layer. A portion of the first redistribution layer contacts the sidewall of the first opening, a portion of the second redistribution layer contacts the sidewall of the first opening, and a portion of the first measurement circuit contacts the sidewall of the first measurement opening.

8. The semiconductor device of claim 7, wherein the measurement opening has a first sidewall and a second sidewall opposite to the first sidewall, and the first measurement circuit has a first portion and a second portion respectively contacting the first sidewall and the second sidewall of the first measurement opening.

9. The semiconductor device of claim 8, wherein the first redistribution layer and the second redistribution layer are substantially parallel, the two ends of the first redistribution layer extend in different directions from each other, the two ends of the second redistribution layer extend in different directions from each other, and the length of the second redistribution layer is substantially equal to the length of the first redistribution layer.

10. The semiconductor device of claim 9, wherein the position of the measuring opening corresponds to the semiconductor die.

11. The semiconductor device of claim 10, wherein the first redistribution layer includes a first portion located on the dielectric layer, and the linewidth of the conductive segment of the first measurement circuit is substantially equal to the linewidth of the first portion of the first redistribution layer.

12. The semiconductor device of claim 11, further comprising: A second dielectric layer is located on the first dielectric layer and in the first opening and the first measurement opening of the first dielectric layer. The second dielectric layer covers the first redistribution layer and the second redistribution layer. The second dielectric layer defines a plurality of openings to expose a portion of the first dielectric layer, a portion of the first redistribution layer, and a portion of the second redistribution layer.

13. The semiconductor device of claim 12, further comprising: An upper patterned circuit layer is located on the second dielectric layer. The upper patterned circuit layer includes multiple redistribution layers and a second measurement circuit. The upper patterned circuit layer contacts the exposed portions of the first redistribution layer and the exposed portions of the second redistribution layer. The second dielectric layer further defines a second measurement opening. The second measurement circuit is located on the second dielectric layer and extends to the second measurement opening.

14. The semiconductor device of claim 13, further comprising: A protective layer is located on the second dielectric layer and in a plurality of openings in the second dielectric layer, the protective layer defining the plurality of openings to expose portions of the upper patterned circuit layer.

15. The semiconductor device of claim 10, wherein the first redistribution layer comprises a first portion and a second portion, the first portion of the first redistribution layer being located on the first dielectric layer, and the second portion of the first redistribution layer being located in the first opening and contacting the first bonding pad and the first passivation layer, the second redistribution layer comprising a first portion and a second portion, the first portion of the second redistribution layer being located on the first dielectric layer, and the second portion of the second redistribution layer being located in the first opening and contacting the second bonding pad and the first passivation layer, wherein the first dielectric layer does not extend between the second portion of the first redistribution layer and the second portion of the second redistribution layer.

16. A method for manufacturing a semiconductor device, comprising: (a) A first semiconductor die is provided, which includes a first bonding pad and a second bonding pad; (b) A second semiconductor die is disposed adjacent to the first semiconductor die, wherein the second semiconductor die includes a third bonding pad and a fourth bonding pad; (c) Forming a dielectric layer to cover the first semiconductor die and the second semiconductor die; (d) A first opening, a second opening, and a first measurement opening are formed in the dielectric layer, wherein the first opening, the second opening, and the first measurement opening are formed simultaneously, the first opening exposes the first bonding pad and the second bonding pad, the second opening exposes the third bonding pad and the fourth bonding pad, and the first measurement opening is in a non-bonding pad area, the first bonding pad and the second bonding pad are exposed in the same first opening, and the third bonding pad and the fourth bonding pad are exposed in the same second opening; and (e) A first redistribution layer, a second redistribution layer, and a first measurement circuit are formed on the dielectric layer, wherein the first redistribution layer extends into the first opening to electrically connect the first bonding pad and into the second opening to electrically connect the third bonding pad; the second redistribution layer extends into the second opening to electrically connect the second bonding pad and into the second opening to electrically connect the fourth bonding pad; the first measurement circuit extends into the first measurement opening, wherein the first redistribution layer, the second redistribution layer, and the first measurement circuit are formed simultaneously; a portion of the first redistribution layer contacts the sidewall of the first opening; a portion of the second redistribution layer contacts the sidewall of the first opening; and a portion of the first measurement circuit contacts the sidewall of the first measurement opening; the depth of the first measurement opening is substantially equal to the depth of the first opening; and the surface condition of the sidewall of the first measurement opening is substantially the same as the surface condition of the sidewall of the first opening. (f) Perform current leakage measurement on the first measurement circuit.

17. The method of claim 16, wherein in (d), the position of the first measuring opening corresponds to the first semiconductor die.

18. The method of claim 16, wherein in (e), the first fold and the second fold are substantially parallel, the two ends of the first fold extend in different directions from each other, the two ends of the second fold extend in different directions from each other, and the length of the second fold is substantially equal to the length of the first fold.

19. The method of claim 18, wherein in (d), the first measuring opening has a first sidewall and a second sidewall opposite to the first sidewall, and the first measuring circuit has a first portion and a second portion respectively contacting the first sidewall and the second sidewall of the first measuring opening.

20. The method of claim 19, wherein in (e), the first measurement circuit comprises at least two conductive segments, and the gap between the conductive segments of the first measurement circuit is substantially equal to or less than the gap between the first redistribution layer and the second redistribution layer on the dielectric layer.

21. The method of claim 20, wherein in (e), the first redistribution layer includes a first portion located on the dielectric layer, and the linewidth of the conductive segment of the first measurement circuit is substantially equal to the linewidth of the first portion of the first redistribution layer.

22. The method of claim 21, wherein the dielectric layer is a first dielectric layer, and wherein after (f), the method further comprises: (g) A second dielectric layer is formed on the first dielectric layer and in the first opening and the second opening of the first dielectric layer, the second dielectric layer covering the first redistribution layer and the second redistribution layer, the second dielectric layer defining a plurality of openings to expose a portion of the first dielectric layer, a portion of the first redistribution layer and a portion of the second redistribution layer, the plurality of openings of the second dielectric layer not perpendicularly overlapping the first opening and the second opening of the first dielectric layer. (h) An upper patterned circuit layer is formed on the second dielectric layer, the upper patterned circuit layer including a plurality of redistribution layers and a second measurement circuit, the upper patterned circuit layer contacting the exposed portion of the first redistribution layer and the exposed portion of the second redistribution layer, the second dielectric layer further defining a second measurement opening, the second measurement opening not perpendicularly overlapping the first measurement opening, the second measurement circuit being located on the second dielectric layer and extending to the second measurement opening; and (i) A protective layer is formed on the second dielectric layer and in a plurality of openings in the second dielectric layer, the protective layer defining the plurality of openings to expose portions of the upper patterned circuit layer.

23. The method of claim 22, wherein after (h) and before (i), the method further comprises: (h1) Perform current leakage measurement on the second measurement circuit.

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