Display Devices

Abstract

The present disclosure relates to a display device, the display device comprising: a base substrate, the base substrate comprising a display area in which pixels are formed and a peripheral area as a non-display area surrounding the display area; a first conductive pattern layer disposed on the base substrate; a first insulating layer disposed on the first conductive pattern layer; a second conductive pattern layer disposed on the first insulating layer; a second insulating layer disposed on the second conductive pattern layer; and a third conductive pattern layer disposed on the second insulating layer. The peripheral area comprises a first wiring area and a circuit area.

Description

Technical Field

[0001] Exemplary embodiments of the inventive concept relate to a display device, and more particularly, to a display device having improved display quality. Background Art

[0002] Recently, light and small display devices have been manufactured. Cathode ray tube (CRT) display devices have been used in the past due to performance and competitive price. However, CRT display devices are large and lack portability. Therefore, display devices such as plasma display devices, liquid crystal display devices or organic light emitting display devices are favored due to their small size, light weight and low power consumption.

[0003] A display device includes a display area and a peripheral area as a non-display area surrounding the display area. Various circuits and wirings driving the display device are arranged in the peripheral area. Various efforts have been made to reduce the size of the peripheral area. Summary of the invention

[0004] One or more exemplary embodiments of the inventive concept provide a display device having a reduced peripheral area and improved display quality by reducing resistance and parasitic capacitance of a signal line.

[0005] According to an exemplary embodiment of the inventive concept, a display device includes: a base substrate, the base substrate including a display area in which pixels are formed and a peripheral area as a non-display area surrounding the display area, wherein the peripheral area includes a first wiring area and a circuit area; a first conductive pattern layer disposed on the base substrate; a first insulating layer disposed on the first conductive pattern layer; a second conductive pattern layer disposed on the first insulating layer; a second insulating layer disposed on the second conductive pattern layer; and a third conductive pattern layer disposed on the second insulating layer. A plurality of signal lines are disposed in the first wiring area, and are spaced apart in a first direction, and extend in a second direction substantially perpendicular to the first direction. A gate signal generator is disposed in the circuit area, and generates a gate signal, and transmits the gate signal to the pixel. A plurality of connection lines are disposed in the peripheral area, and extend in the first direction, and connect the signal lines to the gate signal generators, respectively. The connection lines are formed by the lowest layer or the uppermost layer of the conductive pattern layer. The signal lines are formed by at least two conductive pattern layers overlapping each other.

[0006] In an exemplary embodiment, a display device may further include a thin film transistor disposed in the display area. The thin film transistor may include: a lower conductive pattern disposed on the base substrate; an active pattern overlapping the lower conductive pattern; a gate electrode disposed on the active pattern; and a source electrode and a drain electrode electrically connected to the active pattern. The lower conductive pattern and the connecting line may be formed by the first conductive pattern layer. The gate electrode may be formed by the second conductive pattern layer. The source electrode and the drain electrode may be formed by the third conductive pattern layer. Each of the signal lines may be formed by the second conductive pattern layer and the third conductive pattern layer.

[0007] In an exemplary embodiment, the display device may further include: a lower conductive pattern disposed in the display area of ​​the base substrate; and a thin film transistor disposed in the display area and overlapping the lower conductive pattern. The thin film transistor may include: an active pattern overlapping the lower conductive pattern; a gate electrode disposed on the active pattern; and a source electrode and a drain electrode electrically connected to the active pattern. The lower conductive pattern may be formed by the first conductive pattern layer. The gate electrode may be formed by the second conductive pattern layer. The source electrode and the drain electrode and the connecting line may be formed by the third conductive pattern layer. Each of the signal lines may be formed by the first conductive pattern layer and the second conductive pattern layer.

[0008] In an exemplary embodiment, the display device may further include: a third insulating layer disposed on the third conductive pattern layer, and a fourth conductive pattern layer disposed on the third conductive pattern layer.

[0009] In an exemplary embodiment, the signal line may be formed by the first conductive pattern layer, the second conductive pattern layer, and the third conductive pattern layer. The connection line may be formed by the fourth conductive pattern layer.

[0010] In an exemplary embodiment, the signal line may be formed by the second conductive pattern layer, the third conductive pattern layer, and the fourth conductive pattern layer. The connection line may be formed by the first conductive pattern layer.

[0011] In an exemplary embodiment, the display device may further include: an insulating pattern disposed between the first insulating layer and the second conductive pattern layer and having the same planar shape as the second conductive pattern layer. A portion of the third conductive pattern layer may be electrically connected to a portion of the first conductive pattern layer through a contact hole penetrating the second insulating layer and the first insulating layer. A portion of the fourth conductive pattern layer may be electrically connected to a portion of the third conductive pattern layer through a contact hole penetrating the third insulating layer.

[0012] In an exemplary embodiment, the signal line may be formed of the first conductive pattern layer and the second conductive pattern layer. The connection line may include two layers formed of the third conductive pattern layer and the fourth conductive pattern layer and overlapping each other.

[0013] In an exemplary embodiment, the signal line may be formed of the third conductive pattern layer and the fourth conductive pattern layer. The connection line may include two layers formed of the first conductive pattern layer and the second conductive pattern layer and overlapping each other.

[0014] In an exemplary embodiment, the display device may further include: an insulating pattern disposed between the first insulating layer and the second conductive pattern layer and having the same planar shape as the second conductive pattern layer. A portion of the third conductive pattern layer may be electrically connected to a portion of the first conductive pattern layer through a contact hole penetrating the second insulating layer and the first insulating layer.

[0015] In an exemplary embodiment, the peripheral area may further include a second wiring area provided between the circuit area and the display area. The display device may further include: a plurality of power lines provided in the second wiring area and spaced apart in the first direction and extending in the first direction; and a plurality of power connection lines provided in the peripheral area, the plurality of power connection lines connecting the power lines to the gate signal generator and extending in the first direction. The power connection lines may be formed by the lowermost layer or the uppermost layer of the conductive pattern layer. The power lines may be formed by two or more layers of the conductive pattern layer.

[0016] In an exemplary embodiment, the display device may further include: a third insulating layer disposed on the third conductive pattern layer and a fourth conductive pattern layer disposed on the third insulating layer. The power connection line may be formed by the first conductive pattern layer or the fourth conductive pattern layer, and each of the power lines may be formed by the second conductive pattern layer to the fourth conductive pattern layer or the first conductive pattern layer to the third conductive pattern layer.

[0017] In an exemplary embodiment, the display device may further include: a through insulating layer disposed on the second insulating layer; a first electrode disposed on the through insulating layer in the display area; a light emitting layer disposed on the first electrode; a second electrode disposed on the light emitting layer; and an ELVSS line in the second wiring area, the ELVSS line overlapping at least two of the power lines. The ELVSS line may be electrically connected to the second electrode.

[0018] In an exemplary embodiment, the display device may further include a shielding wiring disposed on the base substrate adjacent to the signal line. The shielding wiring may be formed by one or more conductive pattern layers from the first conductive pattern layer to the third conductive pattern layer, and the signal line is disposed between the shielding wiring and the gate signal generator.

[0019] In an exemplary embodiment, the display device may further include: a gate connection line connecting the gate signal generator and the pixel. The gate connection line may be formed by a lowermost layer or an uppermost layer of the conductive pattern layer.

[0020] In an exemplary embodiment, the signal line may include a first portion and a second portion overlapping the first portion. The first portion and the second portion may be connected through a contact hole penetrating an insulating layer between the first portion and the second portion.

[0021] According to an exemplary embodiment of the inventive concept, a display device includes: a base substrate including a display area in which pixels are formed and a peripheral area as a non-display area surrounding the display area, wherein the peripheral area includes a first wiring area and a circuit area; an active pattern disposed on the base substrate; a gate insulating layer disposed on the active pattern; a gate conductive pattern layer disposed on the gate insulating layer; an interlayer insulating layer disposed on the gate conductive pattern layer; a data conductive pattern layer disposed on the interlayer insulating layer; a plurality of signal lines disposed in the first wiring area, the plurality of signal lines being spaced apart in a first direction and extending in a second direction substantially perpendicular to the first direction; a gate signal generator disposed in the circuit area and transmitting a gate signal to the pixel; and a plurality of connection lines disposed in the peripheral area and connecting the signal lines to the gate signal generator and extending in the first direction. The connection lines are formed by the active pattern. The signal lines are formed by the gate conductive pattern layer and the data conductive pattern layer overlapping each other.

[0022] In an exemplary embodiment, the connection line does not overlap the gate conductive pattern layer.

[0023] In exemplary embodiments, the connection line may be a portion of the active pattern doped with impurities.

[0024] According to an exemplary embodiment of the present invention, a display device includes: a base substrate including a display area in which pixels are formed and a peripheral area as a non-display area surrounding the display area, wherein the peripheral area includes a first wiring area and a circuit area; a first conductive pattern layer disposed on the base substrate; a first insulating layer disposed on the first conductive pattern layer; a second conductive pattern layer disposed on the first insulating layer; a second insulating layer disposed on the second conductive pattern layer; a third conductive pattern layer disposed on the second insulating layer; a third insulating layer disposed on the third conductive pattern layer; a fourth conductive pattern layer disposed on the third insulating layer; a plurality of signal lines, the plurality of signal lines are disposed in the first wiring area, spaced apart in a first direction, and extend in a second direction substantially perpendicular to the first direction; and a plurality of connecting lines, the plurality of connecting lines are disposed in the peripheral area, extend in the first direction, and are respectively connected to the signal lines. The connecting lines are formed by the lowest layer or the uppermost layer of the conductive pattern layer, and the signal lines are formed by at least two conductive pattern layers other than the conductive pattern layer of the connecting lines.

[0025] According to an exemplary embodiment of the inventive concept, a clock signal line is formed of a plurality of conductive pattern layers, and the connection line connecting the clock signal line and the gate signal generator is formed as the uppermost layer or the lowermost layer of the conductive pattern layer. The resistance of the clock signal line is reduced, and the parasitic capacitance between the clock signal line and the connection line can be minimized. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a plan view of a display device according to an exemplary embodiment of the inventive concept.

[0027] Figure 2 Shows Figure 1 The circuits and wiring in area A of the display device.

[0028] Figure 3 yes Figure 2 Detailed plan view of a portion of the first wiring area LA1.

[0029] Figure 4 It is along Figure 3 A cross-sectional view taken along line II'.

[0030] Figure 5 is a cross-sectional view of a portion of a first wiring region of a display device according to an exemplary embodiment of the inventive concept.

[0031] Figure 6 is a detailed plan view of a portion of a first wiring region of a display device according to an exemplary embodiment of the inventive concept.

[0032] Figure 7 It is along Figure 6 A cross-sectional view taken along line II'.

[0033] Figure 8 is a cross-sectional view of a portion of a first wiring region of a display device according to an exemplary embodiment of the inventive concept.

[0034] Fig. 9 is a cross-sectional view of a portion of a first wiring region of a display device according to an exemplary embodiment of the inventive concept.

[0035] Fig.10 is a cross-sectional view of a portion of a first wiring region of a display device according to an exemplary embodiment of the inventive concept.

[0036] Fig.11 is a cross-sectional view of a portion of a first wiring region of a display device according to an exemplary embodiment of the inventive concept.

[0037] Fig.12 is a cross-sectional view of a portion of a first wiring region of a display device according to an exemplary embodiment of the inventive concept.

[0038] Fig.13 is a cross-sectional view of a portion of a first wiring region of a display device according to an exemplary embodiment of the inventive concept.

[0039] Fig.14 is a cross-sectional view of a portion of a first wiring region of a display device according to an exemplary embodiment of the inventive concept.

[0040] Fig.15 is a cross-sectional view of a portion of a first wiring region of a display device according to an exemplary embodiment of the inventive concept.

[0041] Fig.16 It is along Fig.15 A cross-sectional view taken along line II'.

[0042] Fig.17 is a cross-sectional view of a stacked pixel structure in a display area of ​​a display device according to an exemplary embodiment of the inventive concept.

[0043] Fig.18 is a cross-sectional view of a portion of a second wiring area LA2 of a display device according to an exemplary embodiment of the inventive concept.

[0044] Fig.19 is a plan view of a display device according to an exemplary embodiment of the inventive concept.

[0045] Fig. 20 Shows Fig.19 The circuits and wiring in area A of the display device.

[0046] Fig.21 is a plan view of a display device according to an exemplary embodiment of the inventive concept.

[0047] Fig. 22 is a block diagram of an electronic device according to an exemplary embodiment.

[0048] Fig.23A It shows that Fig. 22 An example in which the electronic device is implemented as a television.

[0049] Fig. 23B It shows that Fig. 22 The electronic device is implemented as an example of a smart phone. DETAILED DESCRIPTION

[0050] Hereinafter, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0051] Figure 1 is a plan view of a display device according to an exemplary embodiment of the inventive concept.

[0052] refer to Figure 1 , the display apparatus according to the embodiment includes a display area DA in which an image is displayed and a peripheral area PA which is a non-display area surrounding the display area DA.

[0053] In the display area DA, according to an embodiment, the display device includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels electrically connected to the gate lines and the data lines, respectively. The gate lines extend in a first direction D1, and the data lines extend in a second direction D2 crossing the first direction D1.

[0054] According to an embodiment, each pixel includes a switching element, a liquid crystal capacitor electrically connected to the switching element, and a storage capacitor. The pixels are arranged in a matrix.

[0055] According to an embodiment, a driving circuit for generating a signal for driving the pixel is provided in the peripheral area PA. For example, a gate driver for generating a gate driving signal such as a clock signal and a gate signal generator for generating a gate signal using the gate driving signal are provided in the peripheral area PA. Figure 2 in ASG).

[0056] Figure 2 Shows Figure 1 The circuits and wiring in area A of the display device.

[0057] refer to Figure 1 and Figure 2According to an embodiment, the peripheral area PA of the display device includes a first wiring area LA1, a circuit area CA, and a second wiring area LA2. The circuit area CA is disposed between the first wiring area LA1 and the second wiring area LA2. The second wiring area LA2 is disposed between the circuit area CA and the display area DA. In the figure, line PN represents an end of a base substrate of the display device.

[0058] According to an embodiment, a plurality of gate driving signal lines such as clock signal lines are disposed in the first wiring area LA1. That is, first, second, third and fourth clock signal lines CLK1, CLK2, CLK3 and CLK4 are disposed in the first wiring area LA1.

[0059] According to an embodiment, the first clock signal line CLK1 , the second clock signal line CLK2 , the third clock signal line CLK3 , and the fourth clock signal line CLK4 extend in the second direction D2 , respectively, and are spaced apart in the first direction D1 .

[0060] According to an embodiment, a plurality of power lines are provided in the second wiring area LA2. The power lines include a first power line VSS1, a second power line VSS2, and a third power line VSS3. The first power to the third power are respectively applied to the first power line VSS1 to the third power line VSS3, and the first power to the third power have different voltage levels. In addition, an ELVSS line is also provided in the second wiring area LA2, and the ELVSS line is electrically connected to a second electrode ( Fig.17 183 in the figure) and is spaced apart from the first power line VSS1 to the third power line VSS3. However, the embodiment is not limited thereto. In other embodiments, Fig.18 As shown, the ELVSS line may be disposed to overlap the first to third power lines VSS1 to VSS3 .

[0061] According to an embodiment, the first to fourth clock signal lines CLK1 to CLK4 are connected to the gate signal generator ASG through the first to fourth connection lines CL1 to CL4, respectively. Each of the first to fourth connection lines CL1 to CL4 extends in the first direction D1, and the first to fourth connection lines CL1 to CL4 are spaced apart along the second direction D2. The first connection line CL1 is electrically connected to the first clock signal line CLK1. The second connection line CL2 is electrically connected to the second clock signal line CLK2. The third connection line CL3 is electrically connected to the third clock signal line CLK3. The fourth connection line CL4 is electrically connected to the fourth clock signal line CLK4.

[0062] According to an embodiment, the first power line VSS1 to the third power line VSS3 are connected to the gate signal generator ASG through the first power connection line CL5 to the third power connection line CL7, respectively. Each of the first power connection line CL5 to the third power connection line CL7 extends in the first direction D1, and the first power connection line CL5 to the third power connection line CL7 are spaced apart in the second direction D2. The first power connection line CL5 is electrically connected to the first power line VSS1. The second power connection line CL6 is electrically connected to the second power line VSS2. The third power connection line CL7 is electrically connected to the third power line VSS3.

[0063] According to an embodiment, a plurality of gate signal generators ASG are disposed in the circuit area CA. The gate signal generator ASG receives clock signals from the first to fourth clock signal lines CLK1 to CLK4 and first to third power supplies from the first to third power supply lines VSS1 to VSS3 and generates gate signals.

[0064] In addition, according to an embodiment, a plurality of pixels PX are arranged in the display area DA, and a gate signal is transmitted to each pixel PX through a gate connection line SL. The gate connection line SL electrically connects the gate line in the display area DA to the gate signal generator ASG. In addition, when the layer of the gate line is different from the layer of the gate connection line SL, they have a structure in which the gate line and the gate connection line SL area are connected to each other through a contact hole penetrating the insulating layer.

[0065] In this embodiment, four clock signal (CLK) lines and three power supply voltage (VSS) lines are shown. However, the embodiments of the inventive concept are not limited thereto. In other embodiments, the number and configuration of the clock signal lines and the power supply voltage lines may vary according to the driving method of the display device.

[0066] Figure 3 It is shown Figure 2 Detailed plan view of a portion of the first wiring area LA1. Figure 4 is along Figure 3 A cross-sectional view taken along line II'.

[0067] refer to Figures 1 to 4 According to an embodiment, the display device includes a base substrate 100 , a first conductive pattern layer, a first insulating layer 110 , a second conductive pattern layer, an insulating pattern 115 , a second insulating layer 120 , a third conductive pattern layer, and a third insulating layer 130 .

[0068] According to an embodiment, the base substrate 100 may include a transparent insulating material or an opaque insulating material. For example, the base substrate 100 may be a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluoride-doped quartz substrate, a soda-lime glass substrate, an alkali-free glass substrate, etc. Alternatively, in other embodiments, the base substrate 100 includes a flexible transparent material, such as a flexible transparent resin substrate, such as a polyimide substrate.

[0069] According to an embodiment, the first conductive pattern layer is disposed on the base substrate 100. The first conductive pattern layer includes the first connection line CL1. In addition, the first conductive pattern layer also includes a lower conductive pattern ( Fig.17 in BML).

[0070] According to an embodiment, the first insulating layer 110 is disposed on the base substrate 100 on which the first conductive pattern layer is disposed. The first insulating layer 110 is a buffer layer and can prevent metal atoms or impurities from diffusing from the base substrate 100 to the active pattern ( Fig.17 In addition, the first insulating layer 110 controls the heat transfer rate during the crystallization process of forming the active pattern, thereby obtaining a substantially uniform active pattern. In addition, when the surface of the base substrate 100 is uneven, the first insulating layer 110 can improve the flatness of the surface of the base substrate 100.

[0071] According to an embodiment, the second conductive pattern layer is disposed on the first insulating layer 110. The second conductive pattern layer includes a first layer CLK1G of the first clock signal line CLK1, a first layer CLK2G of the second clock signal line CLK2, a first layer CLK3G of the third clock signal line CLK3, and a first layer CLK4G of the fourth clock signal line CLK4.

[0072] In addition, according to an embodiment, the second conductive pattern layer further includes a gate electrode ( Fig.17 GE in ).

[0073] According to an embodiment, the insulating pattern 115 is disposed between the second conductive pattern layer and the first insulating layer 110 , and has the same plane shape as the second conductive pattern layer.

[0074] According to an embodiment, the second insulating layer 120 is disposed on the first insulating layer 110 on which the second conductive pattern layer is disposed.

[0075] According to an embodiment, the third conductive pattern layer is disposed on the second insulating layer 120. The third conductive pattern layer includes a second layer CLK1D of the first clock signal line CLK1, a second layer CLK2D of the second clock signal line CLK2, a second layer CLK3D of the third clock signal line CLK3, and a second layer CLK4D of the fourth clock signal line CLK4.

[0076] In addition, according to an embodiment, the third conductive pattern layer further includes a source electrode and a drain electrode ( Fig.17 of SE and DE).

[0077] According to an embodiment, the third insulating layer 130 is disposed on the third conductive pattern layer.

[0078] According to an embodiment, the first layer CLK1G of the first clock signal line CLK1 is connected to the second layer CLK1D of the first clock signal line CLK1 through a contact hole penetrating the second insulating layer 120. The second layer CLK1D of the first clock signal line CLK1 is connected to the first connection line CL1 through a contact hole penetrating the second insulating layer 120 and the first insulating layer 110.

[0079] According to an embodiment, the first layer CLK2G of the second clock signal line CLK2 is connected to the second layer CLK2D of the second clock signal line CLK2 through a contact hole penetrating the second insulating layer 120 .

[0080] According to an embodiment, the first layer CLK3G of the third clock signal line CLK3 is connected to the second layer CLK3D of the third clock signal line CLK3 through a contact hole penetrating the second insulating layer 120 .

[0081] According to an embodiment, the first layer CLK4G of the fourth clock signal line CLK4 may be connected to the second layer CLK4D of the fourth clock signal line CLK4 through a contact hole penetrating the second insulating layer 120 .

[0082] According to an embodiment, although the connection relationship between the first clock signal line CLK1 and the first connection line CL1 has been described in detail above, the second clock signal line CLK2 and the second connection line CL2, the third clock signal line CLK3 and the third connection line CL3, and the fourth clock signal line CLK4 and the fourth connection line CL4 are similarly configured.

[0083] Figure 5 is a cross-sectional view of a portion of a first wiring region of a display device according to an exemplary embodiment of the inventive concept.

[0084] refer to Figure 2 and Figure 5 According to an embodiment, in addition to the configuration of the conductive pattern layer of the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3 and the fourth clock signal line CLK4 and the first connection line CL1, the second connection line CL2, the third connection line CL3 and the fourth connection line CL4, the display device and Figures 1 to 4 Therefore, repeated description is omitted.

[0085] According to an embodiment, a display device includes: a base substrate 100, a first conductive pattern layer arranged on the base substrate 100, a first insulating layer 110 arranged on the first conductive pattern layer, a second conductive pattern layer arranged on the first insulating layer 110, an insulating pattern 115 arranged between the second conductive pattern layer and the first insulating layer 110, a second insulating layer 120 arranged on the second conductive pattern layer, a third conductive pattern layer arranged on the second insulating layer 120, and a third insulating layer 130 arranged on the third conductive pattern layer.

[0086] According to an embodiment, the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3 and the fourth clock signal line CLK4 are formed by the first conductive pattern layer and the second conductive pattern layer, and the first connecting line CL1, the second connecting line CL2, the third connecting line CL3 and the fourth connecting line CL4 are formed by the third conductive pattern layer.

[0087] Specifically, according to an embodiment, the first conductive pattern layer includes a first layer CLK1B of a first clock signal line CLK1, a first layer CLK2B of a second clock signal line CLK2, a first layer CLK3B of a third clock signal line CLK3, and a first layer CLK4B of a fourth clock signal line CLK4. The second conductive pattern layer includes a second layer CLK1G of a first clock signal line CLK1, a second layer CLK2G of a second clock signal line CLK2, a second layer CLK3G of a third clock signal line CLK3, and a second layer CLK4G of a fourth clock signal line CLK4. The third conductive pattern layer includes a first connecting line CL1.

[0088] According to an embodiment, the first layer CLK1B of the first clock signal line CLK1 is connected to the first connection line CL1 through a contact hole penetrating the first and second insulating layers 110 and 120. The second layer CLK1G of the first clock signal line CLK1 is connected to the first connection line CL1 through a contact hole penetrating the second insulating layer 120.

[0089] According to an embodiment, although the connection relationship between the first clock signal line CLK1 and the first connection line CL1 has been described in detail above, the second clock signal line CLK2 and the second connection line CL2, the third clock signal line CLK3 and the third connection line CL3, and the fourth clock signal line CLK4 and the fourth connection line CL4 are similarly configured.

[0090] Figure 6 is a detailed plan view of a portion of a first wiring region of a display device according to an exemplary embodiment of the inventive concept. Figure 7 is along Figure 6 A cross-sectional view taken along line II'.

[0091] refer to Figure 2 , Figure 6 and Figure 7 According to an embodiment, in addition to the configuration of the conductive pattern layer of the first to fourth clock signal lines CLK1 to CLK4 and the first to fourth connection lines CL1 to CL4, the display device and Figures 1 to 4 Therefore, repeated description will be omitted.

[0092] According to an embodiment, a display device includes: a base substrate 100, a first conductive pattern layer arranged on the base substrate 100, a first insulating layer 110 arranged on the first conductive pattern layer, a second conductive pattern layer arranged on the first insulating layer 110, an insulating pattern 115 arranged between the second conductive pattern layer and the first insulating layer 110, a second insulating layer 120 arranged on the second conductive pattern layer, a third conductive pattern layer arranged on the second insulating layer 120, an interlayer insulating layer 125 arranged on the third conductive pattern layer, a fourth conductive pattern layer arranged on the interlayer insulating layer 125, and a third insulating layer 130 arranged on the fourth conductive pattern layer.

[0093] According to an embodiment, the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3 and the fourth clock signal line CLK4 are formed by the second conductive pattern layer to the fourth conductive pattern layer, and the first connection line CL1, the second connection line CL2, the third connection line CL3 and the fourth connection line CL4 are formed by the first conductive pattern layer.

[0094] Specifically, according to an embodiment, the first conductive pattern layer includes a first connection line CL1. The second conductive pattern layer includes a first layer CLK1G of a first clock signal line CLK1, a first layer CLK2G of a second clock signal line CLK2, a first layer CLK3G of a third clock signal line CLK3, and a first layer CLK4G of a fourth clock signal line CLK4. The third conductive pattern layer includes a second layer CLK1D1 of a first clock signal line CLK1, a second layer CLK2D1 of a second clock signal line CLK2, a second layer CLK3D1 of a third clock signal line CLK3, and a second layer CLK4D1 of a fourth clock signal line CLK4. The fourth conductive pattern layer includes a third layer CLK1D2 of a first clock signal line CLK1, a third layer CLK2D2 of a second clock signal line CLK2, a third layer CLK3D2 of a third clock signal line CLK3, and a third layer CLK4D2 of a fourth clock signal line CLK4.

[0095] According to an embodiment, the first connection line CL1 is connected to the second layer CLK1D1 of the first clock signal line CLK1 through a contact hole penetrating the first insulating layer 110 and the second insulating layer 120. The first layer CLK1G of the first clock signal line CLK1 is connected to the second layer CLK1D1 of the first clock signal line CLK1 through a contact hole penetrating the second insulating layer 120. The second layer CLK1D1 of the first clock signal line CLK1 is connected to the third layer CLK1D2 of the first clock signal line CLK1 through a contact hole penetrating the interlayer insulating layer 125.

[0096] According to an embodiment, the first layer CLK2G of the second clock signal line CLK2 is connected to the second layer CLK2D1 of the second clock signal line CLK2 through a contact hole penetrating the second insulating layer 120. The second layer CLK2D1 of the second clock signal line CLK2 is connected to the third layer CLK2D2 of the second clock signal line CLK2 through a contact hole penetrating the interlayer insulating layer 125.

[0097] According to an embodiment, the first layer CLK3G of the third clock signal line CLK3 is connected to the second layer CLK3D1 of the third clock signal line CLK3 through a contact hole penetrating the second insulating layer 120. The second layer CLK3D1 of the third clock signal line CLK3 is connected to the third layer CLK3D2 of the third clock signal line CLK3 through a contact hole penetrating the interlayer insulating layer 125.

[0098] According to an embodiment, the first layer CLK4G of the fourth clock signal line CLK4 is connected to the second layer CLK4D1 of the fourth clock signal line CLK4 through a contact hole penetrating the second insulating layer 120. The second layer CLK4D1 of the fourth clock signal line CLK4 is connected to the third layer CLK4D2 of the fourth clock signal line CLK4 through a contact hole penetrating the interlayer insulating layer 125.

[0099] According to an embodiment, although the connection relationship between the first clock signal line CLK1 and the first connection line CL1 has been described in detail above, the second clock signal line CLK2 and the second connection line CL2, the third clock signal line CLK3 and the third connection line CL3, and the fourth clock signal line CLK4 and the fourth connection line CL4 are similarly configured.

[0100] Figure 8 is a cross-sectional view of a portion of a first wiring region of a display device according to an exemplary embodiment of the inventive concept.

[0101] refer to Figure 2 and Figure 8 In addition to the configuration of the conductive pattern layer of the first to fourth clock signal lines CLK1 to CLK4 and the first to fourth connection lines CL1 to CL4, the display device and Figure 6 and Figure 7 Therefore, repeated description will be omitted.

[0102] According to an embodiment, the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3 and the fourth clock signal line CLK4 are formed by the first conductive pattern layer, the second conductive pattern layer and the third conductive pattern layer. The first connection line CL1, the second connection line CL2, the third connection line CL3 and the fourth connection line CL4 are formed by the fourth conductive pattern layer.

[0103] Specifically, according to an embodiment, the first conductive pattern layer includes a first layer CLK1B of a first clock signal line CLK1, a first layer CLK2B of a second clock signal line CLK2, a first layer CLK3B of a third clock signal line CLK3, and a first layer CLK4B of a fourth clock signal line CLK4. The second conductive pattern layer includes a second layer CLK1G of a first clock signal line CLK1, a second layer CLK2G of a second clock signal line CLK2, a second layer CLK3G of a third clock signal line CLK3, and a second layer CLK4G of a fourth clock signal line CLK4. The third conductive pattern layer includes a third layer CLK1D1 of a first clock signal line CLK1, a third layer CLK2D1 of a second clock signal line CLK2, a third layer CLK3D1 of a third clock signal line CLK3, and a third layer CLK4D1 of a fourth clock signal line CLK4. The fourth conductive pattern layer includes a first connecting line CL1.

[0104] According to the embodiment, the connection relationship between the first clock signal line CLK1 and the first connection line CL1 is shown in the figure. The connection relationship between the second clock signal line CLK2 and the second connection line CL2, the connection relationship between the third clock signal line CLK3 and the third connection line CL3, and the connection relationship between the fourth clock signal line CLK4 and the fourth connection line CL4 are similarly configured. The detailed description thereof will be omitted.

[0105] Fig. 9 is a cross-sectional view of a portion of a first wiring region of a display device according to an exemplary embodiment of the inventive concept.

[0106] refer to Fig. 9 According to an embodiment, in addition to the configuration of the conductive pattern layer of the first to fourth clock signal lines CLK1 to CLK4 and the first to fourth connection lines CL1 to CL4, the display device and Figure 6 and Figure 7 Therefore, repeated description will be omitted.

[0107] According to an embodiment, a display device includes: a base substrate 100, a first conductive pattern layer arranged on the base substrate 100, a first insulating layer 110 arranged on the first conductive pattern layer, a second conductive pattern layer arranged on the first insulating layer 110, an insulating pattern 115 arranged between the second conductive pattern layer and the first insulating layer 110, a second insulating layer 120 arranged on the second conductive pattern layer, a third conductive pattern layer arranged on the second insulating layer 120, an interlayer insulating layer 125 arranged on the third conductive pattern layer, a fourth conductive pattern layer arranged on the interlayer insulating layer 125, and a third insulating layer 130 arranged on the fourth conductive pattern layer.

[0108] According to the embodiment, the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3 and the fourth clock signal line CLK4 are formed by the first conductive pattern layer and the second conductive pattern layer, and the first connecting line CL1, the second connecting line CL2, the third connecting line CL3 and the fourth connecting line CL4 are formed by the third conductive pattern layer and the fourth conductive pattern layer. That is, the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3 and the fourth clock signal line CLK4 and each of the first connecting line CL1, the second connecting line CL2, the third connecting line CL3 and the fourth connecting line CL4 have a double-layer structure.

[0109] Specifically, according to an embodiment, the first conductive pattern layer includes a first layer CLK1B of the first clock signal line CLK1, a first layer CLK2B of the second clock signal line CLK2, a first layer CLK3B of the third clock signal line CLK3, and a first layer CLK4B of the fourth clock signal line CLK4. The second conductive pattern layer includes a second layer CLK1G of the first clock signal line CLK1, a second layer CLK2G of the second clock signal line CLK2, a second layer CLK3G of the third clock signal line CLK3, and a second layer CLK4G of the fourth clock signal line CLK4.

[0110] According to an embodiment, the third conductive pattern layer includes the first layer CL1D1 of the first connection wire CL1. The fourth conductive pattern layer includes the second layer CL1D2 of the first connection wire CL1.

[0111] According to an embodiment, the first layer CL1D1 of the first connection line CL1 is connected to the first layer CLK1B of the first clock signal line CLK1 through a contact hole penetrating the second insulating layer 120 and the first insulating layer 110. The first layer CL1D1 of the first connection line CL1 is connected to the second layer CLK1G of the first clock signal line CLK1 through a contact hole penetrating the second insulating layer 120.

[0112] According to an embodiment, the second layer CL1D2 of the first connection line CL1 is connected to the first layer CL1D1 of the first connection line CL1 through a contact hole penetrating the interlayer insulating layer 125 .

[0113] According to an embodiment, although the connection relationship between the first clock signal line CLK1 and the first connection line CL1 has been described in detail above, the second clock signal line CLK2 and the second connection line CL2, the third clock signal line CLK3 and the third connection line CL3, and the fourth clock signal line CLK4 and the fourth connection line CL4 are similarly configured.

[0114] Fig.10 is a cross-sectional view of a portion of a first wiring region of a display device according to an exemplary embodiment of the inventive concept.

[0115] refer to Fig.10 According to an embodiment, the display device and the display device are configured such that the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3 and the fourth clock signal line CLK4 are formed of the third conductive pattern layer and the fourth conductive pattern layer, and the first connection line CL1, the second connection line CL2, the third connection line CL3 and the fourth connection line CL4 are formed of the first conductive pattern layer and the second conductive pattern layer. Fig. 9 Therefore, repeated description will be omitted.

[0116] According to an embodiment, a display device includes: a base substrate 100, a first conductive pattern layer arranged on the base substrate 100, a first insulating layer 110 arranged on the first conductive pattern layer, a second conductive pattern layer arranged on the first insulating layer 110, an insulating pattern 115 arranged between the second conductive pattern layer and the first insulating layer 110, a second insulating layer 120 arranged on the second conductive pattern layer, a third conductive pattern layer arranged on the second insulating layer 120, an interlayer insulating layer 125 arranged on the third conductive pattern layer, a fourth conductive pattern layer arranged on the interlayer insulating layer 125, and a third insulating layer 130 arranged on the fourth conductive pattern layer.

[0117] According to the embodiment, the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3 and the fourth clock signal line CLK4 are formed by the third conductive pattern layer and the fourth conductive pattern layer, and the first connection line CL1, the second connection line CL2, the third connection line CL3 and the fourth connection line CL4 are formed by the first conductive pattern layer and the second conductive pattern layer. That is, the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3 and the fourth clock signal line CLK4 and each of the first connection line CL1, the second connection line CL2, the third connection line CL3 and the fourth connection line CL4 have a double-layer structure.

[0118] Specifically, according to an embodiment, the first conductive pattern layer includes a first layer CL1B of the first connection wires CL1. The fourth conductive pattern layer includes a second layer CL1G of the first connection wires CL1.

[0119] According to an embodiment, the third conductive pattern layer includes a first layer CLK1D1 of the first clock signal line CLK1, a first layer CLK2D1 of the second clock signal line CLK2, a first layer CLK3D1 of the third clock signal line CLK3, and a first layer CLK4D1 of the fourth clock signal line CLK4. The fourth conductive pattern layer includes a second layer CLK1D2 of the first clock signal line CLK1, a second layer CLK2D2 of the second clock signal line CLK2, a second layer CLK3D2 of the third clock signal line CLK3, and a second layer CLK4D2 of the fourth clock signal line CLK4.

[0120] According to an embodiment, the first layer CL1B of the first connection line CL1 is connected to the first layer CLK1D1 of the first clock signal line CLK1 through a contact hole penetrating the second insulating layer 120 and the first insulating layer 110. The second layer CL1G of the first connection line CL1 is connected to the first layer CLK1D1 of the first clock signal line CLK1 through a contact hole formed through the second insulating layer 120.

[0121] According to an embodiment, the second layer CLK1D2 of the first clock signal line CLK1 is connected to the first layer CLK1D1 of the first clock signal line CLK1 through a contact hole penetrating the interlayer insulating layer 125 .

[0122] According to an embodiment, although the connection relationship between the first clock signal line CLK1 and the first connection line CL1 has been described in detail above, the second clock signal line CLK2 and the second connection line CL2, the third clock signal line CLK3 and the third connection line CL3, and the fourth clock signal line CLK4 and the fourth connection line CL4 are similarly configured.

[0123] Fig.11 is a cross-sectional view of a portion of a first wiring region of a display device according to an exemplary embodiment of the inventive concept.

[0124] refer to Fig.11 According to the embodiment, in addition to providing a third conductive pattern layer between the gate insulating layer 117 and the second insulating layer 120, the display device and Figure 7 Therefore, repeated description will be omitted.

[0125] According to an embodiment, a display device includes: a base substrate 100, a first conductive pattern layer arranged on the base substrate 100, a first insulating layer 110 arranged on the first conductive pattern layer, a second conductive pattern layer arranged on the first insulating layer 110, an insulating pattern 115 arranged between the second conductive pattern layer and the first insulating layer 110, a gate insulating layer 117 arranged on the second conductive pattern layer, a third conductive pattern layer arranged on the gate insulating layer 117, a second insulating layer 120 arranged on the third conductive pattern layer, a fourth conductive pattern layer arranged on the second insulating layer 120, and a third insulating layer 130 arranged on the fourth conductive pattern layer.

[0126] According to an embodiment, the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3 and the fourth clock signal line CLK4 are formed by the second conductive pattern layer to the fourth conductive pattern layer, and the first connection line CL1, the second connection line CL2, the third connection line CL3 and the fourth connection line CL4 are formed by the first conductive pattern layer.

[0127] Specifically, according to an embodiment, the first conductive pattern layer includes a first connection line CL1. The second conductive pattern layer includes a first layer CLK1G1 of a first clock signal line CLK1, a first layer CLK2G1 of a second clock signal line CLK2, a first layer CLK3G1 of a third clock signal line CLK3, and a first layer CLK4G1 of a fourth clock signal line CLK4. The third conductive pattern layer includes a second layer CLK1G2 of a first clock signal line CLK1, a second layer CLK2G2 of a second clock signal line CLK2, a second layer CLK3G2 of a third clock signal line CLK3, and a second layer CLK4G2 of a fourth clock signal line CLK4. The fourth conductive pattern layer includes a third layer CLK1D of a first clock signal line CLK1, a third layer CLK2D of a second clock signal line CLK2, a third layer CLK3D of a third clock signal line CLK3, and a third layer CLK4D of a fourth clock signal line CLK4.

[0128] According to an embodiment, the first connection line CL1 is connected to the second layer CLK1G2 of the first clock signal line CLK1 through a contact hole formed through the gate insulating layer 117 and the first insulating layer 110. The second layer CLK1G2 of the first clock signal line CLK1 is connected to the third layer CLK1D of the first clock signal line CLK1 through a contact hole formed through the second insulating layer 120.

[0129] According to the embodiment, the connection relationship between the first clock signal line CLK1 and the first connection line CL1 is as shown in the drawings and as described above. The connection relationship between the second clock signal line CLK2 and the second connection line CL2, the connection relationship between the third clock signal line CLK3 and the third connection line CL3, and the connection relationship between the fourth clock signal line CLK4 and the fourth connection line CL4 are similarly configured. A detailed description thereof will be omitted.

[0130] Fig.12 is a cross-sectional view of a portion of a first wiring region of a display device according to an exemplary embodiment of the inventive concept.

[0131] refer to Fig.12 According to an embodiment, in addition to the configuration of the conductive pattern layer constituting the first to fourth clock signal lines CLK1 to CLK4 and the first to fourth connection lines CL1 to CL4, the display device may be Fig.11 Therefore, repeated description will be omitted.

[0132] The first, second, third and fourth clock signal lines CLK1, CLK2, CLK3 and CLK4 are formed of the first, second and third conductive pattern layers. The connection wirings CL1, CL2, CL3 and CL4 may be formed of the fourth conductive pattern layer.

[0133] Specifically, according to an embodiment, the first conductive pattern layer includes a first layer CLK1B of a first clock signal line CLK1, a first layer CLK2B of a second clock signal line CLK2, a first layer CLK3B of a third clock signal line CLK3, and a first layer CLK4B of a fourth clock signal line CLK4. The second conductive pattern layer includes a second layer CLK1G1 of a first clock signal line CLK1, a second layer CLK2G1 of a second clock signal line CLK2, a second layer CLK3G1 of a third clock signal line CLK3, and a second layer CLK4G1 of a fourth clock signal line CLK4. The third conductive pattern layer includes a third layer CLK1G2 of a first clock signal line CLK1, a third layer CLK2G2 of a second clock signal line CLK2, a third layer CLK3G2 of a third clock signal line CLK3, and a third layer CLK4G2 of a fourth clock signal line CLK4. The fourth conductive pattern layer includes a first connecting line CL1.

[0134] According to an embodiment, the first connection line CL1 is connected to the third layer CLK1G2 of the first clock signal line CLK1 through a contact hole penetrating the second insulating layer 120. The third layer CLK1G2 of the first clock signal line CLK1 is connected to the second layer CLK1G1 of the first clock signal line CLK1 through a contact hole formed through the gate insulating layer 117, and the third layer CLK1G2 of the first clock signal line CLK1 is connected to the first layer CLK1B of the first clock signal line CLK1 through a contact hole penetrating the gate insulating layer 117 and the first insulating layer 110.

[0135] According to an embodiment, the connection relationship between the first clock signal line CLK1 and the first connection line CL1 is as shown in the drawings and as described above. The second clock signal line CLK2 and the second connection line CL2, the third clock signal line CLK3 and the third connection line CL3, and the fourth clock signal line CLK4 and the fourth connection line CL4 may be configured similarly. A detailed description thereof will be omitted.

[0136] Fig.13 is a cross-sectional view of a portion of a first wiring region of a display device according to an exemplary embodiment of the inventive concept.

[0137] refer to Fig.13 According to an embodiment, in addition to the configuration of the conductive pattern layer constituting the first to fourth clock signal lines CLK1 to CLK4 and the first to fourth connection lines CL1 to CL4, the display device and Fig.12 Therefore, repeated description will be omitted.

[0138] According to an embodiment, the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3 and the fourth clock signal line CLK4 include a first conductive pattern layer and a second conductive pattern layer, and the first connection line CL1, the second connection line CL2, the third connection line CL3 and the fourth connection line CL4 include a third conductive pattern layer and a fourth conductive pattern layer. That is, the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3 and the fourth clock signal line CLK4 and each of the first connection line CL1, the second connection line CL2, the third connection line CL3 and the fourth connection line CL4 have a double-layer structure.

[0139] Specifically, according to an embodiment, the first conductive pattern layer includes a first layer CL1B of the first connection wires CL1. The second conductive pattern layer includes a second layer CL1G1 of the first connection wires CL1.

[0140] According to an embodiment, the third conductive pattern layer includes a first layer CLK1G2 of the first clock signal line CLK1, a first layer CLK2G2 of the second clock signal line CLK2, a first layer CLK3G2 of the third clock signal line CLK3, and a first layer CLK4G2 of the fourth clock signal line CLK4. The fourth conductive pattern layer includes a second layer CLK1D of the first clock signal line CLK1, a second layer CLK2D of the second clock signal line CLK2, a second layer CLK3D of the third clock signal line CLK3, and a second layer CLK4D of the fourth clock signal line CLK4.

[0141] According to an embodiment, the first layer CL1B of the first connection line CL1 is connected to the first layer CLK1G2 of the first clock signal line CLK1 through a contact hole penetrating the gate insulating layer 117 and the first insulating layer 110 .

[0142] According to an embodiment, the second layer CLK1D of the first clock signal line CLK1 is connected to the first layer CLK1G2 of the first clock signal line CLK1 through a contact hole penetrating the second insulating layer 120 .

[0143] According to an embodiment, the connection relationship between the first clock signal line CLK1 and the first connection line CL1 is as shown in the drawings and as described above. The second clock signal line CLK2 and the second connection line CL2, the third clock signal line CLK3 and the third connection line CL3, and the fourth clock signal line CLK4 and the fourth connection line CL4 are similarly configured. A detailed description thereof will be omitted.

[0144] Fig.14 is a cross-sectional view of a portion of a first wiring region of a display device according to an exemplary embodiment of the inventive concept.

[0145] refer to Fig.14 According to an embodiment, the display device and the display device are configured such that the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3 and the fourth clock signal line CLK4 are formed of the first conductive pattern layer and the second conductive pattern layer, and the first connection line CL1, the second connection line CL2, the third connection line CL3 and the fourth connection line CL4 are formed of the third conductive pattern layer and the fourth conductive pattern layer. Fig.13 Therefore, repeated description will be omitted.

[0146] Specifically, according to an embodiment, the third conductive pattern layer includes the first layer CL1G2 of the first connection wire CL1. The fourth conductive pattern layer includes the second layer CL1D of the first connection wire CL1.

[0147] According to an embodiment, the first conductive pattern layer includes a first layer CLK1B of a first clock signal line CLK1, a first layer CLK2B of a second clock signal line CLK2, a first layer CLK3B of a third clock signal line CLK3, and a first layer CLK4B of a fourth clock signal line CLK4. The second conductive pattern layer includes a second layer CLK1G1 of a first clock signal line CLK1, a second layer CLK2G1 of a second clock signal line CLK2, a second layer CLK3G1 of a third clock signal line CLK3, and a second layer CLK4G1 of a fourth clock signal line CLK4.

[0148] According to an embodiment, the first layer CL1G2 of the first connection line CL1 is connected to the second layer CLK1G1 of the first clock signal line CLK1 through a contact hole penetrating the gate insulating layer 117, and is connected to the first layer CLK1B of the first clock signal line CLK1 through a contact hole penetrating the gate insulating layer 117 and the first insulating layer 110. The second layer CL1D of the first connection line CL1 is connected to the first layer CL1G2 of the first connection line CL1 through a contact hole penetrating the second insulating layer 120.

[0149] According to an embodiment, the connection relationship between the first clock signal line CLK1 and the first connection line CL1 is as shown in the drawings and as described above. The second clock signal line CLK2 and the second connection line CL2, the third clock signal line CLK3 and the third connection line CL3, and the fourth clock signal line CLK4 and the fourth connection line CL4 are similarly configured. A detailed description thereof will be omitted.

[0150] Fig.15 is a cross-sectional view of a portion of a first wiring region of a display device according to an exemplary embodiment of the inventive concept. Fig.16 is along Fig.15 A cross-sectional view taken along line II'.

[0151] refer to Fig.15 and Fig.16 According to an embodiment, a display device includes: a base substrate 100, a first insulating layer 110 disposed on the base substrate 100, an active pattern layer disposed on the first insulating layer 110, a first conductive pattern layer disposed on the active pattern layer, an insulating pattern 115 disposed between the first conductive pattern layer and the first insulating layer 110, a second insulating layer 120 disposed on the first conductive pattern layer, a second conductive pattern layer disposed on the second insulating layer 120, and a third insulating layer 130 disposed on the second conductive pattern layer.

[0152] According to an embodiment, the active pattern layer includes Figure 1 The active pattern of the thin film transistor in the display area DA ( Fig.17Since the connection line CL1 is used as an electrical wiring, the connection line CL1 has a portion doped with impurities and having improved conductivity.

[0153] At this time, according to an embodiment, in order to dope impurities, the connection line CL1 does not overlap with the first conductive pattern layer. Fig.15 As shown, in a plan view, in a portion where the first connection line CL1 is located, the wiring may be broken (cut) so that the first conductive pattern layer is not formed.

[0154] According to an embodiment, the first conductive pattern layer includes a first layer CLK1G of a first clock signal line CLK1, a first layer CLK2G of a second clock signal line CLK2, a first layer CLK3G of a third clock signal line CLK3, and a first layer CLK4G of a fourth clock signal line CLK4.

[0155] According to an embodiment, the second conductive pattern layer includes a second layer CLK1D of the first clock signal line CLK1 , a second layer CLK2D of the second clock signal line CLK2 , a second layer CLK3D of the third clock signal line CLK3 , and a second layer CLK4D of the fourth clock signal line CLK4 .

[0156] According to an embodiment, the connection line CL1 is connected to the second layer CLK1D of the first clock signal line CLK1 through a contact hole penetrating the second insulating layer 120. The second layer CLK1D of the first clock signal line CLK1 is connected to the first layer CLK1G of the first clock signal line CLK1 through a contact hole penetrating the second insulating layer 120.

[0157] According to an embodiment, although the connection relationship between the first clock signal line CLK1 and the first connection line CL1 has been described in detail above, the second clock signal line CLK2 and the second connection line CL2, the third clock signal line CLK3 and the third connection line CL3, and the fourth clock signal line CLK4 and the fourth connection line CL4 are similarly configured.

[0158] Fig.17 is a cross-sectional view of a stacked pixel structure in a display area of ​​a display device according to an exemplary embodiment of the inventive concept.

[0159] refer to Fig.17 According to an embodiment, in Figure 1 In the display area DA, the display device may include a base substrate 100, a lower conductive pattern BML, a first insulating layer 110, an active pattern ACT, a gate electrode GE, an insulating pattern 115, a second insulating layer 120, a source electrode SE and a drain electrode DE, a third insulating layer 130, a pixel defining layer PDL, a light emitting structure 180 and a thin film encapsulation layer TFE.

[0160] According to an embodiment, the base substrate 100 may be made of a transparent material or an opaque material.

[0161] According to an embodiment, the lower conductive pattern BML is disposed on the base substrate 100. The lower conductive pattern BML is formed of a first conductive pattern layer.

[0162] According to an embodiment, the first insulating layer 110 is disposed on the base substrate 100 on which the lower conductive pattern BML is disposed.

[0163] According to an embodiment, the active pattern ACT is disposed on the first insulating layer 110 and overlaps the lower conductive pattern BML. The active pattern ACT may include amorphous silicon or polycrystalline silicon. The active pattern ACT includes a drain region and a source region doped with impurities and a channel region between the drain region and the source region.

[0164] According to an embodiment, the gate electrode GE is disposed on the channel region of the active pattern ACT. The gate electrode GE is formed of the second conductive pattern layer.

[0165] According to an embodiment, the insulating pattern 115 is disposed between the gate electrode GE and the first insulating layer 110 .

[0166] According to an embodiment, the second insulating layer 120 is disposed on the first insulating layer 110 on which the gate electrode GE is disposed.

[0167] According to an embodiment, the source electrode SE and the drain electrode DE are disposed on the second insulating layer 120. The source electrode SE and the drain electrode DE are electrically connected to the active pattern ACT through a contact hole penetrating the second insulating layer 120. The drain electrode DE is electrically connected to the lower conductive pattern BML through a contact hole penetrating the first insulating layer 110 and the second insulating layer 120. The source electrode SE and the drain electrode DE are formed of a third conductive pattern layer.

[0168] According to an embodiment, the third insulating layer 130 is disposed on the source electrode SE and the drain electrode DE. The third insulating layer 130 is a via insulating layer. The via insulating layer may be formed as a single-layer structure or a multi-layer structure including at least two insulating layers. The via insulating layer may be formed using an organic material such as a photoresist, an acrylic resin, a polyimide resin, a polyamide resin, or a siloxane-based resin.

[0169] According to the embodiment, the light emitting structure 180 includes a first electrode 181 , a light emitting layer 182 , and a second electrode 183 .

[0170] According to an embodiment, the first electrode 181 is disposed on the third insulating layer 130. The first electrode 181 may include a reflective material or a transmissive material according to the emission type of the display device. In an exemplary embodiment, the first electrode 181 may have a single-layer structure or a multi-layer structure, and the first electrode 181 may include a metal film, an alloy film, a metal nitride film, a conductive metal oxide film, or a transparent conductive film.

[0171] According to an embodiment, a pixel defining layer PDL is disposed on a third insulating layer 130 on which a first electrode 181 is disposed. The pixel defining layer PDL is formed using an organic material. For example, the pixel defining layer PDL may include a photoresist, an acrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, and the like. In some exemplary embodiments, an opening exposing the first electrode 181 is formed by etching the pixel defining layer PDL. An emission region and a non-emission region of a display device are defined by an opening of the pixel defining layer PDL. For example, a portion where the opening of the pixel defining layer PDL is located corresponds to an emission region, and a non-emission region corresponds to a portion adjacent to the opening of the pixel defining layer PDL.

[0172] According to an embodiment, the light emitting layer 182 is disposed on the first electrode 181 exposed by the opening of the pixel defining layer PDL. In addition, the light emitting layer 182 extends on the sidewall of the opening of the pixel defining layer PDL. In some exemplary embodiments, the light emitting layer 182 includes an organic light emitting layer (EL), a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), an electron injection layer (EIL), etc. In some exemplary embodiments, in addition to the organic emission layer, the hole injection layer, the hole transport layer, the electron transport layer and the electron injection layer are formed together to correspond to a plurality of pixels. In some exemplary embodiments, according to the color pixels of the display device, a plurality of organic light emitting layers are formed using light emitting materials that generate light of different colors such as red light, green light or blue light. In some exemplary embodiments, the organic light emitting layer of the light emitting layer 182 includes a plurality of stacked light emitting materials that generate red light, green light or blue light, thereby emitting white light. Here, the elements of the light emitting layer 182 are formed together to correspond to a plurality of pixels, and each pixel can be divided by a color filter layer.

[0173] According to an embodiment, the second electrode 183 is disposed on the pixel defining layer PDL and the light emitting layer 182. The second electrode 183 may include a transmissive material or a reflective material according to the emission type of the display device. In an exemplary embodiment, the second electrode 183 may also have a single-layer structure or a multi-layer structure, and the second electrode 183 may include a metal film, an alloy film, a metal nitride film, a conductive metal oxide film, or a transparent conductive film.

[0174] According to an embodiment, a thin film encapsulation layer TFE is disposed on the second electrode 183. The thin film encapsulation layer TFE prevents penetration of external moisture and oxygen. The thin film encapsulation layer TFE includes at least one organic layer and at least one inorganic layer. At least one organic layer and at least one inorganic layer are alternately stacked with each other. For example, the thin film encapsulation layer TFE may include two inorganic layers and one organic layer therebetween, but the embodiment is not limited thereto. In some embodiments, a sealing substrate is provided instead of the thin film encapsulation layer TFE, and the sealing substrate shields external air and moisture from penetrating into the display device.

[0175] Fig.18 is a cross-sectional view of a portion of a second wiring area LA2 of a display device according to an exemplary embodiment of the inventive concept.

[0176] refer to Figure 2 and Fig.18 According to an embodiment, in the second wiring area LA2, the display device includes a first conductive pattern layer, a first insulating layer 110, a second conductive pattern layer, an insulating pattern 115, a second insulating layer 120, a third conductive pattern layer, an interlayer insulating layer 125, a fourth conductive pattern layer and a third insulating layer 130.

[0177] According to an embodiment, the first conductive pattern layer includes a gate connection line SL. The second conductive pattern layer includes a first layer VSS1G of a first power line VSS1, a first layer VSS2G of a second power line VSS2, and a first layer VSS3G of a third power line VSS3. The third conductive pattern layer includes a second layer VSS1D1 of the first power line VSS1, a second layer VSS2D1 of the second power line VSS2, and a second layer VSS3D1 of the third power line VSS3. The first layer VSS1G of the first power line VSS1 is connected to the second layer VSS1D1 of the first power line VSS1 through a contact hole formed through the second insulating layer 120.

[0178] That is, according to the embodiment, the first power line VSS1 , the second power line VSS2 , and the third power line VSS3 have a double-layered structure of the second conductive pattern layer and the third conductive pattern layer.

[0179] According to an embodiment, the fourth conductive pattern layer includes an ELVSS line ELVSS. The ELVSS line ELVSS is electrically connected to the light emitting structure in the display area. Fig.17 The ELVSS line ELVSS overlaps the first power line VSS1, the second power line VSS2, and the third power line VSS3 to reduce the width of the second wiring area LA2.

[0180] According to an embodiment, the first power line VSS1, the second power line VSS2, and the third power line VSS3 are electrically connected to the gate signal generator ASG through the first power connection line CL5, the second power connection line CL6, and the third power connection line CL7. They have a structure similar to the connection structure of the above-mentioned connection line and the clock signal line. Therefore, a detailed description thereof will be omitted.

[0181] Fig.19 is a plan view of a display device according to an exemplary embodiment of the inventive concept. Fig. 20 Shown in Fig.19 The circuits and wiring in area A of the display device.

[0182] refer to Fig.19 and Fig. 20 According to the embodiment, in addition to the display device further including a shield wiring SHL disposed at the outermost portion of the peripheral area PA, the display device and Figures 1 to 4 Therefore, repeated description will be omitted.

[0183] According to an embodiment, the display device further includes a shielding wiring SHL disposed in the peripheral area PA. That is, the shielding wiring SHL is disposed adjacent to the first to fourth clock signal lines CLK1 to CLK4, and is disposed between the first to fourth clock signal lines CLK1 to CLK4 and the end of the base substrate PN. The shielding wiring SHL is formed by any one or more layers or more of the first to third conductive pattern layers, and may be in a floating state or a constant voltage (such as an ELVSS voltage) state. The shielding wiring SHL may prevent static electricity from flowing at the outermost portion of the clock signal line, thereby improving display quality.

[0184] Fig.21 is a plan view of a display device according to an exemplary embodiment of the inventive concept.

[0185] refer to Fig.21 According to the embodiment, the display device and Fig.19 and Fig. 20 Therefore, repeated description is omitted.

[0186] According to an embodiment of the inventive concept, a clock signal line is formed of a plurality of conductive pattern layers, and a connection line connecting the clock signal line to a gate signal generator is formed as the uppermost or lowermost layer of the conductive pattern layer. The resistance of the clock signal line is reduced, and the parasitic capacitance between the clock signal line and the connection line can be minimized.

[0187] Fig. 22 is a block diagram of an electronic device according to an exemplary embodiment. Fig.23AIt shows that Fig. 22 An example in which the electronic device is implemented as a television. Fig. 23B It shows that Fig. 22 The electronic device is implemented as an example of a smart phone.

[0188] refer to Figures 22 to 23B According to an embodiment, the electronic device 500 includes a processor 510, a memory device 520, a storage device 530, an input / output (I / O) device 540, a power supply 550, and a display device 560. Here, the display device 560 corresponds to Figure 1 In addition, the electronic device 500 also includes a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, etc. In an exemplary embodiment, as Fig.23A As shown, the electronic device 500 is implemented as a television. In another exemplary embodiment, as Fig. 23B As shown, the electronic device 500 is implemented as a smart phone. However, the embodiment of the electronic device 500 is not limited thereto. For example, the electronic device 500 can be implemented as a cellular phone, a video phone, a smart tablet computer, a smart watch, a tablet PC, a car navigation system, a computer monitor, a laptop computer, a head mounted display (HMD), etc.

[0189] According to an embodiment, the processor 510 performs various computing functions. The processor 510 may be a microprocessor, a central processing unit (CPU), an application processor (AP), etc. The processor 510 is coupled to other components via an address bus, a control bus, a data bus, etc. In addition, the processor 510 may be coupled to an expansion bus such as a peripheral component interconnect (PCI) bus. The memory device 520 stores data for operating the electronic device 500. For example, the memory device 520 includes at least one nonvolatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc., or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, etc. The storage device 530 may be a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I / O device 540 includes input devices such as a keyboard, a keypad, a mouse device, a touch pad, a touch screen, etc., and output devices such as a printer, a speaker, etc. The power supply 550 provides power for operating the electronic device 500.

[0190] According to an embodiment, the display device 560 may be coupled to other components via a bus or other communication links. In some exemplary embodiments, the display device 560 is included in the I / O device 540. As described above, since the clock signal line of the display device 560 is formed by a plurality of conductive pattern layers, and the connection line connecting the clock signal line and the gate signal generator is formed as the uppermost or lowermost layer of the conductive pattern layer, the resistance of the clock signal line is reduced, and the parasitic capacitance between the clock signal line and the connection line can be minimized.

[0191] Embodiments of the inventive concept may be incorporated into an organic light-emitting display device and various electronic devices including the organic light-emitting display device. For example, embodiments of the inventive concept may be incorporated into mobile phones, smart phones, video phones, smart tablet computers, smart watches, tablet PCs, car navigation systems, televisions, computer monitors, notebook computers, etc.

[0192] The foregoing describes embodiments of the inventive concept and is not to be construed as limiting the embodiments of the inventive concept. Although some exemplary embodiments of the inventive concept have been described, it will be readily appreciated by those skilled in the art that many modifications may be made in the exemplary embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. Therefore, it will be understood that the foregoing describes embodiments of the inventive concept and is not to be construed as being limited to the specific exemplary embodiments disclosed, and modifications to the disclosed exemplary embodiments and other exemplary embodiments are intended to be included within the scope of the appended claims. The inventive concept is defined by the following claims, including the equivalents of the claims.

Claims

1. A display device, wherein: The display device comprises: a base substrate including a display region in which pixels are formed and a peripheral region as a non-display region surrounding the display region, wherein the peripheral region includes a first wiring region and a circuit region; a first conductive pattern layer disposed on the base substrate; a first insulating layer disposed on the first conductive pattern layer; a second conductive pattern layer disposed on the first insulating layer; a second insulating layer disposed on the second conductive pattern layer; a third conductive pattern layer disposed on the second insulating layer; a plurality of signal lines disposed in the first wiring region, wherein the plurality of signal lines are spaced apart in a first direction and extend in a second direction perpendicular to the first direction; a gate signal generator disposed in the circuit region, wherein the gate signal generator generates a gate signal and transmits the gate signal to the pixel; and a plurality of connection lines arranged in the peripheral region, wherein the plurality of connection lines extend in the first direction and connect the signal lines to the gate signal generators, respectively; Wherein, the connecting line is formed by the bottom layer or the top layer of the conductive pattern layer, and The signal line is formed by at least two conductive pattern layers overlapping each other.

2. The display device according to claim 1, wherein: The display device further includes: a thin film transistor disposed in the display area, Wherein, the thin film transistor comprises: a lower conductive pattern disposed on the base substrate; an active pattern overlapping the lower conductive pattern; a gate electrode disposed on the active pattern; and A source electrode and a drain electrode electrically connected to the active pattern, Wherein, the lower conductive pattern and the connecting line are formed by the first conductive pattern layer, The gate electrode is formed by the second conductive pattern layer, The source electrode and the drain electrode are formed by the third conductive pattern layer, and Each of the signal lines is formed by the second conductive pattern layer and the third conductive pattern layer.

3. The display device according to claim 1, wherein: The display device further includes: a lower conductive pattern disposed in the display area of ​​the base substrate; and a thin film transistor disposed in the display area and overlapping the lower conductive pattern, Wherein, the thin film transistor comprises: an active pattern overlapping the lower conductive pattern; a gate electrode disposed on the active pattern; and A source electrode and a drain electrode electrically connected to the active pattern, wherein the lower conductive pattern is formed by the first conductive pattern layer, The gate electrode is formed by the second conductive pattern layer, The source electrode, the drain electrode and the connection line are formed by the third conductive pattern layer, and Each of the signal lines is formed by the first conductive pattern layer and the second conductive pattern layer.

4. The display device according to claim 1, wherein: The display device further includes: a third insulating layer disposed on the third conductive pattern layer; and A fourth conductive pattern layer is disposed on the third insulating layer.

5. The display device according to claim 4, wherein: The signal line is formed by the first conductive pattern layer, the second conductive pattern layer and the third conductive pattern layer, and The connecting line is formed by the fourth conductive pattern layer.

6. The display device according to claim 4, wherein: The signal line is formed by the second conductive pattern layer, the third conductive pattern layer and the fourth conductive pattern layer, and The connecting line is formed by the first conductive pattern layer.

7. The display device according to claim 6, wherein: The display device further includes: an insulating pattern disposed between the first insulating layer and the second conductive pattern layer and having the same planar shape as the second conductive pattern layer, wherein: A portion of the third conductive pattern layer is electrically connected to a portion of the first conductive pattern layer through a contact hole penetrating the second insulating layer and the first insulating layer. A portion of the fourth conductive pattern layer is electrically connected to a portion of the third conductive pattern layer through a contact hole penetrating the third insulating layer.

8. The display device according to claim 4, wherein: The signal line is formed by the first conductive pattern layer and the second conductive pattern layer, and The connection line includes two layers formed of the third conductive pattern layer and the fourth conductive pattern layer overlapping each other.

9. The display device according to claim 4, wherein: The signal line is formed by the third conductive pattern layer and the fourth conductive pattern layer, and The connection line includes two layers formed of the first conductive pattern layer and the second conductive pattern layer overlapping each other.

10. The display device according to claim 1, wherein: The display device further includes: an insulating pattern disposed between the first insulating layer and the second conductive pattern layer and having the same planar shape as the second conductive pattern layer, wherein: A portion of the third conductive pattern layer is electrically connected to a portion of the first conductive pattern layer through a contact hole penetrating the second insulating layer and the first insulating layer.

11. The display device according to claim 1, wherein: The peripheral area further includes a second wiring area provided between the circuit area and the display area. Wherein, the display device further includes: a plurality of power lines arranged in the second wiring area, wherein the plurality of power lines are spaced apart in the first direction and extend in the second direction; and a plurality of power connection lines disposed in the peripheral region, wherein the plurality of power connection lines connect the power line to the gate signal generator and extend in the first direction, Wherein, the power connection line is formed by the lowermost layer or the uppermost layer of the conductive pattern layer, and The power supply line is formed of two or more layers of the conductive pattern layer.

12. The display device according to claim 11, wherein: The display device further includes: a third insulating layer disposed on the third conductive pattern layer; and a fourth conductive pattern layer disposed on the third insulating layer, The power connection line is formed by the first conductive pattern layer or the fourth conductive pattern layer, and each of the power lines is formed by the second conductive pattern layer to the fourth conductive pattern layer or the first conductive pattern layer to the third conductive pattern layer.

13. The display device according to claim 11, wherein: The display device further includes: a through insulating layer disposed on the second insulating layer; a first electrode disposed on the through insulating layer in the display area; a light-emitting layer disposed on the first electrode; a second electrode disposed on the light-emitting layer; and an ELVSS line in the second wiring region, the ELVSS line overlapping at least two of the power supply lines, Wherein, the ELVSS line is electrically connected to the second electrode.

14. The display device according to claim 1, wherein: The display device further includes: a shield wiring disposed on the base substrate adjacent to the signal line, The shielding wiring is formed by one or more conductive pattern layers from the first conductive pattern layer to the third conductive pattern layer, and the signal line is arranged between the shielding wiring and the gate signal generator.

15. The display device according to claim 1, wherein: The display device further includes: connecting the gate signal generator and the gate connection line of the pixel, Wherein, the gate connection line is formed by the lowermost layer or the uppermost layer of the conductive pattern layer.

16. The display device according to claim 1, wherein: The signal line includes a first portion and a second portion overlapping the first portion, and The first portion and the second portion are connected via a contact hole, and the contact hole penetrates the insulating layer between the first portion and the second portion.

17. A display device, wherein: The display device comprises: a base substrate including a display area in which pixels are formed and a peripheral area as a non-display area surrounding the display area, wherein the peripheral area includes a first wiring area and a circuit area; an active pattern disposed on the base substrate; a gate insulating layer disposed on the active pattern; a gate conductive pattern layer disposed on the gate insulating layer; an interlayer insulating layer disposed on the gate conductive pattern layer; a data conductive pattern layer disposed on the interlayer insulating layer; a plurality of signal lines disposed in the first wiring region, wherein the plurality of signal lines are spaced apart in a first direction and extend in a second direction perpendicular to the first direction; a gate signal generator disposed in the circuit region, wherein the gate signal generator transmits a gate signal to the pixel; and a plurality of connection lines disposed in the peripheral region, wherein the plurality of connection lines extend in the first direction and connect the signal line to the gate signal generator, Wherein, the connecting line is formed by the active pattern, The signal line is formed by the gate conductive pattern layer and the data conductive pattern layer overlapping each other.

18. The display device according to claim 17, wherein: The connecting line does not overlap with the gate conductive pattern layer.

19. The display device according to claim 17, wherein: The connection line is a portion of the active pattern doped with impurities.

20. A display device, wherein: The display device comprises: a base substrate including a display area in which pixels are formed and a peripheral area as a non-display area surrounding the display area, wherein the peripheral area includes a first wiring area and a circuit area; a first conductive pattern layer disposed on the base substrate; a first insulating layer disposed on the first conductive pattern layer; a second conductive pattern layer disposed on the first insulating layer; a second insulating layer disposed on the second conductive pattern layer; a third conductive pattern layer disposed on the second insulating layer; a third insulating layer disposed on the third conductive pattern layer; a fourth conductive pattern layer disposed on the third insulating layer; a plurality of signal lines disposed in the first wiring region, wherein the plurality of signal lines are spaced apart in a first direction and extend in a second direction perpendicular to the first direction; and a plurality of connection lines arranged in the peripheral region, wherein the plurality of connection lines extend in the first direction and are respectively connected to the signal lines, Wherein, the connecting line is formed by the bottom layer or the top layer of the conductive pattern layer, and The signal line is formed of at least two conductive pattern layers except the conductive pattern layer of the connection line.

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