Display device

Abstract

The present application relates to a display device. The display device includes: a substrate including pixels; a scan line for supplying a scan signal to the pixel; a data line for supplying a data signal to the pixel; a first power line for supplying a first driving power supply to the pixel; a second power line for supplying a second driving power supply to the pixel; and a third power line for supplying a ground voltage to the pixel. The pixel includes: a first electrode and a second electrode spaced apart from each other on the substrate; a plurality of light-emitting elements, each of which has a first end and a second end in a length direction thereof and is arranged between the first electrode and the second electrode; and a first switch electrically connected between the third power line and the first electrode. The first switch is configured to be turned on by a control signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0015172, filed on February 8, 2019, in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Aspects of embodiments of the present disclosure generally relate to a display device including a micro light emitting element. Background Art

[0004] Light emitting diodes exhibit relatively satisfactory durability even in relatively severe environmental conditions and have excellent performance in terms of life span and brightness. Recently, research on applying such light emitting diodes to various light emitting elements has been actively conducted.

[0005] As part of such research, a technology has been developed to manufacture microscopic light-emitting diodes (e.g., micro- or nano-scale light-emitting diodes) as small as micrometers or nanometers by using an inorganic crystal structure (e.g., a structure in which a nitride-based semiconductor is grown). The light-emitting diodes can be manufactured to have a size small enough to constitute pixels of a display panel, etc. After the light-emitting diodes are grown separately (or independently) on a substrate, the grown light-emitting diodes are separated from the substrate for use in manufacturing a display panel, etc. Summary of the invention

[0006] Embodiments of the present disclosure provide a display device that is manufactured through a relatively simple process that omits a separation process of lines for aligning light emitting elements, and improves reliability by reducing or minimizing defects that may occur during the separation process.

[0007] According to an embodiment of the present disclosure, a display device includes: a substrate including pixels; a scan line for supplying a scan signal to the pixel; a data line for supplying a data signal to the pixel; a first power line for supplying a first driving power supply to the pixel; a second power line for supplying a second driving power supply to the pixel; and a third power line for supplying a ground voltage to the pixel. The pixel includes: a first electrode and a second electrode spaced apart from each other on the substrate; a plurality of light-emitting elements, each of which has a first end and a second end in a length direction thereof and is arranged between the first electrode and the second electrode; and a first switch electrically connected between the third power line and the first electrode. The first switch is configured to be turned on by a control signal.

[0008] The pixel may further include a first conductive line and a second conductive line located on the same plane as the first electrode and the second electrode. The first conductive line and the second conductive line may be spaced apart from each other. When viewed on a plane, the first conductive line and the second conductive line may be located between the first electrode and the second electrode.

[0009] When the first switch is turned on, an AC voltage having a level different from that of the second driving power source may be applied to the second electrode.

[0010] The pixel may also include: a control signal line configured to have a control signal applied thereto; a second switch connected between the first conductive line and the third power line, the second switch configured to be turned on concurrently with the first switch by the control signal; and a third switch connected between the second conductive line and the second power line, the third switch configured to be turned on concurrently with the first switch by the control signal.

[0011] The first conductive line and the second conductive line may be floating electrodes.

[0012] The control signal lines may be located in the same layer as the scan lines.

[0013] Each of the first switch, the second switch, and the third switch may include a thin film transistor.

[0014] Each of the first switch, the second switch, and the third switch may include: a gate electrode on a substrate, the gate electrode being integrated with a control signal line; an active pattern overlapping a region of the gate electrode; and a first terminal and a second terminal contacting both ends of the active pattern.

[0015] The pixel may also include: a pixel circuit connected between the first power line and the first electrode or between the second power line and the second electrode, and the pixel circuit may include a driving transistor for driving the light emitting element and a switching transistor connected between the data line and the driving transistor.

[0016] The driving transistor and the switching transistor may include transistors having the same type as the first switch, the second switch, and the third switch.

[0017] When the first switch, the second switch, and the third switch are concurrently turned on, a ground voltage may be supplied to the first electrode and an AC voltage may be applied to the second electrode, so that an electric field is formed between the first electrode and the second electrode.

[0018] When the first switch, the second switch, and the third switch are concurrently turned off, the first driving power may be applied to the first electrode via the pixel circuit, and the second driving power may be applied to the second electrode.

[0019] The pixel circuit may further include: a first capacitor connected between a gate electrode of the driving transistor and the first power line; and a second capacitor connected between the first electrode and the second power line.

[0020] The first capacitor may include: a first lower electrode located on a substrate; a first upper electrode located on the first lower electrode; and an interlayer insulating layer interposed between the first lower electrode and the first upper electrode. The second capacitor may include: a second lower electrode located in the same layer as the first lower electrode; a second upper electrode located on the second lower electrode; and an interlayer insulating layer interposed between the second lower electrode and the second upper electrode. The first upper electrode and the second upper electrode may be located in the same layer.

[0021] The first conductive line may be electrically connected to the first electrode through the first bridge pattern, and the second conductive line may be electrically connected to the second electrode through the second bridge pattern spaced apart from the first bridge pattern.

[0022] The first bridge pattern and the second bridge pattern may be located in the same layer as the data line.

[0023] When the first switch is turned on, a ground voltage may be applied to each of the first conductive line and the first electrode, and an AC voltage may be applied to each of the second conductive line and the second electrode, so that an electric field is formed between the first electrode and the second electrode.

[0024] The pixel may further include: a first shielding electrode line located between the first electrode and the interlayer insulating layer; a second shielding electrode line located between the first conductive line and the interlayer insulating layer; and a third shielding electrode line located between the second conductive line and the interlayer insulating layer.

[0025] The pixel may further include: a first contact electrode electrically connecting either one of the first end and the second end of each of the light emitting elements to the first electrode; and a second contact electrode electrically connecting the other of the first end and the second end of each of the light emitting elements to the second electrode.

[0026] According to an embodiment of the present disclosure, a display device includes: a substrate having a display area and a non-display area; and a pixel located in the display area and connected to a scan line, a control signal line, and a data line. The pixel includes: a plurality of light-emitting elements connected between a first electrode and a second electrode; a first transistor connected to the data line and the scan line and configured to be turned on by an i-th (where i is a natural number of 2 or greater) scan signal; a second transistor connected between a first node and a first electrode to control the amount of current flowing from a first drive power supply to a second drive power supply via the light-emitting element; a first capacitor connected between a first node and the first drive power supply; and a first switch connected between a power line to which a ground voltage is to be applied and a second node, and configured to be turned on by an i-th control signal.

[0027] The pixel may further include a second capacitor connected between the second node and the second driving power source.

[0028] The pixel may further include: a second switch connected between the second node and the second conductive line, the second switch configured to be turned on by the i-th control signal; and a third switch connected between the second driving power source and the first conductive line, the third switch configured to be turned on by the i-th control signal.

[0029] The light emitting elements may be connected in parallel between the first electrode and the first conductive line, between the first conductive line and the second conductive line, and between the second conductive line and the second electrode, respectively.

[0030] The first electrode, the first and second conductive wires, and the second electrode may be sequentially connected in series via each of the light emitting elements.

[0031] The pixel may also include: a third transistor connected between the second transistor and the first node, the third transistor being configured to be turned on by the i-th scanning signal; a fourth transistor connected between the initialization power line to which the initialization power is to be applied and the first node, the fourth transistor being configured to be turned on by the (i-1)-th scanning signal; a fifth transistor connected between the second transistor and the first driving power source, the fifth transistor being configured to be disconnected when the emission control signal is supplied to the emission control line; a sixth transistor connected between the second transistor and the second node, the sixth transistor being configured to be disconnected when the emission control signal is supplied; and a seventh transistor connected between the initialization power line and the second node.

[0032] According to an embodiment of the present disclosure, a display device includes: a substrate having a display area in which pixels are arranged and a non-display area located at the periphery of the display area; a first power line configured to supply a first driving power supply to the pixel; a second power line configured to supply a second driving power supply to the pixel; a third power line connected to the pixel, the third power line having a ground voltage applied thereto; a control signal line located in the non-display area, the control signal line extending in one direction; and a switch connected to the first power line to the third power line in the non-display area, the switch being configured to be turned on by a control signal of the control signal line. The pixel includes: a first electrode and a second electrode spaced apart from each other on the substrate; a plurality of light-emitting elements, each of the light-emitting elements having a first end and a second end in a length direction thereof, the plurality of light-emitting elements being arranged between the first electrode and the second electrode; and a first conductive line and a second conductive line located on the same plane as the first electrode and the second electrode, the first conductive line and the second conductive line being spaced apart from each other. When the switch is turned on, the first electrode is connected to any one of the first conductive line and the second conductive line, and the second electrode is connected to the other of the first conductive line and the second conductive line. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Exemplary embodiments will now be described more fully below with reference to the accompanying drawings; however, the present disclosure may be implemented in different forms and should not be construed as being limited to the exemplary embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and will fully convey the scope of the present disclosure to those skilled in the art.

[0034] In the drawings, dimensions may be exaggerated for clarity of illustration. Throughout, like reference numerals refer to like elements.

[0035] Figure 1A is a perspective view schematically showing a light emitting element according to an embodiment of the present disclosure.

[0036] Figure 1B yes Figure 1A A cross-sectional view of a light emitting element shown in FIG.

[0037] Figure 1C is a perspective view schematically showing a light emitting element according to another embodiment of the present disclosure.

[0038] Figure 1D yes Figure 1C A cross-sectional view of a light emitting element shown in FIG.

[0039] Figure 2 is used Figure 1A Schematic plan view of a display device according to an embodiment of the present disclosure, in which the light-emitting element shown in FIG. 1 is used as a light-emitting source.

[0040] FIG. 3A to FIG. 3D It is a diagram showing various embodiments according to the present disclosure. Figure 2 A circuit diagram showing an electrical connection relationship between components included in one pixel among the pixels shown in FIG.

[0041] Figure 4 It is shown Figure 3D A plan view of the pixel shown in FIG.

[0042] Figure 5 It is along Figure 4 A cross-sectional view taken along line II' shown in FIG.

[0043] Figure 6 Show Figure 5 The embodiment of the first bank shown in FIG. Figure 4 A cross-sectional view along line II' shown in FIG.

[0044] Figure 7 The capping layer is shown in Figure 5 between the first electrode and the contact electrode and between the second electrode and the contact electrode as shown in Figure 7 is corresponding to Figure 4 A cross-sectional view along line II' shown in FIG.

[0045] Figure 8 It is along Figure 4 A cross-sectional view taken along line II-II' shown in FIG.

[0046] 9A to 9H Each layer is schematically shown Figure 4 A plan view of the components of a pixel is shown in FIG.

[0047] Fig.10 A display device according to another embodiment of the present disclosure is shown and corresponds to Figure 4 A cross-sectional view along line II' shown in FIG.

[0048] FIG. 11A to FIG. 11M The manufacturing sequence is shown in Figure 5 A cross-sectional view of a method of displaying a device as shown in FIG.

[0049] Fig.12 It is shown Figure 3C A plan view of the pixel shown in FIG.

[0050] Fig.13 It is along Fig.12 A cross-sectional view taken along line III-III' shown in FIG.

[0051] Fig.14 is corresponding to Figure 2 0 is an enlarged plan view of portion EA shown in , which is a view schematically showing an embodiment in which the first to third switches are provided in the non-display area of ​​the display device. DETAILED DESCRIPTION

[0052] The present disclosure includes various changes and different shapes in addition to those described herein in conjunction with the illustrated exemplary embodiments. Therefore, the present disclosure is not limited to a specific shape, but can be applied to suitable equivalent materials and substitutions.

[0053] It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it may be directly on, directly connected to, or directly coupled to the other element or layer, or there may be one or more intervening elements or layers. When an element or layer is represented as being directly "on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. For example, when a first element is described as being "coupled to" or "connected to" a second element, the first element may be directly coupled to or directly connected to the second element, or the first element may be indirectly coupled to or indirectly connected to the second element via one or more intervening elements.

[0054] Throughout the text, the same number represents the same element. It will be understood that although the terms "first", "second" and the like can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the present disclosure, the "first" element discussed below may also be referred to as the "second" element. As used herein, singular forms, such as "a" and "an" are intended to also include plural forms, unless the context clearly indicates otherwise.

[0055] It will be further understood that when used in this specification, the terms “includes”, “including”, “comprises” and / or “comprising” specify the presence of the features, integers, steps, operations, elements and / or components, but do not exclude the presence and / or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof. In addition, the expression that an element such as a layer, region, substrate or plate is “on” or “over” another element indicates not only an embodiment in which the element is directly “on” or “directly over” the other element, but also an embodiment in which another element is interposed between the element and the other element. The expression that an element such as a layer, region, substrate or plate is “below” or “beneath” another element indicates not only a case in which the element is directly “below” or “directly under” the other element, but also a case in which another element is interposed between the element and the other element.

[0056] The same reference numerals designate the same elements. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items. In addition, the "may" used when describing an embodiment of the present invention represents "one or more embodiments of the present invention". When a statement such as "at least one of" is located after an element of a list, it modifies the elements of the entire list rather than the individual elements in the list. In addition, the term "exemplary" is intended to represent an example or diagram. As used herein, the terms "use", "using" and "used" can be understood as synonyms with the terms "utilize", "utilize" and "utilize" respectively. As used herein, the terms "substantially", "about" and similar terms are used as approximate terms rather than degree terms, and are intended to explain the inherent changes in the measured or calculated values ​​that will be recognized by those of ordinary skill in the art.

[0057] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0058] Figure 1A is a perspective view schematically showing a light emitting element according to an embodiment of the present disclosure, and Figure 1B yes Figure 1A A cross-sectional view of a light emitting element shown in FIG. Figure 1C is a perspective view schematically showing a light emitting element according to another embodiment of the present disclosure, and Figure 1D yes Figure 1C A cross-sectional view of a light emitting element shown in FIG.

[0059] exist Figures 1A to 1D In the figure, for the convenience of description, a light emitting element in the shape of a cylindrical column is shown, but the type and / or shape of the light emitting element according to the present disclosure is not limited thereto.

[0060] Reference Figures 1A to 1D , each of the light emitting elements LD according to the embodiment of the present disclosure may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 disposed between the first semiconductor layer 11 and the second semiconductor layer 13. In an example, the light emitting element LD may have a stacked structure in which the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 are sequentially stacked (or may be implemented in the stacked structure).

[0061] According to an embodiment of the present disclosure, the light emitting element LD may have (for example, may be arranged to be) a strip shape extending in one direction. When the extending direction of the light emitting element LD is the length direction, the light emitting element LD may have one end and the other end along the extending direction. Either (for example, any one) of the first semiconductor layer 11 and the second semiconductor layer 13 may be arranged at one end, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 may be arranged at the other end.

[0062] The light emitting element LD may have a cylindrical column shape, but the present disclosure is not limited thereto. The light emitting element LD may have a rod-like shape or a bar-like shape that is elongated (e.g., extended or substantially extended) in its length direction (e.g., having an aspect ratio greater than 1). For example, the length L of the light emitting element LD in the length direction may be greater than the diameter D (or the width of the cross section) of the light emitting element LD. The light emitting element LD may include, for example, a light emitting diode manufactured to be small enough to have a micrometer-level or nanometer-level diameter D and / or length L (e.g., a diameter D and / or length L in the micrometer-level or nanometer-level).

[0063] In an embodiment of the present disclosure, the diameter D of the light emitting element LD may be in the range of about 0.5 μm to 500 μm, and the length L of the light emitting element LD may be in the range of about 1 μm to 10 μm. However, the size of the light emitting element LD is not limited thereto, and the light emitting element LD may be modified to be suitable according to the needs and / or requirements of the lighting device or self-luminous display device to which the light emitting element LD is to be applied.

[0064] The first semiconductor layer 11 may include, for example, one or more n-type semiconductor layers. For example, the first semiconductor layer 11 may include a semiconductor material among indium aluminum gallium nitride (InAlGaN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may include a semiconductor layer doped with a first conductive dopant such as silicon (Si), germanium (Ge), or tin (Sn). However, the material constituting the first semiconductor layer 11 is not limited thereto. In addition, various suitable materials may be included in the first semiconductor layer 11.

[0065] The active layer 12 is formed on the first semiconductor layer 11 and may be formed to have a single quantum well structure or a multi-quantum well structure. In an embodiment, a capping layer doped with a conductive dopant may be formed on the top and / or bottom of the active layer 12. In an example, the capping layer may be implemented as an aluminum gallium nitride (AlGaN) layer or an indium aluminum gallium nitride (InAlGaN) layer. In some embodiments, a material such as aluminum gallium nitride (AlGaN) or aluminum indium gallium nitride (AlInGaN) may be used to form the active layer 12. In addition, various suitable materials may be included in the active layer 12.

[0066] When an electric field having a reference voltage (e.g., a predetermined voltage) or more is applied to both ends of the light emitting element LD, the light emitting element LD emits light as electron-hole pairs are combined in the active layer 12. By using this principle to control the light emission of the light emitting element LD, the light emitting element LD can be used as a light source for various light emitting devices including pixels (or parts thereof) of a display device.

[0067] The active layer 12 may include a first surface contacting an upper surface of the first semiconductor layer 11 and a second surface contacting a lower surface of the second semiconductor layer 13. The first surface and the second surface may face each other in a length L direction.

[0068] The second semiconductor layer 13 is formed on the second surface of the active layer 12, and may include a semiconductor layer having a type different from that of the first semiconductor layer 11. In an example, the second semiconductor layer 13 may include one or more p-type semiconductor layers. For example, the second semiconductor layer 13 may include one or more semiconductor materials among InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a semiconductor layer doped with a second conductive dopant such as magnesium (Mg). However, the material constituting the second semiconductor layer 13 is not limited thereto. In addition, various suitable materials may be included in the second semiconductor layer 13.

[0069] According to the embodiments of the present disclosure, Figure 1A and Figure 1B As shown in FIG. 1 , in addition to the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 described above, the light emitting element LD may further include an electrode layer 15 disposed on the top of the second semiconductor layer 13. In addition, in some embodiments, as Figure 1C and Figure 1D As shown in , the light emitting element LD may further include another electrode layer (eg, second electrode layer) 16 provided at one end of the first semiconductor layer 11 in addition to the electrode layer (eg, first electrode layer) 15 .

[0070] The electrode layers 15 and 16 may be ohmic contact electrodes, but the present disclosure is not limited thereto. The electrode layers 15 and 16 may include a metal or a metal oxide. For example, the electrode layers 15 and 16 may include one or more of chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), indium tin oxide (ITO), and oxides or alloys thereof, but the present disclosure is not limited thereto.

[0071] The materials included in the respective electrode layers 15 and 16 may be the same as or different from each other. The electrode layers 15 and 16 may be substantially transparent or translucent. Therefore, light generated from the light emitting element LD may be emitted to the outside of the light emitting element LD by being transmitted through the electrode layers 15 and 16.

[0072] In an embodiment of the present disclosure, the light emitting element LD may further include an insulating film 14. However, in some embodiments, the insulating film 14 may be omitted or may be provided to cover only a portion of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0073] The insulating film 14 can prevent or reduce the risk of an electrical short circuit that may occur when the active layer 12 contacts the conductive materials of the first semiconductor layer 11 and the second semiconductor layer 13. In addition, the insulating film 14 is formed so as to reduce or minimize surface defects of the light emitting element LD, thereby improving the life and efficiency of the light emitting element LD. In addition, when a plurality of light emitting elements LD are densely arranged, the insulating film 14 can prevent or reduce the risk of an undesirable short circuit that may occur between the light emitting elements LD. As long as the active layer 12 can be prevented from being short-circuited with an external conductive material, whether the insulating film 14 is provided is not limited.

[0074] like Figure 1A and Figure 1B As shown in , the insulating film 14 may be provided at a portion other than one or both ends of the ends of the light emitting element LD. The insulating film 14 may expose only the electrode layer 15 provided at one end of the second semiconductor layer 13 of the light emitting element LD, and may completely surround other components of the light emitting element LD except the electrode layer 15 (for example, may completely surround the periphery of the other components). The insulating film 14 may expose at least two of the ends of the light emitting element LD. In the example, in addition to the electrode layer 15 provided at one end of the second semiconductor layer 13, the insulating film 14 may also expose one end of the first semiconductor layer 11.

[0075] In certain embodiments, Figure 1C and Figure 1D As shown in , when the electrode layers 15 and 16 are provided at both ends of the light emitting element LD, the insulating film 14 may expose at least one region of each of the electrode layers 15 and 16. In another embodiment, the insulating film 14 may be omitted.

[0076] According to an embodiment of the present disclosure, the insulating film 14 may include a transparent insulating material. For example, the insulating film 14 may include a material selected from silicon oxide (eg, SiO 2 ), silicon nitride (e.g., Si 3 N 4 ), aluminum oxides (e.g., Al 2 O 3 ) and titanium oxides (e.g., TiO 2 ) is one or more insulating materials selected from the group consisting of . However, the present disclosure is not limited thereto, and the insulating film 14 may include various suitable materials having insulating properties.

[0077] When the insulating film 14 is provided in the light emitting element LD, the active layer 12 may not be short-circuited with the first electrode and / or the second electrode. In addition, the insulating film 14 is formed so as to reduce or minimize surface defects of the light emitting element LD, thereby improving the life and efficiency of the light emitting element LD. In addition, when a plurality of light emitting elements LD are densely arranged, the insulating film 14 may prevent or reduce the risk of an undesirable short circuit that may occur between the light emitting elements LD.

[0078] The light-emitting element LD described above can be used as a light source for various display devices. The light-emitting element LD can be manufactured by a surface treatment process. For example, when a plurality of light-emitting elements LD are mixed in a liquid solution (or solvent) to be supplied to each light-emitting region (e.g., the light-emitting region of each sub-pixel), each light-emitting element LD can be surface-treated so that the light-emitting element LD is not unevenly aggregated (or dispersed) in the solution, but is uniformly or substantially uniformly dispersed in the solution.

[0079] The light-emitting device including the light-emitting element LD described above can be used in various suitable types of devices using light sources, including display devices. When a plurality of light-emitting elements LD are arranged in the light-emitting region of each sub-pixel of the display panel, the light-emitting element LD can be used as the light source of each sub-pixel. However, the application field of the light-emitting element LD is not limited to the examples described above. For example, the light-emitting element LD can be used in other suitable types of devices using light sources, such as lighting devices.

[0080] Figure 2 Show use Figure 1A Schematic plan view of a display device according to an embodiment of the present disclosure, in which the light-emitting element shown in FIG. 1 is used as a light-emitting source.

[0081] exist Figure 2 In the figure, for the convenience of illustration, the structure of the display device is briefly shown based on the display area where the image is displayed. However, in some embodiments, a driving circuit (eg, a scan driver and a data driver) and / or a plurality of signal lines may also be provided in the display device.

[0082] Reference Figure 1A and Figure 2 According to an embodiment of the present disclosure, a display device may include a substrate SUB, a plurality of pixels PXL disposed on the substrate SUB and including one or more light emitting elements LD, a driving unit (e.g., a driver) disposed on the substrate SUB and configured to drive the pixels PXL, and a line unit connecting the pixels PXL and the driving unit to each other.

[0083] According to the driving scheme of the light emitting element LD, the display device may be a passive matrix display device or an active matrix display device. In an example, when the display device is an active matrix display device, each of the pixels PXL may include a driving transistor for controlling the amount of current supplied to the light emitting element LD, a switching transistor for transmitting a data signal to the driving transistor, and the like.

[0084] Recently, from the perspective of resolution, contrast, and operating speed, an active matrix display device in which light is selectively emitted for each pixel PXL has become mainstream. However, the present disclosure is not limited thereto, and a passive matrix display device in which light is emitted for each group of pixels PXL may use a component (e.g., a first electrode, a second electrode, etc.) for driving the light emitting element LD.

[0085] The substrate SUB may include a display area DA and a non-display area NDA.

[0086] In some embodiments, the display area DA may be disposed at a central area of ​​the display device, and the non-display area NDA may be disposed at an edge area of ​​the display device to surround the display area DA (e.g., to surround the periphery of the display area DA). However, the positions of the display area DA and the non-display area NDA are not limited thereto and may be appropriately modified.

[0087] The display area DA may be an area where pixels PXL for displaying an image are disposed. The non-display area NDA may be an area where a driving unit for driving the pixels PXL and a portion of a line unit connecting the pixels PXL and the driving unit to each other are disposed.

[0088] The display area DA may have various suitable shapes. For example, the display area DA may have a closed polygonal shape such as a circle, an ellipse, etc. including curved sides, or a semicircle, a semiellipse, etc. including straight sides and curved sides.

[0089] The non-display area NDA may be disposed at at least one side of the display area DA. In an embodiment of the present disclosure, the non-display area NDA may surround the circumference of the display area DA.

[0090] The substrate SUB may include a transparent insulating material so that light can be transmitted therethrough. The substrate SUB may be a rigid substrate. For example, the substrate SUB may be a glass substrate, a quartz substrate, a glass ceramic substrate, and / or a crystal glass substrate.

[0091] In some embodiments, the substrate SUB may be a flexible substrate. In such an embodiment, the substrate SUB may be a film substrate and / or a plastic substrate including a polymer organic material. For example, the substrate SUB may include one or more of polyethylene, polyvinyl alcohol, polymethacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. However, the material constituting the substrate SUB may be changed variously and appropriately, and the substrate SUB may include fiber reinforced plastic (FRP) or the like.

[0092] One area on the substrate SUB may be a display area DA in which the pixels PXL are disposed, and another area on the substrate SUB may be a non-display area NDA. In an example, the substrate SUB may include a display area DA having a pixel area in which the corresponding pixels PXL are disposed and a non-display area NDA disposed at the periphery of the display area DA.

[0093] Each of the pixels PXL may be disposed in the display area DA. In an embodiment of the present disclosure, the pixels PXL may be arranged in the display area DA in a stripe or pentile arrangement structure, but the present disclosure is not limited thereto. For example, the pixels PXL may be arranged in the display area DA in various suitable arrangement structures currently known in the art.

[0094] Each pixel PXL may include a light emitting element LD driven by a corresponding scan signal and a corresponding data signal. The light emitting element LD may have a size as small as a micrometer or nanometer level, and may be connected in parallel with a light emitting element LD disposed adjacent thereto. However, the present disclosure is not limited thereto. The light emitting element LD may be configured as a light source for each pixel PXL.

[0095] Each pixel PXL may include one or more light sources driven by a control signal (e.g., a predetermined control signal, a scan signal, and / or a data signal) and / or a power source (e.g., a predetermined power source, a first driving power source, and / or a second driving power source). Figure 1A The light-emitting element LD according to the embodiment shown in , for example, one or more micro-strip type light-emitting elements LD having a size as small as micrometer level or nanometer level. However, the type of light-emitting element LD that can be used as the light source of the pixel PXL is not limited thereto. For example, in another embodiment, each pixel PXL may include a light-emitting device having a core-shell structure, which is manufactured by using a growth technique. In an embodiment, the light-emitting device having a core-shell structure may be a micro-light-emitting device having a core-shell structure, which has a size as small as micrometer level or nanometer level, but the size of the light-emitting device having a core-shell structure is not limited thereto.

[0096] In an embodiment of the present disclosure, the color, kind and / or number of the pixels PXL are not particularly limited. In an example, the color of light emitted by each pixel PXL may be modified variously and appropriately.

[0097] The driving unit provides a signal to each pixel PXL through the line unit, and thus, can control driving of the pixel PXL.

[0098] The driving unit may include a scan driver for providing a scan signal to the pixel PXL through a scan line, an emission driver for providing an emission control signal to the pixel PXL through an emission control line, a data driver for providing a data signal to the pixel PXL through a data line, and a timing controller. The timing controller may control the scan driver, the emission driver, and the data driver.

[0099] FIG. 3A to FIG. 3D It is a diagram showing various embodiments according to the present disclosure. Figure 2 A circuit diagram showing an electrical connection relationship between components included in one pixel among the pixels shown in FIG.

[0100] For example, FIG. 3A to FIG. 3D The electrical connection relationship between components included in the pixel PXL applicable to the active display device according to different embodiments of the present disclosure is shown. However, the types of components included in the pixel PXL to which the embodiments of the present disclosure are applicable are not limited thereto.

[0101] exist FIG. 3A to FIG. 3D , Pixel PXL comprehensively includes not only Figure 2 In some embodiments, the components included in each of the pixels PXL shown in FIG. 1 and the region where the components are disposed are also included. FIG. 3A to FIG. 3D Each of the pixels PXL shown in FIG. 1 may be arranged Figure 2 The pixels PXL may be any one of the pixels PXL in the display device shown in FIG. 1 , and the pixels PXL may have the same or substantially similar structures to each other.

[0102] Reference Figure 1A , Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3D One pixel PXL (hereinafter, referred to as "pixel") may include a light emitting unit EMU that generates light having brightness corresponding to a data signal. In addition, the pixel PXL may further selectively include a pixel circuit 144 for driving the light emitting unit EMU.

[0103] In some embodiments, the light emitting unit EMU may include a plurality of light emitting elements LD connected in parallel between a first power line PL1 to which a first driving power source VDD is applied and a second power line PL2 to which a second driving power source VSS is applied. For example, the light emitting unit EMU may include a first electrode EL1 (also referred to as a "first alignment electrode") connected to the first driving power source VDD via the pixel circuit 144 and the first power line PL1, a second electrode EL2 (also referred to as a "second alignment electrode") connected to the second driving power source VSS via the second power line PL2, and a plurality of light emitting elements LD connected in parallel between the first electrode EL1 and the second electrode EL2 in the same direction. In an embodiment of the present disclosure, the first electrode EL1 may be an anode electrode, and the second electrode EL2 may be a cathode electrode.

[0104] In an embodiment of the present disclosure, the light emitting unit EMU may include a first conductive line CL1 and a second conductive line CL2. Either of the first conductive line CL1 and the second conductive line CL2 may be an anode electrode, and the other of the first conductive line CL1 and the second conductive line CL2 may be a cathode electrode. In an embodiment of the present disclosure, the second conductive line CL2 may be an anode electrode, and the first conductive line CL1 may be a cathode electrode. The light emitting unit EMU may include a light emitting element LD connected in parallel between the first electrode EL1 and the first conductive line CL1, a light emitting element LD connected in parallel between the first conductive line CL1 and the second conductive line CL2, and a light emitting element LD connected in parallel between the second conductive line CL2 and the second electrode EL2.

[0105] In an embodiment of the present disclosure, each of the light emitting elements LD included in the light emitting unit EMU may have one end connected to the first driving power source VDD through the first electrode EL1 and the other end connected to the second driving power source VSS through the second electrode EL2 .

[0106] As described above, the light emitting elements LD connected in parallel in the same direction between the first electrode EL1 and the first conductive line CL1, between the first conductive line CL1 and the second conductive line CL2, and between the second conductive line CL2 and the second electrode EL2 supplied with different voltages may respectively form effective light sources. The effective light sources may constitute the light emitting unit EMU of the pixel PXL.

[0107] In some embodiments, the first driving power supply VDD and the second driving power supply VSS may have different potentials. In an example, the first driving power supply VDD may be set as a high potential power supply, and the second driving power supply VSS may be set as a low potential power supply. The potential difference between the first driving power supply VDD and the second driving power supply VSS may be set to a threshold voltage of the light emitting element LD during the light emitting period of the pixel PXL or a voltage greater than that.

[0108] The light emitting element LD of the light emitting unit EMU may emit light having a brightness corresponding to the driving current supplied by the corresponding pixel circuit 144. For example, the pixel circuit 144 may supply a driving current corresponding to the grayscale value of the corresponding frame data to the light emitting unit EMU during each frame period. The driving current supplied to the light emitting unit EMU may be shunted to flow through the light emitting elements LD connected in the same direction. Therefore, while each light emitting element LD emits light having a brightness corresponding to the current flowing therethrough, the light emitting unit EMU is able to emit light having a brightness corresponding to the driving current.

[0109] Although FIG. 3A to FIG. 3D , an embodiment in which the light-emitting element LD is connected between the first driving power source VDD and the second driving power source VSS in the same direction (e.g., the forward direction) is shown, but the present disclosure is not limited thereto. In some embodiments, in addition to the light-emitting element LD forming the corresponding effective light source, the light-emitting unit EMU may also include one or more invalid light sources. In the example, the reverse light-emitting element may also be connected between the first electrode EL1 and the second electrode EL2. The reverse light-emitting element is connected in parallel with the light-emitting element LD forming the effective light source between the first electrode EL1 and the second electrode EL2, and may be connected between the first electrode EL1 and the second electrode EL2 in a direction opposite to the direction in which the light-emitting element LD is connected. However, a driving voltage (e.g., a forward driving voltage) is applied between the first electrode EL1 and the second electrode EL2, the reverse light-emitting element remains in an inactive state, and thus, substantially no current flows through the reverse light-emitting element.

[0110] The pixel circuit 144 may be connected to the scan line Si and the data line Dj of the corresponding pixel PXL. In an example, when it is assumed that the pixel PXL is disposed on the i-th (i is a natural number) row and the j-th (j is a natural number) column of the display area DA, the pixel circuit 144 of the pixel PXL may be connected to the i-th scan line Si and the j-th data line Dj of the display area DA. In some embodiments, such as Figure 3A and Figure 3B As shown in FIG. 1 , the pixel circuit 144 may include a first transistor T1 and a second transistor T2 and a first capacitor C1 and a second capacitor C2. However, the structure of the pixel circuit 144 is not limited to Figure 3A and Figure 3B The embodiment shown in .

[0111] A first terminal of a first transistor (e.g., a switching transistor) T1 may be connected to a data line Dj, and a second terminal of the first transistor T1 may be connected to a first node N1. The first terminal and the second terminal of the first transistor T1 are different terminals. For example, when the first terminal is a source electrode, the second terminal may be a drain electrode. In addition, a gate electrode of the first transistor T1 may be connected to a scan line Si.

[0112] The first transistor T1 may be turned on when a scan signal having a voltage (e.g., a low voltage) capable of turning on the first transistor T1 is supplied to electrically connect the data line Dj and the first node N1 to each other. The data signal of the corresponding frame is supplied to the data line Dj. Therefore, the data signal is transferred to the first node N1. The data signal transferred to the first node N1 is charged into the first capacitor C1.

[0113] A first terminal of a second transistor (e.g., a driving transistor) T2 may be connected to a first driving power source VDD, and a second terminal of the second transistor T2 may be electrically connected to a first electrode EL1 of each of the light emitting elements LD. In addition, a gate electrode of the second transistor T2 may be connected to a first node N1. The second transistor T2 controls the amount of driving current supplied to the light emitting element LD corresponding to the voltage of the first node N1.

[0114] One electrode of the first capacitor C1 may be connected to the first driving power source VDD, and the other electrode of the first capacitor C1 may be connected to the first node N1. The first capacitor C1 charges a voltage corresponding to the data signal supplied to the first node N1, and maintains the charged voltage until a data signal of the next frame is supplied.

[0115] One electrode of the second capacitor C2 may be connected to the second node N2, and the other electrode of the second capacitor C2 may be connected to the second power line PL2 to which the second driving power VSS is applied. Therefore, the second capacitor C2 may reduce coupling of the light emitting element LD of the light emitting unit EMU.

[0116] exist Figure 3A and Figure 3B , the pixel circuit 144 is shown to include a first transistor T1 for transmitting a data signal to the inside of the pixel PXL, a first capacitor C1 for storing the data signal, a second transistor T2 for supplying a driving current corresponding to the data signal to the light emitting element LD, and a second capacitor C2 for reducing coupling of the light emitting element LD.

[0117] However, the present disclosure is not limited thereto, and the structure of the pixel circuit 144 may be modified and implemented differently and appropriately. In an example, the pixel circuit 144 may further include one or more transistor elements, such as a transistor element for compensating for the threshold voltage of the second transistor T2, a transistor element for initializing the first node N1, and / or a transistor element for controlling the emission time of the light emitting element LD, or other suitable circuit elements such as a boosting capacitor for boosting the voltage of the first node N1.

[0118] In addition, although Figure 3A and Figure 3B14 shows an embodiment in which all of the transistors (e.g., the first transistor T1 and the second transistor T2) included in the pixel circuit 144 are implemented as P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first transistor T1 and the second transistor T2 included in the pixel circuit 144 may be implemented as an N-type transistor.

[0119] The configuration of the pixel circuit 144 is not limited to Figure 3A and Figure 3B For example, the pixel circuit 144 may be configured according to Figure 3C and Figure 3D The embodiment configuration shown in .

[0120] like Figure 3C and Figure 3D As shown in , the pixel circuit 144 may be connected to the scan line Si and the data line Dj of the pixel PXL. In the example, when it is assumed that the pixel PXL is disposed on the i-th row and the j-th column of the display area DA, the pixel circuit 144 of the corresponding pixel PXL may be connected to the i-th scan line Si and the j-th data line Dj of the display area DA.

[0121] In some embodiments, the pixel circuit 144 may also be connected to one or more other scan lines. For example, the pixel PXL disposed on the i-th row of the display area DA may also be connected to the (i-1)th scan line Si-1 and / or the (i+1)th scan line Si+1. In addition, in some embodiments, in addition to the first driving power supply VDD and the second driving power supply VSS, the pixel circuit 144 may also be connected to a third power supply. For example, the pixel circuit 144 may also be connected to an initialization power supply Vint.

[0122] The pixel circuit 144 may include first to seventh transistors T1 to T7 and first and second capacitors C1 and C2.

[0123] One electrode (e.g., source electrode) of the first transistor (e.g., driving transistor) T1 may be connected to the first driving power source VDD via the fifth transistor T5, and the other electrode (e.g., drain electrode) of the first transistor T1 may be connected to one end of the light emitting element LD via the sixth transistor T6. In addition, the gate electrode of the first transistor T1 may be connected to the first node N1. The first transistor T1 is configured to control the amount of driving current flowing between the first driving power source VDD and the second driving power source VSS via the light emitting element LD corresponding to the voltage of the first node N1.

[0124] The second transistor (e.g., a switching transistor) T2 may be connected between the j-th data line Dj connected to the pixel PXL and the source electrode of the first transistor T1. In addition, the gate electrode of the second transistor T2 may be connected to the i-th scan line Si connected to the pixel PXL. The second transistor T2 may be turned on when a scan signal having a gate-on voltage (e.g., a low voltage) is supplied to the i-th scan line Si to electrically connect the j-th data line Dj to the source electrode of the first transistor T1. Therefore, when the second transistor T2 is turned on, the data signal supplied from the j-th data line Dj is transferred to the first transistor T1.

[0125] The third transistor T3 may be connected between the drain electrode of the first transistor T1 and the first node N1. In addition, the gate electrode of the third transistor T3 may be connected to the i-th scan line Si. The third transistor T3 may be turned on when a scan signal having a gate-on voltage is supplied from the i-th scan line Si to electrically connect the drain electrode of the first transistor T1 and the first node N1 to each other.

[0126] The fourth transistor T4 may be connected between the first node N1 and the initialization power line IPL to which the initialization power supply Vint is applied. In addition, the gate electrode of the fourth transistor T4 may be connected to a previous scan line, for example, the (i-1)th scan line Si-1. The fourth transistor T4 may be turned on when a scan signal having a gate-on voltage is supplied to the (i-1)th scan line Si-1 to transfer the voltage of the initialization power supply Vint to the first node N1. The initialization power supply Vint may have a voltage equal to or less than the lowest voltage of the data signal.

[0127] The fifth transistor T5 may be connected between the first driving power source VDD and the first transistor T1. In addition, the gate electrode of the fifth transistor T5 may be connected to a corresponding emission control line, for example, the i-th emission control line Ei. The fifth transistor T5 may be turned off when an emission control signal having a gate-off voltage is supplied to the i-th emission control line Ei, and may be turned on in other cases.

[0128] The sixth transistor T6 may be connected between the first transistor T1 and one end of the light emitting element LD. In addition, the gate electrode of the sixth transistor T6 may be connected to the i-th emission control line Ei. The sixth transistor T6 may be turned off when an emission control signal having a gate-off voltage is supplied to the i-th emission control line Ei, and may be turned on in other cases.

[0129] The seventh transistor T7 may be connected between one end of the light emitting element LD and the initialization power line IPL. In addition, the gate electrode of the seventh transistor T7 may be connected to any one of the scan lines of the next stage (for example, the (i+1)th scan line Si+1). The seventh transistor T7 may be turned on when a scan signal having a gate-on voltage is supplied to the (i+1)th scan line Si+1 to supply the voltage of the initialization power supply Vint to one end of the light emitting element LD.

[0130] The first capacitor C1 may be connected between the first driving power source VDD and the first node N1. The first capacitor C1 may store a voltage corresponding to a data signal supplied to the first node N1 in each frame period and a threshold voltage of the first transistor T1.

[0131] The second capacitor C2 may be connected between the second node N2 and the second power line PL2. The second capacitor C2 may reduce coupling of the light emitting element LD of the light emitting unit EMU.

[0132] In an embodiment of the present disclosure, the pixel PXL may further include an alignment unit 145 connected between the third power line PL3 to which the ground voltage GND is applied and the second node N2. FIG. 3A to FIG. 3D As shown in FIG. 1 , the alignment unit 145 is a component provided independently of the pixel circuit 144 . However, in other implementations, the alignment unit 145 may be a component substantially included in the pixel circuit 144 .

[0133] like Figure 3A and Figure 3C As shown in FIG. 1 , the alignment unit 145 may include one switch SW and a control signal line CSi for controlling on / off of the switch SW.

[0134] In an embodiment of the present disclosure, the switch SW may be a transistor. The switch SW may include a gate electrode connected to the control signal line CSi, a first terminal connected to the third power line PL3, and a second terminal connected to the second node N2. The switch SW is turned on when a control signal having a voltage (e.g., a low voltage) that enables the switch SW to be turned on is supplied from the control signal line CSi to electrically connect the third power line PL3 and the second node N2 to each other. The ground voltage GND applied to the third power line PL3 may be supplied to the second conductive line CL2 and the first electrode EL1, and the second conductive line CL2 and the first electrode EL1 are connected to the second node N2.

[0135] When the switch SW included in the alignment unit 145 is turned on, an alignment voltage (e.g., AC voltage) may be applied to the second power line PL2. The alignment voltage applied to the second power line PL2 may be transferred to the second electrode EL2 and the first conductive line CL1. When the switch SW is turned on, a ground voltage GND may be applied to each of the first electrode EL1 and the second conductive line CL2, and the alignment voltage may be applied to each of the second electrode EL2 and the first conductive line CL1.

[0136] Due to the ground voltage GND applied to the first electrode EL1 and the alignment voltage applied to the first conductive line CL1, an electric field due to the potential difference between the first electrode EL1 and the first conductive line CL1 may be formed. Due to the alignment voltage applied to the first conductive line CL1 and the ground voltage GND applied to the second conductive line CL2, an electric field due to the potential difference between the first conductive line CL1 and the second conductive line CL2 may be formed. In addition, due to the ground voltage GND applied to the second conductive line CL2 and the alignment voltage applied to the second electrode EL2, an electric field due to the potential difference between the second conductive line CL2 and the second electrode EL2 may be formed.

[0137] In an embodiment of the present disclosure, the switch SW included in the alignment unit 145 may be turned on after the liquid solution mixed with the light emitting element LD is sprayed and / or applied to the corresponding pixel PXL to induce alignment of the light emitting element LD by forming an electric field in the corresponding pixel PXL. After completing the alignment of the light emitting element LD in the corresponding pixel PXL, the switch SW included in the alignment unit 145 may be turned off.

[0138] When the switch SW is turned on, electric fields are formed between the first electrode EL1 and the first conductive line CL1, between the first conductive line CL1 and the second conductive line CL2, and between the second conductive line CL2 and the second electrode EL2. Therefore, the light emitting elements LD can be aligned in the corresponding pixels PXL by the electric fields.

[0139] When the alignment of the light emitting element LD in the pixel PXL is completed, a control signal having a voltage (e.g., a high voltage) capable of turning off the switch SW is supplied from the control signal line CSi to the switch SW to turn off the switch SW. When the switch SW is turned off, the second node N2 and the third power line PL3 can be electrically separated from each other. After the switch SW is turned off, the voltage of the second driving power supply VSS is applied to the second power line PL2.

[0140] The configuration of the alignment unit 145 is not limited to Figure 3A and Figure 3C For example, the alignment unit 145 may be configured according to Figure 3B and Figure 3D The embodiment configuration shown in .

[0141] Reference Figure 3B and Figure 3D , the alignment unit 145 may include first to third switches SW1 to SW3 and a control signal line CSi for controlling on / off of each of the first to third switches SW1 to SW3 .

[0142] When the alignment unit 145 includes the first to third switches SW1 to SW3 , each of the first and second conductive lines CL1 and CL2 of the light emitting unit EMU may be connected to any one of the switches among the first to third switches SW1 to SW3 .

[0143] In an embodiment of the present disclosure, the first to third switches SW1 to SW3 may be implemented with transistors of the same type as the transistors included in the pixel circuit 144. In addition, the first to third switches SW1 to SW3 may be implemented with transistors of the same type to be turned on / off by one control signal (e.g., turned on / off concurrently or simultaneously).

[0144] The first switch SW1 may be connected between the third power line PL3 and the second node N2. The first switch SW1 may be turned on when a control signal having a voltage (e.g., a low voltage) capable of turning on the first switch SW1 is supplied from the control signal line CSi to electrically connect the third power line PL3 and the second node N2 to each other. The ground voltage GND applied to the third power line PL3 may be supplied to the first electrode EL1 connected to the second node N2.

[0145] The second switch SW2 may be connected between the second node N2 and the second conductive line CL2. The second switch SW2 may be turned on concurrently (e.g., simultaneously) when the first switch SW1 is turned on to electrically connect the second conductive line CL2 and the second node N2 to each other. The ground voltage GND applied to the third power line PL3 may be supplied to the second conductive line CL2 connected to the second node N2.

[0146] The third switch SW3 may be connected between the second power line PL2 and the first conductive line CL1. The third switch SW3 may be turned on concurrently (e.g., simultaneously) when the first switch SW1 and the second switch SW2 are turned on to electrically connect the first conductive line CL1 to the second electrode EL2. Since the second electrode EL2 is electrically connected to the second power line PL2, the first conductive line CL1 may be electrically connected to the second power line PL2 when the third switch SW3 is turned on.

[0147] When the first to third switches SW1 to SW3 included in the alignment unit 145 are turned on, the alignment voltage applied to the second power line PL2 may be transferred to the second electrode EL2 and the first conductive line CL1 .

[0148] In an embodiment of the present disclosure, gate electrodes of the first to third switches SW1 to SW3 included in the alignment unit 145 are commonly connected to the control signal line CSi. Therefore, the first to third switches SW1 to SW3 may be turned on concurrently (e.g., simultaneously) when a control signal having a voltage capable of turning on each switch is supplied from the control signal line CSi, and may be turned off concurrently (e.g., simultaneously) when a control signal having a voltage capable of turning off each switch (e.g., a high voltage) is supplied from the control signal line CSi.

[0149] When the first to third switches SW1 to SW3 are turned on, the ground voltage GND may be applied to each of the first electrode EL1 and the second conductive line CL2, and the alignment voltage may be applied to each of the second electrode EL2 and the first conductive line CL1. Therefore, an electric field may be formed by the potential differences between the first electrode EL1 and the first conductive line CL1, between the first conductive line CL1 and the second conductive line CL2, and between the second conductive line CL2 and the second electrode EL2, respectively.

[0150] In an embodiment of the present disclosure, the first to third switches SW1 to SW3 included in the alignment unit 145 may be turned on before the light emitting elements LD are aligned in the corresponding pixels PXL, and may be turned off after the alignment of the light emitting elements LD is completed.

[0151] When the first to third switches SW1 to SW3 are turned on, the light emitting elements LD may be aligned in corresponding pixels PXL by electric fields formed respectively between the first electrode EL1 and the first conductive line CL1 , between the first conductive line CL1 and the second conductive line CL2 , and between the second conductive line CL2 and the second electrode EL2 .

[0152] When alignment of the light emitting element LD in the pixel PXL is completed, a control signal having a voltage capable of turning off the first to third switches SW1 to SW3 is supplied from the control signal line CSi to the first to third switches SW1 to SW3 , turning off the first to third switches SW1 to SW3 .

[0153] When the first switch SW1 is turned off, the second node N2 and the third power line PL3 may be electrically isolated from each other. When the second switch SW2 is turned off, the second conductive line CL2 may be electrically isolated from the second node N2 and the first electrode EL1 to be in a floating state. When the third switch SW3 is turned off, the first conductive line CL1 may be electrically isolated from the second power line PL2 and the second electrode EL2 to be in a floating state. In other words, when the first to third switches SW1 to SW3 included in the alignment unit 145 are turned off, each of the first conductive line CL1 and the second conductive line CL2 may become an electrically insulated floating electrode.

[0154] When the first to third switches SW1 to SW3 are turned off, the voltage of the second driving power source VSS is applied to the second power line PL2 .

[0155] As described above, after the light emitting elements LD are aligned in the pixel PXL and the first to third switches SW1 to SW3 are turned off, the light emitting unit EMU of the corresponding pixel PXL may include the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 connected in series in the forward direction between the first driving power source VDD and the second driving power source VSS to form an effective light source. In an embodiment of the present disclosure, the first light emitting element LD1 may be any one of the light emitting elements LD disposed between the first electrode EL1 and the first conductive line CL1 as a floating electrode, the second light emitting element LD2 may be any one of the light emitting elements LD disposed between the first conductive line CL1 and the second conductive line CL2 as a floating electrode, and the third light emitting element LD3 may be any one of the light emitting elements LD disposed between the second conductive line CL2 and the second electrode EL2.

[0156] In an embodiment of the present disclosure, the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 may be connected in series between the first driving power source VDD and the second driving power source VSS in the forward direction. For example, one end of the first light emitting element LD1 may be connected to the first driving power source VDD through the first electrode EL1, and the other end of the first light emitting element LD1 may be connected to one end of the second light emitting element LD2 through the first conductive line CL1. One end of the second light emitting element LD2 may be connected to the other end of the first light emitting element LD1, and the other end of the second light emitting element LD2 may be connected to one end of the third light emitting element LD3 through the second conductive line CL2. One end of the third light emitting element LD3 may be connected to the other end of the second light emitting element LD2, and the other end of the third light emitting element LD3 may be connected to the second driving power source VSS through the second electrode EL2. In the method described above, the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 may be sequentially connected in series between the first electrode EL1 and the second electrode EL2 of the light emitting unit EMU. For example, each light emitting element LD may be sequentially connected in series via the first electrode EL1, the first conductive line CL1, the second conductive line CL2, and the second electrode EL2.

[0157] As described above, the light emitting unit EMU may be configured to include one or more series stages having a plurality of light emitting elements LD connected in parallel to each other. For example, the light emitting unit EMU may be configured in a series / parallel combination structure.

[0158] The structure of the pixel PXL applicable to the present disclosure is not limited to FIG. 3A to FIG. 3D, and the corresponding pixel PXL may have various suitable structures. In another embodiment of the present disclosure, each pixel PXL may be configured inside a passive light-emitting display device, etc. Therefore, the pixel circuit 144 may be omitted, and both ends of the light-emitting element LD included in the light-emitting unit EMU may be directly connected to the scan lines Si-1, Si and Si+1, the data line Dj, the first power line PL1 to which the first driving power VDD is applied, the second power line PL2 to which the second driving power VSS is applied, and / or the control line.

[0159] In the pixel PXL, the light emitting element LD is aligned in a desired area of ​​the corresponding pixel PXL by using the alignment unit 145, and one or more switches included in the alignment unit 145 are turned off after the light emitting element LD is aligned, so that the corresponding pixel PXL can be driven separately with respect to the adjacent pixel PXL. Therefore, a process of removing a portion of the alignment line to drive one pixel PXL separately with respect to the adjacent pixel PXL, etc. can be omitted, so that the manufacturing process of the display device according to the embodiment of the present disclosure can be simplified.

[0160] Generally, in a display device of the related art, a first alignment voltage is applied to a first electrode EL1 of each pixel PXL through a first alignment line commonly connected to the pixel PXL, and a second alignment voltage different from the first alignment voltage is applied to a second electrode EL2 of each pixel PXL through a second alignment line commonly connected to the pixel PXL. Due to the first alignment voltage applied to the first electrode EL1 of each pixel PXL and the second alignment voltage applied to the second electrode EL2 of each pixel PXL, an electric field is formed between the first electrode EL1 and the second electrode EL2 of each pixel PXL. The light emitting element LD injected and / or applied to each of the pixels PXL is aligned between the first electrode EL1 and the second electrode EL2 of each pixel PXL by the electric field. In order to drive each pixel PXL individually relative to the adjacent pixel PXL after the light emitting element LD is aligned, the first alignment line is cut off in units of each pixel PXL by removing a portion of the first alignment line commonly connected to the pixel PXL, so that the first electrode EL1 of the pixel PXL can be electrically isolated from the first electrode EL1 of each of the adjacent pixels PXL. The first alignment line cut off in units of each pixel PXL is used to drive the light emitting element LD aligned in the pixel PXL.

[0161] The above process of removing a portion of the alignment line in the display device of the related art is performed by, for example, a wet etching process. Some components such as the first electrode EL1 and the second electrode EL2 disposed and / or formed in the pixel PXL may be damaged by an etchant used when performing the wet etching process.

[0162] Therefore, in the embodiment of the present disclosure, each of the pixels PXL is driven individually using the alignment unit 145, so that the components provided in each pixel PXL can be prevented from being damaged by the etchant used in the wet etching process by omitting the process of removing a portion of the alignment line. Therefore, the reliability of the display device according to the embodiment of the present disclosure is improved.

[0163] In addition, in an embodiment of the present disclosure, when the light-emitting unit EMU of the pixel PXL is configured by connecting multiple light-emitting elements LD in a series / parallel combination structure, the driving current / voltage conditions can be more easily adjusted to suit the specifications of the desired product, and the defect rate caused by short circuits can be reduced.

[0164] Figure 4 It is shown Figure 3D A plan view of a pixel shown in FIG. 1 , and Figure 5 It is along Figure 4 A cross-sectional view taken along line II' shown in FIG. Figure 6 is corresponding to Figure 4 A cross-sectional view of the line II' shown in FIG. Figure 5 Another implementation of the first embankment shown in . Figure 7 is corresponding to Figure 4 A cross-sectional view of the line II' shown in FIG. 1 and showing that the capping layer is arranged Figure 5 Implementation scheme between the first electrode and the contact electrode and between the second electrode and the contact electrode shown in . Figure 8 It is along Figure 4 A cross-sectional view taken along line II-II' shown in FIG. 9A to 9H Each layer is schematically shown Figure 4 A plan view of the components of a pixel is shown in FIG.

[0165] exist Figure 4 In the figure, based on a pixel PXL arranged on the i-th row and the j-th column provided in the display area, three scan lines Si-1, Si and Si+1, an emission control line Ei, a first power line PL1 to a third power line PL3, a control signal line CSi, a data line Dj and an initialization power line IPL connected to the pixel PXL are shown.

[0166] exist Figures 4 to 8 , Fig. 9B and Fig.9DIn the figure, for ease of description, the scan line located on the (i-1)th row is referred to as the "(i-1)th scan line Si-1", the scan line located on the i-th row is referred to as the "i-th scan line Si", the scan line located on the (i+1)th row is referred to as the "(i+1)th scan line Si+1", the emission control line located on the i-th row is referred to as the "emission control line Ei", the data line located on the j-th column is referred to as the "data line Dj", the first power line located on the j-th column is referred to as the "first power line PL1", the second power line located on the j-th column is referred to as the "second power line PL2", the third power line located on the j-th column is referred to as the "third power line PL3", and the control signal line located on the i-th row is referred to as the "control signal line CSi".

[0167] In addition, Figures 4 to 8 , the structure of one pixel PXL is simplified by illustrating each electrode as a single electrode layer and each insulating layer as a single insulating layer. However, the present disclosure is not limited thereto.

[0168] Reference Figure 1A , Figure 2 , Figure 3D , Figures 4 to 8 as well as 9A to 9H , a display device according to an embodiment of the present disclosure may include a substrate SUB, a line unit, and one or more pixels PXL.

[0169] The substrate SUB may include a transparent insulating material so that light can be transmitted therethrough. The substrate SUB may be a rigid substrate or a flexible substrate.

[0170] The rigid substrate may include a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystalline glass substrate.

[0171] The flexible substrate may include a film substrate and a plastic substrate having a polymer organic material. For example, the flexible substrate may include one or more of polyethersulfone (PES), polyacrylate (PA), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate (PAR), polyimide (PI), polycarbonate (PC), triacetyl cellulose (TAC), and cellulose acetate propionate (CAP). In addition, the flexible substrate may include fiberglass reinforced plastic (FRP).

[0172] The material applied to the substrate SUB may have resistance (or heat resistance) to high process temperatures in a manufacturing process of the display device. In an embodiment of the present disclosure, all or at least a portion of the substrate SUB may be flexible.

[0173] The line unit may provide signals to pixels PXL disposed in the display area DA, and may include scan lines Si-1, Si and Si+1, data lines Dj, emission control lines Ei, first to third power lines PL1 to PL3, initialization power lines IPL, control signal lines CSi, and first to third shielding electrode lines SDL1 to SDL3.

[0174] The scan lines Si-1, Si, and Si+1 may extend in the first direction DR1. The scan lines Si-1, Si, and Si+1 may include an (i-1)th scan line Si-1, an i-th scan line Si, and an (i+1)th scan line Si+1 sequentially arranged along a second direction DR2 intersecting the first direction DR1. The scan lines Si-1, Si, and Si+1 may be disposed and / or formed on the gate insulating layer GI. The gate insulating layer GI may be an inorganic insulating layer made of (or including) an inorganic material.

[0175] The scan signal may be supplied to the scan lines Si-1, Si, and Si + 1. For example, the (i-1)th scan signal may be supplied to the (i-1)th scan line Si-1, the i-th scan signal may be supplied to the i-th scan line Si, and the (i+1)th scan signal may be supplied to the (i+1)th scan line Si+1.

[0176] The emission control line Ei may extend in the first direction DR1 and may be disposed to be spaced apart from each of the i-th scan line Si and the (i+1)-th scan line Si+1 between the i-th scan line Si and the (i+1)-th scan line Si+1 when viewed on a plane. An emission control signal may be applied to the emission control line Ei. The emission control line Ei may be disposed in the same layer as the scan lines Si-1, Si, and Si+1 and may include the same (or substantially the same) material as the scan lines Si-1, Si, and Si+1. The emission control line Ei may be disposed and / or formed on the gate insulating layer GI.

[0177] The control signal line CSi may extend in the first direction DR1 and may be disposed to be spaced apart from the (i-1)th scan line Si-1 when viewed on a plane. A control signal may be applied to the control signal line CSi. The control signal line CSi may be disposed in the same layer as the scan lines Si-1, Si, and Si+1, and may include the same (or substantially the same) material as the scan lines Si-1, Si, and Si+1. The control signal line CSi may be disposed and / or formed on the gate insulating layer GI.

[0178] The data line Dj may extend in the second direction DR2 and may be arranged along the first direction DR1. A data signal may be applied to the data line Dj. The data line Dj may be disposed and / or formed on the second interlayer insulating layer ILD2. The second interlayer insulating layer ILD2 may be an inorganic insulating layer made of (or including) an inorganic material or an organic insulating layer made of (or including) an organic material.

[0179] The initialization power line IPL may extend along the second direction DR2 and may be disposed to be spaced apart from the data line Dj. An initialization power source Vint may be applied to the initialization power line IPL. The initialization power line IPL may be disposed in the same layer as the data line Dj and may include the same (or substantially the same) material as the data line Dj. The initialization power line IPL may be disposed and / or formed on the second interlayer insulating layer ILD2. However, the present disclosure is not limited thereto. In some embodiments, the initialization power line IPL may be disposed and / or formed on the first interlayer insulating layer ILD1 located between the data line Dj and the scan lines Si-1, Si, and Si+1.

[0180] The first power line PL1 may extend in the second direction DR2 and may be disposed to be spaced apart from the data line Dj. A first driving power source VDD may be applied to the first power line PL1.

[0181] The third power line PL3 may extend in the second direction DR2 and may be disposed to be spaced apart from the first power line PL1. A ground voltage GND may be applied to the third power line PL3.

[0182] In an embodiment of the present disclosure, the first power line PL1 and the third power line PL3 may be disposed in the same layer as the data line Dj and may include the same (or substantially the same) material as the data line Dj. The first power line PL1 and the third power line PL3 may be disposed and / or formed on the second interlayer insulating layer ILD2.

[0183] The second power line PL2 may extend in the second direction DR2 and may be disposed on the first power line PL1 with a third interlayer insulating layer ILD3 interposed therebetween. A second driving power source VSS may be applied to the second power line PL2.

[0184] The first shielding electrode lines SDL1 may extend in the second direction DR2 and may be disposed to be spaced apart from the second power lines PL2 .

[0185] The second shielding electrode lines SDL2 may extend along the second direction DR2 and may be disposed to be spaced apart from the first shielding electrode lines SDL1 .

[0186] The third shielding electrode lines SDL3 may extend along the second direction DR2 and may be disposed to be spaced apart from the second shielding electrode lines SDL2.

[0187] In an embodiment of the present disclosure, the first shielding electrode line SDL1, the second shielding electrode line SDL2, and the third shielding electrode line SDL3 may be disposed in the same layer as the second power line PL2, and may include the same (or substantially the same) material as the second power line PL2. The first shielding electrode line SDL1, the second shielding electrode line SDL2, and the third shielding electrode line SDL3 may be disposed and / or formed on the third interlayer insulating layer ILD3.

[0188] The pixel PXL may include a display element layer DPL having one or more light emitting elements LD and a pixel circuit layer PCL driving the light emitting elements LD.

[0189] The pixel circuit layer PCL may include an alignment unit 145 for aligning the light emitting element LD in the light emitting area EMA of the pixel PXL, a pixel circuit 144 for driving the light emitting element LD, and a protection layer PSV covering the alignment unit 145 and the pixel circuit 144 .

[0190] The display element layer DPL may include a light emitting element LD, first and second electrodes EL1 and EL2 , first and second conductive lines CL1 and CL2 , a contact electrode CNE, and the like.

[0191] For convenience of description, the display element layer DPL will be described after describing the pixel circuit layer PCL.

[0192] The pixel circuit 144 may include first to seventh transistors T1 to T7 and first and second capacitors C1 and C2. The alignment unit 145 may include first to third switches SW1 to SW3.

[0193] The pixel circuit 144 and the alignment unit 145 may be disposed (or formed) on the substrate SUB with the buffer layer BFL interposed therebetween.

[0194] The buffer layer BFL may prevent or substantially prevent impurities from diffusing into each of the first to seventh transistors T1 to T7 and the first to third switches SW1 to SW3. The buffer layer BFL may be provided as a single layer, but in other embodiments, the buffer layer BFL may have a multilayer structure including a plurality of layers. When the buffer layer BFL has a multilayer structure, the layers may be formed of the same (or substantially the same) material or may be formed of different materials. The buffer layer BFL may be omitted according to the material of the substrate SUB and process conditions.

[0195] The first transistor T1 may include a first gate electrode GE1 , a first active pattern ACT1 , a first source electrode SE1 , a first drain electrode DE1 , and a first connection electrode CNL1 .

[0196] The first gate electrode GE1 may be connected to the 3a-th drain electrode DE3a of the 3a-th transistor T3a and the 4b-th drain electrode DE4b of the 4b-th transistor T4b.

[0197] One end of the first connection electrode CNL1 may be connected to each of the 3a-th drain electrode DE3a and the 4b-th drain electrode DE4b through a first contact opening (e.g., a first contact hole) CH1 penetrating the gate insulating layer GI and the first and second interlayer insulating layers ILD1 and ILD2. The other end of the first connection electrode CNL1 may be connected to the first gate electrode GE1 through a second contact opening (e.g., a second contact hole) CH2 penetrating the first and second interlayer insulating layers ILD1 and ILD2.

[0198] The first active pattern ACT1, the first source electrode SE1, and the first drain electrode DE1 may be formed of a semiconductor layer not doped with impurities or doped with impurities. For example, the first source electrode SE1 and the first drain electrode DE1 may be formed of a semiconductor layer doped with impurities, and the first active pattern ACT1 may be formed of a semiconductor layer not doped (or undoped) with impurities.

[0199] The first active pattern ACT1 may have a strip shape extending in one direction and may have a shape that is bent multiple times along the extending direction. When viewed on a plane, the first active pattern ACT1 may overlap with the first gate electrode GE1. The first active pattern ACT1 is formed into an elongated shape (e.g., having an extended shape), so that the channel region of the first transistor T1 can be formed into an elongated shape (e.g., may have an extended shape). Therefore, the driving range of the gate voltage applied to the first transistor T1 is widened (or increased). Therefore, the grayscale of the light emitted from the light emitting element LD can be finely controlled.

[0200] The first source electrode SE1 may be connected to one end of the first active pattern ACT1. In addition, the first source electrode SE1 may be connected to the second drain electrode DE2 of the second transistor T2 and the fifth drain electrode DE5 of the fifth transistor T5. The first drain electrode DE1 may be connected to the other end of the first active pattern ACT1. In addition, the first drain electrode DE1 may be connected to the 3a source electrode SE3a of the 3a transistor T3a and the sixth source electrode SE6 of the sixth transistor T6.

[0201] The second transistor T2 may include a second gate electrode GE2 , a second active pattern ACT2 , a second source electrode SE2 , and a second drain electrode DE2 .

[0202] The second gate electrode GE2 may be connected to the i-th scan line Si. The second gate electrode GE2 may be a portion of the i-th scan line Si or may have a shape protruding from the i-th scan line Si.

[0203] The second active pattern ACT2, the second source electrode SE2, and the second drain electrode DE2 may be formed of a semiconductor layer that is not doped (e.g., undoped) with impurities or doped with impurities. For example, the second source electrode SE2 and the second drain electrode DE2 may be formed of a semiconductor layer doped with impurities, and the second active pattern ACT2 may be formed of a semiconductor layer that is not doped (or undoped) with impurities.

[0204] The second active pattern ACT2 corresponds to a portion overlapping the second gate electrode GE2. One end of the second source electrode SE2 is connected to the second active pattern ACT2, and the other end of the second source electrode SE2 is connected to the j-th data line Dj through a fifth contact opening (e.g., a fifth contact hole) CH5 penetrating the gate insulating layer GI and the first and second interlayer insulating layers ILD1 and ILD2. One end of the second drain electrode DE2 is connected to the second active pattern ACT2, and the other end of the second drain electrode DE2 is connected to the first source electrode SE1 of the first transistor T1 and the fifth drain electrode DE5 of the fifth transistor T5.

[0205] The third transistor T3 may have a double gate structure to prevent or reduce leakage current. For example, the third transistor T3 may include a 3a-th transistor T3a and a 3b-th transistor T3b.

[0206] The 3ath transistor T3a may include a 3ath gate electrode GE3a, a 3ath active pattern ACT3a, a 3ath source electrode SE3a, and a 3ath drain electrode DE3a. The 3bth transistor T3b may include a 3bth gate electrode GE3b, a 3bth active pattern ACT3b, a 3bth source electrode SE3b, and a 3bth drain electrode DE3b.

[0207] Each of the 3a-th gate electrode GE3a and the 3b-th gate electrode GE3b may be connected to the i-th scan line Si. Each of the 3a-th gate electrode GE3a and the 3b-th gate electrode GE3b may be a portion of the i-th scan line Si or may be in a shape protruding from the i-th scan line Si.

[0208] Each of the 3a-th active pattern ACT3a and the 3b-th active pattern ACT3b, the 3a-th source electrode SE3a and the 3b-th source electrode SE3b, and the 3a-th drain electrode DE3a and the 3b-th drain electrode DE3b may be formed of a semiconductor layer doped with impurities or undoped with impurities. For example, each of the 3a-th source electrode SE3a and the 3b-th source electrode SE3b and the 3a-th drain electrode DE3a and the 3b-th drain electrode DE3b may be formed of a semiconductor layer doped with impurities, and each of the 3a-th active pattern ACT3a and the 3b-th active pattern ACT3b may be formed of a semiconductor layer undoped with impurities. The 3a-th active pattern ACT3a corresponds to a portion overlapping with the 3a-th gate electrode GE3a, and the 3b-th active pattern ACT3b corresponds to a portion overlapping with the 3b-th gate electrode GE3b.

[0209] One end of the 3a source electrode SE3a may be connected to the 3a active pattern ACT3a, and the other end of the 3a source electrode SE3a may be connected to the first drain electrode DE1 of the first transistor T1 and the sixth source electrode SE6 of the sixth transistor T6. One end of the 3a drain electrode DE3a may be connected to the 3a active pattern ACT3a, and the other end of the 3a drain electrode DE3a may be connected to the 3b source electrode SE3b of the 3b transistor T3b.

[0210] One end of the 3b-th source electrode SE3b may be connected to the 3b-th active pattern ACT3b, and the other end of the 3b-th source electrode SE3b may be connected to the 3a-th drain electrode DE3a of the 3a-th transistor T3a. One end of the 3b-th drain electrode DE3b may be connected to the 3b-th active pattern ACT3b, and the other end of the 3b-th drain electrode DE3b may be connected to the 4b-th drain electrode DE4b of the 4b-th transistor T4b. In addition, the other end of the 3b-th drain electrode DE3b may be connected to the first gate electrode GE1 via the first and second contact openings CH1 and CH2 and the first connection electrode CNL1.

[0211] Similar to the third transistor T3, the fourth transistor T4 may have a dual gate structure to prevent or reduce leakage current. For example, the fourth transistor T4 may include a 4a-th transistor T4a and a 4b-th transistor T4b.

[0212] The 4ath transistor T4a may include a 4ath gate electrode GE4a, a 4ath active pattern ACT4a, a 4ath source electrode SE4a, and a 4ath drain electrode DE4a. The 4bth transistor T4b may include a 4bth gate electrode GE4b, a 4bth active pattern ACT4b, a 4bth source electrode SE4b, and a 4bth drain electrode DE4b.

[0213] Each of the 4a-th gate electrode GE4a and the 4b-th gate electrode GE4b may be connected to the (i-1)th scan line Si-1. Each of the 4a-th gate electrode GE4a and the 4b-th gate electrode GE4b may be a portion of the (i-1)th scan line Si-1 or may be in a shape protruding from the (i-1)th scan line Si-1.

[0214] Each of the 4a-th active pattern ACT4a and the 4b-th active pattern ACT4b, the 4a-th source electrode SE4a and the 4b-th source electrode SE4b, and the 4a-th drain electrode DE4a and the 4b-th drain electrode DE4b may be formed of a semiconductor layer doped with impurities or undoped with impurities. For example, each of the 4a-th source electrode SE4a and the 4b-th source electrode SE4b and the 4a-th drain electrode DE4a and the 4b-th drain electrode DE4b may be formed of a semiconductor layer doped with impurities, and each of the 4a-th active pattern ACT4a and the 4b-th active pattern ACT4b may be formed of a semiconductor layer undoped with impurities. The 4a-th active pattern ACT4a corresponds to a portion overlapping with the 4a-th gate electrode GE4a, and the 4b-th active pattern ACT4b corresponds to a portion overlapping with the 4b-th gate electrode GE4b.

[0215] One end of the 4a source electrode SE4a may be connected to the 4a active pattern ACT4a, and the other end of the 4a source electrode SE4a may be connected to the initialization power line IPL through a sixth contact opening (e.g., a sixth contact hole) CH6 penetrating the gate insulating layer GI and the first and second interlayer insulating layers ILD1 and ILD2. One end of the 4a drain electrode DE4a may be connected to the 4a active pattern ACT4a, and the other end of the 4a drain electrode DE4a may be connected to the 4b source electrode SE4b of the 4b transistor T4b.

[0216] One end of the 4b-th source electrode SE4b may be connected to the 4b-th active pattern ACT4b, and the other end of the 4b-th source electrode SE4b may be connected to the 4a-th drain electrode DE4a of the 4a-th transistor T4a. One end of the 4b-th drain electrode DE4b may be connected to the 4b-th active pattern ACT4b, and the other end of the 4b-th drain electrode DE4b may be connected to the 3b-th drain electrode DE3b of the 3b-th transistor T3b. In addition, the other end of the 4b-th drain electrode DE4b may be connected to the first gate electrode GE1 of the first transistor T1 through the first and second contact openings CH1 and CH2 and the first connection electrode CNL1.

[0217] The fifth transistor T5 may include a fifth gate electrode GE5 , a fifth active pattern ACT5 , a fifth source electrode SE5 , and a fifth drain electrode DE5 .

[0218] The fifth gate electrode GE5 may be connected to the emission control line Ei. The fifth gate electrode GE5 may be a portion of the emission control line Ei or may be in a shape protruding from the emission control line Ei.

[0219] The fifth active pattern ACT5, the fifth source electrode SE5, and the fifth drain electrode DE5 may be formed of a semiconductor layer not doped with impurities or doped with impurities. In one example, the fifth source electrode SE5 and the fifth drain electrode DE5 may be formed of a semiconductor layer doped with impurities, and the fifth active pattern ACT5 may be formed of a semiconductor layer not doped with impurities.

[0220] The fifth active pattern ACT5 may correspond to a portion overlapping the fifth gate electrode GE5 .

[0221] One end of the fifth source electrode SE5 may be connected to the fifth active pattern ACT5, and the other end of the fifth source electrode SE5 may be connected to the first power line PL1 through a fourth contact opening (e.g., a fourth contact hole) CH4 penetrating the gate insulating layer GI and the first and second interlayer insulating layers ILD1 and ILD2. One end of the fifth drain electrode DE5 may be connected to the fifth active pattern ACT5, and the other end of the fifth drain electrode DE5 may be connected to the first source electrode SE1 of the first transistor T1 and the second drain electrode DE2 of the second transistor T2.

[0222] The sixth transistor T6 may include a sixth gate electrode GE6 , a sixth active pattern ACT6 , a sixth source electrode SE6 , and a sixth drain electrode DE6 .

[0223] The sixth gate electrode GE6 may be connected to the emission control line Ei. The sixth gate electrode GE6 may be a portion of the emission control line Ei or may be in a shape protruding from the emission control line Ei.

[0224] The sixth active pattern ACT6, the sixth source electrode SE6, and the sixth drain electrode DE6 may be formed of a semiconductor layer not doped with impurities or doped with impurities. For example, the sixth source electrode SE6 and the sixth drain electrode DE6 may be formed of a semiconductor layer doped with impurities, and the sixth active pattern ACT6 may be formed of a semiconductor layer not doped with impurities.

[0225] The sixth active pattern ACT6 may correspond to a portion overlapping the sixth gate electrode GE6 .

[0226] One end of the sixth source electrode SE6 may be connected to the sixth active pattern ACT6, and the other end of the sixth source electrode SE6 may be connected to the first drain electrode DE1 of the first transistor T1 and the 3a source electrode SE3a of the 3a transistor T3a. One end of the sixth drain electrode DE6 may be connected to the sixth active pattern ACT6, and the other end of the sixth drain electrode DE6 may be connected to the second connection electrode CNL2 through the seventh contact opening CH7 penetrating the gate insulating layer GI and the first and second interlayer insulating layers ILD1 and ILD2.

[0227] One end of the second connection electrode CNL2 can be connected to the sixth drain electrode DE6 of the sixth transistor T6 through a seventh contact opening (for example, a seventh contact hole) CH7 that penetrates the gate insulating layer GI and the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2, and the other end of the second connection electrode CNL2 can be connected to the extension electrode ETP through an eighth contact opening (for example, an eighth contact hole) CH8 that penetrates the third interlayer insulating layer ILD3.

[0228] The extension electrode ETP may be disposed on the second connection electrode CNL2, and the third interlayer insulating layer ILD3 is interposed between the extension electrode ETP and the second connection electrode CNL2. One end of the extension electrode ETP may be connected to the second connection electrode CNL2 through the eighth contact opening CH8, and the other end of the extension electrode ETP may be connected to the second protruding electrode PRP2 through the twenty-second contact opening (twenty-second contact hole) CH22 penetrating the protection layer PSV.

[0229] The seventh transistor T7 may include a seventh gate electrode GE7 , a seventh active pattern ACT7 , a seventh source electrode SE7 , and a seventh drain electrode DE7 .

[0230] The seventh gate electrode GE7 may be connected to the (i+1)th scan line Si+1. The seventh gate electrode GE7 may be a portion of the (i+1)th scan line Si+1 or may have a shape protruding from the (i+1)th scan line Si+1.

[0231] The seventh active pattern ACT7, the seventh source electrode SE7, and the seventh drain electrode DE7 may be formed of a semiconductor layer not doped with impurities or doped with impurities. For example, the seventh source electrode SE7 and the seventh drain electrode DE7 may be formed of a semiconductor layer doped with impurities, and the seventh active pattern ACT7 may be formed of a semiconductor layer not doped with impurities.

[0232] The seventh active pattern ACT7 may correspond to a portion overlapping the seventh gate electrode GE7 .

[0233] One end of the seventh source electrode SE7 may be connected to the seventh active pattern ACT7 , and the other end of the seventh source electrode SE7 may be connected to the sixth drain electrode DE6 of the sixth transistor T6 .

[0234] One end of the seventh drain electrode DE7 may be connected to the seventh active pattern ACT7, and the other end of the seventh drain electrode DE7 may be electrically connected to the initialization power line IPL connected to the pixels on the (i+1)th row through a contact opening (e.g., a contact hole). Therefore, the other end of the seventh drain electrode DE7 may be connected to the 4a-th source electrode of the fourth transistor of the pixel disposed on the (i+1)th row.

[0235] The first capacitor C1 may include a first lower electrode LE1 and a first upper electrode UE1.

[0236] The first lower electrode LE1 may be integrally disposed with (eg, formed integrally with) the first gate electrode GE1 of the first transistor T1. When the first lower electrode LE1 is integrally disposed with the first gate electrode GE1, the first lower electrode LE1 may be a portion of the first gate electrode GE1.

[0237] The first upper electrode UE1 may overlap with the first lower electrode LE1. When viewed on a plane, the first upper electrode UE1 may cover the first lower electrode LE1. The overlapping area of ​​the first upper electrode UE1 and the first lower electrode LE1 may be widened so that the capacitance of the first capacitor C1 may increase. The first upper electrode UE1 may be electrically connected to the first power line PL1 through a third contact opening (e.g., a third contact hole) CH3 penetrating the second interlayer insulating layer ILD2. Therefore, the first driving power VDD applied to the first power line PL1 may be transferred to the first upper electrode UE1. The first upper electrode UE1 may include an opening OPN corresponding to a region where the second contact opening CH2 is formed, wherein the first gate electrode GE1 of the first transistor T1 and the first connection electrode CNL1 are connected through the second contact opening CH2.

[0238] The second capacitor C2 may include a second lower electrode LE2 and a second upper electrode UE2.

[0239] When viewed on a plane, the second lower electrode LE2 may be positioned between the emission control line Ei and the (i+1)th scan line Si+1, and may be disposed on the same plane as the first lower electrode LE1. The second lower electrode LE2 may be connected to the third connection electrode CNL3 through a twenty-sixth contact opening (e.g., a twenty-sixth contact hole) CH26 penetrating the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2.

[0240] One end of the third connection electrode CNL3 may be connected to the second power line PL2 through a twenty-first contact opening (e.g., a twenty-first contact hole) CH21 penetrating the third interlayer insulating layer ILD3, and the other end of the third connection electrode CNL3 may be electrically connected to the second lower electrode LE2 through a twenty-sixth contact opening CH26. Since the third connection electrode CNL3 is connected to the second power line PL2, the second driving power VSS applied to the second power line PL2 may be transferred to the second lower electrode LE2 through the third connection electrode CNL3.

[0241] When viewed on a plane, the second upper electrode UE2 may overlap with the second lower electrode LE2 and may cover the second lower electrode LE2. The overlapping area of ​​the second upper electrode UE2 and the second lower electrode LE2 may be widened so that the capacitance of the second capacitor C2 may be increased. The second upper electrode UE2 may be connected to the second connection electrode CNL2 through a ninth contact opening (e.g., a ninth contact hole) CH9 penetrating the second interlayer insulating layer ILD2.

[0242] Next, components included in the alignment unit 145 according to an embodiment of the present disclosure will be further described.

[0243] The alignment unit 145 may include a first switch SW1, a second switch SW2, and a third switch SW3. In an embodiment of the present disclosure, the first switch SW1, the second switch SW2, and the third switch SW3 included in the alignment unit 145 may be configured as the same type as the type of the switching element (e.g., transistor). In addition, the first switch SW1, the second switch SW2, and the third switch SW3 may be configured as transistors of the same type as the first transistor T1 to the seventh transistor T7 included in the pixel circuit 144 (e.g., P-type transistors).

[0244] The first switch SW1 may include a (1-1)th terminal SW1_1 , a (1-2)th terminal SW1_2 , a first switch gate electrode GE_SW1 , and a first switch active pattern ACT_SW1 .

[0245] The first switch active pattern ACT_SW1, the (1-1)th terminal SW1_1, and the (1-2)th terminal SW1_2 may be formed of a semiconductor layer that is not doped with impurities or is doped with impurities. For example, the (1-1)th terminal SW1_1 and the (1-2)th terminal SW1_2 may be formed of a semiconductor layer doped with impurities, and the first switch active pattern ACT_SW1 may be formed of a semiconductor layer that is not doped with impurities (e.g., an undoped semiconductor layer).

[0246] The first switch gate electrode GE_SW1 may be connected to the control signal line CSi. The first switch gate electrode GE_SW1 may be a portion of the control signal line CSi or may be in a shape protruding from the control signal line CSi.

[0247] When viewed on a plane, the first switching active pattern ACT_SW1 may extend along the second direction DR2 and may overlap the first switching gate electrode GE_SW1 .

[0248] One end of the (1-1)th terminal SW1_1 may be connected to the first switch active pattern ACT_SW1, and the other end of the (1-1)th terminal SW1_1 may be connected to the first protruding electrode PRP1 through a thirteenth contact opening (e.g., a thirteenth contact hole) CH13 penetrating the gate insulating layer GI and the first and second interlayer insulating layers ILD1 and ILD2. One end of the (1-2)th terminal SW1_2 may be connected to the first switch active pattern ACT_SW1, and the other end of the (1-2)th terminal SW1_2 may be connected to the first bridge pattern BRP1 through a twenty-third contact opening (e.g., a twenty-third contact hole) CH23 penetrating the gate insulating layer GI and the first and second interlayer insulating layers ILD1 and ILD2.

[0249] In an embodiment of the present disclosure, when the first switch SW1 is a transistor, either one of the (1-1)th terminal SW1_1 and the (1-2)th terminal SW1_2 may be a source electrode, and the other one of the (1-1)th terminal SW1_1 and the (1-2)th terminal SW1_2 may be a drain electrode.

[0250] The first protruding electrode PRP1 may have a shape protruding from the third power line PL3 along the first direction DR1 and may be formed (or disposed) integrally with the third power line PL3. For example, the first protruding electrode PRP1 may be a part of the third power line PL3. Therefore, the other end of the (1-1)th terminal SW1_1 may be connected to the third power line PL3 through the first protruding electrode PRP1.

[0251] One end of the first bridge pattern BRP1 can be connected to the (1-2) terminal SW1_2 of the first switch SW1 through the twenty-third contact opening CH23, and the other end of the first bridge pattern BRP1 can be connected to the third shielding electrode line SDL3 through the fifteenth contact opening (e.g., the fifteenth contact hole) CH15 penetrating the third interlayer insulating layer ILD3.

[0252] The third shielding electrode line SDL3 may be connected to the first bridge pattern BRP1 through a fifteenth contact opening CH15. In addition, the third shielding electrode line SDL3 may be connected to the first electrode EL1 of the display element layer DPL through a sixteenth contact opening (e.g., a sixteenth contact hole) CH16 penetrating the protective layer PSV. The first electrode EL1 may be disposed and / or formed on the third shielding electrode line SDL3, and the protective layer PSV is interposed between the first electrode EL1 and the third shielding electrode line SDL3. Therefore, when viewed on a plane, the first electrode EL1 may overlap with the third shielding electrode line SDL3.

[0253] In an embodiment of the present disclosure, a third shielding electrode line SDL3 may be disposed on a third interlayer insulating layer ILD3 to prevent the alignment and / or driving of the light-emitting element LD from being affected (or substantially affected) by an electric field induced by components included in the pixel circuit 144 (such as the first transistor T1 to the seventh transistor T7, etc.).

[0254] In an embodiment of the present disclosure, the third shielding electrode line SDL3 may include an extension electrode ETP extending in the first direction DR1. The extension electrode ETP may be provided in the same layer as the third shielding electrode line SDL3, and may include the same (or substantially the same) material as the third shielding electrode line SDL3. For example, the extension electrode ETP and the third shielding electrode line SDL3 may be integrally formed to be electrically and / or physically connected to each other. When the extension electrode ETP and the third shielding electrode line SDL3 are integrally provided and / or formed, the extension electrode ETP may be a region of the third shielding electrode line SDL3.

[0255] The second switch SW2 may include a (2-1)th terminal SW2_1 , a (2-2)th terminal SW2_2 , a second switch gate electrode GE_SW2 , and a second switch active pattern ACT_SW2 .

[0256] In an embodiment of the present disclosure, when the second switch SW2 is a transistor, either one of the (2-1)th terminal SW2_1 and the (2-2)th terminal SW2_2 may be a source electrode, and the other one of the (2-1)th terminal SW2_1 and the (2-2)th terminal SW2_2 may be a drain electrode.

[0257] The second switch active pattern ACT_SW2, the (2-1)th terminal SW2_1, and the (2-2)th terminal SW2_2 may be formed of a semiconductor layer that is not doped with impurities or is doped with impurities. For example, the (2-1)th terminal SW2_1 and the (2-2)th terminal SW2_2 may be formed of a semiconductor layer doped with impurities, and the second switch active pattern ACT_SW2 may be formed of a semiconductor layer that is not doped with impurities.

[0258] The second switch gate electrode GE_SW2 may be connected to the control signal line CSi. The second switch gate electrode GE_SW2 may be a portion of the control signal line CSi or may be in a shape protruding from the control signal line CSi.

[0259] When viewed on a plane, the second switching active pattern ACT_SW2 may extend along the second direction DR2 and may overlap the second switching gate electrode GE_SW2.

[0260] One end of the (2-1)th terminal SW2_1 may be connected to the second switch active pattern ACT_SW2, and the other end of the (2-1)th terminal SW2_1 may be connected to the first protruding electrode PRP1 through a fourteenth contact opening (e.g., a fourteenth contact hole) CH14 penetrating the gate insulating layer GI and the first and second interlayer insulating layers ILD1 and ILD2. One end of the (2-2)th terminal SW2_2 may be connected to the second switch active pattern ACT_SW2, and the other end of the (2-2)th terminal SW2_2 may be connected to the second bridge pattern BRP2 through a twenty-fourth contact opening (e.g., a twenty-fourth contact hole) CH24 penetrating the gate insulating layer GI and the first and second interlayer insulating layers ILD1 and ILD2.

[0261] One end of the second bridge pattern BRP2 may be connected to the (2-2)th terminal SW2_2 through the twenty-fourth contact opening CH24 , and the other end of the second bridge pattern BRP2 may be connected to the first shielding electrode line SDL1 through the seventeenth contact opening (eg, seventeenth contact hole) CH17 penetrating the third interlayer insulating layer ILD3 .

[0262] The first shielding electrode line SDL1 may be connected to the second bridge pattern BRP2 through the seventeenth contact opening CH17. In addition, the first shielding electrode line SDL1 may be connected to the second conductive line CL2 of the display element layer DPL through the eighteenth contact opening (e.g., the eighteenth contact hole) CH18 penetrating the protective layer PSV. The second conductive line CL2 may be disposed and / or formed on the first shielding electrode line SDL1, and the protective layer PSV is interposed between the second conductive line CL2 and the first shielding electrode line SDL1. Therefore, when viewed on a plane, the second conductive line CL2 may overlap with the first shielding electrode line SDL1.

[0263] Similar to the third shielding electrode line SDL3 , the first shielding electrode line SDL1 may be disposed on the third interlayer insulating layer ILD3 to prevent alignment and / or driving of the light emitting element LD from being (or substantially) affected by an electric field induced by components included in the pixel circuit 144 .

[0264] The third switch SW3 may include a (3-1)th terminal SW3_1 , a (3-2)th terminal SW3_2 , a third switch gate electrode GE_SW3 , and a third switch active pattern ACT_SW3 .

[0265] In an embodiment of the present disclosure, when the third switch SW3 is a transistor, either one of the (3-1)th terminal SW3_1 and the (3-2)th terminal SW3_2 may be a source electrode, and the other one of the (3-1)th terminal SW3_1 and the (3-2)th terminal SW3_2 may be a drain electrode.

[0266] The third switch active pattern ACT_SW3, the (3-1)th terminal SW3_1, and the (3-2)th terminal SW3_2 may be formed of a semiconductor layer that is not doped with impurities or is doped with impurities. For example, the (3-1)th terminal SW3_1 and the (3-2)th terminal SW3_2 may be formed of a semiconductor layer doped with impurities, and the third switch active pattern ACT_SW3 may be formed of a semiconductor layer that is not doped with impurities.

[0267] The third switch gate electrode GE_SW3 may be connected to the control signal line CSi. The third switch gate electrode GE_SW3 may be a portion of the control signal line CSi or may be in a shape protruding from the control signal line CSi.

[0268] When viewed on a plane, the third switching active pattern ACT_SW3 may extend along the second direction DR2 and may overlap the third switching gate electrode GE_SW3 .

[0269] One end of the (3-1)th terminal SW3_1 may be connected to the third switch active pattern ACT_SW3, and the other end of the (3-1)th terminal SW3_1 may be connected to the fourth bridge pattern BRP4 through a twelfth contact opening (e.g., a twelfth contact hole) CH12 penetrating the gate insulating layer GI and the first and second interlayer insulating layers ILD1 and ILD2. One end of the (3-2)th terminal SW3_2 may be connected to the third switch active pattern ACT_SW3, and the other end of the (3-2)th terminal SW3_2 may be connected to the third bridge pattern BRP3 through a twenty-fifth contact opening (e.g., a twenty-fifth contact hole) CH25 penetrating the gate insulating layer GI and the first and second interlayer insulating layers ILD1 and ILD2.

[0270] One end of the third bridge pattern BRP3 can be connected to the (3-2)th terminal SW3_2 through the twenty-fifth contact opening CH25, and the other end of the third bridge pattern BRP3 can be connected to the second shielding electrode line SDL2 through the nineteenth contact opening (e.g., the nineteenth contact hole) CH19 penetrating the third interlayer insulating layer ILD3.

[0271] When viewed on a plane, the second shielding electrode line SDL2 may be disposed between the first shielding electrode line SDL1 and the third shielding electrode line SDL3, and spaced apart from each of the first shielding electrode line SDL1 and the third shielding electrode line SDL3. The second shielding electrode line SDL2 may be connected to the third bridging pattern BRP3 through the nineteenth contact opening CH19. In addition, the second shielding electrode line SDL2 may be connected to the first conductive line CL1 of the display element layer DPL through the twentieth contact opening (e.g., the twentieth contact hole) CH20 penetrating the protective layer PSV. The first conductive line CL1 may be disposed and / or formed on the second shielding electrode line SDL2, and the protective layer PSV is interposed between the first conductive line CL1 and the second shielding electrode line SDL2. Therefore, when viewed on a plane, the first conductive line CL1 may overlap with the second shielding electrode line SDL2.

[0272] Similar to the first shielding electrode line SDL1 and the third shielding electrode line SDL3, the second shielding electrode line SDL2 may be disposed on the third interlayer insulating layer ILD3 to prevent alignment and / or driving of the light emitting element LD from being affected (or substantially affected) by an electric field induced by components included in the pixel circuit 144.

[0273] The fourth bridge pattern BRP4 may have a shape extending along the first direction DR1. One end of the fourth bridge pattern BRP4 may be connected to the (3-1)th terminal SW3_1 through a twelfth contact opening CH12 penetrating the gate insulating layer GI and the first and second interlayer insulating layers ILD1 and ILD2. The other end of the fourth bridge pattern BRP4 may be connected to the second power line PL2 through an eleventh contact opening (e.g., an eleventh contact hole) CH11 penetrating the third interlayer insulating layer ILD3.

[0274] The second power line PL2 may be connected to the fourth bridge pattern BRP4 through the eleventh contact opening CH11. In addition, the second power line PL2 may be electrically connected to the second electrode EL2 of the display element layer DPL through the tenth contact opening (eg, tenth contact hole) CH10 penetrating the protection layer PSV.

[0275] The second electrode EL2 may be disposed and / or formed on the second power line PL2 with the protection layer PSV interposed therebetween. Thus, when viewed on a plane, the second electrode EL2 may overlap the second power line PL2.

[0276] In an embodiment of the present disclosure, the first transistor T1 to the seventh transistor T7 and the first switch SW1 to the third switch SW3 provided in the pixel PXL may be LTPS thin film transistors, but the present disclosure is not limited thereto. In some embodiments, the first transistor T1 to the seventh transistor T7 and the first switch SW1 to the third switch SW3 may be oxide semiconductor thin film transistors.

[0277] In an embodiment of the present disclosure, after the alignment of the light emitting element LD in the light emitting area EMA of the pixel PXL is completed, the first to third switches SW1 to SW3 maintain a disconnected state (eg, an off state).

[0278] The protection layer PSV may be disposed on the first to seventh transistors T1 to T7 and the first to third switches SW1 to SW3 to cover the first to seventh transistors T1 to T7 and the first to third switches SW1 to SW3 .

[0279] The protective layer PSV may include an inorganic insulating layer and an organic insulating layer disposed on the inorganic insulating layer. The inorganic insulating layer may include silicon oxide (SiO x ) and silicon nitride (SiN x ). The organic insulating layer may include an organic insulating material (e.g., a transparent organic insulating material) through which light can be transmitted. For example, the organic insulating layer may include one or more of a photoresist, a polyacrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and a benzocyclobutene resin.

[0280] Next, the display element layer DPL included in the pixel PXL will be further described.

[0281] The display element layer DPL may include a first bank PW, first and second electrodes EL1 and EL2 , first and second conductive lines CL1 and CL2 , a second bank BNK, a plurality of light emitting elements LD, and a contact electrode CNE disposed on the protection layer PSV.

[0282] The first bank PW may be disposed on the protective layer PSV in the emission area EMA of the pixel PXL. The first bank PW may include an inorganic insulating layer made of (or including) an inorganic material or an organic insulating layer made of (or including) an organic material. In some embodiments, the first bank PW may include a single organic insulating layer and / or a single inorganic insulating layer, but the present disclosure is not limited thereto. In an example, the first bank PW may have a multilayer structure in which a plurality of organic insulating layers and a plurality of inorganic insulating layers are stacked.

[0283] like Figure 5As shown in , the first bank PW may have a trapezoidal cross-section whose width becomes narrower as the first bank PW approaches upward from one surface of the protective layer PSV, but the present disclosure is not limited thereto. In some embodiments, as Figure 6 As shown in , the first bank PW may include a curved surface having a semi-elliptical, semi-circular, etc. cross-section, the width of which becomes narrower as the first bank PW approaches upward from one surface of the protective layer PSV. When viewed in cross section, the shape of the first bank PW is not limited to the embodiment described above and may be variously and appropriately modified within a range capable of improving the efficiency of light emitted from each of the light emitting elements LD.

[0284] The second bank BNK may be disposed in a peripheral region of the pixel PXL (e.g., a non-emitting region in which the light emitting element LD is not aligned) to surround the emission region EMA of the corresponding pixel PXL. The second bank BNK is a structure that defines the emission region EMA of the pixel PXL and may be, for example, a pixel defining layer. The second bank BNK may include one or more of a light blocking material and a reflective material to prevent or reduce light leakage between adjacent pixels PXL. In some embodiments, a reflective material layer may be formed on the second bank BNK to further improve the efficiency of light emitted from the pixel PXL. The second bank BNK may be formed and / or disposed in a layer different from that of the first bank PW, but the present disclosure is not limited thereto. In some embodiments, the second bank BNK may be formed and / or disposed in the same layer as the first bank PW. When the second bank BNK is formed and / or disposed on the same plane as the first bank PW, the second bank BNK and the first bank PW may include the same (or substantially the same) material, but the present disclosure is not limited thereto. In some embodiments, the second bank BNK and the first bank PW may include different materials.

[0285] Each of the first electrode EL1 and the second electrode EL2 may be disposed in the emission area EMA of the pixel PXL and may extend along the second direction DR2 .

[0286] In an embodiment of the present disclosure, the first electrode EL1 may include a second protruding electrode PRP2 protruding in the first direction DR1. The second protruding electrode PRP2 may be disposed in the same layer as the first electrode EL1, and may include the same (or substantially the same) material as the first electrode EL1. For example, the second protruding electrode PRP2 and the first electrode EL1 may be integrally disposed (or formed) to be electrically and / or physically connected to each other. When the second protruding electrode PRP2 and the first electrode EL1 are integrally formed and / or disposed, the second protruding electrode PRP2 may be a region of the first electrode EL1.

[0287] The first electrode EL1 may be electrically connected to the extension electrode ETP through the second protruding electrode PRP2 extending through the twenty-second contact opening CH22. The extension electrode ETP may be connected to each of the sixth drain electrode DE6 of the sixth transistor T6 and the seventh source electrode SE7 of the seventh transistor T7 in the pixel circuit layer PCL through the eighth contact opening CH8 and the second connection electrode CNL2. Therefore, the first electrode EL1 may be connected to the sixth drain electrode DE6 of the sixth transistor T6 and the seventh source electrode SE7 of the seventh transistor T7 through the second protruding electrode PRP2, the extension electrode ETP, and the second connection electrode CNL2.

[0288] In addition, the first electrode EL1 may be electrically connected to the third shielding electrode line SDL3 through the sixteenth contact opening CH16. As described above, the third shielding electrode line SDL3 may be connected to the first bridge pattern BRP1 through the fifteenth contact opening CH15, and the first bridge pattern BRP1 may be connected to the (1-2)th terminal SW1_2 of the first switch SW1 included in the pixel circuit layer PCL through the twenty-third contact opening CH23. When a control signal having a voltage capable of turning on the first switch SW1 is supplied to the first switch gate electrode GE_SW1 of the first switch SW1 through the control signal line CSi, the first switch SW1 may be turned on. When the first switch SW1 is turned on, the third shielding electrode line SDL3 may be connected to the first protruding electrode PRP1 of the third power line PL3 through the first bridge pattern BRP1. Therefore, when the first switch SW1 is turned on, the first electrode EL1 may be electrically connected to the third power line PL3.

[0289] The second electrode EL2 may be connected to the second power line PL2 through the tenth contact opening CH10. As described above, the second power line PL2 may be connected to the fourth bridge pattern BRP4 through the eleventh contact opening CH11, and the fourth bridge pattern BRP4 may be connected to the (3-1)th terminal SW3_1 of the third switch SW3 included in the pixel circuit layer PCL through the twelfth contact opening CH12. When a control signal having a voltage capable of turning on the third switch SW3 is supplied to the third switch gate electrode GE_SW3 of the third switch SW3 through the control signal line CSi, the third switch SW3 may be turned on so that the second power line PL2 may be connected to the first conductive line CL1 through the third bridge pattern BRP3. Therefore, when the third switch SW3 is turned on, the second electrode EL2 may be electrically connected to the first conductive line CL1.

[0290] When viewed on a plane, the first conductive line CL1 may extend along the second direction DR2 and may be disposed between the first electrode EL1 and the second conductive line CL2. As described above, when the third switch SW3 is turned on, the first conductive line CL1 may be electrically connected to the second electrode EL2.

[0291] When the third switch SW3 is turned off, the first conductive line CL1 may be electrically isolated from the second electrode EL2 and may be in a floating state.

[0292] When viewed on a plane, the second conductive line CL2 may extend along the second direction DR2 and may be disposed between the second electrode EL2 and the first conductive line CL1. The second conductive line CL2 may be connected to the first shielding electrode line SDL1 through the eighteenth contact opening CH18.

[0293] As described above, the first shielding electrode line SDL1 may be connected to the second bridge pattern BRP2 through the seventeenth contact opening CH17, and the second bridge pattern BRP2 may be connected to the (2-2)th terminal SW2_2 of the second switch SW2 included in the pixel circuit layer PCL through the twenty-fifth contact opening CH25. When a control signal having a voltage capable of turning on the second switch SW2 is supplied to the second switch gate electrode GE_SW2 of the second switch SW2 through the control signal line CSi, the second switch SW2 may be turned on so that the second bridge pattern BRP2 may be electrically connected to the first protruding electrode PRP1 of the third power line PL3. In addition, when the second switch SW2 is turned on, the second conductive line CL2 may be connected to the third power line PL3 and the first electrode EL1.

[0294] When the second switch SW2 is turned off, the second conductive line CL2 may be electrically isolated from the first electrode EL1 and may be in a floating state.

[0295] In an embodiment of the present disclosure, before the light emitting element LD is aligned in the light emitting area EMA of the pixel PXL, each of the first and second electrodes EL1 and EL2 and the first and second conductive lines CL1 and CL2 may be electrically connected to the alignment unit 145 to serve as an alignment electrode (or alignment line) for aligning the light emitting element LD.

[0296] Before the light emitting element LD is aligned in the light emitting area EMA of the pixel PXL, the first to third switches SW1 to SW3 are concurrently (eg, simultaneously) turned on.

[0297] When the first to third switches SW1 to SW3 are turned on, the first electrode EL1 and the second conductive line CL2 are electrically connected to each other. In addition, the first electrode EL1 and the second conductive line CL2 are connected to the third power line PL3 to which the ground voltage GND is applied, so that the ground voltage GND can be transmitted to each of the first electrode EL1 and the second conductive line CL2.

[0298] When the first to third switches SW1 to SW3 are turned on, the second electrode EL2 and the first conductive line CL1 are electrically connected to each other, and the second electrode EL2 and the first conductive line CL1 are connected to the second power line PL2. An alignment voltage (e.g., an AC voltage) is applied to the second power line PL2. Therefore, the alignment voltage can be transmitted to each of the second electrode EL2 and the first conductive line CL1.

[0299] Therefore, electric fields may be formed between the first electrode EL1 and the first conductive line CL1, between the first conductive line CL1 and the second conductive line CL2, and between the second conductive line CL2 and the second electrode EL2, respectively. The light emitting element LD may be aligned by the electric field between the first electrode EL1 and the first conductive line CL1 on the pixel circuit layer PCL, the electric field between the first conductive line CL1 and the second conductive line CL2 on the pixel circuit layer PCL, and the electric field between the second conductive line CL2 on the pixel circuit layer PCL and the second electrode EL2, respectively.

[0300] After the light emitting element LD is aligned in the light emitting area EMA of the pixel PXL, each of the first electrode EL1 and the second electrode EL2 may serve as a driving electrode (or driving line) for driving the light emitting element LD. After the light emitting element LD is aligned in the light emitting area EMA of the pixel PXL, the first to third switches SW1 to SW3 maintain a disconnected state (e.g., maintained in an off state), and the second driving power source VSS is applied to the second power line PL2.

[0301] The first electrode EL1 and the second electrode EL2 may be made of a material having a constant (or substantially constant) reflectivity so that light emitted from both ends EP1 and EP2 of each of the light emitting elements LD travels in a direction (e.g., a forward direction) in which an image is displayed on the display device. In an embodiment of the present disclosure, the first electrode EL1 and the second electrode EL2, the first conductive line CL1, and the second conductive line CL2 may be disposed in the same layer and may be made of the same (or substantially the same) material.

[0302] The first electrode EL1 and the second electrode EL2, the first conductive line CL1, and the second conductive line CL2 may be made of a conductive material having a constant reflectivity (or may include a conductive material having a constant reflectivity). The conductive material may include a metal such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or any alloy thereof, a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO), a conductive polymer such as PEDOT, etc. The materials of the first electrode EL1 and the second electrode EL2, the first conductive line CL1, and the second conductive line CL2 are not limited to the materials described above.

[0303] In addition, the first electrode EL1 and the second electrode EL2, the first conductive line CL1, and the second conductive line CL2 may be formed in a single layer. However, the present disclosure is not limited thereto, and the first electrode EL1 and the second electrode EL2, the first conductive line CL1, and the second conductive line CL2 may be formed as a multilayer structure in which a plurality of materials among metals, alloys, conductive oxides, and conductive polymers are stacked. In some embodiments, each of the first electrode EL1 and the second electrode EL2, the first conductive line CL1, and the second conductive line CL2 may be a multilayer structure to reduce or minimize a voltage drop caused by a signal delay when a signal is transmitted to both ends EP1 and EP2 of each of the light emitting elements LD.

[0304] Since each of the first electrode EL1 and the second electrode EL2 has a shape corresponding to the shape of the first bank PW, light emitted from both ends EP1 and EP2 of each of the light emitting elements LD is reflected by the first electrode EL1 and the second electrode EL2 to further travel in the forward direction of the display device. Therefore, the efficiency of light emitted from each of the light emitting elements LD can be improved.

[0305] In an embodiment of the present disclosure, each of the first bank PW, the first electrode EL1 and the second electrode EL2, the first conductive line CL1, and the second conductive line CL2 may act as a reflective member that induces light emitted from each of the light emitting elements LD in a desired direction to improve the light efficiency of the display device. For example, each of the first bank PW, the first electrode EL1 and the second electrode EL2, the first conductive line CL1, and the second conductive line CL2 may act as a reflective member that causes light emitted from each of the light emitting elements LD to travel in a forward direction of the display device to improve the light output efficiency of the light emitting element LD.

[0306] Either one of the first electrode EL1 and the second electrode EL2 may be an anode electrode, and the other of the first electrode EL1 and the second electrode EL2 may be a cathode electrode. In an embodiment of the present disclosure, the first electrode EL1 may be an anode electrode, and the second electrode EL2 may be a cathode electrode.

[0307] Each of the light emitting elements LD may be a micro light emitting diode using (or having) an inorganic crystal structure having a size as small as a micrometer level or a nanometer level. The light emitting element LD may be aligned between the first electrode EL1 and the second electrode EL2 in the pixel PXL.

[0308] A plurality of (eg, from about two to several tens of) light emitting elements LD may be disposed in the light emitting area EMA of the pixel PXL, but the present disclosure is not limited thereto. In certain embodiments, the number of light emitting elements LD disposed in the pixel PXL may be variously and appropriately modified.

[0309] Each of the light emitting elements LD may include a light emitting stack structure in which a first semiconductor layer 11, an active layer 12, a second semiconductor layer 13 and an electrode layer 15 are sequentially stacked along their length direction. In addition, each of the light emitting elements LD may further include an insulating film 14 surrounding the outer perimeter of the light emitting stack structure.

[0310] In an embodiment of the present disclosure, each of the light emitting elements LD may have a cylindrical column shape. Each light emitting element LD may include a first end EP1 corresponding to any one of the lower and upper parts of the cylindrical column and a second end EP2 corresponding to the other of the lower and upper parts of the cylindrical column. Any one of the first semiconductor layer 11 and the second semiconductor layer 13 may be disposed at the first end EP1 of each light emitting element LD, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 may be disposed at the second end EP2 of each light emitting element LD.

[0311] In an embodiment of the present disclosure, each of the light emitting elements LD may emit any one of colored light and / or white light. Each of the light emitting elements LD may be aligned between the first electrode EL1 and the second electrode EL2 so that its length direction is parallel to (or substantially parallel to) the first direction DR1. For example, some of the light emitting elements LD may be aligned between the first electrode EL1 and the first conductive line CL1, others of the light emitting elements LD may be aligned between the first conductive line CL1 and the second conductive line CL2, and others of the light emitting elements LD may be aligned between the second conductive line CL2 and the second electrode EL2.

[0312] The first insulating layer INS1 may be disposed between each of the light emitting elements LD and the protection layer PSV.

[0313] The first insulating layer INS1 may be formed in the light emitting area EMA of the pixel PXL and / or disposed at a lower portion of each of the light emitting elements LD between the first electrode EL1 and the second electrode EL2. In the light emitting area EMA of the pixel PXL, the first insulating layer INS1 may fill a space between each of the light emitting elements LD and the protective layer PSV to stably support the light emitting element LD and prevent the light emitting element LD from being separated from the protective layer PSV (or reduce the risk of separation of the light emitting element LD from the protective layer PSV).

[0314] In addition, in the light emitting area EMA of the pixel PXL, the first insulating layer INS1 may expose one area of ​​the first electrode EL1 and cover other areas except the one area to protect the other areas of the first electrode EL1. In addition, the first insulating layer INS1 may expose one area of ​​the second electrode EL2 and cover other areas except the one area to protect the other areas of the second electrode EL2. In addition, the first insulating layer INS1 may expose one area of ​​the first conductive line CL1 and cover other areas except the one area to protect the other areas of the first conductive line CL1. Additionally, the first insulating layer INS1 may expose one area of ​​the second conductive line CL2 and cover other areas except the one area to protect the other areas of the second conductive line CL2.

[0315] In addition, the first insulating layer INS1 may be formed and / or disposed on the protection layer PSV in a peripheral region (eg, a non-emission region in which light is not emitted) of the pixel PXL to protect components disposed in the peripheral region.

[0316] The first insulating layer INS1 may include an inorganic insulating layer made of (or including) an inorganic material or an organic insulating layer made of (or including) an organic material. In an embodiment of the present disclosure, the first insulating layer INS1 may be formed of an inorganic insulating layer to protect the light emitting element LD from the pixel circuit layer PCL, but the present disclosure is not limited thereto. In some embodiments, the first insulating layer INS1 may be formed of an organic insulating layer to flatten the supporting surface of the light emitting element LD.

[0317] The second insulating layer INS2 may be disposed and / or formed on each of the light emitting elements LD. The second insulating layer INS2 may be disposed on each light emitting element LD to cover a portion of the surface of the light emitting element LD (e.g., partially cover the light emitting element LD) while exposing both ends EP1 and EP2 of the light emitting element LD to the outside. The second insulating layer INS2 may be formed as an independent pattern on the light emitting area EMA of the pixel PXL, but the present disclosure is not limited thereto. In some embodiments, the second insulating layer INS2 may be omitted. The contact electrodes CNE electrically isolated from each other may directly contact both ends EP1 and EP2 of each light emitting element LD, respectively.

[0318] The second insulating layer INS2 may be a single layer or may have a multi-layer structure, and may include an inorganic insulating layer having one or more inorganic materials or an organic insulating layer having one or more organic materials. The second insulating layer INS2 may be fixed to each of the light emitting elements LD aligned in the light emitting area EMA of the pixel PXL. In an embodiment of the present disclosure, the second insulating layer INS2 may include an inorganic insulating layer for protecting the active layer 12 of each light emitting element LD from external oxygen and moisture. However, the present disclosure is not limited thereto. According to the design conditions of the display device, the second insulating layer INS2 may include an organic insulating layer having an organic material.

[0319] In an embodiment of the present disclosure, the second insulating layer INS2 is formed on the light emitting element LD after the alignment of the light emitting element LD in the light emitting region EMA of the pixel PXL is completed, so that the light emitting element LD may not be separated (or moved) from the position where the light emitting element LD is aligned. When there is a separation space between the first insulating layer INS1 and the light emitting element LD before the second insulating layer INS2 is formed, the second insulating layer INS2 may fill the separation space in the process of forming the second insulating layer INS2. Therefore, the light emitting element LD can be stably supported.

[0320] In an embodiment of the present disclosure, a second insulating layer INS2 is formed on each of the light emitting elements LD so that the active layer 12 of each light emitting element LD may not contact an external conductive material. The second insulating layer INS2 may cover only a portion of the surface of each of the light emitting elements LD and may expose both end portions EP1 and EP2 of each light emitting element LD to the outside.

[0321] The contact electrode CNE may be disposed on the first electrode EL1 , the second electrode EL2 , the first conductive line CL1 , and the second conductive line CL2 , respectively.

[0322] In some embodiments, the contact electrode CNE may be made of various suitable transparent conductive materials. In an example, the contact electrode CNE may include one or more various suitable transparent conductive materials (including ITO, IZO, and ITZO), and may be substantially transparent or translucent to provide a reference (e.g., predetermined or desired) transmittance. Therefore, light emitted by the light emitting element LD through the first end EP1 and the second end EP2 of the light emitting element LD is transmitted to the outside of the display device through the contact electrode CNE.

[0323] The contact electrode CNE (hereinafter, referred to as “first contact electrode”) located on the first electrode EL1 electrically connects the first electrode EL1 to any one of the ends EP1 and EP2 of each of the light emitting elements LD (hereinafter, referred to as “first light emitting element LD1”) aligned between the first electrode EL1 and the first conductive line CL1.

[0324] A contact electrode CNE (hereinafter, referred to as a "second contact electrode") located on the first conductive line CL1 electrically connects the first conductive line CL1 to the other of the ends EP1 and EP2 of each of the first light emitting elements LD1. The second contact electrode CNE electrically connects the first conductive line CL1 in a floating state to the other end of each of the first light emitting elements LD1. Finally, the first conductive line CL1 and the first electrode EL1 are electrically connected to each other.

[0325] In addition, the second contact electrode CNE electrically connects the first conductive line CL1 to any one of the end portions EP1 and EP2 of each of the light emitting elements LD (hereinafter, referred to as “second light emitting elements LD2 ”) arranged between the first conductive line CL1 and the second conductive line CL2 .

[0326] The contact electrode CNE located on the second conductive line CL2 (hereinafter, referred to as a "third contact electrode") electrically connects the second conductive line CL2 to the other of the ends EP1 and EP2 of each of the second light emitting elements LD2. The third contact electrode CNE electrically connects the second conductive line CL2 in a floating state to each of the second light emitting elements LD2. Finally, the second conductive line CL2 and the first conductive line CL1 are electrically connected to each other.

[0327] In addition, the third contact electrode CNE electrically connects the second conductive line CL2 to any one of the end portions EP1 and EP2 of each of the light emitting elements LD (hereinafter, referred to as “third light emitting element LD3 ”) aligned between the second conductive line CL2 and the second electrode EL2 .

[0328] The contact electrode CNE (hereinafter, referred to as “fourth contact electrode”) located on the second electrode EL2 electrically connects the second electrode EL2 to the other of the end portions EP1 and EP2 of each of the third light emitting elements LD3 .

[0329] The first contact electrode CNE, the second contact electrode CNE, the third contact electrode CNE, and the fourth contact electrode CNE may each have a strip shape extending along the second direction DR2. Each of the first contact electrode CNE, the second contact electrode CNE, the third contact electrode CNE, and the fourth contact electrode CNE may be disposed on the pixel circuit layer PCL on which the second insulating layer INS2 is disposed, and may be spaced apart from the adjacent contact electrode CNE at a certain distance on the second insulating layer INS2. The first contact electrode CNE, the second contact electrode CNE, the third contact electrode CNE, and the fourth contact electrode CNE may be disposed and / or formed in the same layer. However, the present disclosure is not limited thereto. In some embodiments, the first contact electrode CNE, the second contact electrode CNE, the third contact electrode CNE, and the fourth contact electrode CNE may be formed and / or disposed in different layers. This will be referred to later. Fig.10 Describe in more detail.

[0330] A third insulating layer INS3 may be disposed and / or formed on the first, second, third, and fourth contact electrodes CNE.

[0331] The third insulating layer INS3 may be completely disposed and / or formed on the substrate SUB on which the first embankment PW, the first and second electrodes EL1 and EL2, the first and second conductive lines CL1 and CL2, the light emitting element LD, and the contact electrode CNE are formed to cover the first embankment PW, the first and second electrodes EL1 and EL2, the first and second conductive lines CL1 and CL2, the light emitting element LD, and the contact electrode CNE.

[0332] The third insulating layer INS3 prevents the first, second, third and fourth contact electrodes CNE from being exposed to the outside to prevent or reduce corrosion of each of the first, second, third and fourth contact electrodes CNE. The third insulating layer INS3 may be formed of any appropriate one of an inorganic insulating layer and an organic insulating layer.

[0333] An overcoat layer OC may be disposed on the third insulating layer INS3. The overcoat layer OC may be an encapsulation layer that reduces a step difference generated by the first bank PW, the first and second electrodes EL1 and EL2, the first and second conductive lines CL1 and CL2, the contact electrode CNE, etc. disposed thereunder, and may prevent or reduce oxygen and moisture from penetrating into the light emitting element LD. In some embodiments, the overcoat layer OC may be omitted by considering design conditions of the display device.

[0334] As described above, the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 aligned in the light emitting area EMA of the pixel PXL may be electrically connected to each other between the first electrode EL1 and the second electrode EL2. A reference voltage (e.g., a predetermined voltage) may be applied to both ends EP1 and EP2 of each of the light emitting elements LD aligned in the light emitting area EMA of the pixel PXL through the first electrode EL1 and the second electrode EL2. Therefore, each of the light emitting elements LD may emit light when electron-hole pairs are combined in its corresponding active layer 12. The active layer 12 may emit light having a wavelength band of about 400 nm to about 900 nm.

[0335] In certain embodiments, Figure 7 As shown in , the capping layer CPL may be formed and / or disposed in the emission area EMA of the pixel PXL.

[0336] The capping layer CPL may be disposed between the first electrode EL1 and the first contact electrode CNE, between the first conductive line CL1 and the second contact electrode CNE, between the second conductive line CL2 and the third contact electrode CNE, and between the second electrode EL2 and the fourth contact electrode CNE, respectively. The capping layer CPL prevents or reduces damage to the corresponding electrode and the corresponding conductive line due to defects occurring in the manufacturing process of the display device, and also enhances adhesion between the protective layer PSV and each of the corresponding electrode and the corresponding conductive line. The capping layer CPL may be formed of a transparent conductive material such as indium zinc oxide (IZO) to minimize or reduce the loss of light emitted from each of the light emitting elements LD and then reflected in the display direction of the display device by the corresponding electrode and the corresponding conductive line.

[0337] Fig.10 According to another embodiment of the present disclosure Figure 4 The line II' shown in FIG.

[0338] In addition to the contact electrodes on the first electrode and the contact electrodes on the second electrode being arranged in different layers, Fig.10 The display device shown in FIG. 1 may have Figure 5 The configuration of the display device shown in is the same as or a substantially similar configuration.

[0339] In the following Fig.10 In the description of the display device shown in , portions different from those of the embodiment described above will be mainly described. Fig.10 The parts of the display device shown in but not specifically described in this embodiment are the same or substantially similar to the parts of the embodiment described above, and are omitted to avoid redundancy. In addition, the same reference numerals represent the same components, and similar reference numerals represent similar components.

[0340] exist Fig.10 , the structure of the display device is simplified and illustrated as an embodiment in which each electrode is illustrated as a single electrode layer and each insulating layer is illustrated as a single insulating layer. However, the present disclosure is not limited thereto.

[0341] Reference Figure 1A , Figure 2 , Figure 3D , Figure 4 and Fig.10 , the display device may include a substrate SUB, a line unit, and one or more pixels PXL.

[0342] The pixel PXL may include a display element layer DPL having one or more light emitting elements LD and a pixel circuit layer PCL driving the light emitting elements LD.

[0343] The pixel circuit layer PCL may include an alignment unit 145 for aligning the light emitting element LD in the light emitting area EMA of the pixel PXL, a pixel circuit 144 for driving the light emitting element LD, and a protection layer PSV covering the alignment unit 145 and the pixel circuit 144 .

[0344] The display element layer DPL may include a first bank PW, first and second electrodes EL1 and EL2, first and second conductive lines CL1 and CL2, a second bank BNK, a plurality of light emitting elements LD, and first and second contact electrodes CNE1 and CNE2 disposed on the protection layer PSV.

[0345] In an embodiment of the present disclosure, the first contact electrode CNE1 may include a (1-1)th contact electrode CNE1_1 and a (1-2)th contact electrode CNE1_2.

[0346] The (1-1)th contact electrode CNE1_1 may be disposed on the first electrode EL1 to be electrically and / or physically connected to the first electrode EL1. The (1-2)th contact electrode CNE1_2 may be disposed on the second conductive line CL2 to be electrically and / or physically connected to the second conductive line CL2.

[0347] The third insulating layer INS3 may be disposed on the (1-1)th contact electrode CNE1_1 and the (1-2)th contact electrode CNE1_2. The third insulating layer INS3 may correspond to Figure 5 The third insulating layer INS3 is shown in FIG. The third insulating layer INS3 prevents the (1-1)th contact electrode CNE1_1 and the (1-2)th contact electrode CNE1_2 from being exposed to the outside to prevent or reduce corrosion of the (1-1)th contact electrode CNE1_1 and the (1-2)th contact electrode CNE1_2.

[0348] In an embodiment of the present disclosure, the second contact electrode CNE2 may include a (2-1)th contact electrode CNE2_1 and a (2-2)th contact electrode CNE2_2.

[0349] The (2-1)th contact electrode CNE2_1 may be disposed on the first conductive line CL1 to be electrically and / or physically connected to the first conductive line CL1. The (2-2)th contact electrode CNE2_2 may be disposed on the second electrode EL2 to be electrically and / or physically connected to the second conductive line CL2.

[0350] The fourth insulating layer INS4 may be disposed on the (2-1)th contact electrode CNE2_1 and the (2-2)th contact electrode CNE2_2. The fourth insulating layer INS4 prevents the (2-1)th contact electrode CNE2_1 and the (2-2)th contact electrode CNE2_2 from being exposed to the outside to prevent or reduce corrosion of the (2-1)th contact electrode CNE2_1 and the (2-2)th contact electrode CNE2_2. The fourth insulating layer INS4 may be formed of any appropriate one of an inorganic insulating layer and an organic insulating layer.

[0351] An overcoat layer OC may be disposed on the fourth insulating layer INS4.

[0352] As described above, the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed and / or formed in different layers.

[0353] FIG. 11A to FIG. 11M is shown sequentially Figure 5 sectional view of a method for manufacturing a display device shown in .

[0354] exist FIG. 11A to FIG. 11M In the embodiment, the parts different from the parts of the embodiment described above will be mainly described to avoid redundancy. The parts not specifically described in this embodiment follow the parts in the embodiment described above. In addition, the same reference numerals represent the same components, and similar reference numerals represent similar components.

[0355] In the embodiments of the present disclosure, “components and the like are formed and / or disposed in the same layer” may mean that the components and the like are formed in the same process (or during the same process or by using the same process).

[0356] Reference Figure 1A , Figure 2 , Figure 3D , Figure 4 , Figure 5 and Fig.11A A buffer layer BFL is formed on the substrate SUB in each pixel PXL. Subsequently, a semiconductor pattern SMP is formed on the buffer layer BFL. The semiconductor pattern SMP may be a semiconductor layer not doped with impurities (eg, an undoped semiconductor layer).

[0357] Reference Figure 1A , Figure 2 , Figure 3D , Figure 4 , Figure 5 , Fig.11A and Fig. 11B , a gate insulating layer GI is formed over the semiconductor pattern SMP.

[0358] Subsequently, the (i-1)th scan line Si-1, the i-th scan line Si, the (i+1)th scan line Si+1, the emission control line Ei, the control signal line CSi, and the first lower electrode LE1 and the second lower electrode LE2 are formed. The (i-1)th scan line Si-1, the i-th scan line Si, the (i+1)th scan line Si+1, the emission control line Ei, and the control signal line CSi may be formed of the same material (or may include the same material) and may be formed by the same process.

[0359] Impurities are doped (e.g., continuously doped) into the semiconductor pattern SMP by using the (i-1)th scan line Si-1, the i-th scan line Si, the (i+1)th scan line Si+1, the emission control line Ei, the control signal line CSi, and the first and second lower electrodes LE1 and LE2 as masks. Thus, the semiconductor pattern SMP doped with impurities may be formed as source and drain electrodes of each transistor and first and second terminals of each switch.

[0360] Concurrently (or simultaneously), the semiconductor pattern SMP not doped with impurities due to the (i-1)th scan line Si-1, the i-th scan line Si, the (i+1)th scan line Si+1, the emission control line Ei and the control signal line CSi can be formed as an active pattern of each transistor and an active pattern of each switch.

[0361] For example, the first source electrode SE1 and the second source electrode SE2, the 3a source electrode SE3a and the 3b source electrode SE3b, the 4a source electrode SE4a and the 4b source electrode SE4b, the fifth source electrode SE5 to the seventh source electrode SE7, and the (1-1)th terminal SW1_1, the (2-1)th terminal SW2_1, and the (3-1)th terminal SW3_1 may be formed on the buffer layer BFL. In addition, the first drain electrode DE1 and the second drain electrode DE2, the 3a drain electrode DE3a and the 3b drain electrode DE3b, the 4a drain electrode DE4a and the 4b drain electrode DE4b, the fifth drain electrode DE5 to the seventh drain electrode DE7, and the (1-2)th terminal SW1_2, the (2-2)th terminal SW2_2, and the (3-2)th terminal SW3_2 may be formed on the buffer layer BFL. In addition, first and second active patterns ACT1 and ACT2, 3a and 3b active patterns ACT3a and ACT3b, 4a and 4b active patterns ACT4a and ACT4b, fifth to seventh active patterns ACT5 to ACT7, first, second, and third switch active patterns ACT_SW1, ACT_SW2, and ACT_SW3 may be formed on the buffer layer BFL.

[0362] In the embodiment of the present disclosure, a region of the first lower electrode LE1 overlapping with the first active pattern ACT1 may become the first gate electrode GE1, a region of the i-th scan line Si overlapping with the second active pattern ACT2 may become the second gate electrode GE2, a region of the i-th scan line Si overlapping with the 3a-th active pattern ACT3a may become the 3a-th gate electrode GE3a, and a region of the i-th scan line Si overlapping with the 3b-th active pattern ACT3b may become the 3b-th gate electrode GE3b. In addition, a region of the (i-1)-th scan line Si-1 overlapping with the 4a-th active pattern ACT4a may become the 4a-th gate electrode GE4a, a region of the (i-1)-th scan line Si-1 overlapping with the 4b-th active pattern ACT4b may become the 4b-th gate electrode GE4b, and a region of the emission control line Ei overlapping with the fifth active pattern ACT5 may become the fifth gate electrode GE5. In addition, a region of the emission control line Ei overlapping the sixth active pattern ACT6 may become the sixth gate electrode GE6, and a region of the (i+1)th scan line Si+1 overlapping the seventh active pattern ACT7 may become the seventh gate electrode GE7.

[0363] In an embodiment of the present disclosure, a region of the control signal line CSi overlapping with the first switch active pattern ACT_SW1 may become the first switch gate electrode GE_SW1, a region of the control signal line CSi overlapping with the second switch active pattern ACT_SW2 may become the second switch gate electrode GE_SW2, and a region of the control signal line CSi overlapping with the third switch active pattern ACT_SW3 may become the third switch gate electrode GE_SW3.

[0364] Next, refer to Figure 1A , Figure 2 , Figure 3D , Figure 4 , Figure 5 as well as FIG. 11A to FIG. 11C A first interlayer insulating layer ILD1 is formed on the (i-1)th scan line Si-1, the i-th scan line Si, the (i+1)th scan line Si+1, the emission control line Ei, and the control signal line CSi of each pixel PXL.

[0365] Subsequently, the first upper electrode UE1 and the second upper electrode UE2 are formed on the first interlayer insulating layer ILD1. The first upper electrode UE1 and the second upper electrode UE2 may be made of (or may include) the same conductive material and may be formed and / or disposed in the same layer.

[0366] The first upper electrode UE1 may have an opening OPN therein. The first upper electrode UE1 may overlap the first lower electrode LE1 with a first interlayer insulating layer ILD1 interposed therebetween. The first upper electrode UE1 may constitute a first capacitor C1 together with the first lower electrode LE1.

[0367] The second upper electrode UE2 may overlap the second lower electrode LE2 with the first interlayer insulating layer ILD1 interposed therebetween. The second upper electrode UE2 may constitute a second capacitor C2 together with the second lower electrode LE2.

[0368] Next, refer to Figure 1A , Figure 2 , Figure 3D , Figure 4 , Figure 5 as well as FIG. 11A to FIG. 11D , a second interlayer insulating layer ILD2 is formed on the first upper electrode UE1 and the second upper electrode UE2 of each pixel PXL.

[0369] An initialization power line IPL, a data line Dj, a first power line PL1, a third power line PL3, a first connection electrode CNL1, a second connection electrode CNL2, and a third connection electrode CNL3, first to fourth bridge patterns BRP1 to BRP4, and a first protruding electrode PRP1 are formed on the second interlayer insulating layer ILD2. In an embodiment of the present disclosure, the third power line PL3 may include a region protruding along the first direction DR1, and the region of the third power line PL3 may become the first protruding electrode PRP1.

[0370] The initialization power line IPL, the data line Dj, the first power line PL1, the third power line PL3, the first connection electrode CNL1, the second connection electrode CNL2 and the third connection electrode CNL3, the first bridge pattern BRP1 to the fourth bridge pattern BRP4 and the first protruding electrode PRP1 may be made of the same conductive material (or may include the same conductive material) and may be formed and / or arranged in the same layer.

[0371] Next, refer to Figure 1A , Figure 2 , Figure 3D , Figure 4 , Figure 5 as well as FIG. 11A to FIG. 11E A third interlayer insulating layer ILD3 is formed on the entire surface of the second interlayer insulating layer ILD2 on which the initialization power line IPL, the data line Dj, the first power line PL1, the third power line PL3, the first connection electrode CNL1, the second connection electrode CNL2 and the third connection electrode CNL3, the first bridge pattern BRP1 to the fourth bridge pattern BRP4 and the first protruding electrode PRP1 are formed.

[0372] Subsequently, the second power line PL2, the first to third shielding electrode lines SDL1 to SDL3, and the extension electrode ETP are formed on the third interlayer insulating layer ILD3. In an embodiment of the present disclosure, the third shielding electrode line SDL3 may have a region protruding along the first direction DR1 (or protruding in the first direction DR1), and the region becomes (or is) the extension electrode ETP.

[0373] The second power line PL2 , the first to third shielding electrode lines SDL1 to SDL3 , and the extension electrode ETP may be made of (or may include) the same conductive material and may be formed and / or disposed in the same layer.

[0374] Next, refer to Figure 1A , Figure 2 , Figure 3D , Figure 4 , Figure 5 as well as FIG. 11A to FIG. 11FA protection layer PSV is formed on the third interlayer insulating layer ILD3 on which the second power line PL2 , the first to third shielding electrode lines SDL1 to SDL3 , and the extension electrode ETP are formed.

[0375] The protection layer PSV may include a twenty-second contact opening (eg, a twenty-second contact hole) CH22 exposing a region of the extension electrode ETP.

[0376] Subsequently, a first bank PW is formed on the protective layer PSV. One first bank PW may be spaced apart from an adjacent first bank PW on the protective layer PSV by a certain distance. The first bank PW may include an inorganic insulating layer made of (or including) an inorganic material or an organic insulating layer made of (or including) an organic material. In some embodiments, the first bank PW may include a single organic insulating layer and / or a single inorganic insulating layer, but the present disclosure is not limited thereto. In another example, the first bank PW may have a multilayer structure in which a plurality of organic insulating layers and a plurality of inorganic insulating layers are stacked.

[0377] Next, refer to Figure 1A , Figure 2 , Figure 3D , Figure 4 , Figure 5 as well as FIG. 11A to FIG. 11G , a first electrode EL1, a first conductive line CL1, a second conductive line CL2, a second electrode EL2, and a second protruding electrode PRP2 are formed on the protective layer PSV of each pixel PXL, wherein each of the first electrode EL1, the first conductive line CL1, the second conductive line CL2, the second electrode EL2, and the second protruding electrode PRP2 includes a conductive material with high reflectivity. In an embodiment of the present disclosure, the first electrode EL1 may include a region protruding along the first direction DR1, and the region may become (or may be) the second protruding electrode PRP2.

[0378] Each of the first electrode EL1 , the first conductive line CL1 , the second conductive line CL2 , and the second electrode EL2 may be formed and / or disposed on a corresponding first bank PW in the emission area EMA of each pixel PXL.

[0379] The first electrode EL1 , the first conductive line CL1 , the second conductive line CL2 , and the second electrode EL2 may be made of (or may include) the same conductive material and may be formed and / or disposed in the same layer.

[0380] Next, refer to Figure 1A , Figure 2 , Figure 3D , Figure 4 , Figure 5 as well as FIG. 11A to FIG. 11HA first insulating material layer is formed on the entire surface of the protective layer PSV on which the first electrode EL1, the first conductive line CL1, the second conductive line CL2, and the second electrode EL2 are formed. Subsequently, the first insulating layer INS1 is formed by patterning the first insulating material layer (for example, by using) a mask to expose each of a region of the first electrode EL1, a region of the first conductive line CL1, a region of the second conductive line CL2, and a region of the second electrode EL2.

[0381] Next, refer to Figure 1A , Figure 2 , Figure 3D , Figure 4 , Figure 5 as well as FIG. 11A to FIG. 11I The second bank BNK is formed in a peripheral region (eg, a non-emission region in which light is not emitted) positioned at the periphery of the emission region EMA of each pixel PXL.

[0382] The second bank BNK may be a structure that defines (or provides) the emission area EMA of each pixel PXL.

[0383] Next, refer to Figure 1A , Figure 2 , Figure 3D , Figure 4 , Figure 5 as well as FIG. 11A to FIG. 11J , a plurality of light emitting elements LD are injected into the light emitting area EMA of each pixel PXL by using an inkjet printing technique.

[0384] In an example, the light emitting element LD can be injected into the light emitting area EMA of each pixel PXL by setting (or arranging) a nozzle above the protective layer PSV and dripping (or depositing or printing) a solvent including the light emitting element LD. The solvent may include one or more of acetone, water, alcohol, and toluene, but the present disclosure is not limited thereto. For example, the solvent may include a material that evaporates at room temperature or can be evaporated by heat. In addition, the solvent may be ink or paste. The method of injecting the light emitting element LD is not limited thereto, and may be modified differently and appropriately as will be understood by those skilled in the art.

[0385] The solvent may be removed after the light emitting element LD is injected into the light emitting area EMA of each pixel PXL.

[0386] Before the light emitting element LD is injected, a control signal having a voltage to concurrently (eg, simultaneously) turn on the first to third switches SW1 to SW3 is supplied from the control signal line CSi to the first, second, and third switch gate electrodes GE_SW1, GE_SW2, and GE_SW3.

[0387] Therefore, when the first to third switches SW1 to SW3 are turned on, the ground voltage GND from the third power line PL3 is applied to each of the first electrode EL1 and the second conductive line CL2, and the alignment voltage (e.g., AC voltage) from the second power line PL2 is applied to the second electrode EL2 and the first conductive line CL1. Therefore, electric fields may be formed between the first electrode EL1 and the first conductive line CL1, between the first conductive line CL1 and the second conductive line CL2, and between the second conductive line CL2 and the second electrode EL2, respectively.

[0388] Therefore, when the light emitting element LD is injected into the light emitting area EMA of each pixel PXL, the light emitting element LD can be guided to be self-aligned due to the electric field formed between the first electrode EL1 and the first conductive line CL1, between the first conductive line CL1 and the second conductive line CL2, and between the second conductive line CL2 and the second electrode EL2. Therefore, the light emitting element LD can be aligned between the first electrode EL1 and the first conductive line CL1, between the first conductive line CL1 and the second conductive line CL2, and between the second conductive line CL2 and the second electrode EL2. For example, the light emitting element LD can be closely aligned in a desired area (for example, in the light emitting area EMA of each pixel PXL). The light emitting element LD can be aligned on the first insulating layer INS1 in the light emitting area EMA of each pixel PXL.

[0389] After the alignment of the light emitting element LD in the light emitting area EMA of each pixel PXL is completed, a control signal having a voltage to concurrently (e.g., simultaneously) disconnect the first to third switches SW1 to SW3 is supplied from the control signal line CSi to the first switch gate electrode GE_SW1, the second switch gate electrode GE_SW2, and the third switch gate electrode GE_SW3. Therefore, the first to third switches SW1 to SW3 may be disconnected concurrently (or simultaneously). After the first to third switches SW1 to SW3 are disconnected, the second driving power source VSS may be applied.

[0390] Next, refer to Figure 1A , Figure 2 , Figure 3D , Figure 4 , Figure 5 as well as FIG. 11A to FIG. 11K , a second insulating material layer is formed on the entire surface of the protective layer PSV on which the light emitting element LD is aligned. Subsequently, a second insulating layer INS2 disposed in one region of the upper surface of each of the light emitting elements LD and exposing both end portions EP1 and EP2 of each of the light emitting elements LD is formed by patterning the second insulating material layer using a mask. The second insulating layer INS2 may include an inorganic insulating layer made of (or including) an inorganic material or an organic insulating layer made of (or including) an organic material.

[0391] Next, refer to Figure 1A , Figure 2 , Figure 3D , Figure 4 , Figure 5 as well as FIG. 11A to FIG. 11L , a contact electrode CNE is formed on the protection layer PSV including the second insulating layer INS2 disposed thereon by using sputtering.

[0392] In an embodiment of the present disclosure, the contact electrode CNE may be formed and / or disposed on the first electrode EL1 , the first conductive line CL1 , the second conductive line CL2 , and the second electrode EL2 , respectively.

[0393] The contact electrode CNE located on the first electrode EL1 may be directly formed on the first electrode EL1 to be electrically and / or physically connected to the first electrode EL1. Figure 7 When a capping layer CPL shown in FIG. 1 is disposed between the first electrode EL1 and the contact electrode CNE, the contact electrode CNE may be directly formed on the capping layer CPL to be indirectly connected to the first electrode EL1.

[0394] The contact electrode CNE located on the first conductive line CL1 may be directly formed on the first conductive line CL1 to be electrically and / or physically connected to the first conductive line CL1. However, in some embodiments, when the capping layer (eg, Figure 7 When a capping layer CPL shown in FIG. 1 is disposed between the first conductive line CL1 and the contact electrode CNE, the contact electrode CNE may be directly formed on the capping layer CPL to be indirectly connected to the first conductive line CL1.

[0395] The contact electrode CNE located on the second conductive line CL2 may be directly formed on the second conductive line CL2 to be electrically and / or physically connected to the second conductive line CL2. Figure 7 When the capping layer CPL shown in FIG. 1 is disposed between the second conductive line CL2 and the contact electrode CNE, the contact electrode CNE may be directly formed on the capping layer CPL to be indirectly connected to the second conductive line CL2.

[0396] The contact electrode CNE located on the second electrode EL2 may be directly formed on the second electrode EL2 to be electrically and / or physically connected to the second electrode EL2. Figure 7 When the capping layer CPL shown in FIG. 1 is disposed between the second electrode EL2 and the contact electrode CNE, the contact electrode CNE may be directly formed on the capping layer CPL to be indirectly connected to the second electrode EL2.

[0397] The contact electrode CNE on the first electrode EL1, the contact electrode CNE on the first conductive line CL1, the contact electrode CNE on the second conductive line CL2, and the contact electrode CNE on the second electrode EL2 may be made of (or may include) the same conductive material and may be formed and / or set in the same layer.

[0398] Next, refer to Figure 1A , Figure 2 , Figure 3D , Figure 4 , Figure 5 as well as FIG. 11A to FIG. 11M , a third insulating layer INS3 is formed on the entire surface including the protection layer PSV on which the contact electrode CNE is disposed.

[0399] The third insulating layer INS3 may include an inorganic insulating layer made of (or including) an inorganic material or an organic insulating layer made of (or including) an organic material. The third insulating layer INS3 may be a single layer as shown in the drawings. However, the present disclosure is not limited thereto, and the third insulating layer INS3 may have a multi-layer structure.

[0400] Subsequently, an overcoat layer OC is formed on the third insulating layer INS3.

[0401] Fig.12 It is shown Figure 3C A plan view of a pixel shown in FIG. 1 , and Fig.13 It is along Fig.12 A cross-sectional view taken along line III-III' shown in FIG.

[0402] Except that the alignment unit consists of only one switch, Fig.12 and Fig.13 The pixels shown in FIG. 4 may have Figure 4 and Figure 5 The configuration of the pixels shown in is the same or a substantially similar configuration.

[0403] Therefore, relative to Fig.12 and Fig.13 , the parts different from those in the above-described embodiments will be mainly described to avoid redundancy. The parts not specifically described in this embodiment follow the parts in the above-described embodiments. In addition, the same reference numerals represent the same components, and similar reference numerals represent similar components.

[0404] exist Fig.12In FIG. 1 , based on one pixel PXL provided on the i-th row and the j-th column provided in the display area, three scanning lines Si-1, Si and Si+1, an emission control line Ei, first to third power lines PL1 to PL3, a control signal line CSi and a data line Dj connected to one pixel PXL are shown.

[0405] exist Fig.12 and Fig.13 , the structure of one pixel PXL is simplified and illustrated such that each electrode is illustrated as a single electrode layer and each insulating layer is illustrated as a single insulating layer. However, the present disclosure is not limited thereto.

[0406] Refer to the figure Figure 1A , Figure 2 , Figure 3C , Fig.12 and Fig.13 At least one pixel PXL (hereinafter, referred to as "pixel") included in the display device according to an embodiment of the present disclosure may include scan lines Si-1, Si and Si+1, data lines Dj, emission control lines Ei, control signal lines CSi, first power lines PL1 to third power lines PL3, initialization power lines IPL, and first shielding electrode lines SDL1 to third shielding electrode lines SDL3.

[0407] The pixel PXL may include a display element layer DPL having a light emitting element LD and a pixel circuit layer PCL driving the light emitting element LD.

[0408] The pixel circuit layer PCL may include an alignment unit 145 for aligning the light emitting element LD in the light emitting area EMA of the pixel PXL, a pixel circuit 144 for driving the light emitting element LD, and a protection layer PSV covering the alignment unit 145 and the pixel circuit 144 .

[0409] The display element layer DPL may include a plurality of light emitting elements LD, first and second electrodes EL1 and EL2 , first and second conductive lines CL1 and CL2 , a contact electrode CNE, and the like.

[0410] The pixel circuit 144 may include first to seventh transistors T1 to T7 and first and second capacitors C1 and C2. In an embodiment of the present disclosure, the alignment unit 145 may include one or more switches SW (hereinafter, referred to as "switches") turned on / off by a control signal supplied from a control signal line CSi.

[0411] The switch SW included in the alignment unit 145 may be implemented by transistors having the same type as the first to seventh transistors T1 to T7 of the pixel circuit 144 .

[0412] The switch SW may include a switch active pattern ACT_SW, a first terminal SW_1 , a second terminal SW_2 , and a switch gate electrode GE_SW.

[0413] The switch active pattern ACT_SW, the first terminal SW_1, and the second terminal SW_2 may be formed of a semiconductor layer not doped with impurities or doped with impurities. For example, the first terminal SW_1 and the second terminal SW_2 may be formed of a semiconductor layer doped with impurities, and the switch active pattern ACT_SW may be formed of a semiconductor layer not doped with impurities.

[0414] The switch gate electrode GE_SW may be connected to the control signal line CSi. The switch gate electrode GE_SW may be a part of the control signal line CSi or may have a shape protruding from the control signal line CSi.

[0415] When viewed on a plane, the switching active pattern ACT_SW may extend along the second direction DR2 and may overlap the switching gate electrode GE_SW.

[0416] One end of the first terminal SW_1 may be connected to the switch active pattern ACT_SW, and the other end of the first terminal SW_1 may be connected to the first protruding electrode PRP1 through a thirteenth contact opening (e.g., a thirteenth contact hole) CH13 penetrating the gate insulating layer GI and the first and second interlayer insulating layers ILD1 and ILD2. One end of the second terminal SW_2 may be connected to the switch active pattern ACT_SW, and the other end of the second terminal SW_2 may be connected to the first bridge pattern BRP1 through a twelfth contact opening (e.g., a twelfth contact hole) CH12 penetrating the gate insulating layer GI and the first and second interlayer insulating layers ILD1 and ILD2.

[0417] In an embodiment of the present disclosure, when the switch SW is a transistor, either one of the first terminal SW_1 and the second terminal SW_2 may be a source electrode, and the other one of the first terminal SW_1 and the second terminal SW_2 may be a drain electrode.

[0418] The first protruding electrode PRP1 may have a shape protruding from the third power line PL3 in the first direction DR1 and may be a region of the third power line PL3. Since the first protruding electrode PRP1 corresponds to a region of the third power line PL3, the first terminal SW_1 may be connected to the third power line PL3 through the thirteenth contact opening CH13 and the first protruding electrode PRP1.

[0419] The first bridge pattern BRP1 may be connected to the second terminal SW_2 through the twelfth contact opening CH12. In addition, the first bridge pattern BRP1 may be connected to the third shielding electrode line SDL3 through the fifteenth contact opening (fifteenth contact hole) CH15 penetrating the third interlayer insulating layer ILD3. In addition, the first bridge pattern BRP1 may be connected to the first shielding electrode line SDL1 through the seventeenth contact opening (e.g., seventeenth contact hole) CH17 penetrating the third interlayer insulating layer ILD3. Therefore, the first shielding electrode line SDL1 and the third shielding electrode line SDL3 may be electrically connected to each other through the first bridge pattern BRP1.

[0420] The first shielding electrode line SDL1 may be connected to the second conductive line CL2 of the display element layer DPL through an eighteenth contact opening (e.g., an eighteenth contact hole) CH18 penetrating the protection layer PSV. When viewed on a plane, the second conductive line CL2 may be disposed on the first shielding electrode line SDL1 with the protection layer PSV interposed therebetween to overlap with the first shielding electrode line SDL1.

[0421] The third shielding electrode line SDL3 may be connected to the first electrode EL1 of the display element layer DPL through the sixteenth contact opening (e.g., the sixteenth contact hole) CH16 penetrating the protection layer PSV. When viewed on a plane, the first electrode EL1 may be disposed on the third shielding electrode line SDL3 with the protection layer PSV interposed therebetween to overlap with the third shielding electrode line SDL3.

[0422] As described above, when the first and third shielding electrode lines SDL1 and SDL3 are connected to each other through the first bridge pattern BRP1, the first electrode EL1 on the third shielding electrode line SDL3 and the second conductive line CL2 on the first shielding electrode line SDL1 may be electrically connected to each other.

[0423] When a control signal having a voltage capable of turning on the switch SW is transmitted from the control signal line CSi to the switch gate electrode GE_SW, the switch SW is turned on and the ground voltage GND of the third power line PL3 can be concurrently (e.g., simultaneously) transmitted to the first electrode EL1 and the second conductive line CL2 of the display element layer DPL through the first bridge pattern BRP1.

[0424] When a control signal having a voltage that can turn off the switch SW is transmitted from the control signal line CSi to the switch gate electrode GE_SW, the switch SW is turned off and the third power line PL3 and the first bridge pattern BRP1 can be electrically isolated from each other. Although the third power line PL3 and the first bridge pattern BRP1 are electrically isolated from each other, the first electrode EL1 and the second conductive line CL2 can be electrically connected to each other through the first bridge pattern BRP1. Therefore, the first driving power VDD can be transmitted to each of the first electrode EL1 and the second conductive line CL2 via the pixel circuit 144.

[0425] When the switch SW is turned on, an alignment voltage (eg, AC voltage) may be applied to the second power line PL2 , and when the switch SW is turned off, a second driving power source VSS may be applied to the second power line PL2 .

[0426] In an embodiment of the present disclosure, the second power line PL2 may be electrically connected to the second electrode EL2 of the display element layer DPL through a tenth contact opening (e.g., a tenth contact hole) CH10 penetrating the protection layer PSV. In addition, the second power line PL2 may be connected to the second bridge pattern BRP2 through an eleventh contact opening (e.g., an eleventh contact hole) CH11 penetrating the third interlayer insulating layer ILD3.

[0427] The second bridge pattern BRP2 may be connected to the second power line PL2 through the eleventh contact opening CH11. In addition, the second bridge pattern BRP2 may be connected to the second shielding electrode line SDL2 through the fourteenth contact opening (e.g., the fourteenth contact hole) CH14 penetrating the third interlayer insulating layer ILD3. Therefore, the second power line PL2 and the second shielding electrode line SDL2 may be connected to each other through the second bridge pattern BRP2.

[0428] The second shielding electrode line SDL2 may be connected to the first conductive line CL1 through a twentieth contact opening (e.g., a twentieth contact hole) CH20 penetrating the protection layer PSV. When viewed on a plane, the first conductive line CL1 may be disposed on the second shielding electrode line SDL2 with the protection layer PSV interposed therebetween to overlap with the second shielding electrode line SDL2.

[0429] As described above, when the second shielding electrode line SDL2 and the second power line PL2 are connected to each other through the second bridge pattern BRP2, the first conductive line CL1 on the second shielding electrode line SDL2 and the second electrode EL2 on the second power line PL2 may be electrically connected to each other.

[0430] Therefore, when the switch SW is turned on, the alignment voltage applied to the second power line PL2 can be transmitted to each of the second electrode EL2 and the first conductive line CL1. In addition, when the switch SW is turned off, the second driving power VSS applied to the second power line PL2 can be transmitted to each of the second electrode EL2 and the first conductive line CL1.

[0431] Fig.14 is corresponding to Figure 2 EA is an enlarged plan view of a portion EA shown in , and is a view schematically showing an embodiment in which the first to third switches are provided in a non-display area of ​​the display device.

[0432] Fig.14 Each of the first pixel and the second pixel shown in FIG. Figure 4 The configuration of the pixels shown in is the same or a substantially similar configuration.

[0433] Therefore, relative to Fig.14 , the parts different from those in the above-described embodiments will be mainly described to avoid redundancy. The parts not specifically described in this embodiment follow the parts in the above-described embodiments. In addition, the same reference numerals represent the same components, and similar reference numerals represent similar components.

[0434] For convenience of description, based on two pixels PXL1 and PXL2 that are disposed most adjacent to (eg, immediately adjacent to) the non-display area NDA in the display area DA of the substrate and positioned on the same pixel column, Fig.14 Scan lines S0, S1, S2, and S3, a data line Dj, emission control lines E1 and E2, first to third power lines PL1 to PL3, and an initialization power line IPL connected to the two pixels PXL1 and PXL2 are shown.

[0435] In addition, Fig.14 , for ease of description, among the lines provided to (e.g., connected to) the two pixels PXL1 and PXL2, a scan line located on a dummy row among the scan lines S0, S1, S2, and S3 to which a scan signal is applied is referred to as a “dummy scan line S0,” a scan line located on the first row is referred to as a “first scan line S1,” a scan line located on the second row is referred to as a “second scan line S2,” and a scan line located on the third row is referred to as a “third scan line S3.”

[0436] In addition, among the lines provided to the two pixels PXL1 and PXL2, the emission control lines on the first row to which the emission control signals are applied are referred to as “first emission control lines E1” and the emission control lines on the second row are referred to as “second emission control lines E2”.

[0437] exist Fig.14 , the structure of one pixel PXL is simplified and illustrated, wherein each electrode is illustrated as a single electrode layer and each insulating layer is illustrated as a single insulating layer. However, the present disclosure is not limited thereto.

[0438] Reference Figure 1A , Figure 2 and Fig.14 , a display device according to an embodiment of the present disclosure may include a substrate SUB, a line unit, and first and second pixels PXL1 and PXL2.

[0439] The first pixel PXL1 may be a pixel disposed in an intersection area of ​​a first row and a second column in the display area DA, and the second pixel PXL2 may be a pixel disposed in an intersection area of ​​a second row and a second column in the display area DA.

[0440] The line unit may provide a signal to each of the first pixel PXL1 and the second pixel PXL2 disposed in the display area DA, and may include scan lines S0 to S3, data lines Dj, emission control lines E1 and E2, first to third power lines PL1 to PL3, initialization power lines IPL, and first to third shielding electrode lines SDL1 to SDL3.

[0441] The data line Dj may extend along the second direction DR2 and may be provided in common to (e.g., connected in common to) the first pixel PXL1 and the second pixel PXL2 positioned on the same column. The first to third power lines PL1 to PL3 may extend along the second direction DR2 and may be provided in common to the first pixel PXL1 and the second pixel PXL2. The initialization power line IPL may extend along the second direction DR2 and may be provided in common to the first pixel PXL1 and the second pixel PXL2. The first to third shielding electrode lines SDL1 to SDL3 may extend along the second direction DR2 and may be provided in common to the first pixel PXL1 and the second pixel PXL2.

[0442] The dummy scan line S0, the first scan line S1, the second scan line S2, and the first emission control line E1 included in the components in the line unit may be provided to the first pixel PXL1. In addition, the first scan line S1, the second scan line S2, and the third scan line S3, and the second emission control line E2 included in the components in the line unit may be provided to the second pixel PXL2.

[0443] In an embodiment of the present disclosure, each of the first pixel PXL1 and the second pixel PXL2 may include a display element layer DPL having a light emitting element LD and a pixel circuit layer PCL driving the light emitting element LD and connected to a line unit.

[0444] The pixel circuit layer PCL may include a pixel circuit 144 for driving the light emitting element LD aligned in the light emitting area EMA of each of the first pixel PXL1 and the second pixel PXL2 and a protection layer PSV covering the pixel circuit 144 .

[0445] The pixel circuit 144 of each of the first pixel PXL1 and the second pixel PXL2 may include first to seventh transistors T1 to T7 and first and second capacitors C1 and C2. The seventh drain electrode DE7 of the seventh transistor T7 of the first pixel PXL1 may be connected to the initialization power line IPL provided to the second pixel PXL2 through the twenty-seventh contact opening (e.g., the twenty-seventh contact hole) CH27 penetrating the gate insulating layer GI and the first and second interlayer insulating layers ILD1 and ILD2. Therefore, the seventh transistor T7 of the first pixel PXL1 may be electrically connected to the 4a-th transistor T4a of the second pixel PXL2.

[0446] The display element layer DPL of each of the first pixel PXL1 and the second pixel PXL2 may include a light emitting element LD, first and second electrodes EL1 and EL2 , first and second conductive lines CL1 and CL2 , a contact electrode CNE, and the like.

[0447] First to third switches SW1 to SW3 for aligning the light emitting element LD in the emission area EMA of each of the first and second pixels PXL1 and PXL2 may be disposed in a non-display area NDA positioned at a periphery of the display area DA of the display device.

[0448] The first to third switches SW1 to SW3 may be disposed in the non-display area NDA to correspond to the same column as the first and second pixels PXL1 and PXL2. The first to third switches SW1 to SW3 may be electrically and / or physically connected to some of the lines commonly provided to the first and second pixels PXL1 and PXL2.

[0449] The control signal line CS may be disposed in the non-display area NDA. The control signal line CS may include the same conductive material as the scan lines S0 to S3, and may be disposed and / or formed on the gate insulating layer GI by the same process. The gate electrodes GE_SW1, GE_SW2, and GE_SW3 of each of the first to third switches SW1 to SW3 may be connected to the control signal line CS. When a control signal having a voltage that may turn on the first to third switches SW1 to SW3 is supplied from the control signal line CS, the first to third switches SW1 to SW3 may be turned on concurrently (e.g., simultaneously).

[0450] When the first switch SW1 and the second switch SW2 are turned on, the third power line PL3 commonly provided to the first pixel PXL1 and the second pixel PXL2 may be electrically connected to the first electrode EL1 and the second conductive line CL2 of each of the first pixel PXL1 and the second pixel PXL2. Therefore, the ground voltage GND applied to the third power line PL3 may be transferred to the first electrode EL1 and the second conductive line CL2 of each of the first pixel PXL1 and the second pixel PXL2.

[0451] When the first switch SW1 and the third switch SW3 are turned on, the second power line PL2 commonly provided to the first pixel PXL1 and the second pixel PXL2 may be electrically connected to the second electrode EL2 and the first conductive line CL1 of each of the first pixel PXL1 and the second pixel PXL2. Therefore, an alignment voltage (e.g., an AC voltage) applied to the second power line PL2 may be delivered to the second electrode EL2 and the first conductive line CL1 of each of the first pixel PXL1 and the second pixel PXL2.

[0452] As described above, when the first to third switches SW1 to SW3 disposed in the non-display area NDA are concurrently (e.g., simultaneously) turned on, the ground voltage GND may be applied to the first electrode EL1, the alignment voltage may be applied to the first conductive line CL1, the ground voltage GND may be applied to the second conductive line CL2, and the alignment voltage may be applied to the second electrode EL2. Therefore, an electric field may be formed by a potential difference between the first electrode EL1 and the first conductive line CL1, between the first conductive line CL1 and the second conductive line CL2, and between the second conductive line CL2 and the second electrode EL2.

[0453] The light emitting element LD may be aligned in the emission area EMA of each of the first pixel PXL1 and the second pixel PXL2 by electric fields formed between the first electrode EL1 and the first conductive line CL1 , between the first conductive line CL1 and the second conductive line CL2 , and between the second conductive line CL2 and the second electrode EL2 , respectively.

[0454] After the alignment of the light emitting element LD in the light emitting area EMA of each of the first pixel PXL1 and the second pixel PXL2 is completed, a control signal having a voltage that can disconnect the first switch SW1 to the third switch SW3 is supplied from the control signal line CS to the first switch SW1 to the third switch SW3, so that the first switch SW1 to the third switch SW3 are disconnected.

[0455] As described above, in the display device according to an embodiment of the present disclosure, by using one or more switches having the same type as the first transistor T1 to the seventh transistor T7 included in the pixel circuit 144, the light emitting element LD is aligned in the light emitting area EMA of each pixel PXL, and the one or more switches are disconnected after the light emitting element LD is aligned, so that each pixel PXL can be driven individually relative to the adjacent pixel PXL.

[0456] Therefore, in the display device according to the embodiment of the present disclosure, a process of removing a portion of the alignment line so that each pixel PXL can be driven individually with respect to adjacent pixels PXL, etc. is omitted, thereby simplifying the manufacturing process of the display device.

[0457] According to an embodiment of the present disclosure, light emitting elements are aligned in each pixel by using an alignment unit having one or more switches connected to a pixel circuit, thereby simplifying a manufacturing process of a display device by omitting a separate process for aligning lines of light emitting elements.

[0458] In addition, according to the embodiments of the present disclosure, the risk of defects that may occur during a separation process for aligning lines of light emitting elements is reduced or minimized, so that the reliability of the display device may be improved.

[0459] Exemplary embodiments of the present disclosure are disclosed herein, and although specific terms are employed, these terms should be used and interpreted in a general and descriptive sense, and not for limiting purposes. In some cases, as will be apparent to one of ordinary skill in the art upon filing this application, features, characteristics, and / or elements described in conjunction with one embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise specifically indicated. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made to the described embodiments without departing from the spirit and scope of the present disclosure as set forth in the appended claims and their equivalents.

Claims

1. A display device, comprising: a substrate, including pixels; A scanning line, used for supplying a scanning signal to the pixel; A data line, used for supplying a data signal to the pixel; A first power line, used for supplying a first driving power source to the pixel; A second power line, used for supplying a second driving power source to the pixel; as well as a third power line, for supplying a ground voltage to the pixel; Wherein, the pixels include: a first electrode and a second electrode spaced apart from each other on the substrate; a plurality of light emitting elements, each of the light emitting elements having a first end and a second end in a length direction of the light emitting element and arranged between the first electrode and the second electrode; a first conductive line and a second conductive line, the first conductive line and the second conductive line being located between the first electrode and the second electrode when viewed on a plane; and The first switch is electrically connected between the third power line and the first electrode, and the first switch is configured to be turned on by a control signal.

2. The display device according to claim 1, wherein: The first conductive line and the second conductive line are located on the same plane as the first electrode and the second electrode, and the first conductive line and the second conductive line are spaced apart from each other.

3. The display device according to claim 2, wherein: When the first switch is turned on, an alternating voltage having a level different from that of the second driving power source is applied to the second electrode.

4. The display device according to claim 3, wherein: The pixel also includes: a control signal line configured to have the control signal applied to the control signal line; a second switch connected between the second conductive line and the first electrode, the second switch being configured to be turned on concurrently with the first switch by the control signal; and A third switch is connected between the first conductive line and the second power line, and the third switch is configured to be turned on concurrently with the first switch by the control signal.

5. The display device according to claim 4, wherein: The first conductive line and the second conductive line are floating electrodes.

6. The display device according to claim 5, wherein: The control signal line is located in the same layer as the scan line.

7. The display device according to claim 6, wherein: Each of the first switch, the second switch, and the third switch includes a thin film transistor.

8. The display device according to claim 7, wherein: Each of the first switch, the second switch, and the third switch includes: A gate electrode, located on the substrate, wherein the gate electrode is integrated with the control signal line; an active pattern overlapping a region of the gate electrode; and The first terminal and the second terminal contact two ends of the active pattern.

9. The display device according to claim 8, wherein: The pixel further includes: a pixel circuit connected between the first power line and the first electrode or between the second power line and the second electrode, and The pixel circuit includes a driving transistor for driving the light emitting element and a switching transistor connected between the data line and the driving transistor.

10. The display device according to claim 9, wherein: The driving transistor and the switching transistor include transistors having the same type as the first switch, the second switch, and the third switch.

11. The display device according to claim 10, wherein: When the first switch, the second switch, and the third switch are concurrently turned on, the ground voltage is supplied to the first electrode and the AC voltage is applied to the second electrode, so that an electric field is formed between the first electrode and the second electrode.

12. The display device according to claim 10, wherein: When the first switch, the second switch, and the third switch are concurrently turned off, the first driving power is applied to the first electrode via the pixel circuit, and the second driving power is applied to the second electrode.

13. The display device according to claim 10, wherein: The pixel circuit further comprises: a first capacitor connected between the gate electrode of the driving transistor and the first power line; and The second capacitor is connected between the first electrode and the second power line.

14. The display device according to claim 13, wherein: The first capacitor comprises: A first lower electrode, located on the substrate; a first upper electrode, located on the first lower electrode; and an interlayer insulating layer interposed between the first lower electrode and the first upper electrode, Wherein, the second capacitor comprises: a second lower electrode, the second lower electrode being located in the same layer as the first lower electrode; a second upper electrode, located on the second lower electrode; and the interlayer insulating layer is interposed between the second lower electrode and the second upper electrode, and The first upper electrode and the second upper electrode are located in the same layer.

15. The display device according to claim 14, wherein: The first conductive line is electrically connected to the second electrode through a third bridge pattern, and The second conductive line is electrically connected to the first electrode through a second bridge pattern spaced apart from the third bridge pattern.

16. The display device according to claim 15, wherein: The third bridge pattern and the second bridge pattern are located in the same layer as the data line.

17. The display device according to claim 16, wherein: When the first switch is turned on, the ground voltage is applied to each of the second conductive line and the first electrode, and the AC voltage is applied to each of the first conductive line and the second electrode, so that an electric field is formed between the first electrode and the second electrode.

18. The display device according to claim 17, wherein: The pixel also includes: A first shielding electrode line, located between the second conductive line and the interlayer insulating layer; a second shielding electrode line, located between the first conductive line and the interlayer insulating layer; and The third shielding electrode line is located between the first electrode and the interlayer insulating layer.

19. The display device according to claim 1, wherein: The pixel also includes: a first contact electrode electrically connecting any one of the first end portion and the second end portion of each of the light emitting elements to the first electrode; and A second contact electrode electrically connects the other of the first end portion and the second end portion of each of the light emitting elements to the second electrode.

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