Operation timing analysis device and method considering multi-input switching

Abstract

An operation timing analysis device for a semiconductor device considering multi-input switching (MIS) is provided, comprising: a timing input unit, which generates a MIS model for each of a plurality of units constituting the semiconductor device; and a MIS analyzer, which receives timing data for each of the plurality of units and dynamically calculates a MIS coefficient based on the MIS model and the timing data.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] Priority is claimed on Korean Patent Application No. 10-2019-0009811 filed on January 25, 2019, in the Korean Intellectual Property Office (KIPO), the subject matter of which is incorporated herein by reference. Technical Field

[0003] Embodiments of the inventive concept are directed to providing an apparatus and method for providing operation timing analysis related to a semiconductor device including an element or component providing multiple input switching (MIS). Background Art

[0004] Contemporary semiconductor devices are very complex in their design, performance characterization, manufacturing and operation. A wide variety of electrical signals are generated, transmitted, routed and received (hereinafter collectively referred to as "communication") between various circuits, sub-circuits, components, circuit elements, etc. (hereinafter collectively referred to as "elements"). Exemplary semiconductor elements include at least logic elements such as AND, NAND, OR, NOR gates, and combinations thereof (e.g., so-called "AND-OR-Inverting" or "AOI" gates).

[0005] Some semiconductor components receive only a single signal input (single input switching or SIS), while other semiconductor components receive multiple signal inputs (multiple input switching or MIS). Here, many MIS components include multiple transistors that operate in parallel in response to one or more signals. In general, the signal delay associated with MIS components is shorter than the signal delay associated with SIS components.

[0006] Considering the overall complexity involved in the design of contemporary semiconductor devices, it is not surprising that many automated tools are used in the process. In such electronic design automation (EDA) tools, various signal propagation considerations and signal timing relationships must be understood to improve the overall performance of the resulting semiconductor device. Unfortunately, many signal performance analyses of many semiconductor components (e.g., logic cells) make assumptions based on SIS component behavior predictions. Therefore, the analysis caused by these assumptions may not accurately reflect the actual operation of the MIS component. In extreme cases, semiconductor performance that is not well understood and not adequately designed may lead to operational failures (e.g., signal hold time failures). Summary of the invention

[0007] Embodiments of the inventive concept provide apparatus and methods for modeling a multiple-input switching (MIS) element (eg, a logic gate or a cell) in a semiconductor device.

[0008] Embodiments of the inventive concept provide a MIS analysis apparatus and method of a semiconductor device, which can improve the accuracy and efficiency of operation timing analysis by accurately reflecting MIS analysis using a graph-based analysis (GBA) method when analyzing operation timing of a semiconductor device.

[0009] An operation timing analysis device of a semiconductor device including an MIS element according to an embodiment of the present invention includes a timing input unit and a MIS analyzer. The timing input unit generates a MIS model for each of a plurality of units constituting the semiconductor device. The MIS analyzer receives timing data for each of the plurality of units and dynamically calculates a MIS coefficient based on the MIS model and the timing data.

[0010] An operation timing analysis device for a semiconductor device considering the MIS effect according to an embodiment of the inventive concept includes a static timing analysis (STA) module and a MIS analyzer. The STA module generates timing data for each of a plurality of cells constituting the semiconductor device. The MIS analyzer receives a MIS model for each of the plurality of cells and dynamically calculates a MIS coefficient based on the MIS model and the timing data.

[0011] An operation timing analysis method of a semiconductor device including an MIS element according to an embodiment of the present invention includes: generating a model of each of a plurality of MIS elements; generating timing data without considering the MIS effect of each MIS element; calculating the MIS coefficient of each MIS element based on the MIS model and the timing data; and performing STA considering the MIS effect on each MIS element based on the MIS coefficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a block diagram illustrating an operation timing analysis apparatus of a semiconductor device that accurately reflects an MIS effect according to an embodiment of the inventive concept.

[0013] Figure 2 is a flow chart outlining a method of analyzing operation timing of a semiconductor device reflecting MIS effects in one example.

[0014] Figure 3 is a conceptual diagram showing a driving method for an MIS model generator in one example.

[0015] Figure 4 is another conceptual diagram illustrating a driving method for an MIS analyzer in one example.

[0016] Figure 5 is a conceptual diagram showing a set of signal waveforms and a method of generating an MIS model and MIS coefficients.

[0017] Figure 6 is a diagram further illustrating the machine learning method for generating the merged model.

[0018] Figure 7 is another conceptual diagram illustrating a method of calculating the MIS current and the MIS delay.

[0019] Figure 8 is another conceptual diagram illustrating a method of generating a delayed report for a MIS change.

[0020] Fig. 9 is another conceptual diagram illustrating a method of generating minimum operations for MIS optimization.

[0021] The above and other objects, features and advantages of the present inventive concept will become more apparent to those skilled in the art by describing in detail exemplary embodiments of the present inventive concept with reference to the accompanying drawings. DETAILED DESCRIPTION

[0022] Certain embodiments of the inventive concept will now be described with reference to the accompanying drawings. As descriptive examples, these embodiments at least teach the making and use of a specific operation timing analysis device and a corresponding method. Here, the operation timing analysis device and / or method can be beneficially applied to the design, performance characterization, manufacture and / or analysis of semiconductor devices, especially semiconductor devices including MIS components.

[0023] A certain phenomenon has been noted previously in connection with the operation of MIS components. That is, when multiple transistors are switched simultaneously in a MIS component, the signal delay of the MIS component (i.e., the time period required for the signal to propagate through the component) is less than the analog signal delay of the SIS component. Therefore, when conventional operation timing analysis - which cannot accurately distinguish between MIS component signal delay and SIS component signal delay - is performed on certain semiconductor devices, erroneous signal timing conclusions may be obtained. As a result, the actual operation timing differs from the expected (or designed) operation timing, and this variation may cause semiconductor device failure.

[0024] In view of these potential undesirable results, certain embodiments of the present invention provide an operation timing analysis apparatus and / or method that properly considers the presence and actual operation of MIS elements within a semiconductor device. In a related method, one or more MIS coefficients designated as inputs to the operation timing analysis can be used. For example, when the input signal arrival times overlap, the corresponding signal delay can be reduced by applying (e.g., multiplying) the MIS coefficients, so that the MIS phenomenon is taken into account and the input signal arrival times are defined so that they do not arrive in an overlapping manner.

[0025] In another related approach, MIS coefficients may be used to appropriately modify static timing analysis (STA) when overlapping timing windows of signals applied to input pins of a semiconductor device occur.

[0026] The apparatus and method for operation timing analysis of a semiconductor device according to an embodiment of the present invention can use various timing information and a composite current source (CCS) to calculate the MIS coefficient to accurately reflect the MIS phenomenon. In addition, when performing a graph-based analysis (GBA) for operation timing analysis, unnecessary elements can be eliminated by optimizing the minimum operation.

[0027] Figure 1 is a block diagram illustrating an operation timing analysis apparatus of a semiconductor device that may be used to accurately reflect a MIS phenomenon according to an embodiment of the inventive concept.

[0028] Reference Figure 1 , the operation timing analysis apparatus 10 may include a timing input unit 100, a MIS analyzer 200, and a static timing analysis (STA) module 300. The timing input unit 100 may include an integrated circuit (IC) design list 110 (e.g., a netlist), a timing library database (DB) 120, and a MIS model generator 130. The MIS analyzer 200 may include a MIS timing path generator 210, a MIS coefficient generator 220, and a MIS timing information update module 230.

[0029] The components of the timing input unit 100, the MIS analyzer 200, and the STA module constituting the operation timing analysis apparatus 10 may be configured differently using software, hardware, and / or firmware. For example, Figure 1 The operation timing analysis apparatus 10 may be implemented as one or more software programs on a general computing platform (eg, a PC, a laptop, a tablet computer, or a smart phone).

[0030] Figure 2 is a flow chart illustrating a method of analyzing operation timing of a semiconductor device while accurately reflecting the MIS phenomenon in one example. Figure 3 It further shows Figure 1 A conceptual diagram of a possible driving method of the MIS model generator 130.

[0031] Common Reference Figure 1 , 2 and 3, STA module 300 can be used to perform STA as long as an accurate MIS model has been previously generated.

[0032] Therefore, the timing input unit 100 can load the IC design list 110 for the semiconductor device being analyzed, and also load the corresponding timing information for the loaded IC design list from the timing library DB 120. Then, the MIS model generator 130 can generate the MIS model 130a based on the loaded IC design list and the timing information. Since the effect caused by the presence of the MIS element may not only affect the basic unit delay, but also affect the change therein, the MIS change model 130b (S10) can be generated considering this change. The timing input unit 100 can generate MIS model 130a and MIS change model 130b for each of the multiple elements (e.g., cells or logic gates) in the semiconductor device or some of its parts (e.g., chips, chip parts, semiconductor layers, designated circuits or circuit parts, etc.).

[0033] The timing input unit 100 can use the MIS simulation results and the SIS simulation results as training sets for machine learning to generate a learning model. For example, the timing input unit 100 can calculate the MIS coefficient according to the following equation to generate a learning model:

[0034] y=b1*x1+b2*x2+b3*x3+b4*x4+b5,

[0035] Where "y" is the value to be predicted, and "x1, x2, ..." are the independent variables that affect "y".

[0036] Here, the sequential input unit 100 may define "y" and "x1, x2, . . . " to generate training data. The sequential input unit 100 may complete the function of calculating "y" by numerically calculating "b1, b2, . . . , b5". Then, the sequential input unit 100 may predict the value of "y" when actual data is input.

[0037] The timing input unit 100 can generate a prediction model function for on-chip variation (OCV) sigma associated with the MIS element based on the training set. The timing input unit 100 can generate a MIS variation model based on the prediction model function of the OCV sigma (OCV_sigma) of the MIS according to the process variation. When the nominal signal delay is short due to the MIS phenomenon, the OCV sigma associated with the MIS element may be less than the typical OCV sigma (OCV_sigma). The timing input unit 100 can use the prediction model of the OCV sigma OCV_sigma to generate the MIS variation model to improve the accuracy of the MIS analysis of the MIS element (e.g., unit).

[0038] Figure 4 It is further shown in an example for Figure 1 Another flow chart of the driving method of the MIS analyzer 200.

[0039] Reference now Figure 1 , 2 In step S20, the STA module 300 may acquire timing data by performing STA without considering the MIS effect. The timing data acquired in the STA module 300 may include arrival time data, conversion data, load data, and delay data. The STA module 300 may provide the arrival time data, conversion data, load data, and delay data to the MIS analyzer 200. The STA module 300 may acquire arrival time data, conversion data, load data, and signal delay data of each of a plurality of MIS elements (e.g., a plurality of cells) constituting a portion of a semiconductor device (e.g., a chip) without considering the MIS effect.

[0040] Subsequently, the MIS analyzer 200 may dynamically calculate the MIS coefficient based on the MIS model generated by the timing input unit 100 and the arrival time data, transition data, load data, and delay data acquired in the STA module 300 without considering the MIS effect (S30).

[0041] The MIS timing path generator 210 can obtain the timing path of the MIS by analyzing the functional attributes of each of the multiple units constituting the chip. The MIS timing path generator 210 can obtain the timing path in which the delay may change due to the MIS effect. That is, the MIS timing path generator 210 can generate a timing path from the input pin of the unit to the output pin of the unit. The MIS timing path generator 210 analyzes the signal delay of the output switching by switching the input in two or more parallels, and can obtain a path in which the delay is shortened by inputting two or more signals at the same time. The MIS timing path generator 210 can obtain the timing path in which the delay is shortened due to the MIS by parsing the functional attributes stored in the timing library DB 120.

[0042] The MIS coefficient generator 220 of the MIS analyzer 200 may analyze the arrival windows of all MIS timing paths. When STA is performed, the MIS coefficients may be applied when the timing windows of the input pins overlap with each other.

[0043] The MIS coefficient generator 220 can dynamically calculate the MIS coefficient using timing data (e.g., arrival window, conversion data, load data, etc.) and the MIS model. The MIS coefficient generator 220 can merge the values ​​of multiple currents flowing from multiple input pins to multiple output pins of the semiconductor device to generate a merged current (i.e., merged I(t)) value. In order to generate the merged I(t), a method for merging current values ​​should be pre-set. In some embodiments of the present inventive concept, a machine learning method can be used to generate a merged model.

[0044] Subsequently, the MIS timing information update module 230 of the MIS analyzer 200 may update the arrival time of the output pin of the semiconductor device (e.g., IC chip) after reflecting the effect of the MIS (or "MIS impact") (S40). The MIS timing information update module 230 may update the arrival time of the output pin of the semiconductor device (e.g., IC chip) by reflecting the MIS impact. The MIS timing information update module 230 may include a minimum operation optimized for MIS while updating the arrival time of the output pin. That is, the MIS timing information update module 230 may update the MIS timing information, which includes indicating the minimum operation of the input pin with the minimum timing among the multiple input pins.

[0045] Therefore, the described "functional attributes" can be used to represent the logical relationship between input pins and output pins. As an example, in the case of an AND / OR unit, output pin Y can have the following relationship with input pins A and B.

[0046] AND(unit)Y=(A and B) (Example 1)

[0047] OR(unit)Y=(A or B). (Example 2)

[0048] Analysis of the functional properties shows that in the case of the OR cell (Example 2), when A and B become 1 simultaneously (eg, rise time transition), the cell delay is shortened due to MIS.

[0049] Subsequently, the STA module 300 may perform STA considering the MIS effect (S50). As an example, the STA module 300 may analyze the arrival window to calculate the timing variation due to the MIS effect. The STA module 300 may analyze the arrival window of each pin along the MIS timing path, and calculate the timing variation due to the MIS effect by applying the MIS coefficient when the arrival windows overlap each other.

[0050] When the arrival windows do not overlap each other, the STA module 300 can set the MIS coefficient to a default value (e.g., 1.0) and calculate the timing change without considering the MIS effect. That is, the MIS effect can be applied not only to the default unit delay, but also to the change. Finally, the effect caused by MIS can be reflected in the timing. When the output pins are to be merged, the STA module 300 can perform the minimum operation optimized for MIS.

[0051] Figure 5 It is a conceptual collective arrangement of signal waveforms, illustrating a method for generating an MIS model and associated MIS coefficients.

[0052] Reference Figure 5 , the operation timing analysis apparatus 10 may calculate the MIS effect using the CCS model by reflecting the pre-calculated timing information when STA is performed.

[0053] When a transition occurs from an input pin to an output pin based on SIS, the operation timing analysis apparatus 10 of the semiconductor device may store a waveform while performing STA.

[0054] The MIS analyzer 200 may calculate the value of the first SIS I(t) at the timing arc where the signal flows from the input terminal I1 to the output terminal O (I1→O). The MIS analyzer 200 may calculate the value of the second SIS I(t) at the timing arc where the signal flows from the input terminal I2 to the output terminal O (I2→O). The MIS analyzer 200 may calculate a merged I(t) reflecting the MIS situation by merging the value of the first SIS I(t) and the value of the second SIS I(t).

[0055] The MIS analyzer 200 may generate dynamic MIS coefficients. The MIS analyzer 200 may assume that the SIS delays are D1 and D2, respectively, and the combined delay of I(t) is Dm. Here, the dynamic MIS coefficients may be as follows: Figure 5 Dm / D1 and Dm / D2 shown.

[0056] Figure 6 is a diagram that further describes a machine learning method for generating a merged model in one example.

[0057] like Figure 2 and 6 As shown, the method of combining multiple current values ​​to generate a combined I(t) value may be predetermined. However, in some embodiments of the present inventive concept, a machine learning combination model may be used to generate a combined I(t).

[0058] The current may be generated and stored using a piecewise linear model, as shown below in Equation 1. A separate linear function for time may be defined for each timing interval and represented as a nonlinear waveform.

[0059]

[0060] Figure 7 is a conceptual diagram showing one possible method of calculating the MIS current and the MIS delay.

[0061] refer to Figure 1 , 2 , 3 and 7, the timing input unit 100 can perform MIS simulation under various conditions. After performing MIS simulation under various conditions, simulation of SIS can also be performed. The timing input unit 100 can record the results of MIS simulation and SIS simulation, as shown in Table 1 below.

[0062] Table 1

[0063]

[0064] In Table 1, the load upper limit for each time interval of each SIS current, as well as the slope and intercept of the linear function (e.g., training data) may be described. The current value for each interval may also be recorded for the MIS (e.g., training data). In Table 1, "I12(b1)" and "I12(b2)" are the outputs (y) of the training, and the rest may be input variables that affect y.

[0065] The MIS model generator 130 may generate a model “F” that predicts an intercept value in the next interval of a MIS element (eg) for each unit based on the training data.

[0066] Such a model is the result of training performed in advance by a machine learning method using characterization data before STA. The MIS model generated by the MIS model generator 130 may be used as an input to STA.

[0067] When STA is performed by the STA module 300, timing data (arrival time data, transition data, load data, delay data) such as the load upper limit value and the SIS current waveform of each pin after timing analysis can be obtained. Therefore, the STA module 300 can predict the MIS current by applying the timing data to the generated prediction model during characterization.

[0068] The STA module 300 may calculate the intercept of the MIS current. The intercept of the MIS current in the initial time interval may be zero (0). The intercept of the MIS current in the next time interval may be calculated using a model in which one or more MIS intercepts in the previous time interval, the slope of the SIS, and the intercept of the SIS are used as inputs.

[0069] As described above, the STA module 300 may calculate the intercept of the MIS current. The STA module 300 may calculate the MIS delay from the MIS current. The dynamic MIS coefficient may be calculated based on the ratio of the MIS delay to the original delay without considering the MIS.

[0070] Figure 8 is another conceptual diagram illustrating a method of generating a delayed report of MIS changes in one example.

[0071] refer to Figure 1 , 2 , 3 and 8, in order to take into account process variations, when STA is performed, the STA module 300 can analyze not only the nominal delay but also the variation. When STA is performed, the STA module 300 can perform analysis of the nominal delay and the variation to generate a 3-sigma level delay report consistent with Table 2 below.

[0072] Table 2

[0073]

[0074] Among them, Delay_reported=delay_nominal±3*ocv_sigma

[0075] Here, delay_nominal is the delay value when no variation is processed. OCV_sigma may refer to the delay variation at the 1-sigma level. In Table 2, "OCV_sigma" is the output of the training (y), and the rest may be input variables that affect y.

[0076] When the delay is changed due to the MIS effect, the variation may also be changed. Therefore, these two issues should be considered when performing an accurate analysis.

[0077] The MIS model generator 130 may generate a training set using the results of the MIS simulation and the SIS simulation. Subsequently, the MIS model generator 130 may generate a prediction model function "G" for each unit for the OCV sigma (OCV_sigma) of the MIS using the generated training set.

[0078] When performing actual timing analysis, the MIS analyzer 200 may use the MIS coefficient model F to calculate the MIS nominal delay.

[0079] In addition, when the nominal delay is input to the function "G" together with the SIS information of each input pin, the predicted value of the OCV sigma (OCV_sigma) of the MIS can be obtained. At this time, the MIS coefficient for change, that is, the dynamic MIS coefficient for change (dMCV) can be generated. Here, the dMCV can be calculated by the following equation 2.

[0080] dMCV=MIS_OCV_sigma / SIS_OCV_sigma Equation 2

[0081] Fig. 9 is a conceptual diagram illustrating a method of generating a minimum operation optimized for the MIS effect in one example.

[0082] Reference Figure 1 , 2 , 3 and 9, when there is an interval in which the arrival windows of three pins overlap each other, the operation timing analysis apparatus 10 of the semiconductor device may reflect the MIS coefficient (MC) for the timing arc.

[0083] Therefore, the operation timing analysis device 10 applies the GBA method when calculating the timing of multiple paths associated with a unit having multiple input pins. Here, the slowest path and the fastest path can be stored. The operation timing analysis device 10 of the semiconductor device can perform GBA and find the path where problems may occur in the delay timing of the signal. After finding the path that may cause the delay timing problem of the signal, path-based analysis (PBA) can be performed, and finally, the timing analysis can be completed.

[0084] The operation timing analysis device 10 can determine the minimum value at the output pin O, as shown in Table 3 below.

[0085] The operation timing analysis apparatus 10 of the semiconductor device can find the fastest path when the signal flows from three input pins A, B and C to the output pin O. Here, when the signal flows from multiple input pins to the output pin, finding the minimum delay, that is, the fastest path, can be referred to as "MIN operation".

[0086] Table 3

[0087]

[0088] The operation timing analysis device 10 can analyze the timing by dividing the arrival window based on the overlap. Therefore, unnecessary elements in the timing analysis can be eliminated.

[0089] exist Fig. 9, the operation timing analysis device 10 may divide the arrival window A associated with the pin A into a1, a2, and a3. Then, the operation timing analysis device 10 may accurately calculate the MIS effects associated with the divided windows ai, bi, and ci, as shown in Tables 4 and 5 below, where Table 4 is an example of calculating the MIS effect based on the nominal delay and Table 5 is an example of calculating the MIS effect based on the variation-aware timing.

[0090] Table 4

[0091]

[0092] As shown in Table 4, the operation timing analysis device 10 can calculate the MIS effect based on the nominal delay. The operation timing analysis device 10 of the semiconductor device can predict the path "a1→O:a1(e)+D1*dMC(A,B)" with the minimum delay among the paths flowing from the plurality of inputs a, b, and c to the output O, and the delay time "10+5*0.5=12.5" of the path "a1→O:a1(e)+D1*dMC(A,B)".

[0093] Table 5

[0094]

[0095] As shown in Table 5, the operation timing analysis device 10 can calculate the MIS effect according to the change perception timing. The operation timing analysis device 10 of the semiconductor device can predict the path "b1→O:b1(e)+D2" with the minimum delay among the paths flowing from the multiple inputs a, b and c to the output O, and the delay time "5+8-3*0.8=10.6" of the path "b1→O:b1(e)+D2".

[0096] An operation timing analysis apparatus and method for designing and characterizing a semiconductor device according to an embodiment of the inventive concept may dynamically generate the above-mentioned MIS coefficients using information and current waveforms generated when STA is performed.

[0097] The operation timing analysis device and method can obtain a combined current waveform in view of the MIS effect. To this end, a piecewise linear model can be used to combine the current waveform in the form of "a*t+b".

[0098] The operation timing analysis apparatus and method may iteratively calculate the value of the combined current while changing the time interval to calculate the combined current when the MIS occurs.

[0099] The operation timing analysis apparatus and method may perform machine learning to predict the value of OCV sigma (OCV_sigma).

[0100] The operation timing analysis apparatus and method can calculate the MIS impact for a subset of a defined window rather than the entire arrival window. Thus, unnecessary elements that may otherwise interfere with the minimum operation can be eliminated.

[0101] The operation timing analysis apparatus and method may dynamically generate MIS coefficients using information and current waveforms generated when STA is performed.

[0102] When the MIS effect exists, the operation timing analysis device and method can obtain a combined current waveform. To this end, a piecewise linear model can be used to combine the current waveform in the form of a*t+b.

[0103] The operation timing analysis apparatus and method may iteratively calculate the value of the merged current while changing the time interval to calculate the merged current when the MIS occurs.

[0104] The operation timing analysis apparatus and method may perform machine learning to predict the value of OCV sigma.

[0105] The operation timing analysis apparatus and method can calculate the MIS impact associated with a subset window rather than the entire arrival window. Therefore, unnecessary elements that appear in the minimum operation for finding the fastest path (the path with the minimum delay) can be eliminated.

[0106] Although the embodiments of the present invention have been described with reference to the accompanying drawings, it should be understood by those skilled in the art that various modifications may be made without departing from the scope of the present invention and without changing the basic features. Therefore, the above embodiments should be considered only as illustrative and not for limiting purposes.

Claims

1. An apparatus for operation timing analysis of a semiconductor device, comprising a MIS element taking into account a multi-input switching MIS effect, the apparatus comprising: a timing input unit that generates a MIS model for each MIS element; as well as an MIS analyzer that receives the timing data for each MIS element and dynamically calculates the MIS coefficients based on the MIS model and the timing data for each MIS element, When the arrival times of input signals input to the MIS element overlap, the MIS coefficient is applied to reduce the corresponding signal delay so that the input signals do not arrive in an overlapping manner. 2 . The apparatus of claim 1 , wherein the timing input unit loads timing data for the semiconductor device and a design list for the semiconductor device, and generates the MIS model based on the timing data and the design list.

3. The device according to claim 1, wherein: The timing input unit generates a training set using the results of MIS simulation and single-input switching SIS simulation, generates a prediction model function for on-chip variation OCV sigma of MIS based on the training set, and generates a MIS variation model based on the prediction model function for OCV sigma of MIS.

4. The device as claimed in claim 3, wherein: The MIS analyzer calculates a ratio of the MIS delay to the original delay without considering the MIS effect based on a prediction model function of the OCV sigma for the MIS effect, and generates a dynamic MIS coefficient based on the ratio of the MIS delay to the original delay.

5. The device according to claim 1, wherein: The timing data includes at least one of arrival time data, conversion data, load data, and delay data.

6. The apparatus of claim 1, wherein the timing input unit comprises a timing library database DB in which functional attributes of each MIS element are stored, and the MIS analyzer analyzes the functional attributes of each MIS element to obtain a MIS timing path whose delay is changed due to a MIS effect.

7. The apparatus of claim 6, wherein the MIS analyzer generates MIS timing information indicating an input pin having a minimum timing among a plurality of input pins for the MIS element.

8. An apparatus for operation timing analysis of a semiconductor device, comprising a MIS element taking into account a multi-input switching MIS effect, the apparatus comprising: Static Timing Analysis (STA) module, which generates timing data for each MIS element without considering MIS effects; as well as an MIS analyzer that receives the MIS model for each MIS element and dynamically calculates the MIS coefficients based on the MIS model and the timing data, The STA module performs STA taking into account the MIS effect based on the MIS coefficients.

9. The device of claim 8, wherein: The STA module obtains a MIS timing path for each of a plurality of input pins associated with a MIS element, analyzes an arrival window of the MIS timing path, and calculates a timing variation due to a MIS effect by applying a MIS coefficient when the arrival windows of the plurality of input pins overlap with each other.

10. The device of claim 8, wherein: The MIS model of each MIS element includes a MIS variation model based on a prediction model function of an OCV sigma for the MIS, and the STA module performs STA considering MIS effects based on the MIS variation model.

11. A method for analyzing the operation timing of a semiconductor device including an MIS element taking into account a multi-input switching MIS effect, the method comprising: Generate MIS models for each MIS component; Generate timing data for each MIS element without considering the MIS effect; Calculate the MIS coefficient of each MIS element based on the MIS model and the time series data; as well as STA considering the MIS effect is performed for each MIS element based on the MIS coefficient.

12. The method of claim 11, wherein generating a MIS model for each MIS component comprises: loading timing data for the semiconductor device and a design list for the semiconductor device; as well as Generates an MIS model based on the loaded timing data and design list.

13. The method of claim 11, wherein generating a MIS model for each MIS component comprises: Perform MIS simulation; Perform SIS simulation; Generate training sets using MIS simulation and SIS simulation; generating a prediction model function for OCV sigma of the MIS component based on the training set; and The MIS variation model is generated based on a predictive model function of the OCV sigma for the MIS components.

14. The method of claim 13, wherein generating the MIS change model further comprises: Calculate the ratio between the MIS delay and the original delay without considering the MIS effect based on the prediction model function of the OCV sigma for the MIS element, and A dynamic MIS coefficient is generated based on the ratio of the MIS delay to the original delay.

15. The method of claim 11, wherein: The timing data includes at least one of arrival time data, conversion data, load data, and delay data.

16. The method of claim 11, further comprising: Obtain the MIS timing path by analyzing the functional properties of MIS components; as well as By analyzing the functional properties of the MIS elements, the MIS timing paths with altered delays due to the MIS effect are obtained.

17. The method of claim 16, further comprising: The combined current value is generated by combining the values ​​of a plurality of currents flowing from a plurality of input pins to an output pin of the MIS element.

18. The method of claim 17, further comprising: MIS timing information is generated, which includes a minimum operation indicating an input pin having a minimum timing among the plurality of input pins.

19. The method of claim 16, further comprising: obtaining a MIS timing path for each of a plurality of input pins of the MIS component; Analyze the arrival window of the MIS timing path; as well as When the arrival windows of the plurality of input pins overlap with each other, a timing variation due to the MIS effect is calculated by applying the MIS coefficient.

20. The method of claim 16, further comprising: Analyzing the arrival windows of multiple input pins of a semiconductor device for MIS timing arcs; When the arrival windows of the plurality of input pins do not overlap with each other, setting the MIS coefficient to a default value; as well as Calculate the timing changes associated with the MIS effect.

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