An alternating current zero-crossing detection circuit and chip

Abstract

The present invention discloses an alternating current zero-crossing detection circuit and chip, the alternating current zero-crossing detection circuit comprises: a power taking and alternating current shaping unit, which is used to generate a square wave of the same frequency and phase based on the alternating current; an edge pulse generating unit, which is electrically connected to the power taking and alternating current shaping unit, and is used to generate an edge pulse at the zero-crossing point of the alternating current based on the square wave; a zero-crossing pulse generating unit, which is electrically connected to the edge pulse generating unit, and is used to generate a zero-crossing pulse based on the edge pulse. The present invention can simultaneously detect the zero-crossing point of the rising edge and the zero-crossing point of the falling edge of the alternating current, and improves the accuracy of detecting the zero-crossing point.

Description

Technical Field

[0001] The present invention relates to the technical field of alternating current zero-crossing detection, and in particular to an alternating current zero-crossing detection circuit and a chip. Background Art

[0002] The AC zero-crossing detection circuit is a common circuit in the fields of thyristor control circuits, high-power equipment or electrical appliance access, power carrier communication, lighting control, etc. These fields all require accurate detection of the voltage zero-crossing point of the AC power, generating a zero-crossing pulse or level signal at the zero-crossing point as a reference signal for system control, or obtaining information related to the AC cycle, voltage fluctuation, phase, etc. of the AC power based on the zero-crossing detection signal.

[0003] The current AC zero-crossing detection circuits are all based on discrete components. The circuit structure is complex, and the zero-crossing signal can only be generated on the rising edge or falling edge of the AC, such as patent numbers: CN103063904A and CN102508014A. However, the system usually needs zero-crossing signals on both the rising and falling edges of the AC. One approach is to obtain a virtual zero-crossing detection signal on the other edge by calculation based on the zero-crossing detection signal on a single edge. However, this virtual zero-crossing detection signal on the other edge does not actually detect the other zero-crossing point, thereby losing part of the information carried by the zero-crossing point, such as zero-crossing jitter caused by voltage fluctuations. Another approach is to use two identical circuits to detect the zero-crossing points on the rising and falling edges respectively, but the cost, power consumption and complexity of the system are doubled.

[0004] In addition, the number of peripheral devices of the zero-crossing detection circuit based on discrete components is large. Since a large number of diodes, transistors and other current control devices are used, the power consumption of the circuit itself is also large, generally requiring about 50-100mW. Another problem caused by the large number of peripheral devices is that the detection accuracy is also impaired. Generally, the error between the detected zero-crossing point and the actual zero-crossing point is usually more than 20us.

[0005] Therefore, how to design a high-precision zero-crossing detection circuit that can simultaneously detect the zero-crossing points of the rising edge and the falling edge is a technical problem that needs to be solved urgently in the industry. Summary of the invention

[0006] In order to solve the technical problem in the prior art regarding the inaccurate zero-crossing point detection of the rising edge and the falling edge at the same time, the present invention provides an alternating current zero-crossing point detection circuit and chip.

[0007] The technical solution adopted by the present invention is to first provide an AC zero-crossing point detection circuit, including: a power taking and AC shaping unit, which is used to generate a square wave with the same frequency and phase based on the AC; an edge pulse generating unit, which is electrically connected to the power taking and AC shaping unit, and is used to generate an edge pulse at the zero-crossing point of the AC based on the square wave; a zero-crossing pulse generating unit, which is electrically connected to the edge pulse generating unit, and is used to generate a zero-crossing pulse based on the edge pulse.

[0008] In one embodiment, the zero-crossing pulse generating unit includes: a pulse stretching unit electrically connected to the edge pulse generating unit, a bias circuit unit electrically connected to the pulse stretching unit, and an optocoupler driving unit electrically connected to the bias circuit unit and the pulse stretching unit.

[0009] In one embodiment, the zero-crossing pulse generating unit includes: NMOS tubes MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, MN9, PMOS tubes MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8, resistors R2, R3, R4, capacitors C2, C3, and NOT gates U2, U3; the MN7, MN8, MN9, MP6, MP7, MP8, C2, C3, U2, U3, R3 constitute a pulse extension unit; the MN1, MN2, MN3, MP1, MP2, MP3, MP4, MP5, R2, R4 constitute a bias circuit unit; MN4, MN5, MN6 constitute an optocoupler driving unit.

[0010] In one embodiment, the pulse extension unit includes: the edge pulse circuit is electrically connected to the gate of MN7 and the gate of MN9, the drain of MN7 is electrically connected to the gate of MN8, the drain of MN7 is also electrically connected to one end of C2, the drain of MN9 is electrically connected to one end of C3, the source of MN7, the source of MN8, the source of MN9, the other end of C2 and the other end of C3 are electrically connected and grounded; the drain of MP6 is electrically connected to the drain of MN7 through the resistor R3, the drain of MP7 is electrically connected to the gate of MP8 and the drain of MN8, the drain of MP8 is electrically connected to the gate of MP7 and the drain of MN9, the source of MP6, the source of MP7 and the source of MP8 are electrically connected, the drain of MP7 is also electrically connected to the input end of U2, the output end of U2 is electrically connected to the input end of U3, and the output end of U3 is electrically connected to the gate of MP6.

[0011] In one embodiment, the bias circuit unit includes: a source of MP1, a source of MP2, a source of MP3, a source of MP4, a source of MP5 and a source of MP6 are electrically connected, a drain of MP2, a drain of MP3, a gate of MP3, a gate of MP4 and a gate of MP5 are electrically connected, a gate of MP1 is electrically connected to an output end of U2, a gate of MP2 is electrically connected to an output end of U3, a drain of MP5 is electrically connected to a drain of MN7, a drain of MP1 is electrically connected to a gate of MN1, a drain of MN2 and a drain of MN3 through a resistor R4, a drain of MN1 is electrically connected to a drain of MP3, a source of MN1 is electrically connected to a gate of MN2, a source of MN1 is also electrically connected to one end of R2, the other end of R2, a source of MN2 and a source of MN3 are electrically connected to a source of MN7, and a gate of MN3 is electrically connected to an output end of U2.

[0012] In one embodiment, the optocoupler driving unit includes: the drain of MN5 is electrically connected to the gate of MN5, the gate of MN6, the drain of MN4 and the drain of MP4, the source of MN5, the source of MN6, the source of MN4 and the source of MN7 are electrically connected, the gate of MN4 is electrically connected to the output end of U2, and the drain of MN6 outputs the zero-crossing pulse.

[0013] In one embodiment, the power supply and AC shaping unit includes: a resistor R1, diodes D1, D2, a capacitor C1 and a comparator U1; one end of R1 is used to electrically connect the AC power, and the other end of R1 is electrically connected to the non-inverting input end of U1, the non-inverting input end of U1 is also electrically connected to the anode of D1 and the cathode of D2, the cathode of D1 is electrically connected to the power supply end of U1, the anode of D2, the ground end of U1 and the inverting input end of U1 are electrically connected to each other and grounded, C1 is electrically connected between the power supply end and the ground end of U1, and the output end of U1 outputs a square wave with the same frequency and phase as the AC power.

[0014] In one embodiment, the edge pulse generating unit includes: an invertor INV, a delay unit and an XOR gate XOR; INV is electrically connected to the output end of U1, the output end of INV is respectively electrically connected to the first input end of XOR and the input end of the delay unit, the output end of the delay unit is electrically connected to the second input end of XOR, and the output end of XOR outputs the edge pulse.

[0015] In one implementation, R1 in the power taking and AC shaping unit is an external resistor, and C1 is an external capacitor.

[0016] In one embodiment, an external optical coupler is further included, wherein the anode of the light emitting diode in the optical coupler is electrically connected to the power supply terminal of U1, and the cathode of the light emitting diode is electrically connected to the drain of MN6.

[0017] The present invention also provides a chip, which adopts the above-mentioned AC zero-crossing detection circuit.

[0018] Compared with the prior art, the present invention has at least the following advantages.

[0019] By setting the power taking and AC shaping units to generate a square wave with the same frequency and phase as the AC power, and by using the edge pulse generating circuit to generate edge pulses, the zero crossing point of the rising edge and the zero crossing point of the falling edge of the AC power are detected at the same time, and the accuracy of detecting the zero crossing point is improved. By setting the zero crossing pulse generating circuit, the edge pulse is extended to generate a zero crossing pulse of the required width, thereby adjusting the zero crossing pulse width. Furthermore, the AC zero crossing detection circuit is integrated into a chip, which reduces the complexity of the peripheral circuit, makes it easier to use, and reduces energy consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained like these drawings without paying creative labor.

[0021] Figure 1 It is a schematic diagram of the framework of an alternating current zero-crossing detection circuit in one embodiment of the present invention;

[0022] Figure 2 for Figure 1 Circuit diagram of the power extraction and AC shaping unit;

[0023] Figure 3 for Figure 1 The circuit diagram of the middle edge pulse generating unit;

[0024] Figure 4 for Figure 1 The circuit diagram of the zero-crossing pulse generating unit;

[0025] Figure 5 This is a schematic diagram of an application of a chip integrating an alternating current zero-crossing detection circuit in one embodiment of the present invention;

[0026] Figure 6 It is a schematic diagram of the detection effect of detecting the zero-crossing point of alternating current in one embodiment of the present invention. DETAILED DESCRIPTION

[0027] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0028] Thus, a feature indicated in this specification will be used to illustrate one of the features of an embodiment of the present invention, rather than implying that each embodiment of the present invention must have the described feature. In addition, it should be noted that this specification describes many features. Although some features can be combined together to illustrate possible system designs, these features can also be used in other combinations that are not explicitly described. Thus, unless otherwise stated, the described combinations are not intended to be limiting.

[0029] The principle and structure of the present invention are described in detail below with reference to the accompanying drawings and embodiments.

[0030] like Figure 1 As shown, the present invention provides an alternating current zero-crossing detection circuit, which is used to obtain information about the zero-crossing point of the alternating current. The alternating current zero-crossing detection circuit includes: a power taking and alternating current shaping unit, an edge pulse generating unit, and a zero-crossing pulse generating unit, which are electrically connected in sequence. Among them, the power taking and alternating current shaping unit is used to electrically connect the alternating current to be detected, and to generate a square wave of the same frequency and phase based on the alternating current. The edge pulse generating unit is used to generate an edge pulse at the zero-crossing point of the alternating current based on the square wave. The zero-crossing pulse generating unit is used to generate a zero-crossing pulse based on the edge pulse, and the zero-crossing pulse is the information about the zero-crossing point of the alternating current that needs to be obtained through the technical solution of the present invention.

[0031] Compared with the traditional zero-crossing detection solution based on discrete components, the technical solution of the present invention can simultaneously detect the zero-crossing point of the rising edge and the zero-crossing point of the falling edge of the AC (see Figure 6 Schematic diagram of detection effect), the circuit structure is simple, the cost is low, and the detection accuracy is high.

[0032] The various parts of the AC zero-crossing detection circuit of the present invention are described in detail below.

[0033] like Figure 2As shown, the power supply and AC shaping unit includes: a resistor R1, diodes D1, D2, a capacitor C1 and a comparator U1. One end of R1 is used to electrically connect the AC power to be detected, and the other end of R1 is electrically connected to the in-phase input terminal of U1. The in-phase input terminal of U1 is also electrically connected to the anode of D1 and the cathode of D2, the cathode of D1 is electrically connected to the power supply terminal of U1, the anode of D2, the ground terminal of U1 and the inverting input terminal of U1 are electrically connected to each other and grounded, D1 and D2 are ESD protection diodes of the input port, realizing ESD protection of the port and realizing half-wave rectification at the same time. C1 is electrically connected between the power supply terminal and the ground terminal of U1, and the output terminal of U1 outputs a square wave with the same frequency and phase as the AC power. R1 can be a series or parallel connection of multiple resistors. Preferably, D2 is a Zener diode. The comparison threshold of U1 is set to 0V. When the input AC passes through zero, the level of the output of the comparator is flipped, thereby shaping the AC and generating a square wave output with the same frequency and phase as the input AC. Since the comparison threshold of U1 is 0V, there is almost no delay between the zero-crossing pulse and the actual zero-crossing point, so it has extremely high detection accuracy.

[0034] like Figure 3 As shown, the edge pulse generating unit is electrically connected to the power taking and AC shaping unit, and is used to receive the square wave and generate the edge pulse based on the square wave. The edge pulse generating unit includes: an invertor INV, a delay unit and an XOR gate XOR; INV is electrically connected to the output end of U1, the output end of INV is electrically connected to the first input end of XOR and the input end of the delay unit respectively, the output end of the delay unit is electrically connected to the second input end of XOR, and the output end of XOR outputs the edge pulse. The delay unit is composed of an even number of invertors connected in series, and the delay unit is used to delay the square wave at the output end of U1. When the level of the input square wave is flipped, the first input end and the second input end of the XOR gate XOR will generate an edge pulse with the same width as the delay time generated by the delay unit at the output end due to different delays. The width of the edge pulse is in the nanosecond level, while the general requirement for the width of the zero-crossing pulse is in the microsecond to millisecond level, so the width of the edge pulse needs to be extended to meet the demand.

[0035] like Figure 4 As shown, the zero-crossing pulse generating unit is connected to the edge pulse generating unit, and is used to receive the edge pulse and extend the width of the edge pulse to generate the zero-crossing pulse. The zero-crossing pulse generating unit includes: a pulse extension unit electrically connected to the edge pulse generating unit, a bias circuit unit electrically connected to the pulse extension unit, and an optical coupler driving unit electrically connected to the bias circuit unit and the pulse extension unit.

[0036] Specifically, the zero-crossing pulse generating unit includes: NMOS tubes MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, MN9, PMOS tubes MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8, resistors R2, R3, R4, capacitors C2, C3, and NOT gates U2, U3; MN7, MN8, MN9, MP6, MP7, MP8, C2, C3, U2, U3, R3 constitute a pulse extension unit; MN1, MN2, MN3, MP1, MP2, MP3, MP4, MP5, R2, R4 constitute a bias circuit unit; MN4, MN5, MN6 constitute an optocoupler driving unit. Among them, the sources of NMOS tubes MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, and MN9 are connected, and the sources of PMOS tubes MP1, MP2, MP3, MP4, MP5, MP6, MP7, and MP8 are connected. The more specific circuit connection relationship is as follows:

[0037] More specifically, the pulse stretching unit realizes the width extension of the edge pulse, and the pulse stretching unit includes: the edge pulse circuit is electrically connected to the gate of MN7 and the gate of MN9, the drain of MN7 is electrically connected to the gate of MN8, the drain of MN7 is also electrically connected to one end of C2, the drain of MN9 is electrically connected to one end of C3, the source of MN7, the source of MN8, the source of MN9, the other end of C2 and the other end of C3 are electrically connected and grounded; the drain of MP6 is electrically connected to the drain of MN7 through the resistor R3, the drain of MP7 is electrically connected to the gate of MP8 and the drain of MN8, the drain of MP8 is electrically connected to the gate of MP7 and the drain of MN9, the source of MP6, the source of MP7 and the source of MP8 are electrically connected, the drain of MP7 is also electrically connected to the input end of U2, the output end of U2 is electrically connected to the input end of U3, and the output end of U3 is electrically connected to the gate of MP6.

[0038] The bias circuit unit provides current bias for the pulse stretching unit and the optocoupler driving unit. The bias circuit unit includes: the source of MP1, the source of MP2, the source of MP3, the source of MP4, the source of MP5 and the source of MP6 are electrically connected, the drain of MP2, the drain of MP3, the gate of MP3, the gate of MP4 and the gate of MP5 are electrically connected, the gate of MP1 is electrically connected to the output end of U2, the gate of MP2 is electrically connected to the output end of U3, the drain of MP5 is electrically connected to the drain of MN7, the drain of MP1 is electrically connected to the gate of MN1, the drain of MN2 and the drain of MN3 through the resistor R4, the drain of MN1 is electrically connected to the drain of MP3, the source of MN1 is electrically connected to the gate of MN2, the source of MN1 is also electrically connected to one end of R2, the other end of R2, the source of MN2 and the source of MN3 are electrically connected to the source of MN7, and the gate of MN3 is electrically connected to the output end of U2.

[0039] The optocoupler drive unit is used as a constant current source output circuit driven by the optocoupler. The optocoupler drive unit includes: the drain of MN5 is electrically connected to the gate of MN5, the gate of MN6, the drain of MN4 and the drain of MP4, the source of MN5, the source of MN6, the source of MN4 and the source of MN7 are electrically connected, the gate of MN4 is electrically connected to the output end of U2, and the drain of MN6 outputs a zero-crossing pulse. The drain of MN6 is a constant current output port. The use of a constant current source output can realize the rapid opening of the optocoupler and reduce the delay of the optocoupler.

[0040] The AC zero-crossing detection circuit also includes an external optical coupler U4, which is composed of a light-emitting diode and a triode. The anode of the light-emitting diode is electrically connected to the power supply terminal of U1, and the cathode of the light-emitting diode is electrically connected to the drain of MN6. The emitter of the triode is grounded, and the collector of the triode is electrically connected to the resistor R5 and then connected to the power supply.

[0041] The operation process of the above-mentioned zero-crossing pulse generating unit is briefly described below.

[0042] When the input edge pulse is high, MN7 will quickly release the charge in C2, and make the output ENB signal of the NOT gate U2 low, and the output EN signal of the NOT gate U3 high. The EN signal and the ENB signal are the enable signals of the entire circuit. When the EN signal is high, the bias circuit unit starts to work, providing bias for the entire circuit, and at the same time drives the optical coupling unit to output milliampere current from the drain of MN6 to drive the light-emitting diode of the optical coupler to emit light. At this time, MP1, MN1, and MN2 are turned on, and MP2, MN3, and MN4 are turned off. R4 provides uA (microampere) current to MN2. MN2 has a large width-to-length ratio, so its VGS voltage is approximately equal to its threshold voltage VTH, so that the current passing through R2 is stabilized at about VTH / R2. The current passing through R2 is independent of the power supply voltage and serves as the current reference of the entire circuit. The current mirror formed by MP3, MP4, and MP5 directly copies the current of R2, and the current mirror formed by MN5 and MN6 copies the current of MP4.

[0043] When the input edge pulse is low level, MN7 will be turned off, but because the voltage of C2 capacitor is 0 at this time, the EN signal and ENB signal will not change state immediately when MN7 is just turned off. At this time, the voltage of C2 will gradually rise over time due to the nano-ampere charging current provided by MP5. When it rises to the turn-on voltage of MN8, MN8 starts to turn on, thereby turning on MP8, and MP8 starts to charge C3. When the level of C3 gradually increases, MP7 is turned off, and the level of the U2 output ENB signal and the U3 output EN signal is flipped, restoring to the working state before the edge pulse is input.

[0044] When the status of EN and ENB is restored, the bias current and the optocoupler constant current drive output are turned off. At this time, MP1 is turned off, MP2, MN3, and MN4 are turned on, and the gate voltages of MN1, MN5, and MN6 are pulled down to achieve shutdown. The gate voltages of MP3, MP4, and MP5 are pulled up to VDD to achieve shutdown. At the same time, MP6 is turned on, so that the level of C2 is pulled up to the VDD level by MP6 and R3, and there is no uncertain state. As a result, the entire circuit has re-entered the low power consumption state.

[0045] The above operation process realizes the extension of the width of the input nanosecond edge pulse to generate a microsecond zero-crossing pulse through the pulse extension unit, and realizes the constant current source pulse current output through the optocoupler drive unit. It should be noted that the extension width is determined by the bias current of MP5 and the capacitance of C2 and C3. The width of the zero-crossing pulse can be adjusted by adjusting the bias current of MP5 and the capacitance of C2 and C3.

[0046] In a preferred embodiment, R1 in the power taking and AC shaping unit is an external resistor, and C1 is an external capacitor.

[0047] In a preferred embodiment, the optical coupler U4 is an external optical coupler.

[0048] like Figure 5 As shown, a chip adopts the above-mentioned AC zero-crossing detection circuit.

[0049] In a preferred embodiment, the chip adopts the above-mentioned AC zero-crossing detection circuit, but the circuit does not include the above-mentioned resistor R1, capacitor C1, optical coupler U4 and resistor R5, and the resistor R1, capacitor C1, optical coupler U4 and resistor R5 are electrically connected to the chip as peripheral components. Specifically, the chip includes an input terminal IN, a power supply terminal VDD, a ground terminal VSS and an output terminal OUT. The input terminal IN is the same-phase input terminal of U1 in the above-mentioned AC zero-crossing detection circuit, the power supply terminal VDD is the power supply terminal of U1 and the source of MP1-MP8 in the zero-crossing pulse generating unit, the ground terminal VSS is the ground terminal of U1 and the source of MN2-MN9 in the zero-crossing pulse generating unit, and the output terminal OUT is the drain of MN6 in the zero-crossing pulse generating unit. One end of the resistor R1 is electrically connected to the input terminal IN of this chip, one end of the capacitor C1 is electrically connected to the power supply terminal VDD, the other end of the capacitor C1 is electrically connected to the ground terminal VSS, the anode of the light-emitting diode of the optocoupler U4 is electrically connected to the power supply terminal VDD, the cathode of the light-emitting diode is electrically connected to the output terminal OUT, the emitter of the transistor of the optocoupler U4 is grounded, the source of the transistor is electrically connected to one end of the resistor R5, the other end of the resistor R5 is connected to the power supply of the low-voltage system, and the source of the transistor and the resistor R5 are used to output a zero-crossing pulse.

[0050] In an optional embodiment, the resistance value of R1 is between 500K-3MΩ, and the capacitance value of C1 is between 100nF and 470nF. The larger the value of C1 is, the smaller the resistance value of R1 needs to be.

[0051] In one embodiment, R1 is 2 MΩ, and C1 is 220 nF.

[0052] In the technical solution of the present invention, based on the chip, the peripheral circuit only needs 1 optocoupler, 2 resistors and 1 capacitor. The peripheral circuit is extremely simple, easy to connect when in use, and the power consumption of the peripheral circuit is extremely low. Taking R1 as 2MΩ as an example, the power consumption of the AC zero-crossing detection circuit of the present invention is approximately: 220V*220V / 2M=24.2mW, and the overall power consumption is low.

[0053] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An alternating current zero-crossing detection circuit, characterized in that: include: A power taking and AC shaping unit, which is used to generate a square wave with the same frequency and phase based on the AC power; An edge pulse generating unit, which is electrically connected to the power taking and AC shaping unit, and is used to generate an edge pulse at the zero crossing point of the AC power based on the square wave; a zero-crossing pulse generating unit, electrically connected to the edge pulse generating unit, and configured to generate a zero-crossing pulse based on the edge pulse; The zero-crossing pulse generating unit includes: a pulse stretching unit electrically connected to the edge pulse generating unit, a bias circuit unit electrically connected to the pulse stretching unit, and an optical coupling driving unit electrically connected to the bias circuit unit and the pulse stretching unit; The zero-crossing pulse generating unit includes: NMOS tubes MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, MN9, PMOS tubes MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8, resistors R2, R3, R4, capacitors C2, C3, NOT gates U2, U3; MN7, MN8, MN9, MP6, MP7, MP8, C2, C3, U2, U3, R3 constitute a pulse extension unit; MN1, MN2, MN3, MP1, MP2, MP3, MP4, MP5, R2, R4 constitute a bias circuit unit; MN4, MN5, MN6 constitute an optocoupler driving unit; The pulse extension unit includes: the edge pulse generating unit is electrically connected to the gate of MN7 and the gate of MN9, the drain of MN7 is electrically connected to the gate of MN8, the drain of MN7 is also electrically connected to one end of C2, the drain of MN9 is electrically connected to one end of C3, the source of MN7, the source of MN8, the source of MN9, the other end of C2 and the other end of C3 are electrically connected and grounded; the drain of MP6 is electrically connected to the drain of MN7 through the resistor R3, the drain of MP7 is electrically connected to the gate of MP8 and the drain of MN8, the drain of MP8 is electrically connected to the gate of MP7 and the drain of MN9, the source of MP6, the source of MP7 and the source of MP8 are electrically connected, the drain of MP7 is also electrically connected to the input end of U2, the output end of U2 is electrically connected to the input end of U3, and the output end of U3 is electrically connected to the gate of MP6; The bias circuit unit includes: the source of MP1, the source of MP2, the source of MP3, the source of MP4, the source of MP5 and the source of MP6 are electrically connected, the drain of MP2, the drain of MP3, the gate of MP3, the gate of MP4 and the gate of MP5 are electrically connected, the gate of MP1 is electrically connected to the output end of U2, the gate of MP2 is electrically connected to the output end of U3, the drain of MP5 is electrically connected to the drain of MN7, the drain of MP1 is electrically connected to the gate of MN1, the drain of MN2 and the drain of MN3 through the resistor R4, the drain of MN1 is electrically connected to the drain of MP3, the source of MN1 is electrically connected to the gate of MN2, the source of MN1 is also electrically connected to one end of R2, the other end of R2, the source of MN2 and the source of MN3 are electrically connected to the source of MN7, and the gate of MN3 is electrically connected to the output end of U2; The optical coupling driving unit includes: the drain of MN5 is electrically connected to the gate of MN5, the gate of MN6, the drain of MN4 and the drain of MP4, the source of MN5, the source of MN6, the source of MN4 and the source of MN7 are electrically connected, the gate of MN4 is electrically connected to the output end of U2, and the drain of MN6 outputs the zero-crossing pulse; The power supply and AC shaping unit includes: a resistor R1, diodes D1, D2, a capacitor C1 and a comparator U1; one end of R1 is used to electrically connect the AC power, and the other end of R1 is electrically connected to the non-inverting input end of U1, the non-inverting input end of U1 is also electrically connected to the anode of D1 and the cathode of D2, the cathode of D1 is electrically connected to the power supply end of U1, the anode of D2, the ground end of U1 and the inverting input end of U1 are electrically connected to each other and grounded, C1 is electrically connected between the power supply end and the ground end of U1, and the output end of U1 outputs a square wave with the same frequency and phase as the AC power.

2. The AC zero-crossing detection circuit according to claim 1, wherein: The edge pulse generating unit includes: an invertor INV, a delay unit and an XOR gate XOR; INV is electrically connected to the output end of U1, the output end of INV is electrically connected to the first input end of XOR and the input end of the delay unit respectively, the output end of the delay unit is electrically connected to the second input end of XOR, and the output end of XOR outputs the edge pulse.

3. The AC zero-crossing detection circuit according to claim 1, characterized in that: An external optical coupler is also included, wherein the anode of the light emitting diode in the optical coupler is electrically connected to the power supply terminal of U1, and the cathode of the light emitting diode is electrically connected to the drain of MN6.

4. A chip, characterized in that: The chip includes the AC zero-crossing detection circuit as described in claim 2, wherein R1 in the power taking and AC shaping unit is an external resistor, and C1 is an external capacitor.

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