Method of wafer bonding

Abstract

The present invention discloses a method for wafer bonding, belonging to the field of integrated circuit chip manufacturing. This method successively performs a cleaning process and a baking process in an integrated circuit chip manufacturing factory; the following bonding process is carried out through a wafer bonding device: the manipulator transfer area takes out the wafer from the wafer access area; the wafer ID reader and the wafer pre-aligner read the wafer ID and pre-align the wafer; the alignment and pre-bonding unit aligns and pre-bonds the wafer; the vision inspection area inspects whether there are bonding defects in the wafer pair after pre-bonding. If there are, the debonding unit debonds the wafer pair and then places the wafer in the wafer access area; otherwise, the wafer pair is directly placed in the wafer access area. In the bonding process, the wafer and the wafer pair are transferred through the manipulator transfer area and / or the post manipulator. The present invention optimizes the wafer bonding method, improves the productivity of the bonding process, and the wafer bonding device has a compact structure, a small floor area, and low costs.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit chip manufacturing, and particularly to a method for wafer bonding. Background Art

[0002] 3D integration is an integrated circuit in which multiple chips are stacked together and electrical connections are achieved through vertical vias between the chips, and it has been widely regarded as a way of "Beyond Moore". Currently, as the process size decreases, the chip size is gradually increasing, and the factors that determine the circuit performance are gradually shifting from devices to interconnecting leads. The continuous reduction of the process size causes an increase in the parasitic resistance and capacitance of the wiring inside the chip, thereby increasing the interconnect delay; on the other hand, the increase in chip complexity also results in an increase in the lead length. These factors cause an increase in the interconnect lead delay and power consumption. More importantly, as the number of interconnect layers increases, the aspect ratio of the TSV (Through Silicon Via) vias becomes larger and larger, and the traditional etching process has difficulty meeting the technical specification requirements.

[0003] Therefore, the International Technology Roadmap for Semiconductors (ITRS) has taken 3D interconnect methods as a preferred solution to solve the bottleneck problem of interconnecting leads. SoC (System-on-a-Chip) is a solution to realize chip multi-functionalization on a single chip, and an important means to realize SoC is wafer-level bonding. In 3D integration technology, wafer-level bonding is the most important link to realize this technology.

[0004] In the prior art, wafers are activated and cleaned through plasma activation technology. Plasma activation technology achieves the purpose of activation cleaning by bombarding the wafer surface with plasma, which will cause micro-defects on the wafer surface. These micro-defects will cause defects at the bonding interface during the subsequent bonding process.

[0005] Plasma activation technology requires that the wafer bonding equipment includes plasma units (usually 2), and the plasma activation process will also cause contamination on the wafer surface. Therefore, the existing wafer bonding equipment also needs to add cleaning units (usually 2). However, the ultrapure water used in the cleaning will cause corrosion on the surface of the wafer with copper interconnects, resulting in small holes, and further causing problems such as an increase in the subsequent contact resistance.

[0006] Therefore, due to the use of plasma activation technology and the need to use ultrapure water for cleaning in the existing wafer bonding method, the wafer bonding process flow is long, the production capacity of the wafer bonding equipment is low, and the equipment occupies a large area and has high costs. Summary of the Invention

[0007] To solve the above technical problems, the present invention provides a method for wafer bonding. The present invention optimizes the wafer bonding method, improves the productivity of the bonding process, and makes the wafer bonding equipment have a compact structure, small floor area, and low cost.

[0008] The technical solution provided by the present invention is as follows:

[0009] In a first aspect, a method for wafer bonding is provided, and the method includes:

[0010] Performing a cleaning process and a baking process on the wafer in sequence in an integrated circuit chip manufacturing factory;

[0011] Performing a bonding process on the wafer through a wafer bonding equipment;

[0012] The wafer bonding equipment includes a machine platform, and a robot transfer area, a wafer access area, an alignment and pre-bonding unit, a vision inspection area, a debonding unit, a rear robot, a wafer ID reader, and a wafer pre-aligner are arranged on the machine platform;

[0013] The bonding process includes:

[0014] Taking out two wafers to be bonded from the wafer access area through the robot transfer area;

[0015] Reading the wafer ID and pre-aligning the two wafers through the wafer ID reader and the wafer pre-aligner;

[0016] Aligning and pre-bonding the two wafers through the alignment and pre-bonding unit;

[0017] Detecting whether there are bonding defects in the wafer pair after pre-bonding through the vision inspection area. If there are bonding defects, debonding the wafer pair through the debonding unit, placing the two wafers obtained after debonding into the wafer access area, and re-performing the bonding process; if there are no bonding defects, directly placing the wafer pair into the wafer access area;

[0018] Wherein, during the bonding process, the wafer and the wafer pair are transferred through the robot transfer area and / or the rear robot.

[0019] Further, the cleaning process includes a chemical surface activation cleaning process or a cleaning process, wherein:

[0020] The chemical surface activation cleaning process includes:

[0021] Activating and cleaning the wafer with a chemical solution;

[0022] Dry rotation of the wafer;

[0023] Cleaning the wafer with water;

[0024] Dry the wafer with nitrogen;

[0025] The cleaning process includes:

[0026] Clean the wafer with water;

[0027] Dry the wafer with nitrogen;

[0028] The baking process includes:

[0029] Bake the wafer;

[0030] Cool the wafer.

[0031] Furthermore, the time for activating and cleaning the wafer with chemical solution is 20 - 60 s, the dry rotation time of the wafer is 3 - 10 s, the time for cleaning the wafer with water is 20 - 60 s, the time for drying the wafer with nitrogen is 10 - 30 s, the baking temperature of the wafer is 100 - 400 °C, and the baking time is 10 s - 90 s.

[0032] Furthermore, the pH range of the chemical solution is 8 - 10, and the chemical solution consists of all or part of the following substances:

[0033]

[0034] Furthermore, the wafer access area, the wafer ID reader, and the wafer pre - aligner are located in the left - hand area of the machine platform, the alignment and pre - bonding unit is located in the right - hand area of the machine platform, the vision inspection area, the debonding unit, and the post - robot are located in the middle area of the machine platform; the debonding unit is located in the upper part of the middle area, the post - robot is located in the middle of the middle area, and the vision inspection area is located in the lower part of the middle area.

[0035] In a second aspect, a method for wafer bonding is provided, and the method includes:

[0036] Perform a cleaning process on the wafer at an integrated circuit chip manufacturing factory;

[0037] Perform a bonding process on the wafer through a wafer bonding device;

[0038] The wafer bonding device includes a machine platform, and a robot transfer area, a wafer access area, a baking unit, an alignment and pre - bonding unit, a vision inspection area, a debonding unit, a post - robot, a wafer ID reader, and a wafer pre - aligner are arranged on the machine platform;

[0039] The bonding process includes:

[0040] Take out two wafers to be bonded from the wafer access area through the robot transfer area;

[0041] Read the wafer ID through a wafer ID reader and a wafer pre-aligner and pre-align two wafers;

[0042] Bake the wafer through a baking unit;

[0043] Pre-align two wafers through a wafer pre-aligner;

[0044] Align and pre-bond two wafers through an alignment pre-bonding unit;

[0045] Detect whether there are bonding defects in the wafer pair after pre-bonding through a visual inspection area. If there are bonding defects, debond the wafer pair through a debonding unit, place the two wafers obtained after debonding in the wafer access area, and re-perform the bonding process; if there are no bonding defects, directly place the wafer pair in the wafer access area;

[0046] Among them, during the bonding process, transfer the wafer and the wafer pair through a robot transfer area and / or a post-robot.

[0047] Further, the cleaning process includes a chemical surface activation cleaning process or a cleaning process, where:

[0048] The chemical surface activation cleaning process includes:

[0049] Activation-clean the wafer using a chemical solution;

[0050] Dry-rotate the wafer;

[0051] Clean the wafer using water;

[0052] Blow-dry the wafer using nitrogen;

[0053] The cleaning process includes:

[0054] Clean the wafer using water;

[0055] Blow-dry the wafer using nitrogen.

[0056] Further, the time for activation-cleaning the wafer using a chemical solution is 20 - 60 s, the time for dry-rotating the wafer is 3 - 10 s, the time for cleaning the wafer using water is 20 - 60 s, and the time for blow-drying the wafer using nitrogen is 10 - 30 s.

[0057] Further, the pH range of the chemical solution is 8 - 10, and the chemical solution consists of all or part of the following substances:

[0058]

[0059] Further, the wafer access area, the wafer ID reader, and the wafer pre-aligner are located in the left area of the machine table, the alignment and pre-bonding unit is located in the right area of the machine table, and the baking unit, the vision inspection area, the debonding unit, and the post manipulator are located in the middle area of the machine table; there are two baking units, the debonding unit is located in the upper left of the middle area, the post manipulator is located in the middle of the middle area, the vision inspection area is located in the lower left of the middle area, one baking unit is located in the upper right of the middle area, and the other baking unit is located in the lower right of the middle area.

[0060] The present invention has the following beneficial effects:

[0061] 1. By using the equipment and process flow of the integrated circuit chip manufacturing plant itself, and replacing the plasma unit in the bonding equipment with the cleaning process in the manufacturing plant, the defects such as the corrosion of metallic copper on the surface of copper interconnects caused by the technical characteristics of the plasma process are overcome.

[0062] 2. Since plasma technology is not used for activation on the wafer bonding equipment, the cleaning module in the bonding equipment is also omitted, simplifying the process steps of the bonding equipment.

[0063] 3. Using the equipment and process of the integrated circuit chip manufacturing plant itself will not increase the costs for the manufacturing plant.

[0064] 4. Because the bonding process is the key process restricting products in the manufacturing plant, the optimized bonding method of the present invention improves the production capacity of the bonding process.

[0065] 5. The structure of the wafer bonding equipment is compact, reducing the costs and floor space for the manufacturing plant to purchase the bonding equipment. Description of the Drawings

[0066] Figure 1 It is a structural diagram of the wafer bonding equipment shown in Embodiment 1;

[0067] Figure 2 It is a process flow diagram of the wafer bonding equipment shown in Embodiment 1;

[0068] Figure 3 It is a structural diagram of the wafer bonding equipment shown in Embodiment 2;

[0069] Figure 4 It is a process flow diagram of the wafer bonding equipment shown in Embodiment 2. Detailed Embodiments

[0070] To make the technical problems, technical solutions, and advantages to be solved by the present invention clearer, the following will be described in detail in conjunction with the drawings and specific embodiments.

[0071] Embodiment 1:

[0072] An embodiment of the present invention provides a method for wafer bonding, and the method includes:

[0073] S1: Sequentially perform a cleaning process and a baking process on the wafer in an integrated circuit chip manufacturing factory.

[0074] S2: Perform a bonding process on the wafer through a wafer bonding device.

[0075] Among them, as Figure 1 shown, the wafer bonding device includes a machine platform 100, on which a manipulator transfer area 101 (EFEM), a wafer access area 102 (buffer station), an alignment / pre-bonding unit 103, a vision inspection area 104 (AVM), a debonding unit 105, a post manipulator 106, a wafer ID reader 107, and a wafer pre-aligner 108 are provided.

[0076] In the present invention, compared with the prior art, the wafer bonding device reduces two plasma modules and two water cleaning modules, which will greatly reduce the compactness of the machine platform, the floor area of the device, and the cost.

[0077] As Figure 2 shown, the foregoing bonding process includes:

[0078] S21: Take out two wafers to be bonded from the wafer access area 102 through the manipulator transfer area 101.

[0079] A first storage position is provided in the wafer access area, and the wafers to be bonded are stored in the first storage position. Preferably, there can be two first storage positions, which are respectively used to store a first wafer and a second wafer to be bonded, and both the first wafer and the second wafer can be multiple.

[0080] S22: Read the wafer ID through the wafer ID reader 107 and the wafer pre-aligner 108 and pre-align the two wafers.

[0081] S23: Align and pre-bond the two wafers through the alignment / pre-bonding unit 103.

[0082] S24: Detect whether there are bonding defects (such as bubbles or alignment) in the pre-bonded wafer pair through the visual inspection area 104. If there are bonding defects, debond the wafer pair through the debonding unit 105 to obtain the separated first wafer and second wafer, and perform appropriate processing on each of the two wafers. Then, place the two wafers obtained after debonding into the wafer access area 102 and re-perform the bonding process.

[0083] If there are no bonding defects, directly place the wafer pair into the wafer access area 102. There is a second storage position in the wafer storage area for placing the pre-bonded wafer pair; for some processes, annealing may be required. When annealing is required and there are no problems, perform the annealing operation.

[0084] Among them, during the bonding process, the wafers and wafer pairs are transferred through the robot transfer area 101 and / or the post-robot 106.

[0085] In the present invention, the wafers are first subjected to a cleaning process and a baking process in an integrated circuit chip manufacturing factory. Then, a wafer bonding device is used for bonding. The bonding process includes the aforementioned S21 - S24. Moreover, during bonding, bonding defects are detected through the visual inspection area, and the wafer pair with defects after bonding is debonded through the debonding unit. The two wafers after debonding can be reused.

[0086] In summary, the present invention has the following advantages:

[0087] 1. Utilize the equipment and process flow of the integrated circuit chip manufacturing factory itself, and use the cleaning process in the factory to replace the plasma unit in the bonding device, overcoming defects such as metal copper corrosion on the copper interconnect surface caused by the technical characteristics of the plasma process.

[0088] 2. Since plasma technology is not used for activation on the wafer bonding device, the cleaning module in the bonding device is also omitted, simplifying the process steps of the bonding device.

[0089] 3. Utilizing the equipment and process of the integrated circuit chip manufacturing factory itself will not increase the costs for the factory.

[0090] 4. Since the bonding process is a key process restricting products in the manufacturing factory, the optimized bonding method of the present invention improves the productivity of the bonding process.

[0091] 5. The structure of the wafer bonding device is compact, reducing the cost of purchasing the bonding device and the floor area of the manufacturing factory.

[0092] The aforementioned cleaning process includes a chemical surface activation cleaning process or a cleaning process, and the chemical surface activation cleaning process or the cleaning process can be selected according to different process requirements, where:

[0093] The chemical surface activation cleaning process includes:

[0094] S11: Activate and clean the wafer using a chemical solution for 20 - 60 s.

[0095] S12: Dry - rotate the wafer for 3 - 10 s.

[0096] S13: Clean the wafer with water for 20 - 60 s.

[0097] S14: Blow - dry the wafer with nitrogen for 10 - 30 s.

[0098] The cleaning process includes:

[0099] S15: Clean the wafer with water for 20 - 60 s.

[0100] S16: Blow - dry the wafer with nitrogen for 10 - 30 s.

[0101] The aforementioned baking process includes:

[0102] S17: Bake the wafer. Different baking temperatures and times can be selected according to different applications. Exemplarily, the baking temperature can be 100 - 400 °C and the baking time can be 10 s - 90 s.

[0103] S18: Cool the wafer.

[0104] The pH range of the aforementioned chemical solution can be 8 - 10, and the chemical solution can be composed of all or part of the following substances (by weight percentage):

[0105]

[0106] The aforementioned chemical surface activation cleaning process and the components of the chemical solution have good activation cleaning effects.

[0107] To make the equipment structure compact and occupy a small floor area, the specific layout of the wafer bonding equipment is as follows:

[0108] The wafer access area 102, the wafer ID reader 107, and the wafer pre - aligner 108 are located in the left - hand area 110 of the machine platform 100. The alignment and pre - bonding unit 103 is located in the right - hand area 120 of the machine platform. The vision inspection area 104, the debonding unit 105, and the post - manipulator 106 are located in the middle area 130 of the machine platform. The debonding unit 105 is located in the upper part of the middle area 130. The post - manipulator 106 is located in the middle of the middle area 130 and can move left and right. The vision inspection area 104 is located in the lower part of the middle area 130. The manipulator transfer area is located on the machine platform and can move left and right.

[0109] Example 2:

[0110] Another method for wafer bonding provided by an embodiment of the present invention includes:

[0111] S1': Performing a cleaning process on the wafer in an integrated circuit chip manufacturing factory.

[0112] S2': Performing a bonding process on the wafer through a wafer bonding device.

[0113] Among them, as Figure 3 shown, the wafer bonding device includes a machine platform 200, on which a manipulator transfer area 201, a wafer access area 202, baking units 203, 203', an alignment and pre-bonding unit 205, a vision inspection area 206, a debonding unit 207, a post manipulator 208, a wafer ID reader 209, and a wafer pre-aligner 204 are provided.

[0114] As Figure 4 shown, the foregoing bonding process includes:

[0115] S21': Taking out two wafers to be bonded from the wafer access area through the manipulator transfer area.

[0116] S22': Reading the wafer ID through the wafer ID reader and the wafer pre-aligner and pre-aligning the two wafers.

[0117] S23': Baking the wafers through the baking unit.

[0118] S24': Pre-aligning the two wafers through the wafer pre-aligner.

[0119] S25': Aligning and pre-bonding the two wafers through the alignment and pre-bonding unit.

[0120] S26': Detecting whether there are bonding defects in the pre-bonded wafer pair through the vision inspection area. If there are bonding defects, the wafer pair is debonded through the debonding unit, and the two wafers obtained after debonding are placed in the wafer access area and the bonding process is performed again; if there are no bonding defects, the wafer pair is directly placed in the wafer access area.

[0121] Among them, during the bonding process, the wafers and the wafer pair are transferred through the manipulator transfer area and / or the post manipulator.

[0122] In the present invention, the wafer is first subjected to a cleaning process in an integrated circuit chip manufacturing factory, and then bonded using a wafer bonding device. The bonding process includes the aforementioned S21' to S26'. Moreover, during bonding, the bonding defects are detected through a vision inspection area, and the wafer pairs with defects after bonding are debonded through a debonding unit. The two wafers after debonding can be reused.

[0123] For the advantages of the embodiments of the present invention, refer to the description of the aforementioned Embodiment 1, and they will not be elaborated in this embodiment.

[0124] The aforementioned cleaning process includes a chemical surface activation cleaning process or a cleaning process, and the chemical surface activation cleaning process or the cleaning process can be selected according to different process requirements, where:

[0125] The chemical surface activation cleaning process includes:

[0126] S11': Activate and clean the wafer using a chemical solution, and the cleaning time is 20 - 60 s.

[0127] S12': Dry-rotate the wafer, and the dry-rotation time is 3 - 10 s.

[0128] S13': Clean the wafer with water for 20 - 60 s.

[0129] S14': Blow-dry the wafer with nitrogen for 10 - 30 s.

[0130] The cleaning process includes:

[0131] S15': Clean the wafer with water, and the time can be 20 - 60 s.

[0132] S16': Blow-dry the wafer with nitrogen, and the time can be 10 - 30 s.

[0133] The pH range of the aforementioned chemical solution can be 8 - 10, and the chemical solution can be composed of all or part of the following substances (by weight percentage):

[0134]

[0135] To make the device structure compact and occupy a small floor area, the specific layout of the wafer bonding device is as follows:

[0136] The wafer access area 202, the wafer ID reader 209, and the wafer pre-aligner 204 are located in the left area 210 of the machine 200. The alignment and pre-bonding unit 205 is located in the right area 220 of the machine 200. The baking units 203, 203', the vision inspection area 206, the debonding unit 207, and the post manipulator 208 are located in the middle area 230 of the machine 200. The number of the baking units 203, 203' is two. The debonding unit 207 is located in the upper left part of the middle area 230. The post manipulator 208 is located in the middle of the middle area 230. The vision inspection area 206 is located in the lower left part of the middle area 230. One baking unit 203 is located in the upper right part of the middle area 230, and the other baking unit 203 is located in the lower right part of the middle area 230.

[0137] The above are the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle described in the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A method for wafer bonding, characterized in that, The method includes: Performing a cleaning process and a baking process on a wafer in an integrated circuit chip manufacturing factory in sequence; Performing a bonding process on the wafer through a wafer bonding device; The wafer bonding device includes a machine platform, and a robot transfer area, a wafer access area, an alignment and pre-bonding unit, a vision inspection area, a debonding unit, a post-robot, a wafer ID reader, and a wafer pre-aligner are arranged on the machine platform; The bonding process includes: Taking out two wafers to be bonded from the wafer access area through the robot transfer area; Reading the wafer ID through the wafer ID reader and the wafer pre-aligner and pre-aligning the two wafers; Performing alignment and pre-bonding on the two wafers through the alignment and pre-bonding unit; Detecting whether there are bonding defects in the wafer pair after pre-bonding through the vision inspection area. If there are bonding defects, debonding the wafer pair through the debonding unit, placing the two wafers obtained after debonding into the wafer access area, and performing the bonding process again; if there are no bonding defects, directly placing the wafer pair into the wafer access area; Wherein, during the bonding process, the wafer and the wafer pair are transferred through the robot transfer area and / or the post-robot; The cleaning process includes a chemical surface activation cleaning process, and the chemical surface activation cleaning process includes: Activating and cleaning the wafer using a chemical solution; Dry rotating the wafer; Cleaning the wafer using water; Drying the wafer using nitrogen; The pH range of the chemical solution is 8 - 10, and the chemical solution consists of all or part of the following substances: 70 - 90% water; 2. The method for wafer bonding according to claim 1, wherein The time for activating and cleaning the wafer using the chemical solution is 20 - 60 s, the time for dry rotating the wafer is 3 - 10 s, the time for cleaning the wafer using water is 20 - 60 s, the time for drying the wafer using nitrogen is 10 - 30 s, the temperature for baking the wafer is 100 - 400 °C, and the baking time is 10 s - 90 s.

3. The method for wafer bonding according to claim 1 or 2, wherein The wafer access area, the wafer ID reader, and the wafer pre-aligner are located in the left area of the machine platform, the alignment and pre-bonding unit is located in the right area of the machine platform, and the vision inspection area, the debonding unit, and the post-robot are located in the middle area of the machine platform; the debonding unit is located in the upper part of the middle area, the post-robot is located in the middle of the middle area, and the vision inspection area is located in the lower part of the middle area.

4. A method for wafer bonding, characterized in that, The method includes: Performing a cleaning process on a wafer in an integrated circuit chip manufacturing factory; Performing a bonding process on the wafer through a wafer bonding device; The wafer bonding device includes a machine platform, and a robot transfer area, a wafer access area, a baking unit, an alignment and pre-bonding unit, a vision inspection area, a debonding unit, a post-robot, a wafer ID reader, and a wafer pre-aligner are arranged on the machine platform; The bonding process includes: Taking out two wafers to be bonded from the wafer access area through the robot transfer area; Reading the wafer ID through the wafer ID reader and the wafer pre-aligner and pre-aligning the two wafers; Baking the wafer through the baking unit; Pre-aligning the two wafers through the wafer pre-aligner; Align and pre-bond two wafers through an alignment pre-bonding unit; Detect whether there are bonding defects in the pre-bonded wafer pair through a vision inspection area. If there are bonding defects, debond the wafer pair through a debonding unit, place the two wafers obtained after debonding into the wafer access area, and re-perform the bonding process; if there are no bonding defects, directly place the wafer pair into the wafer access area; Among them, during the bonding process, transfer the wafers and wafer pairs through a robotic transfer area and / or a post-robot; The cleaning process includes a chemical surface activation cleaning process, and the chemical surface activation cleaning process includes: Activating and cleaning the wafer with a chemical solution; Dry rotation of the wafer; Cleaning the wafer with water; Drying the wafer with nitrogen; The pH range of the chemical solution is 8-10, and the chemical solution consists of all or part of the following substances:

5. The method for wafer bonding according to claim 4, wherein, The time for activating and cleaning the wafer with the chemical solution is 20-60 s, the time for dry rotation of the wafer is 3-10 s, the time for cleaning the wafer with water is 20-60 s, and the time for drying the wafer with nitrogen is 10-30 s.

6. The method for wafer bonding according to claim 4 or 5, characterized in that, The wafer access area, wafer ID reader, and wafer pre-aligner are located in the left area of the machine platform, the alignment pre-bonding unit is located in the right area of the machine platform, and the baking unit, vision inspection area, debonding unit, and post-robot are located in the middle area of the machine platform; there are two baking units, the debonding unit is located in the upper left of the middle area, the post-robot is located in the middle of the middle area, the vision inspection area is located in the lower left of the middle area, one baking unit is located in the upper right of the middle area, and the other baking unit is located in the lower right of the middle area.

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