Drive circuit

Abstract

The driving circuit of the present invention allows the control circuit driving the power device to operate normally even after a negative voltage is generated. The driving circuit includes: a set-side pulse generating circuit that generates a set signal when a logic input signal changes from a first logic level to a second logic level; a reset-side pulse generating circuit that generates a reset signal when the logic input signal changes to the first logic level; a set-side level shifting circuit that generates a level shift-completed set signal from the set signal; a reset-side level shifting circuit that generates a level shift-completed reset signal from the reset signal; a control circuit that turns on and off the power device based on the level shift-completed set signal and the level shift-completed reset signal; and a guarantee circuit that guarantees a state in which the power device is turned off when the logic input signal is the first logic level and turned on when the logic input signal is the second logic level.

Description

Technical Field

[0001] The invention relates to a driving circuit for driving a power device. Background Art

[0002] As shown in Patent Documents 1 and 2, the half-bridge circuit has the first and second power switch elements connected in series between the high potential terminal and the low potential terminal of the power supply, and the node between the first power switch element and the second power switch element is connected to a load such as a motor. The first power switch element is turned on and off, and the second power switch element is turned on and off in a complementary manner to the first power switch element, thereby driving the load. The second power switch element is driven by a low-side control circuit that operates with the potential of the low potential terminal of the power supply as a reference potential, thereby turning on and off. The first power switch element is driven by a high-side control circuit that operates with the potential of the node between the first power switch element and the second power switch element as a reference potential, thereby turning on and off.

[0003] A level shift circuit is connected to the front stage of the high-side control circuit, and the front stage of the level shift circuit is connected to the front stage circuit. The high-side control circuit and the level shift circuit operate at a high voltage, and the front stage circuit operates at a low voltage. The front stage circuit generates a pulse-type set signal and a reset signal based on a logic input signal from the outside, and the level shift circuit performs level shifting on the set signal and the reset signal. The high-side control circuit generates a drive signal based on the set signal and the reset signal that have completed the level shift, and turns the first power switch element on, off, or on according to the drive signal.

[0004] Patent Literature

[0005] Patent Document 1: International Publication No. 2016 / 163142

[0006] Patent Document 2: International Publication No. 2016 / 009719 Summary of the invention

[0007] Technical problem to be solved by the invention

[0008] However, if the first and second power switch elements are switched on and off, the potential of the node between the first power switch element and the second power switch element may be lower than the potential of the low potential terminal of the power supply due to the influence of the mutual inductance of the load, and the voltage of the node becomes a negative voltage. If the above-mentioned negative voltage is generated, the operation of the previous stage circuit is unstable, and the set signal and the reset signal cannot be stably output from the previous stage circuit. When the voltage of the node returns to the normal state from the negative voltage state, the level of the set signal and the reset signal may also become wrong, and the high-side control circuit may malfunction.

[0009] The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to enable a control circuit for driving a power device to operate normally even when a negative voltage is generated at a node connected to the power device.

[0010] Technical solutions adopted to solve technical problems

[0011] The main invention for achieving the above-mentioned purpose is a driving circuit, comprising: a set-side pulse generating circuit, which generates a set signal through an internal power supply when a logic input signal input from the outside changes from a first logic level to a second logic level; a reset-side pulse generating circuit, which generates a reset signal through the internal power supply when the logic input signal changes from the second logic level to the first logic level; a set-side level shifting circuit, which generates a level shifting completion set signal by level shifting the set signal. a reset-side level shift circuit, which generates a level shift completion reset signal by level shifting the reset signal; a control circuit, which turns on the power device based on the level shift completion set signal and turns off the power device based on the level shift completion reset signal; and a guarantee circuit, which guarantees, based on the logic input signal, that the power device is turned off when the logic input signal is the first logic level and is turned on when the logic input signal is the second logic level.

[0012] Effects of the Invention

[0013] According to the embodiment of the present invention, the control circuit for driving the power device can be operated normally. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a diagram showing a drive circuit, an output circuit, a load, and an external power supply.

[0015] Figure 2 This is a timing diagram that uses the time axis to show the relationship between the high-side input signal, the low-side input signal, the set signal, the level shift completion set signal, the reset signal, the level shift completion reset signal, the output of the latch circuit, and the output signal.

[0016] Figure 3 1 is a diagram showing an external power supply and a circuit preceding the driving circuit.

[0017] Figure 4 This is a timing chart showing the relationship between the high-side input signal and the state of each switching element using a time axis.

[0018] Figure 5The timing chart shows the relationship between the voltage of each node after the high-side power switch element is switched from on to off, the input signal, the output signal, and the output signal of each pulse generating circuit using the time axis.

[0019] Figure 6 The timing chart shows the relationship between the voltage of each node after the high-side power switch element is switched from off to on, the input signal, the output signal, and the output signal of each pulse generating circuit using the time axis. DETAILED DESCRIPTION

[0020] According to the description of this specification and the drawings, at least the following matters are clarified.

[0021] This embodiment

[0022] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the embodiments described below, various technically preferred limitations are added for implementing the present invention, and therefore the scope of the present invention is not limited to the following embodiments and accompanying drawings.

[0023] 1. Overview of drive circuit and output circuit

[0024] Figure 1 1 is a diagram showing a drive circuit 1 , an output circuit 5 , a load 9 , and an external power supply 4 . Figure 2 2 is a timing diagram showing the relationship among the input signal HIN, the input signal LIN, the set signal set, the level shift completion set signal setdrn, the reset signal res, the level shift completion reset signal resdrn, the output of the latch circuit 222 and the output signal HO.

[0025] The external power source 4 generates a constant DC voltage and supplies the DC voltage to the drive circuit 1 .

[0026] The external power supply 4 is connected to a large-capacity capacitor 4a. Therefore, noise generated in the drive circuit 1 and the output circuit 5 is removed by the capacitor 4a, and the external power supply 4 is not affected by the noise. Therefore, the output voltage of the external power supply 4 is stable.

[0027] The drive circuit 1 operates by inputting a high-side input signal HIN and a low-side input signal LIN from a microcomputer (not shown) to the drive circuit 1. The input signal HIN and the input signal LIN are logic input signals that repeatedly switch between a first logic level and a second logic level. Here, the first logic level is referred to as a low level, and the second logic level is referred to as a high level.

[0028] The input signal HIN and the input signal LIN generally have a complementary relationship, that is, when the input signal HIN is at a high level, the input signal LIN is at a low level, and when the input signal HIN is at a low level, the input signal LIN is at a high level.

[0029] In addition, the microcomputer is not affected by noise generated in the drive circuit 1 and the output circuit 5. Therefore, the microcomputer outputs the input signal HIN and the input signal LIN stably.

[0030] When the driving circuit 1 drives the output circuit 5 based on the high-side input signal HIN and the low-side input signal LIN, the output circuit 5 alternately and repeatedly switches between a voltage application state in which the voltage of the high-voltage DC power supply 8 is applied to the load 9, and a ground voltage application state in which the ground voltage is applied to the load 9.

[0031] The output circuit 5 is composed of power switch elements 51 and 52 constituting a half bridge. The power switch elements 51 and 52 are N-channel power MOSFETs, but may also be power devices such as IGBTs or bipolar transistors. The power switch elements 51 and 52 are connected in series between the high potential output terminal and the low potential output terminal of the high voltage DC power supply 8. The node N1 between the power switch element 52 and the low potential output terminal of the high voltage DC power supply 8 is grounded, and the node N1 is set as a reference potential. The node N2 between the power switch element 51 and the power switch element 52 is connected to one end of the load 9. The other end of the load 9 is grounded. The node N2 is connected to the low potential output terminal of the high side DC power supply 6.

[0032] The drive circuit 1 turns the power switch element 51 on and off based on the high-side input signal HIN. In addition, the drive circuit 1 turns the power switch element 52 on and off in a complementary manner to the power switch element 51 based on the low-side input signal LIN. When the power switch element 51 is turned on and the power switch element 52 is turned off, the potential of the node N2 becomes the output voltage of the high-voltage DC power supply 8, and the load 9 is in a voltage application state. When the power switch element 51 is turned off and the power switch element 52 is turned on, the potential of the node N2 becomes the reference potential, and the load 9 is in a ground voltage application state. Therefore, the potential of the node N2 can vary from the reference potential to the output voltage of the high-voltage DC power supply 8. Here, the load 9 switches from the voltage application state to the ground voltage application state after a dead time, and the power switch elements 51 and 52 are turned off together during the dead time, thereby preventing the short circuit and penetration current of the high-voltage DC power supply 8. Similarly, the load 9 switches from the ground voltage application state to the voltage application state after a dead time.

[0033] 2. Structure of the drive circuit

[0034] The driving circuit 1 includes a front-stage circuit 10 , a rear-stage circuit 20 , and a low-side control circuit 40 .

[0035] The driving circuit 1 is built into one chip. However, the front-stage circuit 10 and the rear-stage circuit 20 may be built into a common chip, and the low-side control circuit 40 may be built into other chips. Alternatively, the front-stage circuit 10 and the low-side control circuit 40 may be built into a common chip, and the rear-stage circuit 20 may be built into other chips. The rear-stage circuit 20 and the low-side control circuit 40 may also be built into a common chip, and the rear-stage circuit 10 may be built into other chips. Alternatively, the front-stage circuit 10, the rear-stage circuit 20, and the low-side control circuit 40 may also be built into each chip.

[0036] The front-stage circuit 10 operates at a low voltage, and the rear-stage circuit 20 operates at a high voltage.

[0037] The front-stage circuit 10 includes an internal power supply 11, an input circuit 12, a pulse generating circuit 13, and a buffer circuit 14. The rear-stage circuit 20 includes a level shift circuit 21, a high-side control circuit 22, and diodes 28 and 29.

[0038] 2-1. Low-side control circuit

[0039] The low-side control circuit 40 is supplied with power from the low-side DC power supply 7 and receives an input signal LIN from the microcomputer. The low-side control circuit 40 turns on and off the power switch element 52 in a complementary manner to the power switch element 51 based on the input signal LIN.

[0040] 2-2. Internal power supply

[0041] The internal power supply 11 receives power from the external power supply 4 and generates a constant DC voltage lower than the output voltage of the external power supply 4 from the power of the external power supply 4. The internal power supply 11 supplies the DC voltage to the input circuit 12 and the pulse generation circuit 13.

[0042] 2-3. Input circuit

[0043] Figure 3 1 is a diagram showing the input circuit 12 , the pulse generating circuit 13 , the buffer circuit 14 , and the input control state ensuring circuit 15 . Figure 4 It is a timing chart showing the relationship between the states of the switch elements 133a, 134a, 133b, 134b of the pulse generating circuit 13 and the states of the switch elements 151a, 152a, 151b, 152b of the input control state ensuring circuit 15 and the input signal HIN.

[0044] The input circuit 12 includes a comparator 121 and a noise filter 122. The comparator 121 compares the reference voltage Ref generated by the internal power supply 11 with the level of the input signal HIN. If the level of the input signal HIN is higher than the reference voltage Ref, the output signal of the comparator 121 is a high level. If the level of the input signal HIN is lower than the reference voltage Ref, the output signal of the comparator 121 is a low level.

[0045] The noise filter 122 is, for example, a low-pass filter. The noise filter 122 removes noise from the output signal of the comparator 121. The signal obtained after the noise filter 122 removes the noise is the output signal of the input circuit 12, and the output signal is input to the pulse generation circuit 13. If the delay of the input circuit 12 is not considered, the output signal of the input circuit 12 is synchronized with the input signal HIN.

[0046] 2-4. Pulse generation circuit

[0047] The pulse generating circuit 13 includes a set side pulse generating circuit 13a and a reset side pulse generating circuit 13b. The set side pulse generating circuit 13a generates a pulse when the output signal of the input circuit 12 rises from a low level to a high level, and outputs a set signal set (see Figure 2 ). In addition, the reset side pulse generating circuit 13b generates a pulse when the output signal of the input circuit 12 drops from a high level to a low level, and outputs a reset signal res which is a high level when the pulse is generated and a low level when the pulse disappears (refer to Figure 2 The time when the set signal set is at a high level is offset from the time when the reset signal res is at a high level. The set signal set and the reset signal res are input to the level shift circuit 21 of the subsequent circuit 20.

[0048] The set-side pulse generating circuit 13a includes a set-side edge detecting circuit 131a, an inverter 132a, a switching element (third switching element) 133a, a switching element (fourth switching element) 134a, and a set-side Zener diode (set-side clamping element) 135a. The reset-side pulse generating circuit 13b includes a reset-side edge detecting circuit 131b, an inverter 132b, a switching element (seventh switching element) 133b, a switching element (eighth switching element) 134b, and a reset-side Zener diode (reset-side clamping element) 135b.

[0049] When the set side edge detection circuit 131a detects the rising edge of the output signal of the input circuit 12 changing from a low level to a high level, a pulse is generated. The set side edge detection circuit 131a outputs a signal that is a high level when a pulse is generated and a low level when the pulse disappears to the inverter 132a. The inverter 132a inverts the output signal of the set side edge detection circuit 131a and outputs the inverted signal to the gates of the switching element 133a and the switching element 134a.

[0050] The switch element 133a is a P-channel MOSFET, and the switch element 134a is an N-channel MOSFET. The source of the switch element 133a is connected to the internal power supply 11, the drain of the switch element 133a is connected to the drain of the switch element 134a, and the source of the switch element 134a is grounded and set to a reference potential.

[0051] The set-side Zener diode 135a is reverse-biased and connected between the node N3 and the ground. That is, the cathode of the set-side Zener diode 135a is connected to the node N3, and the anode of the set-side Zener diode 135a is connected to the ground and is set to a reference potential. In addition, the breakdown voltage (e.g., 5.5V) of the set-side Zener diode 135a is higher than the output voltage (e.g., 5V) of the internal power supply 11, and lower than the output voltage (e.g., 30V) of the external power supply 4. Therefore, the set-side Zener diode 135a clamps the voltage of the node N3 at the breakdown voltage, so that the voltage of the node N3 to which the gate of the set-side level shift switch element 211a described later is connected will not be too high.

[0052] When the output signal of the inverter 132a is at a low level, that is, when the input signal HIN rises, the switch element 133a is turned on and the switch element 134a is turned off (refer to Figure 4 ). Therefore, the voltage of the internal power supply 11 is applied to the node N3, and the node N3 becomes a high level. When the output signal of the inverter 132a is a high level, the switch element 133a is turned off and the switch element 134a is turned on. Therefore, the node N3 becomes a low level reference potential. The voltage of the node N3 is output as the set signal set.

[0053] When the reset side edge detection circuit 131b detects the falling edge of the output signal of the input circuit 12 changing from a high level to a low level, a pulse is generated. The reset side edge detection circuit 131b outputs a signal that is a high level when the pulse is generated and a low level when the pulse disappears to the inverter 132b. The inverter 132b inverts the output signal of the reset side edge detection circuit 131b and outputs the inverted signal to the gates of the switching element 133b and the switching element 134b.

[0054] The switch element 133b is a P-channel MOSFET, and the switch element 134b is an N-channel MOSFET. The source of the switch element 133b is connected to the internal power supply 11, the drain of the switch element 133b is connected to the drain of the switch element 134b, and the source of the switch element 134b is grounded and set to a reference potential.

[0055] The reset side Zener diode 135b is reverse biased and connected between the node N4 and the ground. That is, the cathode of the reset side Zener diode 135b is connected to the node N4, and the anode of the reset side Zener diode 135b is connected to the ground and is set to the reference potential. In addition, the breakdown voltage (e.g., 5.5V) of the reset side Zener diode 135b is also the same as that of the set side Zener diode 135a. Therefore, the reset side Zener diode 135b clamps the voltage of the node N4 at the breakdown voltage, so that the voltage of the node N4 to which the gate of the reset side level shift switch element 211b described later is connected will not be too high.

[0056] When the output signal of the inverter 132b is at a low level, that is, when the input signal HIN falls, the switch element 133b is turned on and the switch element 134b is turned off (refer to Figure 4 ). Therefore, the voltage of the internal power supply 11 is applied to the node N4, and the node N4 becomes a high level. When the output signal of the inverter 132b is a high level, the switch element 133b is turned off and the switch element 134b is turned on. Therefore, the node N4 becomes a low level reference potential.

[0057] 2-5. Level shift circuit and clamping diode

[0058] like Figure 1 As shown, the level shift circuit 21 includes a set side level shift circuit 21a and a reset side level shift circuit 21b. The set side level shift circuit 21a inverts the set signal set output by the set side pulse generating circuit 13a, shifts the DC level, and outputs a level shift completed set signal setdrn (see Figure 2 ) is output to the high-side control circuit 22. Furthermore, the reset-side level shift circuit 21b inverts the reset signal res output by the reset-side pulse generating circuit 13b, shifts the DC level, and outputs the reset signal resdrn as the level shift completion reset signal (refer to Figure 2 ) is output to the high-side control circuit 22.

[0059] The set-side level shift circuit 21a includes a set-side level shift switch element 211a and a resistor 212a. The reset-side level shift circuit 21b includes a reset-side level shift switch element 211b and a resistor 212b.

[0060] The level shift switch elements 211a and 211b are high-voltage N-channel MOSFETs, but can also be bipolar transistors. The threshold voltage (e.g., 1.5V) of the set-side level shift switch element 211a is set to be lower than the breakdown voltage (e.g., 5.5V) of the set-side Zener diode 135a, and the threshold voltage of the reset-side level shift switch element 211b is set to be lower than the breakdown voltage of the reset-side Zener diode 135b. The threshold voltage refers to the gate-source voltage when the level shift switch elements 211a and 211b are turned on. In addition, when the level shift switch elements 211a and 211b are bipolar transistors, the threshold voltage is the voltage when the bipolar transistor is turned on (e.g., 0.7V).

[0061] The resistor 212a and the setting side level shift switch element 211a are connected in series between the high potential output terminal and the ground of the high side DC power supply 6. That is, the drain of the setting side level shift switch element 211a is connected to the high potential output terminal of the high side DC power supply 6 via the resistor 212, and the source of the setting side level shift switch element 211a is grounded.

[0062] The resistor 212b and the reset-side level shift switch element 211b are connected in series between the high potential output terminal and the ground of the high-side DC power supply 6. That is, the drain of the reset-side level shift switch element 211b is connected to the high potential output terminal of the high-side DC power supply 6 via the resistor 212, and the source of the reset-side level shift switch element 211b is grounded.

[0063] The anode of the diode 28 is connected to the node N2, and the cathode of the diode 28 is connected to the node N5 between the resistor 212a and the set-side level shift switch element 211a. The diode 28 clamps the potential of the node N5 to the potential of the node N2, so the voltage of the node N5 is based on the potential of the node N2. Therefore, an overvoltage is not input to the high-side control circuit 22.

[0064] The anode of the diode 29 is connected to the node N2, and the cathode of the diode 29 is connected to the node N6 between the resistor 212b and the reset-side level shift switch element 211b. The diode 29 clamps the potential of the node N6 to the potential of the node N2, so the voltage of the node N6 is based on the potential of the node N2. Therefore, the overvoltage is not input to the high-side control circuit 22.

[0065] The gate of the setting side level shift switch element 211a is connected to the output terminal of the setting side pulse generating circuit 13a, that is, the node N3 between the switch element 133a and the switch element 134a. The setting signal set output by the setting side pulse generating circuit 13a is input to the gate of the setting side level shift switch element 211a. The setting side level shift switch element 211a is turned on and off based on the setting signal set. When the setting side level shift switch element 211a is turned off, the drain voltage (the voltage of the node N5) is increased by the high-side DC power supply 6 and becomes a high level. When the setting side level shift switch element 211a is turned on, the voltage of the node N5 is reduced to a low level due to grounding. The voltage of the node N5 is input to the high-side control circuit 22 as the level shift completion setting signal setdrn.

[0066] The gate of the reset side level shift switch element 211b is connected to the output terminal of the reset side pulse generating circuit 13b and to the node N4 between the switch element 133b and the switch element 134b. The reset signal res output by the reset side pulse generating circuit 13b is input to the gate of the reset side level shift switch element 211b. The reset side level shift switch element 211b is turned on and off based on the reset signal res. When the reset side level shift switch element 211b is turned off, the voltage of the node N6 is increased to a high level by the high side DC power supply 6. When the reset side level shift switch element 211b is turned on, the voltage of the node N6 is reduced to a low level due to grounding. The voltage of the node N6 is input to the high side control circuit 22 as the level shift completion reset signal resdrn.

[0067] The time when the level shift completion set signal setdrn is at a low level and the time when the level shift completion reset signal resdrn is at a low level are staggered in time.

[0068] 2-6. High-side control circuit

[0069] The high-side control circuit 22 generates an output signal HO based on the level shift completion set signal setdrn and the level shift completion reset signal resdrm, and outputs the output signal HO to the gate of the power switch element 51. As a result, the high-side control circuit 22 turns the power switch element 51 on and off. When the level shift completion set signal setdrn is at a low level and the level shift completion reset signal resdrm is at a high level, the high-side control circuit 22 sets the output signal HO to a high level. When the level shift completion set signal setdrn and the level shift completion reset signal resdrm are both at a low level or a high level, the high-side control circuit 22 maintains the level of the output signal HO. When the level shift completion set signal setdrn is at a high level and the level shift completion reset signal resdrm is at a low level, the high-side control circuit 22 sets the output signal HO to a low level.

[0070] The high-side control circuit 22 includes a protection circuit 221 , a latch circuit 222 and a high-side driver 223 .

[0071] The voltage of the high-side DC power supply 6 with the potential of the node N2 as a reference is applied to the protection circuit 221. In addition, the level shift completion set signal setdrn and the level shift completion reset signal resdrm are input to the protection circuit 221. The protection circuit 221 controls the latch circuit 222 based on the level shift completion set signal setdrn and the level shift completion reset signal resdrm. Figure 2 As shown, when the level shift completion set signal setdrn is at a low level and the level shift completion reset signal resdrm is at a high level, the protection circuit 221 outputs a high level signal to the latch circuit 222. When the level shift completion set signal setdrn is at a high level and the level shift completion reset signal resdrm is at a low level, the protection circuit 221 outputs a low level signal to the latch circuit 222. When both the level shift completion set signal setdrn and the level shift completion reset signal resdrm are at a low level or a high level, the protection circuit 221 makes the output high impedance.

[0072] The output voltage of the high-side DC power supply 6 with the potential of the node N2 as a reference is provided to the latch circuit 222. The latch circuit 222 is controlled according to the output of the protection circuit 221. If the output of the protection circuit 221 (the input of the latch circuit 222) is high or low, the latch circuit 222 stores and outputs its value. In addition, if the output of the protection circuit 221 is high impedance, the latch circuit 222 holds and outputs the value stored just before the output of the protection circuit 221 becomes high impedance.

[0073] Here, when the driving circuit 1 is normal, when the level shift completion set signal setdrn is at a low level and the level shift completion reset signal resdrm is at a high level, the output of the latch circuit 222 is at a high level. Thereafter, when the level shift completion set signal setdrn and the level shift completion reset signal resdrm are both at a low level, the output of the latch circuit 222 remains at a high level. When the level shift completion set signal setdrn is at a high level and the level shift completion reset signal resdrm is at a low level, the output of the latch circuit 222 is at a low level. Thereafter, when the level shift completion set signal setdrn and the level shift completion reset signal resdrm are both at a low level, the output of the latch circuit 222 remains at a low level.

[0074] On the other hand, if the potential of the nodes N5 and N6 changes, dv / dt noise is generated due to the parasitic capacitance of the level shift switch elements 211a and 211b, and current flows through the level shift switch elements 211a and 211b at the same time. As a result, the level shift completion set signal setdrn and the level shift completion reset signal resdrm both become low levels by mistake. Therefore, the output of the protection circuit 221 becomes high impedance, and the level of the output of the latch circuit 222 is maintained.

[0075] The output voltage of the high-side DC power supply 6 with the potential of the node N2 as a reference is provided to the high-side driver 223. In addition, the output of the latch circuit 222 is input to the high-side driver 223. The high-side driver 223 generates an output signal HO corresponding to the output of the latch circuit 222, and outputs the output signal HO to the gate of the power switch element 51. That is, if the output of the latch circuit 222 is low level, the high-side driver 223 sets the output signal HO to low level, and if the output of the latch circuit 222 is high level, the high-side driver 223 sets the output signal HO to high level.

[0076] In addition, the components of the high-side control circuit 22 may be components disclosed in Japanese Patent No. 3429937.

[0077] 2-7. Buffer circuit

[0078] like Figure 1 and Figure 3 As shown, the output voltage of the external power supply 4 is supplied to the buffer circuit 14 .

[0079] The buffer circuit 14 outputs a signal having the same phase as the input signal HIN and a signal having an opposite phase to the input control state ensuring circuit 15 .

[0080] The buffer circuit 14 includes inverters 141 and 142 .

[0081] The input signal HIN is input to the inverter 141. The inverter 141 inverts the input signal HIN, thereby outputting a signal inverted with respect to the input signal HIN to the inverter 142 and the input control state assurance circuit 15. The inverter 142 inverts the output signal of the inverter 141, thereby outputting a signal in phase with respect to the input signal HIN to the input control state assurance circuit 15.

[0082] In addition, the output signal of the input circuit 12 may be input to the buffer circuit 14 instead of the input signal HIN.

[0083] 2-8. Input control state guarantee circuit

[0084] The output voltage of the external power supply 4 is supplied to the input control state ensuring circuit 15 .

[0085] The input control state ensuring circuit 15 includes a set-side input control state ensuring circuit 15 a and a reset-side input control state ensuring circuit 15 b .

[0086] The setting side input control state guarantee circuit 15a pulls up the voltage of the output terminal of the setting side pulse generating circuit 13a, that is, the voltage of the node N3 between the switch element 133a and the switch element 134a, by using the external power supply 4, based on the output signal of the inverter 141 of the buffer circuit 14 when the input signal HIN is at a high level. Furthermore, the setting side input control state guarantee circuit 15a pulls down the voltage of the node N3 by grounding when the input signal HIN is at a low level based on the output signal of the inverter 141 of the buffer circuit 14. Here, the pull-up and pull-down of the voltage of the node N3 do not affect the on / off operation of the setting side level shift switch element 211a performed by the setting side pulse generating circuit 13a.

[0087] The reset-side input control state assurance circuit 15b pulls up the voltage of the output terminal of the reset-side pulse generating circuit 13b, i.e., the voltage of the node N4 between the switch element 133b and the switch element 134b, based on the output signal of the inverter 142 of the buffer circuit 14 when the input signal HIN is at a low level using the external power supply 4. Furthermore, the reset-side input control state assurance circuit 15b pulls down the voltage of the node N4 by grounding when the input signal HIN is at a high level based on the output signal of the inverter 142 of the buffer circuit 14. The pull-up and pull-down of the voltage of the node N4 do not affect the on / off operation of the reset-side level shift switch element 211b performed by the reset-side pulse generating circuit 13b.

[0088] The set-side input control state ensuring circuit 15a includes a switch element (first switch element) 151a, a switch element (second switch element) 152a, and a set-side resistor 153a. The reset-side input control state ensuring circuit 15b includes a switch element (fifth switch element) 151b, a switch element (sixth switch element) 152b, and a reset-side resistor 153b. The switch elements 151a and 151b are P-channel MOSFETs, and the switch elements 152a and 152b are N-channel MOSFETs.

[0089] The source of the switching element 151a is connected to the external power supply 4. The setting side resistor 153a is connected between the drain of the switching element 151a and the drain of the switching element 152a. The source of the switching element 152a is grounded and set to a reference potential. The gates of the switching element 151a and the switching element 152a are connected to the output terminal of the inverter 141 of the buffer circuit 14. The node between the setting side resistor 153a and the switching element 152a is connected to the output terminal of the setting side pulse generating circuit 13a, that is, the node N3 between the switching element 133a and the switching element 134a.

[0090] The source of the switching element 151b is connected to the external power supply 4. The reset side resistor 153b is connected between the drain of the switching element 151b and the drain of the switching element 152b. The source of the switching element 152b is grounded and set as a reference potential. The gates of the switching element 151b and the switching element 152b are connected to the output terminal of the inverter 142 of the buffer circuit 14. The node between the reset side resistor 153b and the switching element 152b is connected to the output terminal of the reset side pulse generating circuit 13b, that is, the node N4 between the switching element 133b and the switching element 134b.

[0091] The output signal of the inverter 141 is input to the gates of the switching elements 151a and 152a, whereby the switching element 151a is turned on and off in phase with the input signal HIN, and the switching element 152a is turned on and off complementarily to the switching element 151a. When the input signal HIN is at a high level, that is, when the output signal of the inverter 141 is at a low level, the switching element 151a is turned on and the switching element 152a is turned off. Therefore, the voltage of the output terminal (that is, the node N3) of the setting side pulse generating circuit 13a is pulled up by the external power supply 4. On the other hand, when the input signal HIN is at a low level, that is, when the output signal of the inverter 141 is at a high level, the switching element 151a is turned off and the switching element 151b is turned on. Therefore, the voltage of the output terminal of the setting side pulse generating circuit 13a is pulled down by grounding.

[0092] Here, the resistance value of the switch element 133a when it is turned on is denoted as R 133a [Ω], the resistance value of the setting side resistor 153a is set to R 153a [Ω], the resistance value of the switch element 151a when it is turned on is R 151a When [Ω], the following formula (1) holds.

[0093] [Mathematical formula 1]

[0094] R 133a ≮≮R 153a +R 151a (1)

[0095] Therefore, when the switch elements 133a and 151a are turned on and the switch elements 134a and 152a are turned off, the voltage of the node N3 is hardly affected by the external power supply 4 and is determined by the voltage of the internal power supply 11 and the resistance of the switch element 133a when it is turned on. In other words, the level of the high-level set signal set is only slightly pulled up by the external power supply 4. Therefore, the gate of the set-side level shift switch element 211a does not become an overvoltage.

[0096] In addition, when the resistance value of the switch element 134a when it is turned on is set to R 134a [Ω], the output voltage of the external power supply 4 is set to V CC [V], the threshold voltage value of the setting side level shift switch element 211a is set to V THa [V], the following formula (2) holds.

[0097]

[0098] Therefore, when the switch elements 134a and 151a are turned on and the switch elements 133a and 152a are turned off, even if the voltage of the node N3 is pulled up by the external power supply 4, the voltage of the node N3 is still lower than the threshold voltage of the setting side level shift switch element 211a. Therefore, the setting side level shift switch element 211a is turned off. In addition, if the resistance value of the switch element 151a when turned on is large enough, the setting side resistor 153a may not be provided. In this case, R 153a =0.

[0099] The output signal of the inverter 142 is input to the gates of the switching elements 151b and 152b, whereby the switching element 151b is turned on and off in phase with the inverted signal of the input signal HIN, and the switching element 152b is turned on and off complementarily to the switching element 151b. When the input signal HIN is at a high level, that is, when the output signal of the inverter 142 is at a high level, the switching element 152b is turned on and the switching element 151b is turned off. Therefore, the voltage of the output terminal (that is, the node N4) of the reset side pulse generating circuit 13b is pulled down by grounding. On the other hand, when the input signal HIN is at a low level, that is, when the output signal of the inverter 142 is at a low level, the switching element 152b is turned off and the switching element 151b is turned on. Therefore, the voltage of the output terminal of the reset side pulse generating circuit 13b is pulled up by the external power supply 4.

[0100] Here, the resistance value of the switch element 133b when it is turned on is denoted as R 133b [Ω], the resistance value of the reset side resistor 153b is set to R 153b [Ω], the resistance value of the switch element 151b when it is turned on is R 151b[Ω], the resistance value of the switch element 134b when it is turned on is R 134b [Ω], the output voltage of the external power supply 4 is set to V CC [V], the threshold voltage value of the reset-side level shift switch element 211b is set to V THb [V], the following equations (3) and (4) hold.

[0101] [Mathematical formula 3]

[0102] R 133b <<R 153b +R 151b (3)

[0103]

[0104] Since equation (3) holds, when the switch elements 133b and 151b are turned on and the switch elements 134b and 152b are turned off, the level of the high-level reset signal res is only slightly pulled up by the external power supply 4. Therefore, the gate of the set-side switch element 211b does not become an overvoltage.

[0105] In addition, since equation (4) holds, when the switch elements 134b and 151b are turned on and the switch elements 133b and 152b are turned off, even if the voltage of the node N4 is pulled up by the external power supply 4, the voltage of the node N4 is still lower than the threshold voltage of the reset side level shift switch element 211b. Therefore, the reset side level shift switch element 211b is turned off. In addition, if the resistance value of the switch element 151b when turned on is large enough, the reset side resistor 153b may not be provided. In this case, R in the above equation is 153b =0.

[0106] The operation delay time of the combination of the buffer circuit 14 and the set-side input control state guarantee circuit 15a is shorter than the operation delay time of the combination of the input circuit 12 and the set-side pulse generating circuit 13a. This is because the noise filter 122 of the input circuit 12 is a low-pass filter, and the output signal of the noise filter 122 is delayed relative to the input signal.

[0107] Likewise, the operation delay time of the combination of the buffer circuit 14 and the reset-side input control state ensuring circuit 15 b is shorter than the operation delay time of the combination of the input circuit 12 and the reset-side pulse generating circuit 13 b .

[0108] 3. When negative voltage is generated

[0109] After the input signal HIN and the output signal HO rise or fall, that is, after the power switch elements 51 and 52 are switched on or off, due to the influence of the inductance and dv / dt of the load 9, as shown in FIG. Figure 5 and Figure 6As shown in the graph of , the node N2 may become a negative voltage. In addition, when external noise such as three-phase current, lightning strike, ESD surge, etc. is generated, the node N2 may also become a negative voltage.

[0110] When the node N2 becomes a negative voltage, the front-stage circuit 10 is affected by the rear-stage circuit 20, and the operation of the front-stage circuit 10 becomes unstable. In particular, the internal power supply 11 cannot operate normally, and the input circuit 12 and the pulse generating circuit 13 cannot operate normally. Specifically, the output voltage from the internal power supply 11 decreases, and the output of the pulse generating circuit 13 may become a high impedance state. In this case, the output signals (set signal set, reset signal res) of the set side pulse generating circuit 13a and the reset side pulse generating circuit 13b are unstable. Therefore, when the node N2 returns to the normal state from the negative voltage state, the output signals of the set side pulse generating circuit 13a and the reset side pulse generating circuit 13b become uncertain.

[0111] However, the microcomputer and the external power supply 4 that output the input signal HIN are not affected by the subsequent circuit 20, so even if the node N2 becomes a negative voltage, the microcomputer and the external power supply 4 still operate normally. Therefore, the buffer circuit 14, the set side input control state guarantee circuit 15a, and the reset side input control state guarantee circuit 15b that are provided with the external power supply 4 operate normally. Therefore, when the node N2 is restored from the negative voltage state to the normal state, even if the output signals of the set side pulse generating circuit 13a and the reset side pulse generating circuit 13b are unstable, the high side control circuit 22 will not malfunction. Therefore, after the output signal HO of the high side control circuit 22 is restored, the node N2 still maintains the state before it becomes a negative voltage. This point will be described in more detail below.

[0112] 3-1. When the output signal HO is low

[0113] When the input signal HIN falls, the output signal of the reset side pulse generating circuit 13b (reset signal res) temporarily becomes high level, and then the output signal of the reset side pulse generating circuit 13b and the output signal of the set side pulse generating circuit 13a (set signal set) both become low level (refer to Figure 2 ). Therefore, the output signal HO of the high-side control circuit 22 becomes a low level.

[0114] Moreover, after the power switch elements 51 and 52 are switched on and off, due to the influence of the inductance and dv / dt of the load 9 or due to the influence of external noise, such as Figure 5As shown, the node N2 becomes a negative voltage, and the output signal of the set-side pulse generating circuit 13a is unstable, but the switch element 152a is turned on, so the voltage of the output terminal (i.e., node N3) of the set-side pulse generating circuit 13a is pulled down by grounding. Therefore, the set-side level shift switch element 211a cannot be turned on, and the output signal HO of the high-side control circuit 22 is maintained at a low level. On the other hand, the switch element 151b is turned on, so the voltage of the output terminal (i.e., node N4) of the reset-side pulse generating circuit 13b is pulled up by the external power supply 4. Therefore, the output signal of the reset-side pulse generating circuit 13b is unstable, and the output signal HO of the high-side control circuit 22 is maintained at a low level regardless of whether the reset-side level shift switch element 211b is turned on.

[0115] After that, the node N2 recovers from the negative voltage state to the normal state, and the internal power supply 11, the input circuit 12, and the pulse generating circuit 13 recover. At this time, the switch element 152a is turned on, so the voltage of the output terminal of the set side pulse generating circuit 13a is pulled down by grounding. Therefore, even if the output signal of the set side pulse generating circuit 13a is uncertain during recovery, the set side level shift switch element 211a still cannot be turned on, and the output signal HO of the high side control circuit 22 is maintained at a low level. On the other hand, the switch element 151b is turned on, so the voltage of the output terminal of the reset side pulse generating circuit 13b is pulled up by the external power supply 4. Therefore, even if the output signal of the reset side pulse generating circuit 13b is uncertain, regardless of whether the reset side level shift switch element 211b is turned on, the output signal HO of the high side control circuit 22 is maintained at a low level. In addition, here, the case where the reset side level shift switch element 211b is turned on refers to, for example, the case where the switch element 134b is turned off, the node N4 is pulled up, and the voltage of the node N4 becomes the breakdown voltage of the reset side Zener diode 135b. On the other hand, the case where the reset-side level shift switch element 211 b is off refers to, for example, the case where the switch element 134 b is on and the voltage of the node N4 is lower than the threshold voltage.

[0116] Here, as described above, the operation delay time of the combination of the buffer circuit 14 and the setting side input control state guarantee circuit 15a is shorter than the operation delay time of the combination of the input circuit 12 and the setting side pulse generating circuit 13a. Therefore, before the output signal of the setting side pulse generating circuit 13a becomes unstable or uncertain, the voltage of the node N3 is affected by the output of the setting side input control state guarantee circuit 15a. Therefore, it is possible to prevent the malfunction of the setting side level shift switch element 211a.

[0117] 3-2. When the output signal HO is high

[0118] After the input signal HIN rises, when the output signal of the reset side pulse generating circuit 13b and the output signal of the set side pulse generating circuit 13a (set signal set) are both low level, the output signal HO of the high side control circuit 22 is high level. Figure 6 As shown in the figure, when the node N2 becomes a negative voltage due to the influence of external noise, the output signal of the reset side pulse generating circuit 13b is unstable, but since the switch element 152b is turned on, the voltage of the output terminal of the reset side pulse generating circuit 13b is pulled down by grounding. Therefore, the reset side level shift switch element 211b cannot be turned on, and the output signal HO of the high side control circuit 22 is maintained at a high level. Afterwards, when the node N2 is restored from the negative voltage state to the normal state, the switch element 152a is still turned on, so the output terminal of the reset side pulse generating circuit 13b is pulled down by grounding. Therefore, even if the output signal of the reset side pulse generating circuit 13b is uncertain during recovery, the reset side level shift switch element 211b still cannot be turned on, and the output signal HO of the high side control circuit 22 is maintained at a high level. In addition, the switch element 151a is turned on, so the output terminal of the set side pulse generating circuit 13a is pulled up by the external power supply 4. Therefore, when the node N2 is in a negative voltage state or returns to a normal state thereafter, the output signal HO of the high-side control circuit 22 is maintained at a high level regardless of whether the setting-side level shift switch element 211a is turned on or not. In addition, whether the setting-side level shift switch element 211a is turned on or not changes according to the state of the switch element 134a, similarly to whether the reset-side level shift switch element 211b is turned on or not.

[0119] 4. Summary

[0120] (1) When the node N2 becomes a negative voltage, the internal power supply 11, the input circuit 12, and the pulse generating circuit 13 may not operate normally, but the buffer circuit 14 and the input control state guarantee circuit 15 operate normally through the external power supply 4 and the input signal HIN. Therefore, the following beneficial effects (2) to (5) are produced.

[0121] (2) When the input signal HIN is at a low level, the voltage of the output terminal (i.e., the node N3) of the setting side pulse generating circuit 13a is pulled down by grounding. Therefore, even if the node N2 becomes a negative voltage, the setting side level shift switch element 211a will not be turned on. Therefore, the output signal HO of the high side control circuit 22 is maintained at a low level.

[0122] (3) When the input signal HIN is at a high level, the voltage of the output terminal (i.e., node N4) of the reset side pulse generating circuit 13b is pulled down by grounding. Therefore, even if the node N2 becomes a negative voltage, the reset side level shift switch element 211b will not be turned on. Therefore, the output signal HO of the high side control circuit 22 is maintained at a high level.

[0123] (4) When the input signal HIN is at a low level, the voltage of the output terminal of the reset side pulse generating circuit 13b is pulled up by the external power supply 4. Therefore, even if the node N2 becomes a negative voltage, the reset side level shift switch element 211b is easily turned on. Therefore, the output signal HO of the high side control circuit 22 is maintained at a low level.

[0124] (5) When the input signal HIN is at a high level, the voltage of the output terminal of the setting side pulse generating circuit 13a is pulled up by grounding. Therefore, even if the node N2 becomes a negative voltage, the setting side level shift switch element 211a is easily turned on. Therefore, the output signal HO of the high side control circuit 22 is maintained at a high level.

[0125] (6) When the internal power supply 11, the input circuit 12, and the pulse generating circuit 13 operate normally, even if the voltage of the output terminal of the set-side pulse generating circuit 13a is pulled up by the external power supply 4, when the set signal set is at a high level, the voltage of the output terminal of the set-side pulse generating circuit 13a will not exceed the withstand voltage of the set-side level shift switch element 211a. This is because the above formula (1) is satisfied. Similarly, since the above formula (3) is satisfied, when the reset signal res is at a high level, the voltage of the output terminal of the reset-side pulse generating circuit 13b will not exceed the withstand voltage of the reset-side switch element 211b.

[0126] (7) When the internal power supply 11, the input circuit 12, and the pulse generating circuit 13 operate normally, even if the voltage of the output terminal of the setting side pulse generating circuit 13a is pulled up by the external power supply 4, when the setting signal set is at a low level, the voltage of the output terminal of the setting side pulse generating circuit 13a does not exceed the threshold voltage of the setting side switch element 211a, and the setting side level shift switch element 211a is turned off. This is because the above formula (2) is satisfied. Similarly, since the above formula (4) is satisfied, when the reset signal res is at a low level, the reset side level shift switch element 211b is turned off.

[0127] (8) Since the node N2 becomes a negative voltage, when the internal power supply 11, the input circuit 12, and the pulse generating circuit 13 operate abnormally, the switch elements 133a and 134a are sometimes turned off. In such a case, when the switch element 151a is turned on and the switch element 152a is turned off by the input signal HIN, the voltage of the output terminal of the set-side pulse generating circuit 13a is clamped by the set-side Zener diode 135a so that the voltage of the output terminal of the set-side pulse generating circuit 13a does not exceed the breakdown voltage of the set-side Zener diode 135a. As a result, an overvoltage is not applied to the gate of the switch element 211a, and damage to the switch element 211a can be prevented. When the internal power supply 11, the input circuit 12, and the pulse generating circuit 13 operate abnormally, when the switch element 151b is turned on and the switch element 152b is turned off, an overvoltage is not applied to the gate of the switch element 211b, and damage to the switch element 211b can be prevented.

[0128] (9) The operation delay time of the combination of the buffer circuit 14 and the input control state guarantee circuit 15 is shorter than the operation delay time of the combination of the input circuit 12 and the pulse generating circuit 13. Therefore, before the output signal of the pulse generating circuit 13 becomes unstable or uncertain due to the node N2 becoming a negative voltage, the voltages of the nodes N3 and N4 are affected by the output of the input control state guarantee circuit 15. Therefore, it is possible to prevent malfunction of the level shift switch elements 211a and 211b.

[0129] 5. Modifications

[0130] In addition, the above-mentioned embodiments are used to facilitate understanding of the present invention, and are not used to limit and interpret the present invention. In addition, the present invention can be changed or improved without departing from its purpose, and its equivalent content is of course also included in the present invention.

[0131] For example, in order to make the delay time between the input circuit 12 and the pulse generating circuit 13 longer than the delay time between the buffer circuit 14 and the input control state ensuring circuit 15 , a delay circuit may be provided in the input circuit 12 .

[0132] Description of symbols

[0133] 1. Driving circuit

[0134] 4 External power supply

[0135] 6 High-side DC power supply (high-side power supply)

[0136] 11 Internal Power Supply

[0137] 13a Set side pulse generation circuit

[0138] 13b Reset side pulse generation circuit

[0139] 15a Set side input control state assurance circuit

[0140] 15b Reset side input control state assurance circuit

[0141] 21a Set side level shift circuit

[0142] 21b Reset side level shift circuit

[0143] 22 High-side control circuit (control circuit)

[0144] 51 Power switching elements (power devices)

[0145] 131a Set side edge detection circuit

[0146] 131b Reset side edge detection circuit

[0147] 133a Switching element (third switching element)

[0148] 133b Switching element (seventh switching element)

[0149] 134a Switching element (fourth switching element)

[0150] 134b Switching element (eighth switching element)

[0151] 135a Set-side Zener diode (set-side clamping element)

[0152] 135b Reset side Zener diode (reset side clamping element)

[0153] 151a Switching element (first switching element)

[0154] 151b Switching element (fifth switching element)

[0155] 152a Switching element (second switching element)

[0156] 152b Switching element (sixth switching element)

[0157] 153a Set side resistor

[0158] 153b Reset side resistor

[0159] 211a Setting side level shift switch element

[0160] 211b Reset side level shift switch element

[0161] N3 node (node ​​between the third switching element and the fourth switching element)

[0162] N4 node (a node between the seventh switching element and the eighth switching element).

Claims

1. A driving circuit, characterized in that: include: a set-side pulse generating circuit that generates a set signal by an internal power supply when a logic input signal input from the outside changes from a first logic level to a second logic level; a reset-side pulse generating circuit that generates a reset signal through the internal power supply when the logic input signal changes from the second logic level to the first logic level; A setting side level shift circuit, which generates a level shift completion setting signal by level shifting the setting signal; a reset-side level shift circuit, which generates a level shift completion reset signal by level shifting the reset signal; a control circuit, the control circuit turning on the power device based on the level shift completion set signal, and turning off the power device based on the level shift completion reset signal; as well as A guarantee circuit, which pulls up or down the output voltage of the set side pulse generating circuit and the output voltage of the reset side pulse generating circuit respectively based on the logic input signal, so as to ensure that the power device is turned off when the logic input signal is the first logic level and is turned on when the logic input signal is the second logic level.

2. The driving circuit according to claim 1, characterized in that: The guarantee circuit comprises: a set-side guarantee circuit that pulls down an output voltage of the set-side pulse generating circuit by a reference potential when the logic input signal is at the first logic level; and A reset-side guarantee circuit pulls down an output voltage of the reset-side pulse generating circuit by the reference potential when the logic input signal is at the second logic level.

3. The driving circuit according to claim 2, characterized in that: The set side guarantee circuit pulls up the output voltage of the set side pulse generating circuit through an external power supply when the logic input signal is at the second logic level. The reset-side guarantee circuit pulls up the output voltage of the reset-side pulse generating circuit through the external power supply when the logic input signal is at the first logic level.

4. The driving circuit according to claim 3, characterized in that: The set side guarantee circuit comprises: a first switch element connected to the external power supply, turned on when the logic input signal is at the second logic level and turned off when the logic input signal is at the first logic level; and a second switch element connected in series with the first switch element via a set-side resistor between the reference potential and the external power supply, and turned on and off complementarily with the first switch element based on the logic input signal, A node between the set-side resistor and the second switch element is connected to an output of the set-side pulse generating circuit.

5. The driving circuit according to claim 4, characterized in that: The set side pulse generating circuit comprises: a set-side edge detection circuit, the set-side edge detection circuit detecting a situation in which the logic input signal changes from the first logic level to the second logic level; a third switch element connected to the internal power supply and turned on and off based on an output signal of the set-side edge detection circuit; and a fourth switch element, which is connected in series with the third switch element between the reference potential and the internal power supply, and is turned on and off complementarily with the third switch element based on an output signal of the set side edge detection circuit, The node between the third switching element and the fourth switching element is connected to the node between the setting side resistor and the second switching element, and the setting side pulse generating circuit outputs the voltage of the node between the third switching element and the fourth switching element as the setting signal to the setting side level shifting circuit.

6. The driving circuit according to claim 5, characterized in that: A resistance value of the third switching element when on is smaller than a sum of a resistance value of the first switching element when on and a resistance value of the set-side resistor.

7. The driving circuit according to claim 5 or 6, characterized in that: The setting side level shift circuit includes: a setting side level shift switch element, which is connected between a high side power supply and the reference potential and is turned on and off based on the setting signal. The setting-side level shift circuit outputs the voltage of the terminal on the high-side power supply side of the setting-side level shift switch element to the control circuit as the level shift completion setting signal.

8. The driving circuit according to claim 7, characterized in that: When the first switching element and the fourth switching element are turned on and the second switching element and the third switching element are turned off, an output voltage of the set-side pulse generating circuit is lower than a threshold voltage of the set-side level shift switch element.

9. The driving circuit according to claim 7, characterized in that: The threshold voltage of the set-side level shift switch element is greater than the product of the quotient obtained by dividing the resistance value of the fourth switch element when it is turned on by the sum of the resistance value of the fourth switch element when it is turned on, the resistance value of the set-side resistor, and the resistance value of the first switch element when it is turned on, and the voltage of the external power supply.

10. The driving circuit according to claim 7, characterized in that: The set-side pulse generating circuit further includes a set-side clamping element that clamps a voltage of a node between the third switching element and the fourth switching element to be lower than a predetermined voltage.

11. The driving circuit according to claim 10, characterized in that: The set-side clamping element is a set-side Zener diode connected to a node between the third switching element and the fourth switching element in a reverse biased manner. The predetermined voltage is a breakdown voltage of the set-side Zener diode. A threshold voltage of the setting-side level shift switch element is lower than a breakdown voltage of the setting-side Zener diode.

12. The driving circuit according to claim 3, characterized in that: The reset side guarantee circuit comprises: a fifth switch element connected to the external power supply, turned on when the logic input signal is at the first logic level and turned off when the logic input signal is at the second logic level; and a sixth switch element, which is connected in series with the fifth switch element via a reset-side resistor between the reference potential and the external power supply, and is turned on and off complementarily to the fifth switch element based on the logic input signal, A node between the reset-side resistor and the sixth switch element is connected to an output of the reset-side pulse generating circuit.

13. The driving circuit according to claim 12, characterized in that: The reset side pulse generating circuit comprises: a reset side edge detection circuit, the reset side edge detection circuit detecting a situation where the logic input signal changes from the second logic level to the first logic level; a seventh switch element, the seventh switch element being connected to the internal power supply and being turned on and off based on an output signal of the reset side edge detection circuit; and an eighth switch element, which is connected in series with the seventh switch element between the reference potential and the internal power supply, and is turned on and off complementarily with the seventh switch element based on an output signal of the reset side edge detection circuit, The node between the 7th switching element and the 8th switching element is connected to the node between the reset side resistor and the 6th switching element, and the reset side pulse generating circuit outputs the voltage of the node between the 7th switching element and the 8th switching element as the reset signal to the reset side level shifting circuit.

14. The driving circuit according to claim 13, characterized in that: The resistance value of the seventh switching element when it is turned on is smaller than the sum of the resistance value of the fifth switching element when it is turned on and the resistance value of the reset-side resistor.

15. The driving circuit according to claim 13 or 14, characterized in that: The reset side level shift circuit includes: a reset side level shift switch element, which is connected between the high side power supply and the reference potential and is turned on and off based on the reset signal. The reset-side level shift circuit outputs the voltage of the terminal on the high-side power supply side of the reset-side level shift switch element to the control circuit as the level shift completion reset signal.

16. The driving circuit according to claim 15, characterized in that: When the fifth and eighth switching elements are turned on and the sixth and seventh switching elements are turned off, an output voltage of the reset-side pulse generating circuit is lower than a threshold voltage of the reset-side level shift switch element.

17. The driving circuit according to claim 15, characterized in that: The threshold voltage of the reset side level shift switch element is greater than the product of the quotient obtained by dividing the resistance value of the 8th switch element when it is turned on by the sum of the resistance value of the 8th switch element when it is turned on, the resistance value of the reset side resistor and the resistance value of the 5th switch element when it is turned on, and the voltage of the external power supply.

18. The driving circuit according to claim 15, characterized in that: The reset-side pulse generating circuit further includes a reset-side clamping element that clamps a voltage of a node between the seventh switching element and the eighth switching element to be lower than a predetermined voltage.

19. The driving circuit according to claim 18, characterized in that: The reset-side clamping element further includes a reset-side Zener diode connected in a reverse biased manner to a node between the seventh switching element and the eighth switching element. The prescribed voltage is the breakdown voltage of the reset-side Zener diode, A threshold voltage of the reset-side level shift switch element is lower than a breakdown voltage of the reset-side Zener diode.

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