Low-temperature polycrystalline oxide array substrate and method for manufacturing the same

Abstract

The present invention provides a low-temperature polycrystalline oxide array substrate and a manufacturing method thereof. The array substrate provided by the present invention includes a substrate and a thin-film transistor assembly disposed on the substrate. The thin-film transistor assembly includes a first semiconductor layer, a first source electrode, a first drain electrode, a second semiconductor layer, a second source electrode, a second drain electrode, and a common gate electrode. The first semiconductor layer, the first source electrode, the first drain electrode, and the common gate electrode form a first thin-film transistor, and the second semiconductor layer, the second source electrode, the second drain electrode, and the common gate electrode form a second thin-film transistor. The second thin-film transistor is disposed above the first thin-film transistor, and the first thin-film transistor and the second thin-film transistor have an overlapping region in the vertical direction. Among them, one of the first semiconductor layer and the second semiconductor layer is a polysilicon semiconductor layer, and the other is a metal oxide semiconductor layer. The array substrate provided by the present invention can increase the pixel aperture ratio and reduce power consumption while meeting the requirements of high resolution.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and particularly to a low-temperature polycrystalline oxide array substrate and a manufacturing method thereof. Background Art

[0002] Thin Film Transistor Liquid Crystal Display (TFT-LCD) has the characteristics of small size, low power consumption, and no radiation, and occupies a dominant position in the current flat panel display market. In recent years, with the rapid development of TFT-LCD, especially the development of liquid crystal televisions is even more rapid, and large-size and high-resolution liquid crystal televisions have become the mainstream of TFT-LCD development.

[0003] Traditional TFT-LCD usually uses polysilicon thin film transistors, which have a relatively high mobility, with a mobility greater than 30 cm 2 / V·s. Polysilicon thin film transistors are generally fabricated by the Excimer Laser Annealing (ELA) process. However, during laser annealing, due to the limitation of the laser pulse width, the formed polysilicon has poor uniformity, which directly affects the uniformity of the thin film transistors and makes them unsuitable for large-size liquid crystal panels. In addition, although polysilicon thin film transistors have a high mobility, their off-state current is large, and the power consumption is relatively high when driving pixel electrodes. Currently, TFT-LCD also uses metal oxide thin film transistors, which also have a relatively high mobility, generally around 10 - 30 cm 2 / V·s. Although the mobility is slightly lower than that of polysilicon thin film transistors, it can fully meet the driving requirements of the pixel area, and the off-state current of metal oxide thin film transistors is much smaller than that of polysilicon thin film transistors. Using it to drive pixel electrodes can reduce the power consumption of the display panel.

[0004] However, with the development of display products towards large size and high resolution, the area ratio of thin film transistors in pixels is increasing, resulting in a decrease in the aperture ratio of pixels and an increase in power consumption. Summary of the Invention

[0005] The present invention provides a low-temperature polycrystalline oxide array substrate and a manufacturing method thereof. While meeting the requirements of high resolution, the array substrate can increase the pixel aperture ratio and reduce power consumption.

[0006] One aspect of the present invention provides a low-temperature polycrystalline oxide array substrate, which includes a substrate and a thin-film transistor component disposed on the substrate. The thin-film transistor component includes a first semiconductor layer, a first source electrode, a first drain electrode, a second semiconductor layer, a second source electrode, a second drain electrode, and a common gate electrode. The first source electrode and the first drain electrode are respectively connected to both sides of the first semiconductor layer, and the second source electrode and the second drain electrode are respectively connected to both sides of the second semiconductor layer;

[0007] The first semiconductor layer, the first source electrode, the first drain electrode, and the common gate electrode form a first thin-film transistor, and the second semiconductor layer, the second source electrode, the second drain electrode, and the common gate electrode form a second thin-film transistor. The second thin-film transistor is disposed above the first thin-film transistor along the stacking direction of the array substrate, and the orthographic projection of one of the first thin-film transistor and the second thin-film transistor on the substrate is within the coverage of the orthographic projection of the other on the substrate;

[0008] Wherein, one of the first semiconductor layer and the second semiconductor layer is a polysilicon semiconductor layer, and the other is a metal oxide semiconductor layer.

[0009] In a possible implementation manner, the common gate electrode is disposed between the first semiconductor layer and the second semiconductor layer along the stacking direction of the array substrate, and the common gate electrode is used to drive the first thin-film transistor and the second thin-film transistor.

[0010] In a possible implementation manner, the thin-film transistor component further includes a buffer layer disposed on the substrate, and the first semiconductor layer is disposed on the buffer layer; wherein, the buffer layer includes a first buffer layer and a second buffer layer stacked in sequence on the substrate.

[0011] In a possible implementation manner, the thin-film transistor component further includes a gate insulating layer and a gate protection layer stacked in sequence on the buffer layer. The gate insulating layer covers the first semiconductor layer, the common gate electrode is disposed on the gate insulating layer, and the gate protection layer covers the common gate electrode; wherein, contact holes communicating to the first semiconductor layer are provided in the gate protection layer and the gate insulating layer, and the first source electrode and the first drain electrode are disposed in the gate protection layer and contact the first semiconductor layer through the contact holes.

[0012] In a possible implementation manner, the gate protection layer includes a first gate protection layer and a second gate protection layer stacked in sequence on the gate insulating layer, and the first source electrode and the first drain electrode are disposed between the first gate protection layer and the second gate protection layer.

[0013] In a possible implementation manner, the thin-film transistor component further includes an oxide insulating layer and a metal oxide protection layer stacked in sequence on the gate protection layer. The second semiconductor layer, the second source electrode, and the second drain electrode are all disposed on the oxide insulating layer, and the metal oxide protection layer covers the second semiconductor layer, the second source electrode, and the second drain electrode.

[0014] Another aspect of the present invention provides a method for manufacturing a low-temperature polycrystalline oxide array substrate for manufacturing the low-temperature polycrystalline oxide array substrate as described in any one of the above, and the manufacturing method includes the following steps:

[0015] Form a first thin-film transistor on a substrate; wherein, the first thin-film transistor includes a first semiconductor layer, a first source electrode, a first drain electrode, and a common gate electrode, and the first source electrode and the first drain electrode are respectively connected to both sides of the first semiconductor layer;

[0016] Form a second thin-film transistor on the first thin-film transistor, and the second thin-film transistor and the first thin-film transistor have an overlapping area in a direction perpendicular to the substrate; wherein, the second thin-film transistor includes a second semiconductor layer, a second source electrode, a second drain electrode, and a common gate electrode, the second source electrode and the second drain electrode are respectively connected to both sides of the second semiconductor layer, and one of the first semiconductor layer and the second semiconductor layer is a polycrystalline silicon semiconductor layer, and the other is a metal oxide semiconductor layer.

[0017] In a possible implementation manner, forming a second thin-film transistor on the first thin-film transistor specifically includes:

[0018] Form a second thin-film transistor on the first thin-film transistor that is within the coverage range of the first thin-film transistor; or,

[0019] Form a second thin-film transistor on the first thin-film transistor that completely covers the first thin-film transistor.

[0020] In a possible implementation manner, forming a second thin-film transistor on the first thin-film transistor specifically includes:

[0021] Form a common gate electrode above the first semiconductor layer, the first source electrode, and the first drain electrode, and the common gate electrode is used to drive the first thin-film transistor and the second thin-film transistor;

[0022] Form a second semiconductor layer, a second source electrode, and a second drain electrode above the common gate electrode.

[0023] In a possible implementation manner, forming a first thin-film transistor on a substrate specifically includes:

[0024] Form a buffer layer on the substrate; wherein, the buffer layer includes a first buffer layer and a second buffer layer that are sequentially stacked on the substrate;

[0025] Form a first semiconductor layer on the buffer layer;

[0026] Form a gate insulating layer on the buffer layer, and the gate insulating layer covers the first semiconductor layer;

[0027] Form a common gate electrode on the gate insulating layer;

[0028] A gate protection layer is formed on the gate insulating layer, and the gate protection layer covers the common gate.

[0029] A first source electrode and a first drain electrode are formed in the gate protection layer, and the first source electrode and the first drain electrode are in contact with the first semiconductor layer.

[0030] In a possible implementation manner, forming a first source electrode and a first drain electrode in the gate protection layer specifically includes:

[0031] A first gate protection layer is formed on the gate insulating layer, and the first gate protection layer covers the common gate.

[0032] A contact hole communicating with the first semiconductor layer is formed in the first gate protection layer and the gate insulating layer.

[0033] A first source electrode and a first drain electrode are formed on the first gate protection layer, and the first source electrode and the first drain electrode are in contact with the first semiconductor layer through the contact hole.

[0034] A second gate protection layer is formed on the first gate protection layer, and the second gate protection layer covers the first source electrode and the first drain electrode.

[0035] In a possible implementation manner, forming a second thin film transistor on the first thin film transistor specifically includes:

[0036] An oxide insulating layer is formed on the second gate protection layer.

[0037] A second semiconductor layer is formed on the oxide insulating layer.

[0038] A second source electrode and a second drain electrode are formed on the oxide insulating layer, and the second source electrode and the second drain electrode are respectively lapped on both sides of the second semiconductor layer.

[0039] A metal oxide protection layer is formed on the oxide insulating layer, and the metal oxide protection layer covers the second semiconductor layer and the second source electrode and the second drain electrode.

[0040] The present invention provides a low-temperature polycrystalline oxide array substrate and a manufacturing method thereof. The array substrate forms a thin-film transistor component by arranging a first thin-film transistor and a second thin-film transistor on a substrate. The semiconductor layer of the first thin-film transistor adopts a polysilicon semiconductor layer, and the semiconductor layer of the second thin-film transistor adopts a metal oxide semiconductor layer. The first thin-film transistor is driven by the polysilicon semiconductor layer, and the second thin-film transistor is driven by the metal oxide semiconductor layer. The first thin-film transistor and the second thin-film transistor act together on each pixel of the array substrate, meeting the high-resolution requirements of large-size display panels. At the same time, by arranging the first thin-film transistor and the second thin-film transistor along the stacking direction of the array substrate, and having an overlapping area in the vertical direction between the first thin-film transistor and the second thin-film transistor, the area ratio occupied by the thin-film transistor component in the pixel can be reduced, the pixel aperture ratio can be increased, and the power consumption can be reduced.

[0041] The LTPO (Low Temperature Polycrystalline Oxide) thin-film transistor array substrate integrates two devices, namely low-temperature polysilicon (LTPS) TFT and oxide (Oxide) TFT, within one sub-pixel. The LTPO panel technology combines the advantages of the strong driving ability of the LTPS TFT process and the small leakage current and low power consumption of the Oxide TFT process. The LTPS TFT is used to drive the display, and the Oxide TFT is used for switching, thus effectively reducing the power consumption of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative labor.

[0043] Figure 1 It is a schematic structural diagram of the low-temperature polycrystalline oxide array substrate provided in Embodiment 1 of the present invention;

[0044] Figure 2 It is a schematic flow chart of the manufacturing method of the low-temperature polycrystalline oxide array substrate provided in Embodiment 2 of the present invention;

[0045] Figure 3 It is a schematic flow chart of forming the first thin-film transistor on the substrate provided in Embodiment 2 of the present invention;

[0046] Figure 4Schematic diagram of forming a buffer layer on a substrate according to the second embodiment of the present invention;

[0047] Figure 5 Schematic diagram of forming a first semiconductor layer on the buffer layer according to the second embodiment of the present invention;

[0048] Figure 6 Schematic diagram of forming a gate insulating layer on the buffer layer according to the second embodiment of the present invention;

[0049] Figure 7 Schematic diagram of forming a common gate on the gate insulating layer according to the second embodiment of the present invention;

[0050] Figure 8 Schematic diagram of forming a first gate protection layer on the gate insulating layer according to the second embodiment of the present invention;

[0051] Figure 9 Schematic diagram of forming a contact hole in the first gate protection layer and the gate insulating layer according to the second embodiment of the present invention;

[0052] Figure 10 Schematic diagram of forming a first source electrode and a first drain electrode on the first gate protection layer according to the second embodiment of the present invention;

[0053] Figure 11 Schematic diagram of forming a second gate protection layer on the first gate protection layer according to the second embodiment of the present invention;

[0054] Figure 12 Flow chart of forming a second thin film transistor on the first thin film transistor according to the second embodiment of the present invention;

[0055] Figure 13 Schematic diagram of forming an oxide insulating layer on the second gate protection layer according to the second embodiment of the present invention;

[0056] Figure 14 Schematic diagram of forming a second semiconductor layer on the oxide insulating layer according to the second embodiment of the present invention;

[0057] Figure 15 Schematic diagram of forming a second source electrode and a second drain electrode on the oxide insulating layer according to the second embodiment of the present invention;

[0058] Figure 16 Schematic diagram of forming a metal oxide protection layer on the oxide insulating layer according to the second embodiment of the present invention.

[0059] Explanation of reference numerals:

[0060] 1 - Substrate substrate; 2 - Buffer layer; 31 - First semiconductor layer; 32 - First source electrode; 33 - First drain electrode; 4 - Gate insulating layer; 41 - Contact hole; 5 - Common gate; 6 - Gate protection layer; 61 - First gate protection layer; 62 - Second gate protection layer; 7 - Oxide insulating layer; 81 - Second semiconductor layer; 82 - Second source electrode; 83 - Second drain electrode; 9 - Metal oxide protection layer. Detailed implementation manners

[0061] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below with reference to the accompanying drawings in the present invention. Apparently, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art without making creative efforts based on the embodiments in the present invention belong to the scope of protection of the present invention.

[0062] In recent years, thin film transistor liquid crystal displays (TFT-LCDs) have achieved rapid development. Especially for liquid crystal televisions, their sizes and resolutions have been continuously increasing. Currently, the largest liquid crystal television in the world has exceeded 100 inches.

[0063] Currently, most of the thin film transistors (TFTs) in TFT-LCDs are polysilicon TFTs with relatively high mobilities. Polysilicon TFTs are usually fabricated by an excimer laser annealing (ELA) process. Due to the limitation of the laser pulse width, the formed polysilicon has poor uniformity, which directly affects the uniformity of the TFTs and severely limits their applications. TFTs generally can only be used for display panels below 6G (1200*1800 mm) and are not suitable for large-size display panels.

[0064] In addition, although polysilicon TFTs have relatively high mobilities, the off-state current of polysilicon TFTs is large, and when used to drive pixel electrodes, the power consumption is relatively high. Therefore, in the prior art, metal oxide TFTs are used to replace polysilicon TFTs. The mobilities of metal oxide TFTs are also relatively high (slightly lower than those of polysilicon TFTs), which can fully meet the pixel driving requirements; moreover, metal oxide TFTs have a lower off-state current, and when used to drive pixel electrodes, the power consumption of the display panel can be reduced.

[0065] However, as the resolution of the display panel increases, for both polysilicon TFTs and metal oxide TFTs, the area ratio occupied by the TFTs in the pixel becomes larger and larger, the aperture ratio of the pixel decreases accordingly, and the power consumption of the display panel increases.

[0066] Therefore, this embodiment provides a low-temperature polycrystalline oxide array substrate and a manufacturing method thereof, so as to reduce the area ratio occupied by the TFT in the pixel, improve the aperture ratio of the pixel, and reduce the power consumption of the display panel while meeting the high-resolution requirements of a large-size display panel.

[0067] Among them, the LTPO (Low Temperature Polycrystalline Oxide) array substrate integrates two devices, namely low-temperature polysilicon (LTPS) TFT and oxide (Oxide) TFT, within a single sub-pixel. The LTPO panel technology combines the advantages of strong driving ability of the LTPS TFT process and low leakage current and low power consumption of the Oxide TFT process. The LTPS TFT is used to drive the display, and the Oxide TFT is used for switching, thus effectively reducing the power consumption of the display panel.

[0068] Embodiment 1

[0069] Figure 1 It is a schematic structural diagram of the low-temperature polycrystalline oxide array substrate provided in Embodiment 1 of the present invention. As Figure 1 shown, this embodiment provides a low-temperature polycrystalline oxide array substrate, which can be applied and is not limited to the OLED, Mini-LED, Micro-LED, and liquid crystal display fields.

[0070] The low-temperature polycrystalline oxide array substrate (hereinafter referred to as the array substrate) includes a substrate 1 and a thin-film transistor assembly disposed on the substrate 1. The thin-film transistor assembly includes a first thin-film transistor and a second thin-film transistor. The second thin-film transistor is disposed above the first thin-film transistor along the stacking direction of the array substrate, and the first thin-film transistor and the second thin-film transistor have an overlapping area in the vertical direction.

[0071] As Figure 1 shown, the array substrate includes a substrate 1. The substrate 1 serves as the basic bearing structure of the array substrate, and the remaining hierarchical structures of the array substrate are all formed on the substrate 1. Among them, the substrate 1 can be a quartz substrate or a glass substrate.

[0072] The array substrate forms a pixel area for displaying an image on the substrate 1. Multiple data lines and multiple scan lines are distributed in the pixel area. The multiple data lines and multiple scan lines divide the pixel area into multiple sub-pixels arranged in a matrix in the plane. At least one thin-film transistor (Thin-film transistor, hereinafter referred to as TFT) is provided in each sub-pixel, and the display state of the corresponding sub-pixel is controlled by each TFT.

[0073] Specifically, multiple data lines are arranged parallel to each other and at equal intervals, multiple scanning lines are arranged parallel to each other and at equal intervals, and the data lines and the scanning lines are arranged horizontally and vertically intersecting in space. For example, taking the shape of the array substrate as a rectangle, the data lines can extend along the width direction of the array substrate, and the scanning lines can extend along the length direction of the array substrate, so as to divide the pixel regions on the array substrate into multiple sub-pixels arranged in a matrix form by the data lines and the scanning lines. For example, multiple sub-pixels with the same size and in the shape of a rectangle can be formed.

[0074] With the continuous increase of the size of TFT-LCDs and the continuous improvement of the resolution, in order to improve the display quality, TFT-LCDs adopt a driving circuit with a higher frequency to drive pixels. The mobility of the existing amorphous silicon TFTs is difficult to meet the requirements. The mobility of amorphous silicon TFTs is generally about 0.5 cm 2 / V·s. When the size of the liquid crystal display exceeds 80 inches and the driving frequency is 120 Hz, a mobility of more than 1 cm 2 / V·s is required, and the mobility of the existing amorphous silicon is obviously difficult to meet.

[0075] In this regard, as Figure 1 shown, for the array substrate provided in this embodiment, by providing a thin film transistor component on the substrate 1, the thin film transistor component includes a first thin film transistor and a second thin film transistor. It can be understood that a thin film transistor component is provided in each sub-pixel, that is, a first thin film transistor and a second thin film transistor are provided in each sub-pixel. For a large-size and high-resolution display panel, by jointly driving the sub-pixels by the first thin film transistor and the second thin film transistor, not only can the driving requirements of the sub-pixels be met, but also the mobility of the thin film transistor component can be improved to meet the high-resolution requirements.

[0076] In addition, with the improvement of the resolution, the more sub-pixels arranged in the array substrate, the smaller the area of each sub-pixel. Correspondingly, since the size of the TFTs in the sub-pixels is relatively fixed, the area ratio of the sub-pixels occupied by the TFTs increases relatively, resulting in a decrease in the aperture ratio of the sub-pixels and an increase in the power consumption of the display panel.

[0077] In this embodiment, in the stacking direction of the array substrate, by arranging the second thin film transistor above the first thin film transistor, and the second thin film transistor and the first thin film transistor have an overlapping area in the vertical direction, the overall area occupied by the thin film transistor component is smaller than the sum of the areas occupied by the first thin film transistor and the second thin film transistor respectively.

[0078] With such a setting, when the first thin-film transistor and the second thin-film transistor are used to jointly drive the sub-pixel, the driving ability of the thin-film transistor component for the sub-pixel is enhanced. While meeting the requirements of high resolution, the area ratio of the sub-pixel occupied by the thin-film transistor component composed of the first thin-film transistor and the second thin-film transistor is reduced, the aperture ratio of the sub-pixel is increased, and the power consumption of the display panel is reduced.

[0079] Among them, the first thin-film transistor includes a first semiconductor layer 31, a first source electrode 32 and a first drain electrode 33 respectively connected to both sides of the first semiconductor layer 31. The second thin-film transistor includes a second semiconductor layer 81, a second source electrode 82 and a second drain electrode 83 respectively connected to both sides of the second semiconductor layer 81. And one of the first semiconductor layer 31 and the second semiconductor layer 81 is a polysilicon semiconductor layer, and the other is a metal oxide semiconductor layer.

[0080] As Figure 1 shown, specifically, the first thin-film transistor includes a first semiconductor layer 31, a first source electrode 32 and a first drain electrode 33. The first source electrode 32 and the first drain electrode 33 are respectively located on both sides of the first semiconductor layer 31, and both the first source electrode 32 and the first drain electrode 33 are connected to the first semiconductor layer 31. In a specific application, the first source electrode 32 can be connected to the data line in the array substrate, and the data line transmits the signal to the first source electrode 32. The first source electrode 32 transmits the signal to the first drain electrode 33 through the first semiconductor layer 31.

[0081] Similarly, the second thin-film transistor includes a second semiconductor layer 81, a second source electrode 82 and a second drain electrode 83. The second source electrode 82 and the second drain electrode 83 are respectively located on both sides of the second semiconductor layer 81, and both the second source electrode 82 and the second drain electrode 83 are connected to the second semiconductor layer 81. In a specific application, the second source electrode 82 can be connected to the data line in the array substrate, and the data line transmits the signal to the second source electrode 82. The second source electrode 82 transmits the signal to the second drain electrode 83 through the second semiconductor layer 81.

[0082] It should be noted that for the same sub-pixel, the first source electrode 32 and the second source electrode 82 can be connected to the same data line, and the data line transmits signals to the first source electrode 32 and the second source electrode 82 at the same time; or, there are different data lines in the array substrate that are respectively connected to the first source electrode 32 and the second source electrode 82, and signals are transmitted to the first source electrode 32 and the second source electrode 82 through different data lines. For example, the data line corresponding to the first source electrode 32 is arranged in the same layer as the first source electrode 32, and the data line corresponding to the second source electrode 82 is arranged in the same layer as the second source electrode 82.

[0083] Further, the materials of the semiconductor layers in the first thin-film transistor and the second thin-film transistor of this embodiment are different. One of the first semiconductor layer 31 and the second semiconductor layer 81 is a polysilicon semiconductor layer, and the other is a metal oxide semiconductor layer.

[0084] Taking the first semiconductor layer 31 as a polysilicon semiconductor layer and the second semiconductor layer 81 as a metal oxide semiconductor layer as an example, that is, the first thin-film transistor is a polysilicon TFT, and the second thin-film transistor is a metal oxide TFT. By setting the polysilicon TFT as the first thin-film transistor, the polysilicon TFT has a high mobility and can meet the driving circuit with a relatively high frequency. By setting the metal oxide TFT as the second thin-film transistor, although the mobility of the metal oxide TFT is slightly lower than that of the polysilicon TFT, it can meet the driving requirements for sub-pixels. Moreover, the metal oxide TFT has good uniformity and high transparency, and the manufacturing process is simple, which can better meet the requirements of large-size liquid crystal displays and active organic electroluminescence, and can meet the requirements of LCD and OLED with high refresh frequencies and high mobilities.

[0085] Since the off-state current of the polysilicon TFT is larger than that of the metal oxide TFT, in some embodiments, for a sub-pixel, due to the smaller off-state current of the metal oxide TFT, it can mainly act as a switch, that is, mainly used to control the on and off of the sub-pixel; while the off-state current of the polysilicon TFT is larger, it can mainly play a role in controlling the sub-pixel, that is, mainly used to control the brightness and darkness of the sub-pixel. This embodiment does not make specific limitations on this.

[0086] The off-state current of the TFT refers to the leakage current generated in the TFT when the TFT is in the off state.

[0087] As Figure 1 shown, in this embodiment, the thin-film transistor assembly may further include a common gate 5. The common gate 5 is disposed between the first semiconductor layer 31 and the second semiconductor layer 81 along the stacking direction of the array substrate. The common gate 5 is used to drive the first thin-film transistor and the second thin-film transistor.

[0088] Usually, the TFTs provided in each sub-pixel in the array substrate include gates. The gates are used to control the properties of the semiconductor layers of the TFTs, so that the semiconductor layers are conductorized to transmit signals. Specifically, the gates are usually connected to scan lines. After the scan lines are powered on to generate electrical signals, the electrical signals are transmitted to the gates. After the gates are charged, the semiconductor layers can be conductorized. The conductorized semiconductor layers transmit the electrical signals of the source electrodes to the drain electrodes, thereby conducting the TFTs and making the TFTs in the on state. At this time, the TFTs can control the corresponding sub-pixels to display images.

[0089] In this embodiment, a thin-film transistor component is formed by providing a first thin-film transistor and a second thin-film transistor in each sub-pixel. By providing a common gate 5 to drive the first thin-film transistor and the second thin-film transistor simultaneously, that is, the common gate 5 can drive the first semiconductor layer 31 in the first thin-film transistor to be conductive and can also drive the second semiconductor layer 81 in the second thin-film transistor to be conductive. This makes the driving of the first thin-film transistor and the second thin-film transistor simpler, simplifies the structure of the thin-film transistor component, and reduces the area ratio of the thin-film transistor component occupying the sub-pixel.

[0090] It should be noted that for one of the sub-pixels, the first thin-film transistor and the second thin-film transistor can share the scanning line, that is, the first thin-film transistor and the second thin-film transistor are driven by the same scanning line, and this scanning line is connected to the common gate 5 on the same layer. For example, the common gate 5 can be a branch extending from this scanning line.

[0091] In order to further reduce the area ratio of the thin-film transistor component occupying the sub-pixel, in a possible implementation manner, the orthographic projection of one of the first thin-film transistor and the second thin-film transistor on the substrate 1 can be located within the coverage range of the orthographic projection of the other on the substrate 1.

[0092] As Figure 1 shown, in the stacking direction of the array substrate, the common gate 5 is correspondingly provided between the first semiconductor layer 31 of the first thin-film transistor and the second semiconductor layer 81 of the second thin-film transistor, and the common gate 5 is located within the coverage range of the orthographic projections of the first thin-film transistor and the second thin-film transistor.

[0093] In a specific embodiment, the coverage area of the first thin-film transistor is larger than that of the second thin-film transistor, and the orthographic projection of the second thin-film transistor on the substrate 1 is completely located within the coverage range of the orthographic projection of the first thin-film transistor on the array substrate; in another specific embodiment, the coverage area of the second thin-film transistor is larger than that of the first thin-film transistor, and the orthographic projection of the first thin-film transistor on the substrate 1 is completely located within the coverage range of the orthographic projection of the second thin-film transistor on the array substrate.

[0094] Regardless of either of the above two embodiments, the area occupied by the thin-film transistor component in the sub-pixel is the area occupied by the larger one of the first thin-film transistor and the second thin-film transistor. Therefore, the occupied area of the thin-film transistor can be further reduced, the aperture ratio of the sub-pixel can be increased, and the power consumption of the display panel can be reduced.

[0095] As Figure 1As shown, in a possible implementation, the thin film transistor component may further include a buffer layer 2 disposed on the substrate 1, and the first semiconductor layer 31 is disposed on the buffer layer 2. By providing the buffer layer 2 on the substrate 1 and disposing the first semiconductor layer 31 on the buffer layer 2, the first semiconductor layer 31 is prevented from being directly disposed on the substrate 1. The buffer layer 2 can protect the first semiconductor layer 31 to prevent the semiconductor properties of the first semiconductor layer 31 from being affected.

[0096] In a specific implementation, the buffer layer 2 may include a first buffer layer and a second buffer layer that are sequentially stacked on the substrate 1. By sequentially providing the first buffer layer and the second buffer layer on the substrate 1 and disposing the first semiconductor layer 31 on the second buffer layer, the first buffer layer and the second buffer layer have a better protective effect on the first semiconductor layer 31.

[0097] For example, the first buffer layer is a silicon nitride layer, and the second buffer layer is a silicon oxide layer. The silicon nitride layer, as the first buffer layer, is directly formed on the substrate 1 and has a good effect of isolating water vapor, which can isolate the water vapor outside the array substrate or from the substrate 1 and prevent the water vapor from entering the semiconductor layer; the silicon oxide layer, as the second buffer layer, is directly in contact with the first semiconductor layer 31 and has good density and contains a large number of oxygen atoms. These oxygen atoms can diffuse into the first semiconductor layer 31 to supplement the oxygen atoms in the first semiconductor layer 31 and help the first semiconductor layer 31 maintain its semiconductor characteristics, preventing the oxygen atoms in the first semiconductor layer 31 from combining with the metal ions in the first source electrode 32 or the first drain electrode 33 and causing it to lose its semiconductor characteristics.

[0098] As Figure 1 As shown, in this embodiment, the thin film transistor component may further include a gate insulating layer 4 disposed on the buffer layer 2. The gate insulating layer 4 covers the first semiconductor layer 31, and the common gate electrode 5 is disposed on the gate insulating layer 4. By providing the gate insulating layer 4 between the common gate electrode 5 and the first semiconductor layer 31, on the one hand, the gate insulating layer 4 is insulatingly disposed between the first semiconductor layer 31 and the common gate electrode 5. In this way, when an electrical signal is generated in the common gate electrode 5, the common gate electrode 5 can conduct the first semiconductor layer 31 through the gate insulating layer 4, enabling the first semiconductor layer 31 to transfer the signal in the first source electrode 32 to the first drain electrode 33; on the other hand, the gate insulating layer 4 can protect the first semiconductor layer 31 from being affected by the common gate electrode 5 and enable the first semiconductor layer 31 to maintain its semiconductor properties.

[0099] Exemplarily, the gate insulating layer 4 may be a silicon oxide layer, or the gate insulating layer 4 may be a metal oxide layer. For example, the gate insulating layer 4 is composed of Al2O3.

[0100] In addition, in this embodiment, the common gate 5 provided on the gate insulating layer 4 may have a double-layer structure. The bottom layer directly formed on the gate insulating layer 4 is used to increase the adhesion between the upper layer stacked thereon and the gate insulating layer 4. For example, the bottom layer of the common gate 5 may be composed of metals such as Mo, Ti, W or alloy materials such as Mo alloy and Ti alloy. The upper layer of the common gate 5 may be composed of metal Cu. Metal Cu has low resistance and good electrical conductivity, which can effectively improve the delay phenomenon of the gate signal and enhance the display effect of the display panel. In this regard, the bottom layer of the common gate 5 can also prevent the Cu in the upper layer of the common gate 5 from diffusing into the gate insulating layer 4.

[0101] In the thin-film transistor assembly of this embodiment, a gate protection layer 6 is further provided on the gate insulating layer 4, and the gate protection layer 6 covers the common gate 5. Among them, a contact hole 41 communicating with the first semiconductor layer 31 is provided in the gate protection layer 6 and the gate insulating layer 4. The first source electrode 32 and the first drain electrode 33 are provided in the gate protection layer 6 and contact the first semiconductor layer 31 through the contact hole 41.

[0102] As Figure 1 shown, in this embodiment, the second thin-film transistor is stacked on the first thin-film transistor. By providing the gate protection layer 6 on the gate insulating layer 4, the second thin-film transistor can be provided on the gate protection layer 6. The gate protection layer 6 is used to be spaced between the common gate 5 and the second semiconductor layer 81 of the second thin-film transistor to protect the semiconductor performance of the second semiconductor layer 81 from being affected.

[0103] Exemplarily, similar to the buffer layer 2 provided between the substrate 1 and the first semiconductor layer 31, the gate protection layer 6 may include a first gate protection layer 61 and a second gate protection layer 62 stacked in sequence on the gate insulating layer 4. The first gate protection layer 61 may be, for example, a silicon nitride layer or a silicon oxynitride layer, which directly covers the common gate 5 and can effectively prevent the Cu in the common gate 5 from diffusing into the second semiconductor layer 81 to prevent the semiconductor performance of the second semiconductor layer 81 from failing. The second gate protection layer 62 stacked on the first gate protection layer 61 may be, for example, an organic resin layer. By providing the organic resin layer as the second gate protection layer 62, a planarization effect can be achieved and it has an insulating function at the same time.

[0104] Among them, the first source electrode 32 and the first drain electrode 33 respectively connected to both sides of the first semiconductor layer 31 are provided in the gate protection layer 6. By providing a communicating contact hole 41 in the gate protection layer 6 and the gate insulating layer 4, the contact hole 41 communicates with the surface of the first semiconductor layer 31. It can be understood that contact holes 41 are provided on both sides of the first semiconductor layer 31, and the first source electrode 32 and the first drain electrode 33 respectively contact the first semiconductor layer 31 through the corresponding contact holes 41.

[0105] Specifically, the first source electrode 32 and the first drain electrode 33 can be formed of the same metal material through the same process. For example, the first source electrode 32 and the first drain electrode 33 can be made of metals or alloy materials such as Cr, W, Ti, Ta, Mo, Al, Cu, etc. Alternatively, similar to the common gate electrode 5, the first source electrode 32 and the first drain electrode 33 can both be double-layer structures. The bottom layer of the first source electrode 32 and the first drain electrode 33 can be made of metals such as Mo, Ti, W or Mo alloys, Ti alloys, etc., and the upper layer of the first source electrode 32 and the first drain electrode 33 can be made of metal Cu.

[0106] As Figure 1 shown, for the case where the gate protection layer 6 is composed of a first gate protection layer 61 and a second gate protection layer 62 stacked on the first gate protection layer 61, the first source electrode 32 and the first drain electrode 33 can be disposed on the first gate protection layer 61. In this way, the second gate protection layer 62 is spaced between the first source electrode 32, the first drain electrode 33 and the second thin-film transistor, which can protect the second semiconductor layer 81 from the influence of the first source electrode 32 and the first drain electrode 33. In addition, the first source electrode 32, the first drain electrode 33 and the common gate electrode 5 can be separated by the first gate protection layer 61 to prevent the Cu in the common gate electrode 5 from diffusing and connecting with the first source electrode 32 and the first drain electrode 33, resulting in the short-circuit failure of the first thin-film transistor.

[0107] In a possible implementation manner, the thin-film transistor assembly may further include an oxide insulating layer 7 disposed on the gate protection layer 6, and the second semiconductor layer 81, the second source electrode 82 and the second drain electrode 83 are all disposed on the oxide insulating layer 7. As Figure 1 shown, an oxide insulating layer 7 is further disposed on the second gate protection layer 62, and the second semiconductor layer 81, the second source electrode 82 and the second drain electrode 83 of the second thin-film transistor are all disposed on the oxide insulating layer 7. Among them, the oxide insulating layer 7 can be, for example, a silicon oxide layer, and the oxygen atoms rich in the silicon oxide layer can diffuse into the second semiconductor layer 81 to supplement the oxygen atoms in the second semiconductor layer 81 and help the second semiconductor layer 81 maintain its semiconductor characteristics.

[0108] The second semiconductor layer 81 disposed on the oxide insulating layer 7 is a metal oxide semiconductor layer. For example, the metal oxide constituting the second semiconductor layer 81 is indium gallium zinc oxide (abbreviated as IGZO), or the second semiconductor layer 81 can also adopt Ln-IZO, ITZO, ITGZO, HIZO, IZO (InZnO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, Cd-Sn-O or other metal oxides.

[0109] The second source electrode 82 and the second drain electrode 83 connected to both sides of the second semiconductor layer 81 can be made of metals or alloys such as Cr, W, Ti, Ta, Mo, Al, Cu, etc., or the second source electrode 82 and the second drain electrode 83 can adopt the same double-layer structure as the common gate electrode 5, which will not be elaborated here.

[0110] As Figure 1 shown, in a possible implementation manner, the thin film transistor assembly may further include a metal oxide protection layer 9 disposed on the oxide insulating layer 7, and the metal oxide protection layer 9 can cover the second semiconductor layer 81, the second source electrode 82, and the second drain electrode 83. By covering the metal oxide protection layer 9 on the second semiconductor layer 81, the second source electrode 82, and the second drain electrode 83 of the second thin film transistor, the second semiconductor layer 81 is protected. Among them, the metal oxide protection layer 9 can be an oxide or a nitride oxide to isolate external water vapor through the metal oxide protection layer 9, or supplement oxygen atoms in the second semiconductor layer 81 to maintain its semiconductor performance.

[0111] The array substrate provided in this embodiment forms a thin film transistor assembly by disposing a first thin film transistor and a second thin film transistor on a substrate substrate. The semiconductor layer of the first thin film transistor adopts a polysilicon semiconductor layer, and the semiconductor layer of the second thin film transistor adopts a metal oxide semiconductor layer; the first thin film transistor is driven by the polysilicon semiconductor layer, and the second thin film transistor is driven by the metal oxide semiconductor layer. The first thin film transistor and the second thin film transistor act together on each pixel of the array substrate, which can meet the high-resolution requirements of large-size display panels; at the same time, by arranging the first thin film transistor and the second thin film transistor along the stacking direction of the array substrate, and the first thin film transistor and the second thin film transistor have an overlapping area in the vertical direction, this can reduce the area ratio occupied by the thin film transistor assembly in the pixel, increase the pixel aperture ratio, and reduce power consumption.

[0112] Embodiment 2

[0113] Figure 2 is a schematic flow chart of a manufacturing method for a low-temperature polycrystalline oxide array substrate provided in Embodiment 2 of the present invention. As Figure 2 shown, this embodiment provides a manufacturing method for a low-temperature polycrystalline oxide array substrate, and this manufacturing method is used to manufacture the low-temperature polycrystalline oxide array substrate described in Embodiment 1. Among them, the structure, function, and working principle of the low-temperature polycrystalline oxide array substrate are introduced in detail in Embodiment 1, and will not be elaborated here.

[0114] As Figure 2 shown, the manufacturing method of the low-temperature polycrystalline oxide array substrate includes the following steps:

[0115] S100. Form a first thin-film transistor on the substrate 1. Among them, the first thin-film transistor includes a first semiconductor layer 31, a first source electrode 32, a first drain electrode 33, and a common gate electrode 5. The first source electrode 32 and the first drain electrode 33 are respectively connected to both sides of the first semiconductor layer 31.

[0116] In this embodiment, first, a first thin-film transistor is formed on the substrate 1, and then a second thin-film transistor is formed above the first thin-film transistor. The second thin-film transistor and the first thin-film transistor together constitute the thin-film transistor components corresponding to each sub-pixel in the array substrate to meet the requirements of the driving performance of the thin-film transistor components for large-size and high-resolution display panels.

[0117] Among them, the first thin-film transistor at least includes a first semiconductor layer 31, a first source electrode 32, and a first drain electrode 33 connected to both sides of the first semiconductor layer 31.

[0118] S200. Form a second thin-film transistor on the first thin-film transistor. The second thin-film transistor and the first thin-film transistor have an overlapping area in the direction perpendicular to the substrate 1. Among them, the second thin-film transistor includes a second semiconductor layer 81, a second source electrode 82, a second drain electrode 83, and a common gate electrode. The second source electrode 82 and the second drain electrode 83 are respectively connected to both sides of the second semiconductor layer 81, and one of the first semiconductor layer 31 and the second semiconductor layer 81 is a polysilicon semiconductor layer, and the other is a metal oxide semiconductor layer.

[0119] After forming the first thin-film transistor, a second thin-film transistor is formed above the first thin-film transistor. Each sub-pixel of the array substrate is driven by the first thin-film transistor and the second thin-film transistor together to meet the requirements of the driving ability of the TFT for large-size and high-resolution display panels.

[0120] In addition, the second thin-film transistor and the first thin-film transistor have an overlapping area in the stacking direction of the array substrate. This can reduce the area ratio of the sub-pixels occupied by the thin-film transistor components, increase the aperture ratio of the sub-pixels, and reduce the power consumption of the display panel. Among them, the second thin-film transistor at least includes a second semiconductor layer 81, a second source electrode 82, and a second drain electrode 83 connected to both sides of the second semiconductor layer 81.

[0121] One of the first semiconductor layer 31 of the first thin-film transistor and the second semiconductor layer 81 of the second thin-film transistor is a polysilicon semiconductor layer, and the other is a metal oxide semiconductor layer. That is, one of the first thin-film transistor and the second thin-film transistor is a polysilicon TFT, and the other is a metal oxide TFT.

[0122] In this embodiment, the first thin-film transistor and the second thin-film transistor share the above-mentioned common gate 5, and the second thin-film transistor is formed on the first thin-film transistor. The specific steps are as follows:

[0123] A common gate 5 is formed above the first semiconductor layer 31, the first source electrode 32, and the first drain electrode 33. The common gate 5 is used to drive the first thin-film transistor and the second thin-film transistor.

[0124] In the stacking direction of the array substrate, by forming the common gate 5 between the first semiconductor layer 31 and the second semiconductor layer 81, the first thin-film transistor and the second thin-film transistor are simultaneously driven by the common gate 5. This can simplify the structure of the thin-film transistor component and further reduce the area ratio of the sub-pixel occupied by the thin-film transistor component.

[0125] In a possible implementation manner, forming the second thin-film transistor on the first thin-film transistor may specifically include:

[0126] Forming a second thin-film transistor on the first thin-film transistor within the coverage range of the first thin-film transistor; or, forming a second thin-film transistor on the first thin-film transistor that completely covers the first thin-film transistor.

[0127] By making the second thin-film transistor completely cover the first thin-film transistor, or the second thin-film transistor is within the coverage range of the first thin-film transistor, the area occupied by the overall thin-film transistor component is only the area occupied by the one with the larger coverage area among the first thin-film transistor and the second thin-film transistor. This can further effectively reduce the occupied area of the thin-film transistor, further increase the aperture ratio of the sub-pixel, and reduce the power consumption of the display panel.

[0128] Figure 3 It is a schematic flow diagram of forming the first thin-film transistor on the substrate provided in the second embodiment of the present invention; Figure 4 It is a schematic structural diagram of forming a buffer layer on the substrate provided in the second embodiment of the present invention; Figure 5 It is a schematic structural diagram of forming the first semiconductor layer on the buffer layer provided in the second embodiment of the present invention; Figure 6 It is a schematic structural diagram of forming a gate insulating layer on the buffer layer provided in the second embodiment of the present invention; Figure 7 It is a schematic structural diagram of forming a common gate on the gate insulating layer provided in the second embodiment of the present invention; Figure 8 It is a schematic structural diagram of forming a first gate protection layer on the gate insulating layer provided in the second embodiment of the present invention; Figure 9 It is a schematic structural diagram of forming a contact hole in the first gate protection layer and the gate insulating layer provided in the second embodiment of the present invention; Figure 10 It is a schematic structural diagram of forming the first source electrode and the first drain electrode on the first gate protection layer provided in the second embodiment of the present invention;Figure 11 It is a schematic structural diagram of forming a second gate protection layer on the first gate protection layer provided in the second embodiment of the present invention.

[0129] As Figure 3 shown, in this embodiment, to form a first thin film transistor on the substrate 1, the following steps may be specifically included:

[0130] S110. Form a buffer layer 2 on the substrate 1; wherein, the buffer layer 2 includes a first buffer layer and a second buffer layer that are sequentially stacked on the substrate 1.

[0131] As Figure 4 shown, specifically, a buffer layer 2 with a thickness of 2000 - 15000 Å is continuously deposited on the substrate 1 by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. The buffer layer 2 may be a double-layer structure including a first buffer layer and a second buffer layer. For example, the bottom first buffer layer may be a silicon nitride layer, and the deposition thickness of the silicon nitride layer is 1000 - 4000 Å, and the reaction gases for depositing the silicon nitride layer are SiH4, NH3, N2 or SiH2Cl2, NH3, N2; the upper second buffer layer may be a silicon oxide layer, and the deposition thickness of the silicon oxide layer is 200 - 2000 Å, and the corresponding reaction gases are SiH4, N2O.

[0132] Taking the first thin film transistor as a polysilicon TFT as an example, it should be noted that if the second buffer layer directly contacting the first semiconductor layer 31 is composed of silicon nitride or silicon oxynitride, since the H content in the second buffer layer is relatively high, in order to improve the stability of the first thin film transistor, a high-temperature annealing process may be performed on the second buffer layer to reduce the H in the second buffer layer, and at the same time, the H explosion in the ELA annealing process during the formation of the first semiconductor layer 31 (polysilicon semiconductor layer) can be avoided, while improving the performance of the polysilicon TFT, preventing the polysilicon TFT from having an H explosion.

[0133] S120. Form a first semiconductor layer 31 on the buffer layer 2.

[0134] Taking the first thin film transistor as a polysilicon TFT as an example, that is, the first semiconductor layer 31 is a polysilicon semiconductor layer. As Figure 5 shown, an amorphous silicon thin film with a thickness of 200 - 800 Å is continuously deposited on the buffer layer 2 by a PECVD process, and then the amorphous silicon thin film is subjected to high-temperature annealing. For example, it is annealed by an ELA process to melt the amorphous silicon thin film and recrystallize it into a polysilicon thin film in a short time; or, a rapid annealing furnace may also be used for high-temperature annealing, such as annealing at a temperature above 600 °C to melt the amorphous silicon thin film and then grow it into a polysilicon thin film.

[0135] Thereafter, a patterned first semiconductor layer 31 (polycrystalline silicon semiconductor layer) is formed by a first photolithography process.

[0136] A photolithography process is performed on the polycrystalline silicon thin film to form the first semiconductor layer 31. The specific process may be as follows: First, a photoresist layer is coated on the polycrystalline silicon thin film, and a mask is disposed above the polycrystalline silicon thin film. The mask has a light-transmitting region and a light-blocking region. Ultraviolet light is irradiated onto the surface of the photoresist layer through the mask, causing a chemical reaction in the photoresist in the exposed region of the photoresist layer. Then, the exposed photoresist (positive photoresist) or the unexposed photoresist (negative photoresist) is dissolved and removed through a developing technique; thus, the remaining photoresist in the photoresist layer only covers the region corresponding to the first semiconductor layer 31 in the polycrystalline silicon thin film, and the other regions of the polycrystalline silicon thin film are exposed. At this time, the exposed region of the polycrystalline silicon thin film is etched, and finally only the first semiconductor layer 31 is retained. Finally, the photoresist covering the first semiconductor layer 31 is removed, and the first semiconductor layer 31 can be formed on the buffer layer 2.

[0137] It can be understood that the exposure and development process of using ultraviolet light to irradiate the photoresist layer through the mask to transfer the mask pattern on the mask to the photoresist layer to form a photoresist layer pattern, and the process of etching the region not covered by the photoresist layer after forming the photoresist layer pattern are the same as or similar to the above process flow. For the exposure, development, and etching processes that appear after this embodiment, they will not be described in detail one by one.

[0138] S130. A gate insulating layer 4 is formed on the buffer layer 2, and the gate insulating layer 4 covers the first semiconductor layer 31.

[0139] As Figure 6 shown, after completing step S120, a gate insulating layer 4 with a thickness of 2000 - 10000 Å is deposited on the buffer layer 2 by PECVD process, and the gate insulating layer 4 covers the first semiconductor layer 31. For example, the gate insulating layer 4 may be a silicon oxide layer, and the corresponding reaction gases may be SiH4 and N2O; or, the gate insulating layer 4 may be a metal oxide layer, for example, an Al2O3 thin film is formed by magnetron sputtering.

[0140] S140. A common gate 5 is formed on the gate insulating layer 4.

[0141] As Figure 7As shown, a gate metal layer with a thickness of about 1000 - 1500 Å is deposited on the gate insulating layer 4 by sputtering or thermal evaporation. The gate metal layer can be divided into two layers. For example, the upper layer can be a Cu layer, which mainly plays a conductive role, and the lower layer directly formed on the gate insulating layer 4 can be composed of metals such as Mo, Ti, W or alloy materials such as Mo alloy, Ti alloy. The lower layer of the common gate 5 is used to increase the adhesion between the Cu layer and the gate insulating layer 4 and prevent Cu in the Cu layer from diffusing into the gate insulating layer 4.

[0142] After that, a patterned common gate 5 is formed through a second photolithography process.

[0143] S150. A gate protection layer 6 is formed on the gate insulating layer 4, and the gate protection layer 6 covers the common gate 5.

[0144] After forming the common gate 5, a gate protection layer 6 with a thickness of 2000 - 15000 Å is continuously deposited on the gate insulating layer 4 by PECVD process.

[0145] S160. A first source electrode 32 and a first drain electrode 33 are formed in the gate protection layer 6, and the first source electrode 32 and the first drain electrode 33 are in contact with the first semiconductor layer 31.

[0146] Specifically, as Figure 8 shown, first, a first gate protection layer 61 is formed on the gate insulating layer 4, and the first gate protection layer 61 covers the common gate 5.

[0147] The gate protection layer 6 is divided into a first gate protection layer 61 and a second gate protection layer 62. First, the first gate protection layer 61 is deposited. For example, the first gate protection layer 61 is a silicon nitride layer or a silicon oxynitride layer, and the deposition thickness is 1500 - 10000 Å. Exemplarily, a silicon nitride layer can be preferably used as the first gate protection layer 61. The silicon nitride layer can effectively prevent Cu in the common gate 5 from diffusing and prevent Cu from diffusing into the second semiconductor layer 81 (metal oxide semiconductor layer) to cause metal oxide TFT failure; at the same time, it can effectively prevent Cu in the common gate 5 from diffusing to the connection with the first source electrode 32 and the first drain electrode 33 to cause polysilicon TFT short - circuit failure. Among them, the reaction gases for forming the silicon nitride layer can be SiH4, NH3, N2 or SiH2Cl2, NH3, N2.

[0148] As Figure 9 shown, after forming the first gate protection layer 61, next, contact holes 41 connecting to the first semiconductor layer 31 are formed in the first gate protection layer 61 and the gate insulating layer 4. Through a third photolithography process, contact holes 41 located on both sides of the first semiconductor layer 31 are correspondingly formed in the first gate protection layer 61 and the gate insulating layer 4. For example, the contact holes 41 can be formed by dry etching.

[0149] AsFigure 10 As shown, after forming the contact hole 41, a first source electrode 32 and a first drain electrode 33 are formed on the first gate protection layer 61. The first source electrode 32 and the first drain electrode 33 are in contact with the first semiconductor layer 31 through the contact hole 41.

[0150] A first source-drain metal layer with a thickness of about 500 - 4000 angstroms is continuously deposited by sputtering or thermal evaporation. The first source-drain metal layer can be made of metals or alloys such as Cr, W, Ti, Ta, Mo, Al, Cu, etc., or the first source-drain metal layer can have the same structure as the common gate 5. Through the fourth photolithography process, the first source-drain metal layer is patterned into the first source electrode 32 and the first drain electrode 33.

[0151] As Figure 11 shown, after forming the first source electrode 32 and the first drain electrode 33, a second gate protection layer 62 is formed on the first gate protection layer 61. The second gate protection layer 62 covers the first source electrode 32 and the first drain electrode 33. For example, an organic resin can be spin-coated on the first gate protection layer 61 as the second gate protection layer 62. The thickness of the organic resin after baking is 4000 - 50000 angstroms, which can perform the functions of planarization and insulation.

[0152] Figure 12 It is a schematic flow chart for forming a second thin film transistor on the first thin film transistor provided by the second embodiment of the present invention; Figure 13 It is a schematic structural diagram for forming an oxide insulating layer on the second gate protection layer provided by the second embodiment of the present invention; Figure 14 It is a schematic structural diagram for forming a second semiconductor layer on the oxide insulating layer provided by the second embodiment of the present invention; Figure 15 It is a schematic structural diagram for forming a second source electrode and a second drain electrode on the oxide insulating layer provided by the second embodiment of the present invention; Figure 16 It is a schematic structural diagram for forming a metal oxide protection layer on the oxide insulating layer provided by the second embodiment of the present invention.

[0153] As Figure 12 shown, forming a second thin film transistor on the first thin film transistor can specifically include the following steps:

[0154] S210. Form an oxide insulating layer 7 on the second gate protection layer 62.

[0155] As Figure 13 shown, after forming the second gate protection layer 62, an oxide insulating layer 7 with a thickness of 300 - 2000 angstroms is deposited thereon by PECVD process. The oxide insulating layer 7 can be, for example, a silicon oxide layer, and the corresponding reaction gases can be SiH4 and N2O; or, the oxide insulating layer 7 can be other metal oxide layers, such as Al2O3, HfOx, Ta2O5, etc.

[0156] S220. Form a second semiconductor layer 81 on the oxide insulating layer 7.

[0157] As Figure 14 shown, after forming the oxide insulating layer 7, deposit a second semiconductor metal layer with a thickness of about 100 - 2000 Å on the oxide insulating layer 7 by sputtering or thermal evaporation. For example, the second semiconductor metal layer can be a metal oxide semiconductor metal layer, and the metal oxide semiconductor metal layer can be composed of, for example, IGZO, or Ln-IZO, ITZO, ITGZO, HIZO, IZO (InZnO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, Cd-Sn-O or other metal oxides can also be used. Then, pattern the metal oxide semiconductor metal layer into the second semiconductor layer 81 through the fifth photolithography process.

[0158] S230. Form a second source electrode 82 and a second drain electrode 83 on the oxide insulating layer 7, and the second source electrode 82 and the second drain electrode 83 are respectively connected to both sides of the second semiconductor layer 81.

[0159] As Figure 15 shown, after forming the second semiconductor layer 81, continuously deposit a second source-drain metal layer with a thickness of about 2000 - 15000 Å on the oxide insulating layer 7 by sputtering or thermal evaporation. The second source-drain metal layer can be composed of metals or alloys such as Cr, W, Ti, Ta, Mo, Al, Cu, etc., or the second source-drain metal layer can be similar to the structure of the common gate electrode 5. Then, pattern the second source-drain metal layer into the second source electrode 82 and the second drain electrode 83 through the sixth photolithography process.

[0160] S240. Form a metal oxide protection layer 9 on the oxide insulating layer 7, and the metal oxide protection layer 9 covers the second semiconductor layer 81 and the second source electrode 82 and the second drain electrode 83.

[0161] As Figure 16 shown, finally deposit a metal oxide protection layer 9 with a thickness of 2000 - 10000 Å on the oxide insulating layer 7 by PECVD process. The metal oxide protection layer 9 can be an oxide or a nitride oxide. The reaction gas corresponding to the oxide of silicon can be SiH4, N2O, and the reaction gas corresponding to the nitride or nitride oxide can be SiH4, NH3, N2 or SiH2Cl2, NH3, N2.

[0162] This embodiment also provides a display panel, which includes a color filter substrate, a liquid crystal layer, and an array substrate. The color filter substrate and the array substrate are disposed opposite to each other, and the liquid crystal layer is sandwiched between the color filter substrate and the array substrate. By applying an electric field between the array substrate and the color filter substrate, the voltage in the electric field can control the alignment of liquid crystal molecules in the liquid crystal layer, thereby achieving the purpose of light shielding and light transmission, so that the display panel displays an image.

[0163] Among them, the structure, function, and working principle of the array substrate are introduced in detail in Embodiment 1, and will not be elaborated here.

[0164] On the other hand, this embodiment also provides a display device, which includes the above-mentioned display panel. Exemplarily, in this embodiment, the display device can be a liquid crystal TV, a notebook computer, a tablet computer, an e-paper, etc.

[0165] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A low-temperature polycrystalline oxide array substrate, characterized in that: The thin film transistor assembly includes a base substrate and a thin film transistor assembly disposed on the base substrate, wherein the thin film transistor assembly includes a first semiconductor layer, a first source electrode, a first drain electrode, a second semiconductor layer, a second source electrode, a second drain electrode, and a common gate electrode, wherein the first source electrode and the first drain electrode are respectively connected to two sides of the first semiconductor layer, and the second source electrode and the second drain electrode are respectively connected to two sides of the second semiconductor layer; The first semiconductor layer, the first source electrode, the first drain electrode, and the common gate electrode form a first thin film transistor; the second semiconductor layer, the second source electrode, the second drain electrode, and the common gate electrode form a second thin film transistor; the second thin film transistor is arranged above the first thin film transistor along the stacking direction of the array substrate; and an orthographic projection of one of the first thin film transistor and the second thin film transistor on the base substrate is located within a coverage range of an orthographic projection of the other thin film transistor on the base substrate; Wherein, one of the first semiconductor layer and the second semiconductor layer is a polycrystalline silicon semiconductor layer, and the other is a metal oxide semiconductor layer; The thin film transistor assembly further includes a buffer layer disposed on the base substrate, a gate insulating layer and a gate protection layer stacked sequentially on the buffer layer, and an oxide insulating layer and a metal oxide protection layer stacked sequentially on the gate protection layer; The gate protection layer and the gate insulating layer are provided with contact holes connected to the first semiconductor layer, the first source electrode and the first drain electrode are provided in the gate protection layer and contact the first semiconductor layer through the contact holes, the gate protection layer includes a first gate protection layer and a second gate protection layer sequentially stacked on the gate insulating layer, and the first source electrode and the first drain electrode are provided between the first gate protection layer and the second gate protection layer; The second semiconductor layer and the second source and the second drain are all disposed on the oxide insulating layer, and the metal oxide protection layer covers the second semiconductor layer and the second source and the second drain; The common gate has a double-layer structure, wherein the bottom layer of the common gate is composed of Mo, Ti, W or Mo alloy, Ti alloy, and the upper layer of the common gate is composed of metal Cu; The coverage area of the second thin film transistor is larger than the coverage area of the first thin film transistor, and the orthographic projection of the first thin film transistor on the base substrate is completely located within the coverage range of the orthographic projection of the second thin film transistor on the base substrate.

2. The low-temperature polycrystalline oxide array substrate according to claim 1, wherein: The common gate is disposed between the first semiconductor layer and the second semiconductor layer along a stacking direction of the array substrate, and the common gate is used to drive the first thin film transistor and the second thin film transistor.

3. The low-temperature polycrystalline oxide array substrate according to claim 2, wherein: The first semiconductor layer is disposed on the buffer layer; wherein the buffer layer includes a first buffer layer and a second buffer layer sequentially stacked on the base substrate.

4. The low-temperature polycrystalline oxide array substrate according to claim 3, wherein: The gate insulating layer covers the first semiconductor layer, the common gate is disposed on the gate insulating layer, and the gate protection layer covers the common gate.

5. A method for manufacturing a low-temperature polycrystalline oxide array substrate, for manufacturing the low-temperature polycrystalline oxide array substrate according to any one of claims 1 to 4, characterized in that: The steps include: A first thin film transistor is formed on the base substrate; wherein the first thin film transistor includes a first semiconductor layer, a first source electrode, a first drain electrode and a common gate electrode, and the first source electrode and the first drain electrode are respectively connected to two sides of the first semiconductor layer; A second thin film transistor is formed on the first thin film transistor, and the second thin film transistor has an overlapping area with the first thin film transistor in a direction perpendicular to the substrate; wherein the second thin film transistor includes a second semiconductor layer, a second source, a second drain and the common gate, the second source and the second drain are respectively connected to both sides of the second semiconductor layer, and one of the first semiconductor layer and the second semiconductor layer is a polycrystalline silicon semiconductor layer, and the other is a metal oxide semiconductor layer.

6. The method for manufacturing a low-temperature polycrystalline oxide array substrate according to claim 5, wherein: The forming of the second thin film transistor on the first thin film transistor specifically includes: A second thin film transistor is formed on the first thin film transistor to completely cover the first thin film transistor.

7. The method for manufacturing a low-temperature polycrystalline oxide array substrate according to claim 5, wherein: The forming of the second thin film transistor on the first thin film transistor specifically includes: forming the common gate above the first semiconductor layer, the first source electrode, and the first drain electrode, wherein the common gate is used to drive the first thin film transistor and the second thin film transistor; The second semiconductor layer, a second source electrode, and a second drain electrode are formed above the common gate.

8. The method for manufacturing a low-temperature polycrystalline oxide array substrate according to claim 7, wherein: The step of forming a first thin film transistor on a substrate specifically includes: forming a buffer layer on the base substrate; wherein the buffer layer comprises a first buffer layer and a second buffer layer sequentially stacked on the base substrate; forming a first semiconductor layer on the buffer layer; forming a gate insulating layer on the buffer layer, wherein the gate insulating layer covers the first semiconductor layer; forming a common gate on the gate insulating layer; forming a gate protection layer on the gate insulating layer, wherein the gate protection layer covers the common gate; A first source electrode and a first drain electrode are formed in the gate protection layer, wherein the first source electrode and the first drain electrode are in contact with the first semiconductor layer.

9. The method for manufacturing a low-temperature polycrystalline oxide array substrate according to claim 8, wherein: The forming of a first source electrode and a first drain electrode in the gate protection layer specifically includes: forming a first gate protection layer on the gate insulating layer, wherein the first gate protection layer covers the common gate; forming a contact hole communicating with the first semiconductor layer in the first gate protection layer and the gate insulating layer; forming a first source electrode and a first drain electrode on the first gate protection layer, wherein the first source electrode and the first drain electrode are in contact with the first semiconductor layer through the contact hole; A second gate protection layer is formed on the first gate protection layer, and the second gate protection layer covers the first source electrode and the first drain electrode.

10. The method for manufacturing a low-temperature polycrystalline oxide array substrate according to claim 9, wherein: The forming of the second thin film transistor on the first thin film transistor specifically includes: forming an oxide insulating layer on the second gate protection layer; forming a second semiconductor layer on the oxide insulating layer; forming a second source electrode and a second drain electrode on the oxide insulating layer, wherein the second source electrode and the second drain electrode are respectively overlapped on two sides of the second semiconductor layer; A metal oxide protection layer is formed on the oxide insulating layer, and the metal oxide protection layer covers the second semiconductor layer and the second source and the second drain.

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