Display device

Abstract

The present disclosure relates to a display device, comprising: a first conductive layer, a first insulating layer disposed on the first conductive layer, and an active pattern disposed on the first insulating layer. The display device further comprises: a second conductive layer disposed on the active pattern and including a first gate electrode and a driving gate electrode overlapping a channel region of the active pattern; a second insulating layer disposed on the second conductive layer; a third conductive layer including a capacitor electrode and at least one scanning line disposed on the second insulating layer; a third insulating layer disposed on the third conductive layer; and an electrode layer including a first electrode disposed on the third insulating layer. The first electrode is connected to the capacitor electrode, the capacitor electrode overlaps the driving gate electrode, and the capacitor electrode and the driving gate electrode form a capacitor.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0032344, filed on Mar. 21, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Exemplary embodiments of the present disclosure relate to a display device. Background Art

[0004] Light-emitting diode displays have self-emitting characteristics and, unlike liquid crystal displays, do not require a separate light source. Accordingly, the thickness and weight of the display can be reduced. In addition, light-emitting diode displays have advanced characteristics such as, for example, low power consumption, high brightness, and high response speed.

[0005] Generally, a light-emitting diode display includes: a substrate; a plurality of thin film transistors disposed on the substrate; a plurality of insulating layers disposed between wirings forming the thin film transistors; and a light-emitting element connected to the thin film transistors. The light-emitting element may be, for example, an organic light-emitting element. Summary of the Invention

[0006] Exemplary embodiments provide a display device in which the resistance of wirings can be reduced and display quality can be improved.

[0007] According to an exemplary embodiment, a display device includes: a substrate; a first conductive layer disposed on the substrate; a first insulating layer disposed on the first conductive layer; and a plurality of active patterns disposed on the first insulating layer. The active patterns include a source region, a channel region, and a drain region. The display device further includes: a second conductive layer disposed on the active patterns and including a first gate electrode and a driving gate electrode overlapping the channel region; a second insulating layer disposed on the second conductive layer; a third conductive layer including a capacitor electrode and at least one scanning line disposed on the second insulating layer; a third insulating layer disposed on the third conductive layer; and an electrode layer including a first electrode disposed on the third insulating layer. The first electrode is connected to the capacitor electrode, the capacitor electrode overlaps the driving gate electrode, and the capacitor electrode and the driving gate electrode form a capacitor.

[0008] In an exemplary embodiment, the capacitor electrode is electrically connected to the first conductive layer.

[0009] In an exemplary embodiment, the second conductive layer further includes an overlapping gate pattern overlapping the at least one scanning line.

[0010] In an exemplary embodiment, the third insulating layer includes an organic material.

[0011] In an exemplary embodiment, the display device further includes a fourth conductive layer disposed between the third insulating layer and the electrode layer. The fourth conductive layer includes data lines, driving voltage lines, common voltage lines, initialization voltage lines, and a plurality of connection patterns.

[0012] In an exemplary embodiment, the at least one scanning line includes a first scanning line and a second scanning line, the second conductive layer further includes a second gate electrode, and the first scanning line and the second gate electrode are connected to each other through one of the plurality of connection patterns.

[0013] In an exemplary embodiment, the first electrode and the capacitor electrode are connected to each other through one of the plurality of connection patterns.

[0014] In an exemplary embodiment, the third conductive layer further includes a plurality of connection electrodes, the plurality of active patterns include a first active pattern, a second active pattern, and a third active pattern, and each active pattern is connected to at least one of the plurality of connection electrodes of the third conductive layer.

[0015] In an exemplary embodiment, the resistance of the third conductive layer is lower than the resistance of the second conductive layer.

[0016] According to an exemplary embodiment, a display device includes: a substrate; a first conductive layer disposed on the substrate; a first insulating layer disposed on the first conductive layer; and a plurality of active patterns disposed on the first insulating layer and including a source region, a channel region, and a drain region. The display device further includes: a second conductive layer disposed on the active patterns and including a plurality of data overlap lines; a second insulating layer disposed on the second conductive layer; a third conductive layer disposed on the second insulating layer and including a plurality of data lines, a common voltage line, and at least one scanning line; a third insulating layer disposed on the third conductive layer; and an electrode layer including a first electrode disposed on the third insulating layer. The plurality of data lines overlap the plurality of data overlap lines respectively, and the at least one scanning line overlaps the first conductive layer.

[0017] In an exemplary embodiment, the second conductive layer further includes a common voltage overlap line, the common voltage line overlaps the common voltage overlap line and the first conductive layer, and the common voltage line is electrically connected to the common voltage overlap line and the first conductive layer.

[0018] In an exemplary embodiment, the third conductive layer further includes a driving voltage line and an initialization voltage line, the second conductive layer includes a plurality of gate patterns, and the plurality of gate patterns, the driving voltage line, and the initialization voltage line overlap with each other, respectively.

[0019] In an exemplary embodiment, the first conductive layer includes a plurality of lower patterns, and one of the plurality of lower patterns is disposed in a direction intersecting the common voltage line and connected to the common voltage line.

[0020] In an exemplary embodiment, the plurality of active patterns include a first active pattern, a second active pattern, and a third active pattern, the at least one scanning line includes a first scanning line and a second scanning line, an extending portion of the first scanning line extends in a direction different from a remaining portion of the first scanning line, and the extending portion of the first scanning line overlaps with channel regions of the first active pattern and the third active pattern.

[0021] In an exemplary embodiment, an extending portion of the second scanning line extends in a direction different from a remaining portion of the second scanning line, and the extending portion of the second scanning line overlaps with the channel region of the second active pattern.

[0022] In an exemplary embodiment, the display device further includes a pad electrode disposed on the same layer as the third conductive layer, and a pad connection electrode disposed on the same layer as the second conductive layer. The pad electrode is electrically connected to the first conductive layer, and the pad electrode is electrically connected to the pad connection electrode.

[0023] In an exemplary embodiment, the second conductive layer further includes a driving gate electrode, and the third conductive layer further includes a capacitor overlapping with the driving gate electrode.

[0024] In an exemplary embodiment, the first conductive layer includes a plurality of lower patterns, and at least one of the plurality of lower patterns overlaps with the capacitor electrode.

[0025] In an exemplary embodiment, the display device further includes a first electrode connected to the capacitor electrode.

[0026] According to an exemplary embodiment, a display device includes a substrate, a first conductive layer disposed on the substrate, and a transistor disposed on the first conductive layer and including a gate electrode and an overlapping gate electrode. The gate electrode is formed in a second conductive layer disposed on the first conductive layer, and the overlapping gate electrode is formed in a third conductive layer disposed on the second conductive layer. The display device further includes: a capacitor including a driving gate electrode and a capacitor electrode; and a scanning line formed in the third conductive layer. The capacitor electrode overlaps with the driving gate electrode, the capacitor electrode is formed in the third conductive layer, and the driving gate electrode is formed in the second conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0028] Figure 1 is a schematic cross-sectional view of a display device according to an exemplary embodiment of the present disclosure.

[0029] Figure 2 is a schematic cross-sectional view of a display device according to an exemplary embodiment of the present disclosure.

[0030] Figure 3 is a circuit diagram of a pixel of a display device according to an exemplary embodiment of the present disclosure.

[0031] Figure 4 is a planar layout diagram of a plurality of pixels of a display device according to an exemplary embodiment of the present disclosure.

[0032] Figure 5 is taken along line Va-Vb according to an exemplary embodiment of the present disclosure Figure 4 of a cross-sectional view of the display device.

[0033] Figure 6 is taken along line VIa-VIb according to an exemplary embodiment of the present disclosure Figure 4 of a cross-sectional view of the display device.

[0034] Figure 7 is taken along line VIa-VIb according to an exemplary embodiment of the present disclosure Figure 4 of a cross-sectional view of the display device.

[0035] Figure 8 is taken along line VIIa-VIIb according to an exemplary embodiment of the present disclosure Figure 4 of a cross-sectional view of the display device.

[0036] Figure 9 is taken along line IXa-IXb according to an exemplary embodiment of the present disclosureFigure 4 Cross-sectional view of a display device.

[0037] Figure 10 It is a layout diagram of a display device according to an exemplary embodiment of the present disclosure.

[0038] Figure 11 It is taken along the line Xa-Xa' according to an exemplary embodiment of the present disclosure Figure 10 Cross-sectional view of a display device. Detailed implementation manners

[0039] Hereinafter, exemplary embodiments of the present disclosure will be described more fully with reference to the accompanying drawings. Throughout the drawings, the same reference numerals may refer to the same elements.

[0040] It will be understood that the terms "first", "second", "third", etc. are used herein to distinguish one element from another, and these elements are not limited by these terms. Thus, the "first" element in an exemplary embodiment may be described as the "second" element in another exemplary embodiment.

[0041] It should be understood that unless the context clearly indicates otherwise, the description of the features or aspects in each exemplary embodiment is generally considered applicable to other similar features or aspects in other exemplary embodiments.

[0042] As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly indicates otherwise.

[0043] For ease of description, spatial relative terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature to another (or others) as shown in the figures. It will be understood that, in addition to the orientation depicted in the drawings, the spatial relative terms are also intended to cover different orientations of the device during use or operation. For example, if the device in the drawings is flipped, the element described as "under" or "below" or "beneath" other elements or features will then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "below" may include both orientations of "above" and "below".

[0044] It will be understood that when a component such as a film, region, layer, or element is referred to as being "on", "connected to", "coupled to", or "adjacent to" another component, it can be directly on the other component, connected to, coupled to, or adjacent to the other component, or there can also be an intermediate component. It should also be understood that when a component is referred to as being "between" two components, it can be the only component between the two components, or there can also be one or more intermediate components. It should also be understood that when a component is referred to as "covering" another component, it can be the only component covering the other component, or one or more intermediate components can also cover the other component. Other words used to describe the relationship between elements should be interpreted in a similar manner.

[0045] Hereinafter, a display device according to an exemplary embodiment of the present disclosure will be described with reference to the accompanying drawings.

[0046] Figure 1 and Figure 2 A cross-section of a display device according to an exemplary embodiment of the present disclosure is schematically shown.

[0047] Reference Figure 1 , a display device according to an exemplary embodiment of the present disclosure includes a lower pattern 111 formed on a substrate 110. A buffer layer 120, which is an insulating layer, is provided on the lower pattern 111. The buffer layer 120 may also be referred to as an insulating layer herein.

[0048] An active layer including a source region SA, a channel region CA, and a drain region DA is provided on the buffer layer 120. The active layer may correspond to an active pattern, the source region SA may correspond to a source area, the channel region CA may correspond to a channel area, and the drain region DA may correspond to a drain area. An insulating pattern 144 is formed on the active layer. The insulating pattern 144 may also be referred to as a first insulating layer herein. The insulating pattern 144 may overlap with the channel region CA.

[0049] A second conductive layer may be provided on the insulating pattern 144. The second conductive layer may include a first gate electrode G1 and a first capacitor electrode C1. The first capacitor electrode C1 may also be referred to as a driving gate electrode C1 herein. The first gate electrode G1 may overlap with the channel region CA. The first gate electrode G1 may be aligned with the channel region CA. For example, an end of the first gate electrode G1 may be aligned with an end of the channel region CA.

[0050] A second insulating layer 145 may be provided on the second conductive layer. A third conductive layer may be provided on the second insulating layer 145. The third conductive layer includes a first overlapping gate electrode G2 overlapping with the first gate electrode G1, a second capacitor electrode C2 overlapping with the driving gate electrode C1, and a scan line SC.

[0051] The first gate electrode G1, the first overlapping gate electrode G2, the source region SA, the channel region CA, and the drain region DA form a transistor T1.

[0052] Since the second capacitor electrode C2, which is part of the third conductive layer, overlaps with the driving gate electrode C1, which is part of the second conductive layer, the second capacitor electrode C2 and the driving gate electrode C1 can together form a capacitor. According to an exemplary embodiment, using electrodes belonging to the second conductive layer and the third conductive layer respectively to form a capacitor, forming the scan line SC as part of the third conductive layer, and forming the gate electrode of the transistor T1 to include a multi-gate electrode structure (e.g., gate electrodes G1 and G2) spanning the second conductive layer and the third conductive layer reduces the resistance and load of the display device.

[0053] In addition, the third conductive layer may include a source connection pattern GS that contacts the source region SA and a drain connection pattern GD that contacts the drain region DA. The drain connection pattern GD can be electrically connected to the lower pattern 111 through contact holes provided in the buffer layer 120 and the second insulating layer 145. The first electrode 191 can be electrically connected to the second capacitor electrode C2 via one of the source connection patterns GS, and the second capacitor electrode C2 can be electrically connected to the lower pattern 111.

[0054] The third insulating layer 160 can be provided on the third conductive layer. The fourth conductive layer can be provided on the third insulating layer 160. The fourth conductive layer can include a source electrode SE and a drain electrode DE.

[0055] The fourth insulating layer 180 can be provided on the fourth conductive layer. The first electrode 191 is provided on the fourth insulating layer 180. The fourth insulating layer 180 includes contact holes, and the first electrode 191 can be connected to the drain electrode DE through the contact holes.

[0056] The partition wall 350 can be provided on the first electrode 191. The partition wall 350 can include an opening overlapping with the first electrode 191.

[0057] The second electrode 270 can be provided on the partition wall 350. The second electrode 270 can overlap with the first electrode 191. The light-emitting element layer 370 can be provided in the opening in the partition wall 350 between the first electrode 191 and the second electrode 270.

[0058] Reference Figure 1 According to an exemplary embodiment, the display device includes a second conductive layer and a third conductive layer. The second conductive layer includes the first gate electrode G1 and the first capacitor electrode C1. The third conductive layer includes: the first overlapping gate electrode G2, which is electrically connected to and overlaps with the first gate electrode G1; and the second capacitor electrode C2, which overlaps with the driving gate electrode C1.

[0059] As a result of this configuration, since the gate electrode of the transistor T1 includes the first gate electrode G1 and the first overlapping gate electrode G2, it can have a reduced resistance. In addition, a capacitor of the display device is provided between the driving gate electrode C1 and the second capacitor electrode C2.

[0060] A scan line SC of the display device is formed of a third conductive layer. Accordingly, the scan line SC is provided on the same layer as the first overlapping gate electrode G2 and the second capacitor electrode C2.

[0061] In an exemplary embodiment, the second conductive layer may be a double layer of molybdenum and titanium, and the third conductive layer may be a triple layer of titanium / aluminum / titanium. The thickness of molybdenum in the second conductive layer may be, for example, between about and about and the thickness of titanium may be, for example, between about and about In addition, in the third conductive layer, the thickness of titanium may be, for example, between about and about and the thickness of aluminum may be, for example, between about and about Therebetween.

[0062] In this case, the third conductive layer has a lower resistance than the second conductive layer. Accordingly, due to this lower resistance, the scan line SC can be formed together with the third conductive layer.

[0063] In Figure 1 , the scan line SC is formed of a single layer of the third conductive layer. However, the exemplary embodiment is not limited thereto. For example, in the exemplary embodiment, the scan line SC may be formed of the second conductive layer and the third conductive layer that are electrically connected to each other and overlap each other. In this case, the resistance of the scan line SC can be further reduced. For example, according to the exemplary embodiment, the scan line SC may be formed only in the third conductive layer, or may be formed in the third conductive layer and the second conductive layer.

[0064] Referring to Figure 2 , a display device according to an exemplary embodiment is similar to an exemplary embodiment of Figure 1 except that Figure 2 the display device of

[0065] In Figure 2 the exemplary embodiment of

[0066] The buffer layer 120 is disposed on the lower pattern 111. An active layer including a source region SA, a channel region CA, and a drain region DA is disposed on the buffer layer 120. The source region SA and the drain region DA of the active layer may be, for example, n+-doped. The insulating pattern 144 overlaps with the channel region CA.

[0067] The first gate electrode G1, the first capacitor electrode C1, and the pad lower electrode (pad connection electrode) P1 are disposed on the active layer.

[0068] The third insulating layer 160 is disposed on the first gate electrode G1, the first capacitor electrode C1, and the pad lower electrode P1.

[0069] The source electrode SE, the drain electrode DE, the second capacitor electrode C2, and the pad electrode PE are disposed on the third insulating layer 160.

[0070] The source electrode SE is connected to the first lower pattern 111a through a contact hole formed in the third insulating layer 160 and the buffer layer 120. In addition, the source electrode SE is connected to the source region SA of the active layer through a contact hole formed in the third insulating layer 160, and the drain electrode DE is connected to the drain region DA of the active layer through a contact hole formed in the third insulating layer 160.

[0071] The first capacitor electrode C1 and the second capacitor electrode C2 form a capacitor, and the third insulating layer 160 is disposed between the first capacitor electrode C1 and the second capacitor electrode C2.

[0072] The pad electrode PE is connected to the pad lower electrode P1 through a contact hole formed in the third insulating layer 160. In addition, the pad electrode PE is connected to the second lower pattern 111b through a contact hole formed in the third insulating layer 160 and the buffer layer 120.

[0073] The fourth insulating layer 180a is disposed on the source electrode SE, the drain electrode DE, the second capacitor electrode C2, and the pad electrode PE. The fourth insulating layer 180a includes an opening overlapping with the pad electrode PE. The protection electrode TE may be disposed in the opening. The protection electrode TE may include, for example, a transparent conductive oxide.

[0074] The fifth insulating layer 180b is disposed on the fourth insulating layer 180a. The fifth insulating layer 180b may include an opening overlapping with the protection electrode TE.

[0075] The first electrode 191 is disposed on the fifth insulating layer 180b. The first electrode 191 is connected to the source electrode SE through contact holes formed in the fourth insulating layer 180a and the fifth insulating layer 180b.

[0076] The partition wall 350 is provided on the first electrode 191. The second electrode 270 may overlap with the first electrode 191. The light-emitting element layer 370 may be provided in the opening between the first electrode 191 and the second electrode 270 in the partition wall 350.

[0077] Reference Figure 2 , in the pad portion PA of the pad region, a second lower pattern 111b, a pad lower electrode P1, and a pad electrode PE are provided. The second lower pattern 111b, the pad lower electrode P1, and the pad electrode PE overlap each other and are electrically connected to each other. Accordingly, the resistance of the pad portion can be reduced.

[0078] Figure 3 is a circuit diagram of a pixel of a display device according to an exemplary embodiment of the present disclosure.

[0079] Reference Figure 3 , a display device according to an exemplary embodiment includes a plurality of pixels. Each pixel may include a plurality of transistors T1, T2, and T3, a capacitor Cst, and at least one light-emitting diode (also referred to as a light-emitting element) ED. Here, an example in which each pixel includes one light-emitting diode ED will be described.

[0080] The plurality of transistors T1, T2, and T3 include a first transistor T1, a second transistor T2, and a third transistor T3. Source electrodes and drain electrodes to be described below are provided to distinguish between two electrodes provided on opposite sides of the channel of each of the transistors T1, T2, and T3, and these two terms may be interchanged.

[0081] The gate electrode G1 of the first transistor T1 is connected to the first end of the capacitor Cst. The source electrode S1 of the first transistor T1 is connected to a driving voltage line that transmits the driving voltage ELVDD. The drain electrode D1 of the first transistor T1 is connected to the anode of the light-emitting diode ED and the second end of the capacitor Cst. The first transistor T1 receives a data voltage DAT according to the switching operation of the second transistor T2 and supplies a driving current to the light-emitting diode ED according to the voltage stored in the capacitor Cst.

[0082] The gate electrode G2 of the second transistor T2 is connected to the first scan line that transmits the first scan signal SC SIG . The source electrode S2 of the second transistor T2 is connected to a data line that can transmit a reference voltage or a data voltage DAT. The drain electrode D2 of the second transistor T2 is connected to the first end of the capacitor Cst and the gate electrode G1 of the first transistor T1. The second transistor T2 is turned on according to the first scan signal SC SIG and transmits the reference voltage or the data voltage DAT to the gate electrode G1 of the first transistor T1 connected to the first end of the capacitor Cst.

[0083] The gate electrode G3 of the third transistor T3 is connected to the second scan line that transmits the second scan signal SS SIG The source electrode S3 of the third transistor T3 is connected to the second end of the capacitor Cst, the drain electrode D1 of the first transistor T1, and the anode of the light-emitting diode ED. And the drain electrode D3 of the third transistor T3 is connected to the initialization voltage line that transmits the initialization voltage INIT. The third transistor T3 is turned on by the second scan signal SS SIG to transmit the initialization voltage INIT to the anode of the light-emitting diode ED and the second end of the capacitor Cst, so that the voltage of the anode of the light-emitting diode ED can be initialized.

[0084] The first end of the capacitor Cst is connected to the gate electrode G1 of the first transistor T1, and the second end of the capacitor Cst is connected to the source electrode S3 of the third transistor T3 and the anode of the light-emitting diode ED. The cathode of the light-emitting diode ED is connected to the common voltage line that transmits the common voltage ELVSS.

[0085] The light-emitting diode ED can emit light according to the driving current formed by the first transistor T1.

[0086] Now, an operation example of the circuit shown will be described, for example, when the circuit operates during one frame Figure 3 Here, the transistors T1, T2, and T3 are exemplarily described as N-channel transistors. However, the transistors T1, T2, and T3 are not limited thereto.

[0087] When a frame starts, a high-level first scan signal SC SIG and a high-level second scan signal SS SIG are supplied. Thus, the second transistor T2 and the third transistor T3 are turned on during the initialization period. The reference voltage from the data line is supplied to the gate electrode G1 of the first transistor T1 and the first end of the capacitor Cst through the turned-on second transistor T2, and the initialization voltage INIT is supplied to the drain electrode D1 of the first transistor T1 and the anode of the light-emitting diode ED through the turned-on third transistor T3. Therefore, during the initialization period, the drain electrode D1 of the first transistor T1 and the anode of the light-emitting diode ED are initialized by the initialization voltage INIT. In this case, the voltage difference between the reference voltage and the initialization voltage INIT is stored in the capacitor Cst.

[0088] Next, when the first scan signal SC SIG maintains a high level during the sensing period SIGWhen it becomes low level, the second transistor T2 remains conducting and the third transistor T3 is cut off. The gate electrode G1 of the first transistor T1 and the first end of the capacitor Cst maintain a reference voltage through the conducting second transistor T2, and the drain electrode D1 of the first transistor T1 and the anode of the light-emitting diode ED are disconnected from the initialization voltage INIT through the cut-off third transistor T3. Therefore, when the voltage of the drain electrode D1 becomes "reference voltage - Vth" and current flows from the source electrode S1 to the drain electrode D1, the first transistor T1 is cut off. Here, Vth represents the threshold voltage of the first transistor T1. In this case, the voltage difference between the gate electrode G1 and the drain electrode D1 of the first transistor T1 is stored in the capacitor Cst, and the sensing of the threshold voltage Vth of the first transistor T1 is completed. Since data signals compensated by reflecting the sensed characteristic information are generated during each sensing period, the characteristic deviation of the transistor T1 can be compensated from the outside, and the characteristic deviation may be different for each pixel.

[0089] Next, when a high-level first scan signal SC is supplied during the data input period SIG and a low-level second scan signal SS SIG are supplied, the second transistor T2 is turned on and the third transistor T3 is turned off. The data voltage DAT from the data line is supplied to the gate electrode G1 of the first transistor T1 and the first end of the capacitor Cst through the turned-on second transistor T2. In this case, due to the first transistor T1 being in the cut-off state, the drain electrode D1 of the first transistor T1 and the anode of the light-emitting diode ED can maintain their electric potentials during the sensing period.

[0090] Next, the first transistor T1 is turned on by the data voltage DAT transmitted to the gate electrode G1, a driving current is generated according to the data voltage DAT during the light-emitting period, and the light-emitting diode ED emits light due to the driving current.

[0091] Next, the display device according to an exemplary embodiment of the present disclosure will be described in more detail with reference to the detailed layout plan and cross-sectional view.

[0092] Figure 4 is a layout plan of a plurality of pixels PX1, PX2, and PX3 of the display device 1000a according to an exemplary embodiment of the present disclosure. Figure 5 is taken along the line Va - Vb according to an exemplary embodiment of the present disclosure Figure 4 of the cross-sectional view of the display device 1000a. Figure 6 is taken along the line VIa - VIb according to an exemplary embodiment of the present disclosure Figure 4 of the cross-sectional view of the display device 1000a. Figure 7 is taken along the line VIa - VIb according to an exemplary embodiment of the present disclosureFigure 4 Cross-sectional view of the display device 1000a. Figure 8 It is taken along line VIIa-VIIb according to an exemplary embodiment of the present disclosure Figure 4 Cross-sectional view of the display device 1000a. Figure 9 It is taken along line IXa-IXb according to an exemplary embodiment of the present disclosure Figure 4 Cross-sectional view of the display device 1000a. For ease of explanation, further description of the previously described elements and technical aspects may be omitted herein.

[0093] The display device 1000a according to an exemplary embodiment may include a substrate 110. The substrate 110 may include an insulating material, for example, glass, plastic, etc. The substrate 110 may be a flexible substrate, for example.

[0094] A barrier layer as an insulating layer may be disposed on the substrate 110, and a lower pattern 111 is disposed on the barrier layer as a first conductive layer. That is, the lower pattern 111 may also be referred to as the first conductive layer herein. The lower pattern 111 has conductivity and may include various conductive metals or semiconductor materials having conductive characteristics similar to those of conductive metals.

[0095] A buffer layer 120 as an insulating layer is disposed on the lower pattern 111. That is, the lower pattern 111 may be disposed between the substrate 110 and the buffer layer 120.

[0096] An active layer including a plurality of active patterns 130a, 130b, and 130c is disposed on the buffer layer 120. That is, the lower pattern 111 may be disposed between the substrate 110 and the active layer. The active patterns 130a, 130b, and 130c disposed on the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include channel regions 134a, 134b, and 134c that form channels of the above-described plurality of transistors T1, T2, and T3, and conductive regions connected to the channel regions 134a, 134b, and 134c. The conductive regions of the active patterns 130a, 130b, and 130c may include source regions 133a, 133b, and 133c and drain regions 135a, 135b, and 135c of the corresponding transistors T1, T2, and T3. In each of the pixels PX1, PX2, and PX3, the first active pattern 130a and the third active pattern 130c may be connected to each other.

[0097] The active layer may include a semiconductor material such as amorphous silicon, polycrystalline silicon, or an oxide semiconductor, for example.

[0098] An insulating pattern 144 serving as a first insulating layer is disposed on the active layer. For example, the insulating pattern 144 may be disposed on the channel regions 134a, 134b, and 134c while overlapping the channel regions 134a, 134b, and 134c of the active patterns 130a, 130b, and 130c. In an exemplary embodiment, the insulating pattern 144 does not overlap the conductive regions of the active patterns 130a, 130b, and 130c.

[0099] A second conductive layer may be disposed on the insulating pattern 144. The second conductive layer may include, for example, a driving gate electrode 155, and the driving gate electrode 155 includes a first gate electrode 154a, a second gate electrode 154b, a third gate electrode 154c, and a gate pattern 154d.

[0100] The second conductive layer may be a bilayer of, for example, molybdenum and titanium. For example, in the second conductive layer, the thickness of molybdenum may be between about and about and the thickness of titanium may be between about and about between.

[0101] The driving gate electrode 155 may include: an extending portion 155a that protrudes upward and extends substantially in a second direction DR2; and a first gate electrode 154a that protrudes downward and extends substantially in the second direction DR2. Compared with other driving gate electrodes 155 disposed in other pixels PX1 and PX2, the driving gate electrode 155 may occupy a smaller area in the third pixel PX3. For example, in an exemplary embodiment, the driving gate electrode 155 disposed in the third pixel PX3 is smaller than the driving gate electrodes 155 disposed in the first pixel PX1 and the second pixel PX2.

[0102] The first gate electrode 154a overlaps the channel region 134a of the first active pattern 130a while crossing the first active pattern 130a. The second gate electrode 154b overlaps the channel region 134b of the second active pattern 130b while crossing the second active pattern 130b. The third gate electrode 154c overlaps the channel region 134c of the third active pattern 130c while crossing the third active pattern 130c. The gate pattern 154d may be electrically connected to the horizontal initialization voltage line 153 through a contact hole 71.

[0103] A second insulating layer 145 is disposed on the second conductive layer.

[0104] Next, a third conductive layer is disposed on the second insulating layer 145. The third conductive layer includes a first scan line 151 for transmitting the first scan signal SC SIG and a second scan line for transmitting the second scan signal SS SIGThe second scan line 152, the horizontal initialization voltage line 153 for transmitting the initialization voltage INIT, the horizontal driving voltage line 172 for transmitting the driving voltage ELVDD, the capacitor electrode 157, and the plurality of connection electrodes 163a, 163b, 163c, 163d, 163e, and 163f.

[0105] The first scan line 151 and the second scan line 152, the horizontal initialization voltage line 153 and the horizontal driving voltage line 172 may extend in the first direction DR1, respectively. The capacitor electrode 157 may be disposed between the first scan line 151 and the second scan line 152.

[0106] The second gate electrode 154b is connected to the connection electrode 163f through the contact hole 53. The second gate electrode 154b is connected to the first scan line 151 through the connection electrode 163f. The third gate electrode 154c is connected to the connection electrode 163e through the contact hole 45 and is connected to the second scan line 152 through the connection electrode 163e. The second gate electrode 154b and the third gate electrode 154c may be island-shaped electrodes.

[0107] The capacitor electrode 157 provided in each of the pixels PX1, PX2, and PX3 may include: a first extension portion 157a that protrudes upward and thus extends substantially in the second direction DR2; and a second extension portion 157b that protrudes downward and thus extends substantially in the second direction DR2.

[0108] The second extension portion 157b of the capacitor electrode 157 is connected to the lower pattern 111 through the contact hole 54. In addition, the end of the second extension portion 157b is connected to the active patterns 130a and 130c through at least one contact hole 55.

[0109] The first connection electrode 163a is connected to the driving voltage line 172a through at least one contact hole 41. The second connection electrode 163b is connected to the connection pattern 174d through at least one contact hole 42. The third connection electrode 163c is connected to the driving gate electrode 155 through the contact hole 43. The fourth connection electrode 163d is connected to the data line 171a through the contact hole 44. The fifth connection electrode 163e is connected to the third gate electrode 154c through the contact hole 45, and another part of the fifth connection electrode 163e is connected to the connection pattern 174c through the contact hole 63.

[0110] The third connection electrode 163c is connected to the second active pattern 130b through at least one contact hole 68. The second connection electrode 163b is connected to the active pattern 130c through at least one contact hole 70.

[0111] The third conductive layer may be a three-layer including, for example, titanium / aluminum / titanium. In the third conductive layer, the thickness of the titanium may be about Peace and the thickness of the aluminum can be between Peace between.

[0112] The third insulating layer 160 may be disposed on the third conductive layer.

[0113] The third insulating layer 160 may be, for example, an inorganic layer or an organic layer. When the third insulating layer 160 is an organic layer, the step difference caused by the second conductive layer and the third conductive layer may be compensated and flattened. Therefore, the parasitic capacitance between the third conductive layer and the fourth conductive layer (described later) may be reduced.

[0114] The fourth conductive layer may be disposed on the third insulating layer 160. The fourth conductive layer includes a plurality of data lines 171a, 171b, and 171c, a plurality of driving voltage lines 172a, 172b, and 172c, a common voltage line 170, an initialization voltage line 173, and a plurality of connection patterns 174a, 174b, 174c, and 174d.

[0115] The data lines 171 a , 171 b and 171 c , the driving voltage lines 172 a , 172 b and 172 c , the common voltage line 170 and the initialization voltage line 173 respectively extend substantially in the second direction DR2 and thus may cross the first scan line 151 and / or the second scan line 152 .

[0116] Figure 4 A group of repeated pixels PX1, PX2 and PX3 shown in the figure may be arranged along the first direction DR1 and adjacent to each other. The common voltage line 170 may be provided on the left and right sides of the group of pixels PX1, PX2 and PX3. For example, one common voltage line 170 may be provided for each of the repeated plurality of pixels PX1, PX2 and PX3. When the repeated group of the plurality of pixels PX1, PX2 and PX3 includes three pixels PX1, PX2 and PX3, three data lines 171a, 171b and 171c, three driving voltage lines 172a, 172b and 172c and at least one initialization voltage line 173 may be provided between two adjacent common voltage lines 170.

[0117] Each of the data lines 171 a , 171 b , and 171 c is electrically connected to the source region 133 b of the second active pattern 130 b through at least one contact hole 64 of the second insulating layer 145 and the third insulating layer 160 .

[0118] exist Figure 4Among them, each of the driving voltage lines 172a, 172b, and 172c is disposed in each of the pixels PX1, PX2, and PX3. However, the driving voltage line 172a can be disposed in one pixel, for example, in the pixel PX1, and the driving voltage pattern electrically connected to the driving voltage line can be disposed in the other pixels PX2 and PX3.

[0119] Each of the driving voltage lines 172a, 172b, and 172c is electrically connected to the source region 133a of the first active pattern 130a through at least one contact hole 61 ( Figure 4 two contact holes 61 are shown therein) of the second insulating layer 145 and the third insulating layer 160. In addition, each of the driving voltage lines 172a, 172b, and 172c is electrically connected to the horizontal driving voltage line 172 through at least one contact hole 60 of the second insulating layer 145 and the third insulating layer 160.

[0120] Therefore, the horizontal driving voltage line 172 can transmit the driving voltage ELVDD together with the driving voltage lines 172a, 172b, and 172c, and in the entire display device 1000a, the driving voltage ELVDD can be transmitted in a mesh configuration along both the first direction DR1 and the second direction DR2.

[0121] The initialization voltage line 173 is electrically connected to the horizontal initialization voltage line 153 through the contact hole 69 of the second insulating layer 145 and the third insulating layer 160. Therefore, the horizontal initialization voltage line 153 can transmit the initialization voltage INIT together with the initialization voltage line 173. Therefore, even if the initialization voltage line 173 is formed in each of the three pixels PX1, PX2, and PX3, the initialization voltage INIT can be transmitted to all three pixels PX1, PX2, and PX3 through the horizontal initialization voltage line 153.

[0122] The first connection pattern 174a is connected to the capacitor electrode 157 through the contact hole 62 passing through the second insulating layer 145 and the third insulating layer 160. The first connection pattern 174a is connected to the first electrode 191 through the contact hole 80.

[0123] The second connection pattern 174b connects the first scan line 151 and the sixth connection electrode 163f to each other through the contact holes 51 and 52. The sixth connection electrode 163f is connected to the second gate electrode 154b through the contact hole 53.

[0124] The third connection pattern 174c is connected to the fifth connection electrode 163e through the contact hole 63, and is connected to the second scan line 152 through the contact hole 65.

[0125] The fourth connection pattern 174d is connected to the second connection electrode 163b through the contact hole 66 and is electrically connected to the horizontal initialization voltage line 153 through the contact hole 67.

[0126] The horizontal initialization voltage line 153 extends above three adjacent pixels PX1, PX2, and PX3 in the first direction DR1 and can be disposed between two adjacent common voltage lines 170 without crossing the two adjacent common voltage lines 170. The horizontal initialization voltage line 153 can extend only up to the initialization voltage line 173 while crossing three adjacent data lines 171a, 171b, and 171c.

[0127] The first electrode 191 of the pixel electrode layer can be electrically connected to the first connection pattern 174a through the contact hole 80.

[0128] Each first electrode 191 is electrically connected to the drain region 135a of the first transistor T1 via the capacitor electrode 157 and the first connection pattern 174a, such that the first electrode 191 can receive a voltage from the first transistor T1.

[0129] Reference Figure 5 , a capacitor Cst of the display device 1000a is formed between the driving gate electrode 155 and the capacitor electrode 157. A partition wall 350 is disposed on the first electrode 191. The second electrode 270 is disposed overlapping the first electrode 191 at the same time, and the light-emitting element layer 370 can be disposed in an opening of the partition wall 350 between the first electrode 191 and the second electrode 270. The first electrode 191, the light-emitting element layer 370, and the second electrode 270 form a light-emitting element ED.

[0130] In addition, reference Figure 4 and Figure 6 , scan lines such as the horizontal driving voltage line 172 are disposed on the second insulating layer 145. That is, in Figure 4 , different patterns are used to show the second conductive layer and the third conductive layer, and as shown in Figure 4 , the third conductive layer includes a first scan line 151 for transmitting the first scan signal SC SIG , a second scan line 152 for transmitting the second scan signal SS SIG , a horizontal initialization voltage line 153 for transmitting the initialization voltage INIT, a horizontal driving voltage line 172 for transmitting the driving voltage ELVDD, a capacitor electrode 157, and a plurality of connection electrodes 163a, 163b, 163c, 163d, 163e, and 163f.

[0131] In accordance with Figures 4 to 7In an exemplary embodiment, the third conductive layer may have a lower resistance than the second conductive layer. Accordingly, the load of the display device may be reduced by forming wirings such as scan lines having the third conductive layer with a lower resistance.

[0132] Although shown in Figure 4 that the lower pattern 111 is disposed only around the first transistor T1, the exemplary embodiment is not limited thereto. For example, according to the exemplary embodiment, the lower pattern 111 may overlap with the common voltage line 170, or the first scan line 151 and the second scan line 152, or other elements that are not shown due to being overlapped in Figure 4 .

[0133] Figure 6 shows a configuration in which a scan line such as the horizontal driving voltage line 172 is formed of a single layer of the third conductive layer. However, the exemplary embodiment is not limited thereto. For example, according to the exemplary embodiment, the scan line may have a stacked structure of the second conductive layer and the third conductive layer (e.g., stacked along the third direction DR3).

[0134] Referring to Figure 7 , the second conductive layer may further include an overlapping gate pattern 154e, and the overlapping gate pattern 154e and the horizontal driving voltage line 172 may overlap each other. The overlapping gate pattern 154e and the horizontal driving voltage line 172 may be electrically connected to each other. In this case, the resistance of the horizontal driving voltage line 172 may be further reduced.

[0135] has been described with reference to the horizontal driving voltage line 172 Figure 7 . According to the exemplary embodiment, the first scan line 151, the second scan line 152, and the horizontal initialization voltage line 153 may also have a structure in which the second conductive layer and the third conductive layer are stacked.

[0136] Referring to Figure 8 , the voltage of the second scan line 152 is transmitted to the third connection pattern 174c through the contact hole 65, to the fifth connection electrode 163e through the contact hole 63, and then to the third gate electrode 154c through the contact hole 45.

[0137] Referring to Figure 9 , the first connection electrode 163a, the second extension portion 157b of the capacitor electrode 157, and the second connection electrode 163b are respectively connected to the active layer 130 through the contact holes 61, 55, and 70.

[0138] Hereinafter, a display device according to an exemplary embodiment of the present disclosure will be described with reference to Figure 10 .

[0139] Figure 10It is a layout diagram of the display device 1000b according to an exemplary embodiment of the present disclosure. Figure 11 It is taken along the line Xa-Xa' according to an exemplary embodiment of the present disclosure Figure 10 of the cross-sectional view of the display device 1000b.

[0140] Regarding the connection relationship between the constituent elements and the layered structure, according to Figure 10 the exemplary embodiment of the display device 1000b is substantially the same as that of the display device 1000a according to Figure 4 the exemplary embodiment. However, the detailed shapes and connection methods of each constituent element may be different. For the sake of convenience of explanation, the further description of the previously described elements and technical aspects may be omitted herein, and the description may mainly focus on Figure 4 and Figure 10 the differences therebetween.

[0141] Multiple repeating groups of pixels PX4, PX5, and PX6 may be arranged adjacent to each other in the second direction DR2.

[0142] An array of pixels PX4, PX5, and PX6 may be disposed between two adjacent common voltage lines 170, and multiple data lines 171a, 171b, and 171c may be disposed between the array of pixels PX4, PX5, and PX6 and one common voltage line 170. In addition, the driving voltage line 172 and the initialization voltage line 173 may be disposed between the array of pixels PX4, PX5, and PX6 and the other common voltage line 170. That is, multiple data lines 171a, 171b, and 171c may be disposed on one side, the driving voltage line 172 and the initialization voltage line 173 may be disposed on the other side, and the array of pixels PX4, PX5, and PX6 may be disposed therebetween. The capacitor electrodes 175 and the connection members 177 may be disposed on the same layer as the data lines 171a, 171b, and 171c, the driving voltage line 172, and the initialization voltage line 173.

[0143] The first scan line 151 and the second scan line 152 may be respectively disposed above and below a group of a plurality of adjacent pixels PX4, PX5, and PX6. The first data overlap line 150a, the second data overlap line 150b, the third data overlap line 150c, and the common voltage overlap line 150d may be disposed on the same layer where the first scan line 151 and the second scan line 152 are disposed. Additionally, the driving gate electrode 155 may be disposed on the same layer. Additionally, a plurality of gate patterns 150e, 150f, 150g, 150h, 150i, and 150j may overlap with the driving voltage line 172 and the initialization voltage line 173. Each of the gate patterns 150e, 150f, 150g, 150h, 150i, and 150j is electrically connected to the driving voltage line 172 and the initialization voltage line 173 through a plurality of contact holes 98 and 99. Therefore, the resistance of the driving voltage line 172 and the resistance of the initialization voltage line 173 can be reduced.

[0144] A part of the first scan line 151 includes a protruding portion (extended portion) 151a extending in the second direction DR2. A part of the second scan line 152 includes a protruding portion (extended portion) 152a extending in the second direction DR2. That is, the extended portion 151a of the first scan line 151 extends in a direction different from the remaining portion of the first scan line 151. The extended portion 152a of the second scan line 152 extends in a direction different from the remaining portion of the second scan line 152.

[0145] The first data overlap line 150a, the second data overlap line 150b, the third data overlap line 150c, and the common voltage overlap line 150d respectively overlap with a plurality of data lines 171a, 171b, and 171c and the common voltage line 170. The first data overlap line 150a, the second data overlap line 150b, and the third data overlap line 150c are connected to the corresponding data lines 171a, 171b, and 171c through a plurality of contact holes 61a. Additionally, the common voltage overlap line 150d is connected to the common voltage line 170 through a plurality of contact holes 60a.

[0146] The first data overlap line 150a, the second data overlap line 150b, the third data overlap line 150c, and the common voltage overlap line 150d are electrically connected to the corresponding data lines 171a, 171b, and 171c and the common voltage line 170 through a plurality of contact holes 61a and 60a, thereby reducing their resistance.

[0147] The lower pattern 111 includes a plurality of lower patterns 111a, 111b, 111c, 111d, and 111e. The lower pattern 111 may include, for example, TiCu. As described above, the lower pattern 111 corresponds to the first conductive layer 111.

[0148] The first lower pattern 111a overlaps with the common voltage line 170 and is connected to the common voltage line 170 through a plurality of contact holes 60b.

[0149] In addition, the second lower pattern 111b, the third lower pattern 111c, and the fourth lower pattern 111d are respectively disposed in pixels PX4, PX5, and PX6, and are respectively connected to the capacitor electrode 175 through contact holes 62b, 62c, and 62d. The fifth lower pattern 111e is connected to the common voltage line 170 through the contact hole 65a.

[0150] The driving gate electrode 155 and the capacitor electrode 175 form a capacitor Cst.

[0151] The active layer 130 includes a first active pattern 130a, a second active pattern 130b, and a third active pattern 130c.

[0152] The first active pattern 130a is connected to the driving voltage line 172 through the contact hole 91. On the other side of the first active pattern 130a, it is connected to the capacitor electrode 175 through the contact hole 92.

[0153] The source region 133a, the channel region 134a, and the drain region 135a of the first active pattern 130a and the first gate electrode 154a, which is a part of the driving gate electrode 155, form a first transistor T1.

[0154] The second active pattern 130b is connected to the corresponding data lines 171a, 171b, and 171c through the contact hole 93. On the other side of the second active pattern 130b, it is connected to the connection member 177 through the contact hole 94.

[0155] The source region 133b, the channel region 134b, and the drain region 135b of the second active pattern 130b and the second gate electrode 154b, which is a part of the protruding portion 151a of the first scan line 151, form a second transistor T2.

[0156] The third active pattern 130c is connected to the initialization voltage line 173 through the contact hole 95. On the other side of the third active pattern 130c, it is connected to the capacitor electrode 175 through the contact hole 96.

[0157] The source region 133c, the channel region 134c, and the drain region 135c of the third active pattern 130c and the third gate electrode 154c, which is a part of the protruding portion 152a of the second scan line 152, form a third transistor T3.

[0158] The connection member 177 is connected to the second active pattern 130b through the contact hole 94 and is connected to the driving gate electrode 155 through another contact hole 97.

[0159] The first electrodes 191a, 191b, and 191c of the corresponding pixels PX4, PX5, and PX6 are electrically connected to the capacitor electrode 175 through the contact holes 80.

[0160] Reference Figure 10 , each common voltage line 170 and the first scan line 151 can be electrically connected to the lower pattern 111 while overlapping with the lower pattern 111. The lower pattern 111 may include, for example, TiCu. Accordingly, the resistance of the common voltage line 170 and the resistance of the first scan line 151 can be reduced.

[0161] In addition, the first data overlap line 150a, the second data overlap line 150b, the third data overlap line 150c, and the plurality of gate patterns 150e, 150f, 150g, 150h, 150i, and 150j are also disposed below the data lines 171a, 171b, and 171c, the driving voltage line 172, and the initialization voltage line 173 while overlapping with them and electrically connected to each other. In this case, the resistance of the data lines 171a, 171b, and 171c, the resistance of the driving voltage line 172, and the resistance of the initialization voltage line 173 can be reduced.

[0162] Figure 11 is a cross-sectional view taken along line Xa-Xa' according to an exemplary embodiment of the present disclosure Figure 10 Reference Figure 11 , the common voltage line 170 overlaps with the first lower pattern 111a, the insulating pattern 144, and the common voltage overlap line 150d. Each layer is connected to each other through the contact holes. Accordingly, the resistance of the common voltage line 170 can be reduced.

[0163] As described above, the display device according to the exemplary embodiment forms a capacitor by using a second conductive layer and a third conductive layer, arranges the scan line in the same layer as the third conductive layer, and the gate electrode of the transistor includes a multi-gate electrode including the second conductive layer and the third conductive layer. Accordingly, the load of the display device can be reduced. In this case, the resistance of the third conductive layer can be lower than the resistance of the second conductive layer.

[0164] In addition, the display device according to the exemplary embodiment can reduce the resistance by forming the common voltage line, the data line, etc. in a structure in which the common voltage line and the data line overlap with the same layer and the lower pattern and are electrically connected to each other. Similarly, by overlapping the scan line with the same layer, the driving voltage line and the initialization voltage line can be formed in an electrically connected structure to reduce the resistance.

[0165] Although the present disclosure has been specifically shown and described with reference to its exemplary embodiments, those of ordinary skill in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A display device, wherein, The display device includes: a substrate; a first conductive layer disposed on the substrate; a first insulating layer disposed on the first conductive layer; a plurality of active patterns disposed on the first insulating layer and including a source region, a channel region, and a drain region; a second conductive layer disposed on the active patterns and including a first gate electrode and a driving gate electrode overlapping with the channel region; a second insulating layer disposed on the second conductive layer; a third conductive layer including a capacitor electrode and at least one scan line disposed on the second insulating layer; a third insulating layer disposed on the third conductive layer; and an electrode layer including a first electrode disposed on the third insulating layer, wherein the first electrode is connected to the capacitor electrode, and the capacitor electrode overlaps with the driving gate electrode, and the capacitor electrode and the driving gate electrode form a capacitor.

2. The display device according to claim 1, wherein, The capacitor electrode is electrically connected to the first conductive layer.

3. The display device according to claim 1, wherein, The second conductive layer further includes an overlapping gate pattern overlapping with the at least one scan line.

4. The display device according to claim 1, wherein, The third insulating layer includes an organic material.

5. The display device according to claim 1, wherein, The display device further includes: a fourth conductive layer disposed between the third insulating layer and the electrode layer, wherein the fourth conductive layer includes data lines, driving voltage lines, common voltage lines, initialization voltage lines, and a plurality of connection patterns.

6. The display device according to claim 5, wherein, The at least one scan line includes a first scan line and a second scan line; The second conductive layer further includes a second gate electrode; and The first scan line and the second gate electrode are connected to each other through one of the plurality of connection patterns.

7. The display device according to claim 5, wherein, The first electrode and the capacitor electrode are connected to each other through one of the plurality of connection patterns.

8. The display device according to claim 1, wherein, The third conductive layer further includes a plurality of connection electrodes; The plurality of active patterns include a first active pattern, a second active pattern, and a third active pattern; and each active pattern is connected to at least one of the plurality of connection electrodes of the third conductive layer.

9. The display device according to claim 8, wherein, The resistance of the third conductive layer is lower than that of the second conductive layer.

10. A display device, wherein, The display device includes: a substrate; a first conductive layer disposed on the substrate; a first insulating layer disposed on the first conductive layer; a plurality of active patterns disposed on the first insulating layer and including a source region, a channel region, and a drain region; a second conductive layer disposed on the active patterns and including a plurality of data overlapping lines; a second insulating layer disposed on the second conductive layer; a third conductive layer disposed on the second insulating layer and including a plurality of data lines, common voltage lines, and at least one scan line; a third insulating layer disposed on the third conductive layer; and an electrode layer including a first electrode disposed on the third insulating layer, wherein the plurality of data lines respectively overlap with the plurality of data overlapping lines, and the at least one scan line overlaps with the first conductive layer.

11. The display device according to claim 10, wherein, The second conductive layer further includes a common voltage overlapping line; The common voltage line overlaps with the common voltage overlapping line and the first conductive layer; and The common voltage line is electrically connected to the common voltage overlapping line and the first conductive layer.

12. The display device according to claim 10, wherein, The third conductive layer further includes driving voltage lines and initialization voltage lines; The second conductive layer includes a plurality of gate patterns; and the plurality of gate patterns, the driving voltage line, and the initialization voltage line overlap with each other respectively.

13. The display device according to claim 10, wherein, The first conductive layer includes a plurality of lower patterns; and one of the plurality of lower patterns is disposed in a direction intersecting with the common voltage line and connected to the common voltage line.

14. The display device according to claim 10, wherein, The plurality of active patterns include a first active pattern, a second active pattern, and a third active pattern; The at least one scanning line includes a first scanning line and a second scanning line; An extension portion of the first scanning line extends in a direction different from that of the remaining portion of the first scanning line; and The extension portion of the first scanning line overlaps with the channel regions of the first active pattern and the third active pattern.

15. The display device according to claim 14, wherein, An extension portion of the second scanning line extends in a direction different from that of the remaining portion of the second scanning line; and The extension portion of the second scanning line overlaps with the channel region of the second active pattern.

16. The display device according to claim 10, wherein, The display device further includes: a pad electrode disposed on the same layer as the third conductive layer; and a pad connection electrode disposed on the same layer as the second conductive layer, wherein the pad electrode is electrically connected to the first conductive layer, and the pad electrode is electrically connected to the pad connection electrode.

17. The display device according to claim 10, wherein, The second conductive layer further includes a driving gate electrode, and the third conductive layer further includes a capacitor overlapping with the driving gate electrode.

18. The display device according to claim 17, wherein, The first conductive layer includes a plurality of lower patterns, and at least one of the plurality of lower patterns overlaps with a capacitor electrode.

19. The display device according to claim 17, wherein, The display device further includes: a first electrode connected to the capacitor electrode.

20. A display device, wherein, The display device includes: a substrate; a first conductive layer disposed on the substrate; a transistor disposed on the first conductive layer and including a gate electrode and an overlapping gate electrode, wherein the gate electrode is formed in a second conductive layer disposed on the first conductive layer, and the overlapping gate electrode is formed in a third conductive layer disposed on the second conductive layer; a capacitor including a driving gate electrode and a capacitor electrode, wherein the capacitor electrode overlaps with the driving gate electrode, the capacitor electrode is formed in the third conductive layer, and the driving gate electrode is formed in the second conductive layer; and a scanning line formed in the third conductive layer.

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