A transmitting detection circuit based on the detection mark signal processing of the transceiver component

Abstract

The present invention discloses a transmission detection circuit based on the processing of detection mark signals of a transceiver component. By setting a detection control terminal, a transmission signal source, an FPGA logic control circuit, a DAC module and a radio frequency channel, the detection control terminal is used to provide a transmission detection control signal for the FPGA logic control circuit and the radio frequency channel, and the transmission signal source is used to provide a signal source for transmission detection for the FPGA logic control circuit and the DAC module; then, the radio frequency channel detects and outputs the transmission signal according to the received transmission detection control signal, and at the same time, feeds back the detection mark signal to the FPGA logic control circuit when the radio frequency is output; finally, the FPGA logic control circuit is used to output the detection result according to the received transmission detection control signal, the signal source and the detection mark signal. The present invention is equipped with a detection control device, a DAC module and an FPGA logic control circuit on the basis of the radio frequency channel. It aims to solve the technical problem that the judgment accuracy of the successful transmission of the signal on the transceiver component is not high in the prior art.

Description

Technical Field

[0001] The invention relates to the field of communications, and in particular to a transmission detection circuit based on detection mark signal processing of a transceiver component. Background Art

[0002] When the transceiver component is performing normal transmission operation, it needs to know whether the signal is actually transmitted. Detection (amplitude demodulation) is the inverse process of amplitude modulation. Through the detection operation, it can be known whether the signal is transmitted through the antenna.

[0003] At present, the circuits for realizing detection are all analog circuits. The detection circuit mainly consists of three parts: high-frequency modulated signal source, nonlinear device, and RC low-pass filter. The output of this detector depends on the amplitude of the signal (there is no definite threshold), and when the transceiver component is transmitting normally, the amplitude of the modulated wave position signal is also uncertain. If it is judged only by the output of this detector, the false alarm rate will be high. Therefore, how to improve the judgment accuracy of the successful transmission of the signal on the transceiver component is a technical problem that needs to be solved urgently.

[0004] The above contents are only used to assist in understanding the technical solution of the present invention and do not constitute an admission that the above contents are prior art. Summary of the invention

[0005] The main purpose of the present invention is to provide a transmission detection circuit based on the detection mark signal processing of the transceiver component, aiming to solve the technical problem in the prior art that the judgment accuracy of the successful transmission of the signal on the transceiver component is not high.

[0006] To achieve the above-mentioned purpose, the present invention proposes a transmission detection circuit based on the detection mark signal processing of the transceiver component, the transmission detection circuit comprising: a detection control terminal, a transmission signal source, an FPGA logic control circuit, a DAC module and a radio frequency channel; the first output end of the detection control terminal is connected to the control signal input end of the radio frequency channel, and the second output end of the detection control terminal is connected to the control signal input end of the FPGA logic control circuit; the first output end of the transmission signal source is connected to the transmission signal input end of the FPGA logic control circuit, and the second output end of the transmission signal source is connected to the transmission signal input end of the DAC module; the transmission signal output end of the DAC module is connected to the transmission signal input end of the radio frequency channel; the first output end of the radio frequency channel is connected to the detection mark signal input end of the FPGA logic control circuit; wherein:

[0007] Preferably, the detection control terminal provides a transmission detection control signal for the FPGA logic control circuit and the radio frequency channel; the transmission signal source provides a transmission detection signal source for the FPGA logic control circuit and the DAC module;

[0008] Preferably, the RF channel detects the transmission signal and outputs it as RF according to the received transmission detection control signal, or inputs the received signal as RF; and at the same time, feeds back the detection flag signal to the FPGA logic control circuit during RF output;

[0009] Preferably, the FPGA logic control circuit is connected to the control end of the DAC module to provide it with a clock signal and a control signal. At the same time, the FPGA logic control circuit outputs a detection result based on the received transmission detection control signal, signal source and detection flag signal.

[0010] Preferably, the RF channel includes an RF transmitting channel, an RF receiving channel, an RF status switching circuit, an RF power switching circuit and a first power supply; wherein the output end of the RF transmitting channel and the input end of the RF receiving channel receive the transmitting antenna, and the access of the RF transmitting channel and the RF receiving channel is controlled by the RF status switching circuit; the RF power switching circuit controls the connection access of the RF channel with the first power supply.

[0011] Preferably, the RF channel also includes a detection circuit, which is connected to the RF transmitting channel and the receiving transmitting antenna. When the RF channel receives the signal source of the DAC module and transmits the output, the detection circuit returns the detection flag signal of the RF channel to the FPGA logic control circuit.

[0012] Preferably, the DAC module includes a DAC chip, a DAC power switch circuit and a second power supply; wherein the DAC chip receives a clock signal and a chip control signal sent by an FPGA logic control circuit, converts a digital signal transmitted via a transmitting signal source into an analog signal and transmits it to a radio frequency channel; and the DAC power switch circuit controls the connection between the DAC chip and the second power supply.

[0013] Preferably, the detection control terminal is used to send a transmit detection control signal to the RF channel and the FPGA logic control circuit respectively, and the detection control signal includes a transmit-receive switching control signal TR and a transmit power switch control signal AM; wherein the RF channel controls the RF channel to send signals and output a detection flag signal according to the transmit-receive switching control signal TR and the transmit power switch control signal AM, and the FPGA logic control circuit receives the detection flag signal sent by the RF channel according to the transmit-receive switching control signal TR and the transmit power switch control signal AM.

[0014] Preferably, the FPGA logic control circuit executes a state machine to output a transmission detection result according to the amplitude value of the signal I / Q sent by the transmission signal source and the received detection flag signal.

[0015] In the present invention, by setting a detection control terminal, a transmission signal source, an FPGA logic control circuit, a DAC module and a radio frequency channel, the detection control terminal is used to provide a transmission detection control signal for the FPGA logic control circuit and the radio frequency channel, and the transmission signal source is used to provide a signal source for transmission detection for the FPGA logic control circuit and the DAC module; then, the radio frequency channel detects the transmission signal according to the received transmission detection control signal and outputs it by radio frequency, and at the same time, the detection flag signal is fed back to the FPGA logic control circuit during the radio frequency output; finally, the FPGA logic control circuit is used to output the detection result according to the received transmission detection control signal, the signal source and the detection flag signal. On the basis of the radio frequency channel, the present invention is equipped with a detection control device, a DAC module for radio frequency transmission and an FPGA logic control circuit for judging and outputting the detection result. It is intended to solve the technical problem that the judgment accuracy of the successful transmission of the signal on the transceiver component is not high in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0017] Figure 1 This is a structural schematic diagram of a transmission detection circuit based on the processing of the detection mark signal of the transceiver component proposed by the present invention;

[0018] Figure 2 This is a diagram of the operating principle and steps of an embodiment of a transmission detection circuit based on the detection mark signal processing of the transceiver component proposed by the present invention.

[0019] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0020] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0021] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0023] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0024] The present invention proposes an embodiment, referring to Figure 1 , Figure 1 The present invention provides a schematic diagram of the structure of a transmitting detection circuit based on the processing of a detection mark signal of a transceiver component.

[0025] like Figure 1 As shown, in this embodiment, a transmission detection circuit based on the detection mark signal processing of the transceiver component, the transmission detection circuit includes: a detection control terminal, a transmission signal source, an FPGA logic control circuit, a DAC module and a radio frequency channel; the first output end of the detection control terminal is connected to the control signal input end of the radio frequency channel, and the second output end of the detection control terminal is connected to the control signal input end of the FPGA logic control circuit; the first output end of the transmission signal source is connected to the transmission signal input end of the FPGA logic control circuit, and the second output end of the transmission signal source is connected to the transmission signal input end of the DAC module; the transmission signal output end of the DAC module is connected to the transmission signal input end of the radio frequency channel; the first output end of the radio frequency channel is connected to the detection mark signal input end of the FPGA logic control circuit; wherein:

[0026] It should be noted that the detection control terminal provides a transmission detection control signal for the FPGA logic control circuit and the radio frequency channel; the transmission signal source provides a transmission detection signal source for the FPGA logic control circuit and the DAC module;

[0027] It should be noted that the RF channel detects the transmission signal and outputs it as RF according to the received transmission detection control signal, or inputs the received signal as RF; and at the same time, feeds back the detection flag signal to the FPGA logic control circuit during RF output;

[0028] It should be noted that the FPGA logic control circuit is connected to the control end of the DAC module to provide it with a clock signal and a control signal. At the same time, the FPGA logic control circuit outputs a detection result based on the received transmission detection control signal, signal source and detection flag signal.

[0029] Furthermore, the RF channel in this embodiment includes an RF transmitting channel, an RF receiving channel, an RF status switching circuit, an RF power switching circuit and a first power supply; wherein, the output end of the RF transmitting channel and the input end of the RF receiving channel receive the transmitting antenna, and the access of the RF transmitting channel and the RF receiving channel is controlled by the RF status switching circuit; the RF power switching circuit controls the connection between the RF channel and the first power supply.

[0030] In this embodiment, the RF channel also includes a detection circuit, which is connected to the RF transmitting channel and the receiving transmitting antenna. When the RF channel receives the signal source of the DAC module and transmits the output, the detection circuit returns the detection flag signal of the RF channel to the FPGA logic control circuit.

[0031] Furthermore, the DAC module in this embodiment includes a DAC chip, a DAC power switch circuit, and a second power supply; wherein the DAC chip receives a clock signal and a chip control signal sent by the FPGA logic control circuit, converts a digital signal transmitted via a transmitting signal source into an analog signal and transmits it to a radio frequency channel; and the DAC power switch circuit controls the connection between the DAC chip and the second power supply.

[0032] Furthermore, the detection control terminal in this embodiment is used to send a transmit detection control signal to the RF channel and the FPGA logic control circuit respectively, and the detection control signal includes a transmit-receive switching control signal TR and a transmit power switch control signal AM; wherein the RF channel controls the RF channel to send signals and output a detection flag signal according to the transmit-receive switching control signal TR and the transmit power switch control signal AM, and the FPGA logic control circuit receives the detection flag signal sent by the RF channel according to the transmit-receive switching control signal TR and the transmit power switch control signal AM.

[0033] Furthermore, the FPGA logic control circuit described in this embodiment executes the state machine to output the transmission detection result according to the amplitude value of the signal I / Q sent by the transmission signal source and the received detection flag signal.

[0034] It is important to understand that Figure 2 As shown, the transmission detection method of this embodiment mainly includes the following steps:

[0035] S1. Assume that the transceiver function of the transceiver assembly is controlled by control signals TR and AM:

[0036] TR is the control signal for switching between transmit and receive. When TR=1, it means switching to the transmit state; when TR=0, it means switching to the receive state.

[0037] AM is the transmitting power switch control signal, when AM=1, the transmitting power switch is turned on, and when AM=0, the transmitting power switch is turned off;

[0038] S2. Before transmitting the signal, first set TR = 1, switch to the transmitting state, then set the control signal AM = 1, turn on the transmitting power switch, and start transmitting the signal;

[0039] S3. When the signal is transmitted through the RF channel, the RF channel will output a detection flag signal (if the flag signal is directly used as the final judgment result of the transmission detection, the judgment will be unstable or even wrong);

[0040] S4. After the signal transmission is completed, first set AM = 0, then set the control signal TR = 0, enter the receiving state, and wait for the next transmission process to come.

[0041] S5. The controller (FPGA) executes the program running state machine according to the amplitude value of the transmit signal I / Q and the detection flag signal obtained in S3, and finally outputs the transmit detection decision signal.

[0042] In an embodiment of the present application, if the transmitting power supply is in the on state (AM=1) and switched to the receiving state (TR=0), in this case, the transmitting signal will linger in the transmitting channel and eventually burn the device, so this situation must be avoided; therefore, in the receiving state (TR=0), the transmitting power switch (AM=0) must be turned off a period of time in advance (1us in the embodiment of the present application).

[0043] In the receiving state, no signal is sent to the RF channel through the digital-to-analog converter (DAC). It is normal for the RF channel to not output a transmission detection flag signal in this state. Therefore, the program must avoid judging the transmission detection in the receiving state.

[0044] To this end, we first set a fixed threshold value d0 according to the bit width of the DAC. On the one hand, multiple experiments have proved that if the value of d0 is sent to the DAC and transmitted through the RF channel, the FPGA can receive the transmission detection flag signal; on the other hand, the I / Q value sent to the DAC in the receiving state is 0, and the amplitude value cannot exceed d0, which effectively avoids the judgment of the transmission detection in the receiving state. In addition, in order to obtain a stable and correct final judgment result, the number of detections needs to be accumulated. Therefore, the program uses a state machine to implement this process, specifically:

[0045] Specifically, the implementation of step S5 includes the following steps:

[0046] S501. Calculate (I max and Q max are both determined by the bit width of the digital-to-analog converter. For example, if the bit width of the digital-to-analog converter is 14 bits, then I max = 16384, Q max = 16384, d0 = 5793).

[0047] S502. The program sets a detection counter, and when powered on and reset, the detection counter is set to a fixed initial value c0 (in this example, c0 = 40).

[0048] S503. During the time when TR = 1 and AM = 1, the controller (FPGA) calculates the amplitude value of the transmitted data I / Q

[0049] S504. For each transmission, if d1 >= d0, it is considered that the transmitted I / Q data is valid detection data. The program state machine will check the detection flag signal returned by the radio frequency channel in the next state and count it into the detection counter: when the detection flag is detected, c0 + 1 (the detection counter is set with a maximum detection count c1, in this example, c1 = 250), when the detection flag is not detected, c0 - 1 (the detection counter is set with a minimum detection count c2, in this example, c2 = 10), until the end of this transmission process; if d1 < d0, it is considered that the transmitted I / Q data is invalid detection data, and the program state machine will maintain the current state until the end of this transmission process (regardless of the relationship between d1 and d0, the I / Q data is still normally transmitted).

[0050] S505. When the system is transmitting normally (usually multiple consecutive transmissions), if the value of the detection counter is lower than c2, it is determined that the transmission detection is faulty, otherwise it is determined that the transmission detection is normal.

[0051] In the embodiments of the present application, the specific implementation principle of the transmission detection circuit based on the detection flag signal processing of the transceiver component is as follows:

[0052] The FPGA is set at the output end of the radio frequency channel in the transceiver component, and the FPGA program processes the transmission detection flag signal output by the radio frequency channel. In this embodiment, the TR and AM signals are generated by the baseband processing device or an external device; the TR signal is used to control the transceiver switching switch. When TR=0, the transceiver switching switch is switched to the receiving channel to connect the receiving channel with the transceiver antenna; when TR=1, the transceiver switching switch is switched to the transmitting channel to connect the transmitting channel with the transceiver antenna; in the entire embodiment, power is supplied by an external power supply. Except for the transmitting channel and DAC, other parts are always powered as long as the transceiver component is started; and the power supply of the external power supply to the transmitting channel and DAC needs to pass through the transmitting power switch, and the on and off of the transmitting power switch is controlled by the AM signal; when AM=1, the transmitting power switch is turned on, and when AM=0, the transmitting power switch is turned off; in this embodiment, the TR and AM signals generated by the baseband signal processing device or the external device need to be transmitted to the FPGA at the same time, so as to realize the final judgment of the transmission detection according to the above steps S501 to S505.

[0053] The I / Q data rate transmitted from the channel to the DAC (14 bits) is 80MHz. First, the I / Q data is converted into the amplitude value of the signal after being transformed by Cordic (IP core). On the one hand, the program state machine of the FPGA compares the amplitude value with the fixed threshold (5793); on the other hand, the amplitude value is simultaneously transmitted to the DAC, and the DAC then transmits the output analog signal through the RF channel. Since the RF channel contains an analog circuit for detection, when the amplitude of the transmitted signal is not less than 5793, the RF channel will output a detection flag signal to the FPGA. The FPGA accumulates and counts the detection flag signal output by the RF channel through the program running state machine. Practice has proved that if there is a problem with the RF channel, during the transmission, the program state machine will continuously reduce the detection counter by 1 until the detection counter reaches the lower limit, and (quickly) output the detection fault information; otherwise, it will quickly output the detection normal information.

[0054] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A transmitting detection circuit based on the detection mark signal processing of the transceiver component, characterized in that: The transmitting detection circuit includes: a detection control terminal, a transmitting signal source, an FPGA logic control circuit, a DAC module and a radio frequency channel; the first output end of the detection control terminal is connected to the control signal input end of the radio frequency channel, and the second output end of the detection control terminal is connected to the control signal input end of the FPGA logic control circuit; the first output end of the transmitting signal source is connected to the transmitting signal input end of the FPGA logic control circuit, and the second output end of the transmitting signal source is connected to the transmitting signal input end of the DAC module; the transmitting signal output end of the DAC module is connected to the transmitting signal input end of the radio frequency channel; the first output end of the radio frequency channel is connected to the detection flag signal of the FPGA logic control circuit Input end; wherein: the detection control terminal provides a transmission detection control signal for the FPGA logic control circuit and the radio frequency channel; the transmission signal source provides a signal source for the transmission detection for the FPGA logic control circuit and the DAC module; the radio frequency channel detects the transmission signal according to the received transmission detection control signal and outputs it as a radio frequency, or inputs the received signal as a radio frequency; and at the same time, feeds back a detection flag signal to the FPGA logic control circuit during the radio frequency output; the FPGA logic control circuit is connected to the control end of the DAC module to provide it with a clock signal and a control signal, and at the same time, the FPGA logic control circuit outputs the detection result according to the received transmission detection control signal, the signal source and the detection flag signal; The FPGA logic control circuit outputs the detection result according to the received transmission detection control signal, signal source and detection flag signal, specifically including: The program sets the detection counter, and the detection counter is set to a fixed initial value c0 when the power is reset; During the time when the transmitting detection circuit is in the transmitting state and the transmitting power supply is in the on state, the FPGA calculates the amplitude value of the transmitted data I / Q; For each transmission, if the threshold value d1>=threshold value d0, the transmitted I / Q data is considered to be valid detection data, and the program state machine will check the detection mark signal returned by the RF channel in the next state and count it into the detection counter: if the detection mark is detected, it is c0+1, if the detection mark is not detected, it is c0-1, until the end of this transmission process; if the threshold value d1<threshold value d0, the transmitted I / Q data is considered to be invalid detection data, and the program state machine will maintain the current state until the end of this transmission process; When the transmitting detection circuit transmits normally, if the detection counter value is lower than the minimum detection count c2, the transmitting detection is judged to be faulty, otherwise the transmitting detection is judged to be normal.

2. A transmitting detection circuit based on the detection mark signal processing of the transceiver component as claimed in claim 1, characterized in that: The RF channel includes an RF transmitting channel, an RF receiving channel, an RF state switch circuit, an RF power switch circuit and a first power supply; wherein the output end of the RF transmitting channel and the input end of the RF receiving channel receive the transmitting antenna, and the access of the RF transmitting channel and the RF receiving channel is controlled by the RF state switch circuit; the RF power switch circuit controls the connection access of the RF channel and the first power supply.

3. A transmitting detection circuit based on the detection mark signal processing of the transceiver component as claimed in claim 2, characterized in that: The RF channel also includes a detection circuit, which is connected to the RF transmitting channel and the receiving transmitting antenna. When the RF channel receives the signal source of the DAC module and transmits the output, the detection circuit returns the detection flag signal of the RF channel to the FPGA logic control circuit.

4. A transmitting detection circuit based on the detection mark signal processing of the transceiver component as claimed in claim 3, characterized in that: The DAC module includes a DAC chip, a DAC power switch circuit and a second power supply; wherein the DAC chip receives a clock signal and a chip control signal sent by an FPGA logic control circuit, converts a digital signal transmitted via a transmitting signal source into an analog signal and transmits it to a radio frequency channel; and the DAC power switch circuit controls the connection between the DAC chip and the second power supply.

5. A transmitting detection circuit based on the detection mark signal processing of the transceiver component as claimed in claim 4, characterized in that: The detection control terminal is used to send a transmission detection control signal to the RF channel and the FPGA logic control circuit respectively, and the detection control signal includes a transceiver switching control signal TR and a transmission power switch control signal AM; wherein the RF channel controls the RF channel to send signals and output a detection flag signal according to the transceiver switching control signal TR and the transmission power switch control signal AM, and the FPGA logic control circuit receives the detection flag signal sent by the RF channel according to the transceiver switching control signal TR and the transmission power switch control signal AM.

6. A transmitting detection circuit based on the detection mark signal processing of the transceiver component as claimed in claim 5, characterized in that: The FPGA logic control circuit executes the state machine to output the transmission detection result according to the amplitude value of the signal I / Q sent by the transmission signal source and the received detection flag signal.

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