A processor including a debugging unit and a debugging system

Abstract

The present invention discloses a debugging unit, comprising: a write register, adapted to store kernel write data written by a processor kernel, the kernel write data being read by a debugger coupled to the processor; a kernel write identification bit, adapted to indicate the data validity of the kernel write data; and a control unit, adapted to control the processor kernel and the debugger's access to the write register according to the data validity indicated by the write identification bit. The present invention also discloses a corresponding processor, a debugger and a debugging system.

Description

Technical Field

[0001] The present invention relates to the field of processors, and in particular to the field of kernel debugging in processors. Background Art

[0002] Modern processors generally include debugging capabilities. Debugging can not only identify flaws in the processor design process, but also help programmers better analyze the robustness of the code executed in the processor and improve code performance.

[0003] Processor debugging has various requirements, such as the need to understand the current state of registers and memory contents during processor execution in real time, as well as the need to modify register and memory contents and processor status. To achieve this, processor debugging requires establishing a communication channel between the processor core and the debugger to facilitate data transfer between the two.

[0004] One existing solution is to have the debugger generate an interrupt to notify the processor core to initiate data transfers. However, this approach requires a separate interrupt vector number and requires consideration of interrupt priority. If the system assigns a low interrupt priority, the debugger interrupt may remain unresponsive to the processor core for a long time, resulting in inefficient communication.

[0005] Therefore, a new debugging method is needed that can efficiently establish a communication channel and transmit debugging data. Summary of the Invention

[0006] To this end, the present invention provides a new processor and a debugging unit therein, in an effort to solve or at least alleviate at least one of the above problems.

[0007] According to one aspect of the present invention, a debugging unit is provided, comprising: a write register adapted to store kernel write data written by a processor core, the kernel write data being read by a debugger coupled to the processor; a kernel write identification bit adapted to indicate data validity of the kernel write data; and a control unit adapted to control access to the write register by the processor core and the debugger based on the data validity indicated by the write identification bit.

[0008] Optionally, in the debugging unit according to the present invention, the control unit is adapted to allow the processor core to write core write data to the write register when the core write flag indicates that the data is invalid, and to prevent the processor core from writing core write data to the write register when the core write flag indicates that the data is valid; and after the processor core writes the core write data, set the core write flag to indicate that the data is valid.

[0009] Optionally, in the debugging unit according to the present invention, the control unit is adapted to indicate to the debugger the data validity of the read kernel write data according to the kernel write identification bit when the debugger reads the kernel write data from the write register; and after the debugger reads the kernel write data, the kernel write identification bit is set to indicate that the data is invalid.

[0010] Optionally, the debug unit according to the present invention further comprises a jump enable register including a write enable bit, the write enable bit indicating whether a write jump request is generated. The control unit is adapted to, when the write enable bit indicates the generation of a write jump request, send the write jump request to the processor core after the debugger reads the core write data.

[0011] Optionally, the debugging unit according to the present invention further includes a jump information maintenance unit adapted to store a handler address and processor state information. The control unit is adapted to store a first handler address and a first processor state suitable for processing the write jump request in the jump information maintenance unit before sending the write jump request to the processor core, so that when the processor core processes the write jump request, it sets the processor state to the first processor state and jumps to the first handler address to execute the program.

[0012] Optionally, the debugging unit according to the present invention also includes: a read register, suitable for storing core read data written by the debugger, and the core read data is read by the processor core; a core read identification bit, suitable for indicating the data validity of the core read data; and a control unit suitable for controlling the access of the processor core and the debugger to the read register according to the data validity indicated by the core read identification bit.

[0013] Optionally, in the debugging unit according to the present invention, the control unit is adapted to allow the debugger to write kernel read data to the read register when the kernel read flag indicates that the data is invalid, and to prevent the debugger from writing kernel read data to the read register when the kernel read flag indicates that the data is valid; and after the debugger writes the kernel read data, the kernel read flag is set to indicate that the data is valid.

[0014] Optionally, in the debugging unit according to the present invention, the control unit is suitable for indicating the data validity of the read core read data to the processor core according to the core read identification bit when the processor core reads the core read data from the read register; and after the processor core reads the core read data, setting the core read identification bit to indicate that the data is invalid.

[0015] Optionally, in the debugging unit according to the present invention, the jump enable register includes a read enable bit, which indicates whether a read jump request is generated; and the control unit is adapted to send a read jump request to the processor core after the debugger writes the core read data when the read enable bit indicates that a read jump request is generated.

[0016] Optionally, in the debugging unit according to the present invention, the control unit is suitable for storing a second handler address and a second processor state suitable for processing the read jump request in the jump information maintenance unit before sending the read jump request to the processor core, so that when the processor core processes the read jump request, it sets the processor state to the second processor state and jumps to the second handler address to execute the program.

[0017] Optionally, in the debugging unit according to the present invention, the first handler address includes an entry address of a first handler, the first handler includes a program instructing the processor core to write processor write data to the debugging unit; and the second handler address includes an entry address of a second handler, the second handler includes a program instructing the processor core to read processor read data from the debugging unit.

[0018] Optionally, in the debugging unit according to the present invention, the core write flag is contained in the write register, and the core read flag is contained in the read register.

[0019] According to another aspect of the present invention, a processor is provided, comprising: the above-mentioned debugging unit; and a processor core, comprising a read-write unit and a jump processing unit, wherein the read-write unit is suitable for writing core write data to the write register of the debugging unit and reading core read data from the read register of the debugging unit, and the jump processing unit is suitable for processing jump requests issued by the debugging unit.

[0020] According to another aspect of the present invention, a debugger is provided, comprising: a debugging host adapted to generate debugging commands to be sent to a processor according to the present invention, and to present debugging data sent by the processor in response to the debugging commands; and a protocol converter adapted to convert the debugging commands, send the converted debugging commands to the processor, and receive debugging data returned from the processor.

[0021] According to another aspect of the present invention, a debugging system is provided, comprising the above-mentioned processor and debugger.

[0022] According to the solution of the present invention, a debugging unit is built into the processor to process debug data communication between the processor core and an external debugger. A control unit in the debugging unit controls debug data transmission between the processor core and the debugger based on a processor core read flag and a processor core write flag. This eliminates the need for the processor core to determine whether to perform debug data transmission by querying a register, thereby improving debugging efficiency.

[0023] On the other hand, according to the solution of the present invention, when the debugger writes data to be transmitted to the processor core, a debug jump can be immediately generated, allowing the processor core to read the data, completing a communication transmission from the debugger to the processor core with minimal delay. After the debugger reads the data transmitted by the processor core, a debug jump can also be immediately generated, causing the processor core to write new data again, initiating the next communication transmission from the processor core to the debugger with minimal delay. The debug jump solution provided by this solution eliminates the need to use interrupts to notify the processor core of data transmission, eliminates the need to occupy interrupt vector number resources, and thus eliminates the problem of slow response caused by interrupt priority determination. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] To achieve the above and related purposes, certain illustrative aspects are described herein in conjunction with the following description and accompanying drawings, which indicate various ways in which the principles disclosed herein may be practiced, and all aspects and their equivalents are intended to fall within the scope of the claimed subject matter. The above and other objects, features, and advantages of the present disclosure will become more apparent by reading the following detailed description in conjunction with the accompanying drawings. Throughout this disclosure, the same reference numerals generally refer to the same parts or elements.

[0025] Figure 1 FIG. 1 is a schematic diagram showing a debugging system 100 according to an embodiment of the present invention;

[0026] Figure 2 A flowchart 400 illustrating a processor core sending debug data to a debugger according to an embodiment of the present invention is shown; and

[0027] Figure 3 A flowchart 500 of a debugger sending debug data to a processor core according to another embodiment of the present invention is shown. DETAILED DESCRIPTION

[0028] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0029] Figure 1 FIG. 1 is a schematic diagram of a debugging system 100 according to an embodiment of the present invention. Figure 1 As shown, the debugging system includes a processor 110 and a debugger 120 , and the processor 110 includes a processor core 200 and a debugging unit 300 .

[0030] The debugger 120 is a device for debugging the processor 110. The processor 110 communicates with the debugger 120 through the debug unit 300. According to one embodiment, the debugger 120 and the debug unit 300 communicate via a JTAG interface and in accordance with a JTAG communication protocol compatible with the IEEE-1149.1 standard. The present invention is not limited to the specific form of the JTAG interface for communication between the debugger 120 and the processor 110 (debug unit 300). The JTAG interface can be integrated with an existing JTAG component or an independent JTAG controller. The present invention is also not limited to the JTAG protocol, and all methods for transmitting debug commands and data between the debugger 120 and the processor 110 are within the scope of protection of the present invention.

[0031] Optionally, the debugger 120 includes a debug host 122 and a protocol converter 124. The debug host 122 can be a computer running debugging software and can issue high-level debug commands, such as setting breakpoints, accessing memory or registers, and writing debug data to memory or registers. The debug host 122 sends these debug commands to the protocol converter 124. The protocol converter 124 converts the high-level debug commands into low-level JTAG commands and then transmits the JTAG commands to the debug unit 300 via the JTAG interface. Similarly, if the debug unit 300 initiates a data transfer to the debugger 120, the debug unit 300 issues a JTAG command to the debugger 120 via the JTAG interface. The protocol converter 124 receives the JTAG command, converts it into a high-level command, and then transmits it to the debug host 122, so that the debug host 122 can display the received debug data.

[0032] The processor 110 provides debugging functionality for the debugger 120 coupled to the processor 110 via the debug unit 300. The debugger 120 needs to transmit data with the processor core 200 for debugging. According to one embodiment, the debug unit 300 can be used to establish a debug communication channel between the debugger 120 and the processor core 200 to implement data transmission between the debugger 120 and the processor core 200. Debug communication includes two scenarios: one in which the processor core 200 transmits data to the debugger 120, and the other in which the debugger 120 transmits data to the processor core 200. The debug unit 300 is required to implement debug communication in both scenarios.

[0033] like Figure 1 As shown, the debug unit 300 includes a write register 310. The core write register 310 is, for example, a 32-bit or 33-bit register, in which core write data 312 written by the processor core 200 can be stored. The core write data 312 is read by the debugger 120 to implement data transmission from the processor core 200 to the debugger 120.

[0034] The debug unit 300 also includes a kernel write flag 320. The kernel write flag 320 indicates the validity of the kernel write data 312 in the write register 310. The validity of the kernel write data 312 means that the data is written to the register 310 by the processor core 200 and has not been read by the debugger 120. If the debugger 120 has read the kernel write data, the kernel write flag 320 indicates that the kernel write data 312 is invalid. According to one embodiment of the present invention, a value of 1 for the kernel write flag 320 indicates that the data is valid, and a value of 0 indicates that the data is invalid.

[0035] Optionally, the core write flag 320 may be included in the write register 310. The core write flag 320 may also be independent of the write register 310, for example, located in a register other than the write register 310.

[0036] In the case where the core write flag 320 is included in the write register 310, according to one embodiment, the write register 310 is a 32-bit register, one bit of which is used as the core write flag 320, and the other 31 bits are used to store the core write data 312. According to another embodiment, the write register 310 is a 33-bit register, one bit of which is used as the core write flag 320, and the other 32 bits are used to store the core write data 312.

[0037] The advantage of including the core write flag 320 in the write register 310 is that the core write flag 320 and the core write data 312 can be obtained at once by reading the write register 310. However, when the core write flag 320 is stored independently of the write register 310, it is necessary to first read the core write flag, and then read the core write data 312 stored in the write register 310 based on the value of the core write flag, which increases the number of register reads.

[0038] like Figure 1 As shown, the debug unit 300 further includes a control unit 330. The control unit 330 controls access to the write register 310 by the processor core 200 and the debugger 120, i.e., writing core write data 312 and reading core write data 312. The control unit 330 controls access to the write register 310 based on the value of the core write flag 320, i.e., the data validity indicated.

[0039] The processor core 200 writes the core write data 312 into the write register 310 via the control unit 330. According to one embodiment, Figure 1As shown, the processor core 200 includes a read / write unit 210. The processor core 200 sends core write data 312 to the debug unit 300 via the read / write unit 210. When the value of the core write flag 320 indicates valid data, it means that the value currently in the core write register 310 has not been read by the debugger 120. Therefore, the control unit 330 prevents the processor core 200 (i.e., the read / write unit 210) from writing the core write data 312 to the write register 310. Conversely, when the value of the core write flag 320 indicates invalid data, it means that the value currently in the core write register 310 has been read by the debugger 120. Therefore, the control unit 330 allows the processor core 200 to write the core write data 312 to the write register 310. After writing the core write data 312, the control unit 330 sets the value of the core write flag 320 to indicate valid data, thereby preventing the processor core 200 from further writing the core write data 312.

[0040] According to one embodiment, the kernel write flag 320 is included in the write register 310. In this case, the kernel write flag 320 (the value of which is 1, indicating that the data is valid) and the kernel write data 312 can be written into the write register 310 at once, without having to write the kernel write data 312 and modify the value of the kernel write flag 320 separately.

[0041] Similarly, the debugger 120 reads kernel write data 312 from the write register 310 via the control unit 330. When the debugger 120 reads kernel write data 312, the control unit 330 indicates to the debugger 120 the validity of the kernel write data 312 based on the value of the kernel write flag 320. According to one embodiment, the control unit 330 may directly send the value of the kernel write flag to the debugger 120 so that the debugger 120 can perform subsequent processing based on the value. When the value of the kernel write flag 320 indicates that the data is valid, the debugger 120 may use the read kernel write data 312 for subsequent processing. However, when the value of the kernel write flag 320 indicates that the data is invalid, it indicates that the debugger 120 has previously read the kernel write data 312, and therefore the debugger 120 should discard the kernel write data 312 currently being read. Each time after the debugger 120 reads the kernel write data 312 , the value of the kernel write flag 320 is set to indicate that the data is invalid (eg, set to 0) to indicate that the current kernel write data 312 has been read by the debugger 120 and is no longer valid.

[0042] According to one embodiment, when the kernel write flag 320 is included in the write register 310, the value in the write register 310 can be read once to obtain the value of the kernel write flag 320 and the kernel write data 312 at the same time, without having to read the value of the kernel write data 312 and the value of the kernel write flag 320 separately.

[0043] According to one embodiment, after the debugger 120 reads the current kernel write data 312, it is necessary to notify the processor core 200 so that the processor core 200 can perform subsequent processing, such as continuing to write new kernel write data 312. To this end, the control unit 330 can send a write jump request to the processor core 200 after the debugger 120 reads the current kernel write data 312. Figure 1 As shown, the processor core 200 includes a jump processing unit 220 to process jump requests from the debug unit 300. When the jump processing unit 220 receives a write jump request from the control unit 330, it indicates that the current kernel write data 312 has been read by the debugger 120. Therefore, the jump processing unit 220 can call a corresponding program to process the write jump request, for example, writing new kernel write data to the write register 310 again.

[0044] Alternatively, as Figure 1 As shown, debug unit 300 also includes a jump enable register 340. Jump enable register 340 includes a write enable bit 342. The write enable bit indicates whether a write jump request is generated. According to one embodiment, when the value of write enable bit 342 is 1, it indicates that a write jump request is generated, while when the value of write enable bit 342 is 0, it indicates that a write jump request is not generated. Control unit 330 determines whether to send a write jump request based on the value of write enable bit 342. When the value of write enable bit 342 indicates that a write jump request is generated (the value is 1), control unit 330 sends a write jump request to processor core 200 after debugger 120 reads current kernel write data 312. Correspondingly, when the value of write enable bit 342 indicates that a write jump request is not generated (the value is 0), control unit 330 does not send a write jump request after debugger 120 reads current kernel write data 312.

[0045] According to one embodiment of the present invention, Figure 1As shown, the debug unit 300 also includes a jump information maintenance unit 350. The jump information maintenance unit 350 can store a handler address and processor state information. Before sending a write jump request, the control unit 330 stores a write jump request handler address and processor state for processing the write jump request in the jump information maintenance unit 350. When processing the write jump request, the jump processing unit 220 can read the write jump request handler address and processor state stored in the jump information maintenance unit 350, set the processor state to the read processor state, and jump to the program address of the write jump request handler to execute the write jump request handler. Depending on the embodiment, the debugger 120 or the processor core 200 can pre-set the write jump request handler address and processor state in the debug unit 300 to flexibly control the processing of the write jump request. For example, the write jump request handler can include a process for instructing the processor core 200 to rewrite the core write data 312, thereby achieving continuous debug data output of the processor core 200.

[0046] like Figure 1 As shown, debug unit 300 includes a read register 360. Core read register 360 is, for example, a 32- or 33-bit register, in which core read data 362 written by debugger 120 can be stored. Core read data 362 is also read by processor core 200, i.e., read / write unit 210, to implement data transmission from debugger 120 to processor core 200.

[0047] The debug unit 300 also includes a core read flag 370. The core read flag 370 indicates the validity of the core read data 362 in the read register 370. The validity of the core read data 362 means that the data is written to the register 360 by the debugger 120 and has not been read by the processor core 200. If the processor core 200 has already read the core read data, the core read flag 370 indicates that the core read data 362 is invalid. According to one embodiment of the present invention, a value of 1 for the core read flag 370 indicates that the data is valid, and a value of 0 indicates that the data is invalid.

[0048] Optionally, the core read flag 370 may be included in the read register 360. According to one embodiment, the read register 360 is a 33-bit register, one bit of which is used as the core read flag 370 and the other 32 bits are used to store the core read data 362.

[0049] The core read flag 370 may also be independent of the read register 360 , for example, located in a register other than the read register 360 .

[0050] The advantage of including the core read flag 370 in the read register 360 is that the core read flag 370 and the core read data 362 can be obtained at once by reading the read register 360. However, when the core read flag 370 is stored independently of the read register 360, it is necessary to first read the core read flag, and then read the core read data 362 stored in the read register 360 based on the value of the core read flag, which increases the number of register reads.

[0051] Control unit 330 also controls access to read register 360 by processor core 200 and debugger 120, ie, writing and reading core read data 362. Control unit 330 controls access to read register 360 based on the value of core read flag 370, ie, the data validity indicated.

[0052] The debugger 120 writes the core read data 362 into the read register 360 via the control unit 330. According to one embodiment, when the value of the core read flag 370 indicates valid data, it means that the value currently in the core read register 360 has not been read by the processor core 200. Therefore, the control unit 330 prevents the debugger 120 from writing the core read data 362 into the read register 360. Conversely, when the value of the core read flag 370 indicates invalid data, it means that the value currently in the core read register 360 has been read by the processor core 200. Therefore, the control unit 330 allows the debugger 120 to write the core read data 312 into the read register 360. After writing the core read data 362, the control unit 330 sets the value of the core read flag 370 to indicate valid data, thereby preventing the debugger 120 from further writing the core read data 362.

[0053] According to one embodiment, the core read flag 370 is included in the read register 360. In this case, the core read flag 370 (the value of which is 1, indicating that the data is valid) and the core read data 362 can be written into the read register 360 at once, without having to write the core read data 362 and modify the value of the core read flag 370 separately.

[0054] Similarly, processor core 200 reads kernel read data 362 from debug unit 300 via read / write unit 210. Read / write unit 210 reads kernel read data 362 from read register 360 via control unit 330. When read / write unit 210 reads kernel read data 362, control unit 330 indicates the validity of the kernel read data 362 to read / write unit 210 based on the value of kernel read flag 370. According to one embodiment, control unit 330 may directly send the value of kernel read flag 370 to read / write unit 210 so that read / write unit 210 can perform subsequent processing based on the value. When the value of kernel read flag 370 indicates valid data, read / write unit 210 may use the read kernel read data 362 for subsequent processing. When the value of kernel read flag 370 indicates invalid data, read / write unit 210 has previously read kernel read data 362, and therefore read / write unit 210 should discard the kernel read data 362. Each time after the read / write unit 210 reads the kernel read data 362, the value of the kernel read flag 370 is set to indicate that the data is invalid (for example, set to 0) to indicate that the current kernel read data 362 has been read by the read / write unit 210 and is no longer valid.

[0055] According to one embodiment, when the core read flag 370 is included in the read register 360, the value in the read register 360 can be read once to obtain the value of the core read flag 370 and the core read data 362 at the same time, without having to read the value of the core read data 362 and the core read flag 370 separately.

[0056] According to one embodiment, after the debugger 120 writes the new kernel read data 362, it is necessary to notify the processor core 200 so that the processor core 200 can perform subsequent processing, such as reading the newly written kernel read data 362. To this end, the control unit 330 can send a read jump request to the processor core 200 after the debugger 120 writes the new kernel read data 362. When the jump processing unit 220 in the processor core 200 receives the read jump request from the control unit 330, it indicates that the debugger 120 has written the new kernel read data 362. Therefore, the jump processing unit 220 can call a corresponding program to process the read jump request, such as reading the newly written kernel read data from the read register 360.

[0057] Alternatively, as Figure 1As shown, the jump enable register 340 includes a read enable bit 344. The read enable bit indicates whether a read jump request is generated. According to one embodiment, when the value of the read enable bit 344 is 1, it indicates that a read jump request is generated, and when the value of the read enable bit 344 is 0, it indicates that a read jump request is not generated. The control unit 330 determines whether to send a read jump request based on the value of the read enable bit 344. When the value of the read enable bit 344 indicates that a read jump request is generated (the value is 1), the control unit 330 sends a read jump request to the processor core 200 after the debugger 120 writes the new core read data 362. Correspondingly, when the value of the read enable bit 344 indicates that a read jump request is not generated (the value is 0), the control unit 330 does not send a read jump request after the debugger 120 writes the new core read data 362.

[0058] According to one embodiment of the present invention, before sending a read jump request, the control unit 330 stores a read jump request handler address and processor status for processing the read jump request in the jump information maintenance unit 350. When processing the read jump request, the jump processing unit 220 can read the read jump request handler address and processor status stored in the jump information maintenance unit 350, set the processor status to the read processor status, and jump to the program address of the read jump request handler to execute the read jump request handler. Depending on the embodiment, the debugger 120 or the processor core 200 can pre-set the read jump request handler address and processor status in the debug unit 300 to flexibly control the processing of the read jump request. For example, the read jump request handler can include a process for instructing the processor core 200 to read the core read data 362, thereby enabling continuous debug data writing by the debugger 120.

[0059] The jump processing unit 220 processes the jump request from the debugging unit 300. The jump processing unit 220 does not distinguish between read jump requests and write jump requests. When receiving a jump request, the jump processing unit 220 stores the current address of the program currently being executed by the processor core 200 (for example, the value of the program counter PC), and at the same time stores the current processor state value. Subsequently, the jump processing unit 220 reads the jump request handler address and processor state stored by the control unit 330 before issuing the jump request from the jump information maintenance unit 350 via the control unit 330, sets the processor state to the read processor state, and jumps to the corresponding request handler starting position by setting the PC value to the read jump request handler address to start executing the request handler.

[0060] After the execution of the request processing program to which the jump is directed is completed, the jump processing unit 220 can read the current address and processor state of the program that was previously stored and was being executed by the processor core 200 before the jump request was processed, set the processor to the read processor state, and set the PC value to the read program address to continue executing the program that was being executed before the jump request was processed.

[0061] Optionally, the jump processing unit 220 is suitable for storing the current address and current processor state of the program currently being executed by the processor core 200 in the jump information maintenance unit 350 of the debugging unit 300. In this way, when the corresponding request processing program is executed, the address and processor state of the program to be continued can be obtained from the jump information maintenance unit 350, and the program can be continued.

[0062] According to one embodiment, a dedicated debug jump complete instruction is provided. Executing this instruction allows the control unit 330 to retrieve the address and processor status of the program to be continued from the jump information maintenance unit 350 and continue program execution. This debug jump complete instruction can be executed upon completion of the request processing program to resume execution of the previous program.

[0063] According to another embodiment, as described above, considering that the execution of a write jump request and a read jump request generally involves the processor core 200 (i.e., the read / write unit 210) performing a write operation on the write register 310 and / or a read operation on the read register 360 (resulting in a change in the value of the processor core read flag bit), the control unit 330 can monitor changes in the values ​​of the various registers (310 and 360) caused by the operations of the read / write unit 210. When these register values ​​change, the control unit 330 initiates a debug jump return operation to instruct the jump processing unit 220 to obtain the address of the program to be continued and the processor state from the jump information maintenance unit 350, set the processor state to the read current processor state, and jump to the address of the program to be continued to continue executing the program.

[0064] According to the above solution, when the debugger 120 writes data to be transmitted to the processor core into the read register 360 via the control unit 330, the control unit 330 can immediately generate a read debug jump request and send it to the processor core 200. The jump processing unit 220 in the processor core 200 interrupts the currently executing program and jumps to the program that handles the read jump request. In this program, the data is read from the read register 360 via the read / write unit 210, thereby completing the communication transmission from the debugger 120 to the processor core 200 with minimal delay.

[0065] Similarly, after the debugger 120 reads the data transmitted by the processor core 200 from the write register 310 via the control unit 330, the control unit 330 may immediately generate a write debug jump request and send it to the processor core 200. The jump processing unit 220 in the processor core 200 interrupts the currently executing program and jumps to the program that handles the write jump request. In this program, the read / write unit 210 continues to write data to the write register 310, thereby initiating the next communication transmission from the processor core 200 to the debugger 120 with minimal delay.

[0066] Figure 2 A flow chart 400 of sending debug data from a processor core to a debugger according to one embodiment of the present invention is shown. Figure 2 The debug data transfer process shown in Figure 1 The debugging system 100 is shown.

[0067] In step S410, the read / write unit 210 in the processor core 200 requests, through the control unit 330, that the processor core write data 312 be written to the write register 310. Subsequently, in step S415, the control unit 330 makes a determination based on the value of the core write flag 320. When the value of the core write flag 320 is 0, indicating that the core write data 312 is invalid, then in step S420, the control unit 330 allows the read / write unit 210 to write the processor core write data 312 and sets the value of the core write flag 320 to 1. When the value of the core write flag 320 is 1, the read / write unit 210 is prevented from writing data, so that the read / write unit 210 waits for the core write data 312 to be read by the debugger 120 before attempting to write again.

[0068] Subsequently, in step S430, the debugger 120 reads the processor core write data 312 and the value of the core write flag 320 in the write register 310 through the control unit 330, and sets the value of the core write flag 320 to 0. In step S435, a judgment is made based on the read value of the core write flag 320. If the value of the core write flag 320 is 0, then in step S438, the debugger 120 discards the read processor core write data. If the value of the core write flag 320 is 1, then in step S440, a judgment is made based on the value of the write enable bit 342 in the jump enable register 340. If the value of the write enable bit 342 is 0, indicating that a jump request is not generated, then in step S445, the control unit 330 does not generate a write jump request, and the debugger 120 uses the read processor core write data 312 for subsequent processing. If the value of the write enable bit is 1, then in step S450 , the control unit 330 stores the program address and processor status information of the write jump request processing program in the jump information maintenance unit 350 , and issues a write jump request to the processor core 200 .

[0069] In step S460, the jump processing unit 220 in the processor core 200 processes the write jump request, stores the address of the currently executing program and the current processor state in the jump information maintenance unit 350 through the control unit 330, reads the program address and processor state information of the program processing the write jump request from the jump information maintenance unit 350 through the control unit 330, sets the processor state to the read processor state, and sets the PC value to the read program address, so as to jump to the program processing the write jump request to start execution.

[0070] Then, in step S470, the program for processing the write jump request instructs the read / write unit 210 to write new data into the write register. This part of the processing is similar to the processing of steps S410 to S420 and will not be described in detail.

[0071] After the write jump request handler is executed, in step S480, the jump processing unit 220 reads the program address and processor status of the previously executed program from the jump information maintenance unit 350, sets the processor status to the read processor status, and sets the PC value to the read program address to continue the execution of the previous program.

[0072] pass Figure 2 The processing flow shown completes a data transmission from the processor core 200 to the debugger 120 and prepares the data to be read next time for the debugger 120 .

[0073] Figure 3 A flow chart 500 of sending debug data from a debugger to a processor core according to one embodiment of the present invention is shown. Figure 3 The debug data transfer process shown in Figure 1 The debugging system 100 is shown.

[0074] In step S510, the debugger 120 requests, through the control unit 330, that the processor core read data 362 be written to the read register 360. Subsequently, in step S515, the control unit 330 makes a determination based on the value of the core read flag 370. If the value of the core read flag 370 is 0, indicating that the core read data 362 is invalid, then in step S520, the control unit 330 allows the debugger 120 to write the processor core read data 362 and sets the value of the core read flag 370 to 1. If the value of the core read flag 370 is 1, the debugger 120 is prevented from writing data, so that the debugger 120 waits until the core read data 362 is read by the read / write unit 210 of the processor core 200 before attempting to write again.

[0075] Subsequently, in step S530, a determination is made based on the value of the read enable bit 344 in the jump enable register 340. If the value of the read enable bit 344 is 0, indicating that no read jump request is to be generated, then in step S535, the control unit 330 does not generate a read jump request, and the process ends. If the value of the read enable bit is 1, then in step S540, the control unit 330 stores the program address and processor status information of the program that processes the read jump request in the jump information maintenance unit 350, and issues a read jump request to the processor core 200.

[0076] In step S550, the jump processing unit 220 in the processor core 200 processes the read jump request, stores the address of the currently executing program and the current processor state in the jump information maintenance unit 350 through the control unit 330, reads the program address and processor state information of the program processing the read jump request from the jump information maintenance unit 350 through the control unit 330, sets the processor state to the read processor state, and sets the PC value to the read program address, so as to jump to the program processing the read jump request to start execution.

[0077] Subsequently, in step S560, the read jump request handler instructs the read / write unit 210 to read the processor core read data 362 and the value of the core read flag 370 from the read register 360 through the control unit 330, and to set the value of the core read flag 370 to 0. In step S565, a judgment is made based on the value of the read core read flag 370. If the value of the core read flag 370 is 0, then in step S568, the read / write unit 210 discards the read processor core read data. If the value of the core read flag 370 is 1, then in step S570, the read / write unit 210 uses the read processor core read data for subsequent processing.

[0078] After the read jump request handler is executed, in step S580, the jump processing unit 220 reads the program address and processor status of the previously executed program from the jump information maintenance unit 350, sets the processor status to the read processor status, and sets the PC value to the read program address to continue the execution of the previous program.

[0079] pass Figure 3 The processing flow shown completes a debugging data transmission from the debugger 120 to the processor core 200.

[0080] The debug jump solution provided by this solution does not require the use of interrupts to inform the processor core to perform data transmission, and does not require the use of interrupt vector number resources. Therefore, there is no problem of slow response caused by interrupt priority determination.

[0081] It should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed method should not be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the claims below, inventive aspects lie in less than all the features of the individual embodiments disclosed above. Accordingly, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of the invention.

[0082] Those skilled in the art will appreciate that the modules, units, or components of the devices in the examples disclosed herein may be arranged in the device described in the embodiment, or alternatively may be located in one or more devices different from the devices in the examples. The modules in the foregoing examples may be combined into one module or further divided into multiple submodules.

[0083] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and in addition may be divided into multiple submodules or subunits or subcomponents. All features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed herein may be combined in any combination, except that at least some of such features and / or processes or units are mutually exclusive. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature providing the same, equivalent or similar purpose.

[0084] Furthermore, those skilled in the art will appreciate that although some embodiments described herein include certain features included in other embodiments but not other features, combinations of features from different embodiments are intended to be within the scope of the present invention and to form different embodiments. For example, in the claims below, any of the claimed embodiments may be used in any combination.

[0085] In addition, some of the embodiments are described herein as methods or combinations of method elements that can be implemented by a processor of a computer system or by other devices that perform the functions described. Thus, a processor having the necessary instructions for implementing the method or method element forms a device for implementing the method or method element. Furthermore, the elements described herein of the device embodiments are examples of devices for implementing the functions performed by the elements for the purpose of implementing the invention.

[0086] As used herein, unless otherwise specified, the use of ordinal numbers "first," "second," "third," etc. to describe common objects merely indicates that different instances of similar objects are involved and are not intended to imply that the objects so described must have a given order in time, space, ranking, or in any other manner.

[0087] Although the present invention has been described with respect to a limited number of embodiments, it will be apparent to those skilled in the art, having benefit of the foregoing description, that other embodiments are contemplated within the scope of the invention thus described. Furthermore, it should be noted that the language used in this specification has been selected primarily for readability and didactic purposes, rather than for the purpose of explaining or limiting the subject matter of the present invention. Consequently, many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the appended claims. The disclosure of the present invention is intended to be illustrative rather than restrictive of the scope of the invention, which is defined by the appended claims.

Claims

1. A debugging unit, comprising: a write register adapted to store kernel write data written by a processor kernel, the kernel write data being read by a debugger coupled to the processor; A kernel write flag, adapted to indicate the validity of the kernel write data; as well as a control unit, adapted to control the access of the processor core and the debugger to the write register according to the data validity indicated by the write flag, and indicate the data validity of the read core write data to the debugger according to the core write flag when the debugger reads the core write data from the write register; as well as A jump enable register, comprising a write enable bit, wherein the write enable bit indicates whether a write jump request is generated; wherein the control unit is adapted to send a write jump request to the processor core after the debugger reads the core write data when the write enable bit indicates the generation of a write jump request; A jump information maintenance unit, adapted to store a processing program address and processor status information; The control unit is suitable for storing a first handler address and a first processor state suitable for processing the write jump request in the jump information maintenance unit before sending the write jump request to the processor core, so that when the processor core processes the write jump request, the processor state is set to the first processor state and jumps to the first handler address to execute the program.

2. The debugging unit according to claim 1, wherein the control unit is adapted to: When the kernel write flag indicates that the data is invalid, allowing the processor kernel to write the kernel write data to the write register, and when the kernel write flag indicates that the data is valid, preventing the processor kernel from writing the kernel write data to the write register; After the processor core writes the core write data, the core write flag is set to indicate that the data is valid.

3. The debugging unit according to claim 1 or 2, wherein the control unit is adapted to: After the debugger reads the kernel write data, the kernel write flag is set to indicate that the data is invalid.

4. The debugging unit according to claim 1 or 2, further comprising: a read register adapted to store kernel read data written by the debugger, the kernel read data being read by the processor core; A kernel read flag, adapted to indicate data validity of the kernel read data; as well as A control unit is adapted to control the access of the processor core and the debugger to the read register according to the data validity indicated by the core read identification bit.

5. The debugging unit according to claim 4, wherein the control unit is adapted to: When the kernel read flag indicates that the data is invalid, allowing the debugger to write the kernel read data to the read register, and when the kernel read flag indicates that the data is valid, preventing the debugger from writing the kernel read data to the read register; and After the debugger writes the kernel read data, the kernel read flag is set to indicate that the data is valid.

6. The debugging unit according to claim 4, wherein the control unit is adapted to: When the processor core reads the core read data from the read register, indicating data validity of the read core read data to the processor core according to the core read identification bit; and After the processor core reads the core read data, the core read flag is set to indicate that the data is invalid.

7. The debug unit of claim 4, wherein the jump enable register comprises a read enable bit, wherein the read enable bit indicates whether a read jump request is generated; and The control unit is adapted to send a read jump request to the processor core when the read enable bit indicates the generation of a read jump request and after the debugger writes the core read data.

8. A debugging unit as described in claim 7, wherein the control unit is suitable for storing a second handler address and a second processor state suitable for processing the read jump request in the jump information maintenance unit before sending the read jump request to the processor core, so that when the processor core processes the read jump request, the processor state is set to the second processor state and jumps to the second handler address to execute the program.

9. The debug unit of claim 1, wherein the first handler address comprises an entry address of a first handler, the first handler comprising a program instructing the processor core to write processor write data to the debug unit.

10. The debug unit according to claim 8, wherein the second processing program address comprises an entry address of a second processing program, the second processing program comprising a program instructing the processor core to read the processor read data from the debug unit.

11. The debug unit of claim 4, wherein the core write flag is contained in the write register, and the core read flag is contained in the read register.

12. A processor, comprising: A debugging unit as claimed in any one of claims 1 to 11; as well as Processor core, including read / write unit and jump processing unit, wherein the read / write unit is adapted to write kernel write data to the write register of the debug unit, and read kernel read data from the read register of the debug unit, and The jump processing unit is adapted to process a jump request issued by the debugging unit.

13. A processor as described in claim 12, wherein the jump processing unit is suitable for storing the current handler address and the current processor state when processing the jump request, setting the processor state to the processor state stored in the jump information maintenance unit of the debug unit, and jumping to the address of the jump handler stored in the jump information maintenance unit of the debug unit for execution.

14. The processor of claim 13, wherein the jump processing unit is adapted to store the current handler address and the current processor state in the jump information maintenance unit of the debug unit.

15. The processor according to claim 13 or 14, wherein the jump processing unit is adapted to set the processor state to the stored current processor state and jump to the stored current handler address to continue executing the current handler when the jump handler is executed.

16. The processor according to claim 15, wherein the jump processing unit is adapted to execute a debug jump completion instruction when the jump processing program is executed, so as to set the processor state to the stored current processor state and jump to the stored current processing program address to continue executing the current processing program.

17. The processor of claim 15, wherein the jump processing program comprises a program for instructing the processor core to write processor write data to the debug unit and / or a program for instructing the processor core to read processor read data from the debug unit, and the control unit of the debug unit is adapted to, after detecting the read / write operation of the jump processing program on the debug unit, instruct the jump processing unit to set the processor state to the stored current processor state and jump to the stored current processing program address to continue executing the current processing program.

18. A debugger comprising: a debug host adapted to generate debug commands to be sent to a processor as claimed in any one of claims 12 to 17, and to present debug data sent by the processor in response to the debug commands; as well as A protocol converter, adapted to convert the debugging command, send the converted debugging command to the processor, and receive debugging data returned from the processor; The protocol converter is adapted to write core read data related to the debug command into a read register of a debug unit in the processor, and read core write data from a write register of the debug unit as the debug data.

19. A debugging system, comprising: A processor as claimed in any one of claims 12 to 17; as well as The debugger of claim 18.

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