Display device and its driving method

Abstract

The present disclosure relates to a display device and a driving method thereof. The display device includes: a pixel including a first pixel transistor, a gate electrode of the first pixel transistor being connected to a first node, a back gate electrode of the first pixel transistor being connected to a back gate line, a first electrode of the first pixel transistor being connected to a second node, and a second electrode of the first pixel transistor being connected to a third node; a back gate voltage determiner configured to converge a variable back gate voltage to a first level when the display device displays a moving image, and to converge the variable back gate voltage to a second level when the display device displays a still image; and a back gate stage configured to apply the variable back gate voltage to the back gate line.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10-2019-0033893, filed with the Korean Intellectual Property Office on Mar. 25, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present disclosure relate to a display device and a driving method thereof. Background Art

[0004] With the development of information technology, the importance of a display device as a connection medium between a user and information has become significant. Accordingly, display devices such as liquid crystal display devices, organic light emitting diode display devices, and plasma display devices have been increasingly used.

[0005] A pixel may include a light emitting diode and a driving transistor for controlling a driving current supplied to the light emitting diode. The hysteresis characteristic of the driving transistor may cause a step efficiency problem and a transient afterimage problem. Summary of the Invention

[0006] Embodiments of the present disclosure provide a display device and a driving method thereof, which can alleviate a step efficiency problem and a transient afterimage by using a variable back gate voltage when displaying a movie image / moving image and a still image.

[0007] A display device according to an embodiment of the present disclosure includes: a pixel including a first pixel transistor, a gate electrode of the first pixel transistor being connected to a first node, a back gate electrode of the first pixel transistor being connected to a back gate line, a first electrode of the first pixel transistor being connected to a second node, and a second electrode of the first pixel transistor being connected to a third node; a back gate voltage determiner configured to converge a variable back gate voltage to a first level when the display device displays a moving image, and to converge the variable back gate voltage to a second level when the display device displays a still image; and a back gate stage configured to apply the variable back gate voltage to the back gate line.

[0008] The display device may further include a scan stage configured to apply a scan signal to a scan line, wherein the pixel further includes a second pixel transistor, a gate electrode of the second pixel transistor being connected to the scan line, a first electrode of the second pixel transistor being connected to a data line, and a second electrode of the second pixel transistor being connected to the second node, and wherein the back gate stage is configured to apply the variable back gate voltage to the back gate line while the scan stage applies the scan signal of a cut-off level to the scan line.

[0009] The back gate stage can be configured to apply a fixed back gate voltage of a third level between the first level and the second level to the back gate line while the scan stage applies the scan signal of the conductive level to the scan line.

[0010] The scan stage can include: a first scan transistor configured to apply the scan signal of the cut-off level to the scan line when a first control signal of the conductive level is applied to the gate electrode of the first scan transistor; and a second scan transistor configured to apply the scan signal of the conductive level to the scan line when a second control signal of the conductive level is applied to the gate electrode of the second scan transistor, and wherein the back gate stage is configured to apply the variable back gate voltage or the fixed back gate voltage to the back gate line according to the first control signal or the second control signal.

[0011] The back gate stage can include: a first back gate transistor configured to apply the variable back gate voltage to the back gate line when a first control signal of the conductive level is applied to the gate electrode of the first back gate transistor; and a second back gate transistor configured to apply the fixed back gate voltage to the back gate line when a second control signal of the conductive level is applied to the gate electrode of the second back gate transistor.

[0012] The pixel can further include: a third pixel transistor, the gate electrode of the third pixel transistor being connected to the scan line, the first electrode of the third pixel transistor being connected to the first node, and the second electrode of the third pixel transistor being connected to the third node.

[0013] The back gate voltage determiner can be configured to change the variable back gate voltage from the first level to the second level during a first transition period when the display device displays the still image after displaying the moving image, wherein the back gate voltage determiner is configured to change the variable back gate voltage from the second level to the first level during a second transition period when the display device displays the moving image after displaying the still image, and wherein the first transition period is longer than the second transition period.

[0014] A driving method of a display device according to an embodiment of the present disclosure is a driving method of a display device including pixels, where the pixels include: a first pixel transistor, a gate electrode of the first pixel transistor is connected to a first node, a back gate electrode of the first pixel transistor is connected to a back gate line, a first electrode of the first pixel transistor is connected to a second node, and a second electrode of the first pixel transistor is connected to a third node; and a second pixel transistor, a gate electrode of the second pixel transistor is connected to a scan line, a first electrode of the second pixel transistor is connected to a data line, a second electrode of the second pixel transistor is connected to the second node, and the driving method includes: applying a variable back gate voltage to the back gate line while applying a scan signal of a cut-off level to the scan line; and applying a fixed back gate voltage to the back gate line while applying a scan signal of a conductive level to the scan line.

[0015] The driving method may further include: when the display device displays a moving image, converging the variable back gate voltage to a first level; and when the display device displays a still image, converging the variable back gate voltage to a second level.

[0016] The fixed back gate voltage may have a third level between the first level and the second level.

[0017] The driving method may further include: when the display device displays the still image after displaying the moving image, changing the variable back gate voltage from the first level to the second level during a first transition period; and when the display device displays the moving image after displaying the still image, changing the variable back gate voltage from the second level to the first level during a second transition period, where the first transition period is longer than the second transition period.

[0018] A driving method of a display device according to an embodiment of the present disclosure includes: applying a variable back gate voltage to a back gate electrode of a first pixel transistor of a pixel; when the display device displays a moving image, converging the variable back gate voltage to a first level; and when the display device displays a still image, converging the variable back gate voltage to a second level.

[0019] The driving method may further include: when the display device displays the still image after displaying the moving image, changing the variable back gate voltage from the first level to the second level during a first transition period; and when the display device displays the moving image after displaying the still image, changing the variable back gate voltage from the second level to the first level during a second transition period, where the first transition period is longer than the second transition period.

[0020] The driving method may further include applying a fixed back-gate voltage to the back-gate electrode, where the fixed back-gate voltage has a third level between the first level and the second level.

[0021] The first pixel transistor may include a gate electrode connected to a first node, a back-gate electrode connected to a back-gate line, a first electrode connected to a second node, and a second electrode connected to a third node, where the pixel further includes a second pixel transistor, a gate electrode of the second pixel transistor is connected to a scan line, a first electrode of the second pixel transistor is connected to a data line, and a second electrode of the second pixel transistor is connected to the second node, where the variable back-gate voltage is applied to the back-gate line while a scan signal of a cut-off level is applied to the scan line, and where the fixed back-gate voltage is applied to the back-gate line while a scan signal of a conductive level is applied to the scan line.

[0022] A display device according to an embodiment of the present disclosure may alleviate a step efficiency problem and a transient afterimage by using a variable back-gate voltage when displaying a moving image and a still image. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a diagram for showing a display device according to an embodiment of the present disclosure.

[0024] Figure 2 is a diagram for showing a scan driver according to an embodiment of the present disclosure.

[0025] Figure 3 is a diagram for showing a scan stage and a back-gate stage according to an embodiment of the present disclosure.

[0026] Figure 4 is a diagram for showing a pixel according to an embodiment of the present disclosure.

[0027] Figure 5 is a diagram for showing a driving method of a pixel according to an embodiment of the present disclosure.

[0028] Figure 6 is a diagram for showing a change of a variable back-gate voltage according to an embodiment of the present disclosure when a still image is displayed after a moving image is displayed.

[0029] Figure 7 is a diagram for showing alleviating a transient afterimage according to a magnitude of a variable back-gate voltage.

[0030] Figure 8 is a diagram for showing a change of a variable back-gate voltage according to an embodiment of the present disclosure when a moving image is displayed after a still image is displayed.

[0031] Figure 9 and Figure 10 is a diagram for showing alleviating the step efficiency problem according to the magnitude of a variable back gate voltage. Detailed implementation manners

[0032] The features of the inventive concept and the method of implementing the inventive concept can be more easily understood by referring to the detailed descriptions of the embodiments and the accompanying drawings. Hereinafter, the embodiments will be described in more detail with reference to the drawings. However, the described embodiments can be embodied in various different forms and should not be construed as being limited to the embodiments shown herein. Instead, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects and features of the inventive concept to those skilled in the art. Therefore, processes, elements, and techniques that are not necessary for those of ordinary skill in the art to fully understand the aspects and features of the inventive concept may not be described.

[0033] Unless otherwise specified, throughout the drawings and the written description, the same reference numerals denote the same elements, and thus, their descriptions will not be repeated. In addition, parts that are not relevant to the description of the embodiments may not be shown to make the description clear. In the drawings, the relative dimensions of elements, layers, and regions may be exaggerated for clarity.

[0034] In this document, various embodiments are described with reference to cross-sectional views that are schematic diagrams of embodiments and / or intermediate structures. As such, variations in the shape of the illustrated are anticipated, for example, due to manufacturing techniques and / or tolerances. In addition, for the purpose of describing embodiments according to the concepts of the present disclosure, the specific structures or functionalities disclosed herein are illustrative only. Therefore, the embodiments disclosed herein should not be construed as being limited to the specifically shown shapes of regions, but will include, for example, shape deviations caused by manufacturing. For example, an implanted region shown as rectangular will generally have rounded or curved features at its edges and / or a gradient of implant concentration, rather than a binary change from the implanted region to the non-implanted region. Similarly, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implantation occurs. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device, nor are they intended to be limiting. Additionally, as those skilled in the art will recognize, the described embodiments can be modified in various different ways without departing from the spirit and scope of the present disclosure.

[0035] In the detailed description, for purposes of illustration, numerous specific details are set forth to provide a thorough understanding of the various embodiments. However, it is apparent that the various embodiments can be practiced without these specific details or by one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various embodiments.

[0036] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer, or part described below may be referred to as the second element, component, region, layer, or part.

[0037] It will be understood that when an element, layer, region, or component is referred to as being "on", "connected to", or "coupled to" another element, layer, region, or component, the element, layer, region, or component can be directly on, directly connected to, or directly coupled to the other element, layer, region, or component, or there may be one or more intermediate elements, layers, regions, or components. However, "directly connected / coupled" means that one component is directly connected or directly coupled to another component without an intermediate component. At the same time, other expressions describing the relationship between components such as "between", "directly between", or "adjacent to" and "directly adjacent to" can be similarly interpreted. Additionally, it will also be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or there may also be one or more intermediate elements or layers.

[0038] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a" and "an" are also intended to include the plural forms. It will be further understood that when used in this specification, the terms "comprises", "comprising", "includes", and "having" specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0039] As used herein, the terms "substantially", "about", "approximate" and similar terms are used as approximating terms and not as terms of degree, and are intended to account for the inherent deviations of measured or calculated values recognized by a person of ordinary skill in the art. Given the measurements under discussion and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), as used herein, the term "about" or "approximate" includes the stated value and represents within an acceptable deviation of the particular value determined by a person of ordinary skill in the art. For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5% of the stated value. Additionally, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure".

[0040] When an embodiment can be implemented differently, a particular process order can be performed in an order different from that described. For example, two consecutively described processes can be performed substantially simultaneously, or in an order opposite to that described.

[0041] An electronic or electrical device and / or any other relevant device or component according to an embodiment of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., an application specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, the various components of these devices can be formed on one integrated circuit (IC) chip or on separate IC chips. Additionally, the various components of these devices can be implemented on a flexible printed circuit film, tape carrier package (TCP), printed circuit board (PCB), or formed on a substrate. Further, the various components of these devices can be processes or threads running on one or more processors in one or more computing devices that execute computer program instructions and interact with other system components for performing the various functions described herein. The computer program instructions are stored in a memory, which can be implemented in a computing device using a standard storage device such as, by way of example, random access memory (RAM). The computer program instructions can also be stored in other non-transitory computer-readable media, such as, by way of example, a CD-ROM or a flash drive. Moreover, those skilled in the art will recognize that, without departing from the spirit and scope of the embodiments of the present disclosure, the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed over one or more other computing devices.

[0042] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive concept belongs. It will also be understood that terms, such as those defined in a general dictionary, should be interpreted as having a meaning that is consistent with their meaning in the relevant art and / or the context of this specification, and should not be interpreted in an idealized or overly formal sense, unless expressly so defined herein.

[0043] Figure 1 is a diagram for showing a display device according to an embodiment of the present disclosure.

[0044] Referring Figure 1 , a display device 10 according to an embodiment of the present disclosure may include: a timing controller 11, a data driver 12, a scan driver 13, a transmission driver 14, a display unit 15, and a backgate voltage determiner 16.

[0045] The timing controller 11 may receive a grayscale value and a control signal from an external processor. The timing controller 11 may render the grayscale value corresponding to the specification of the display device 10. For example, the external processor may provide a red grayscale value, a green grayscale value, and a blue grayscale value for each unit dot. However, for example, when the display unit 15 has a Pentile structure, adjacent unit dots share pixels, such that each grayscale value may not correspond to only a single pixel. In such a case, rendering the grayscale value is useful. When each grayscale value corresponds to one pixel, rendering the grayscale value by the timing controller 11 may be unnecessary. The rendered or unrendered grayscale value may be provided to the data driver 12. In addition, the timing controller 11 may provide control signals suitable for each specification of the data driver 12, the scan driver 13, the transmission driver 14, and the backgate voltage determiner 16 to display these grayscale values.

[0046] When the display device 10 displays a moving image, the backgate voltage determiner 16 may converge (e.g., gradually adjust) a variable backgate voltage VB to a first level, and when the display device 10 displays a still image, the backgate voltage determiner 16 may converge the variable backgate voltage VB to a second level. The first level and the second level may be different levels. Converging a voltage level to a given level (e.g., a specific level) in an embodiment of the present disclosure may mean that the voltage level does not immediately change to the given level, but gradually changes to the given level over a period of time (e.g., a certain time period). At this time, the period of time may be several image frame periods or even dozens of image frame periods.

[0047] The back-gate voltage determiner 16 can receive image information MI from the timing controller 11. The image information MI can indicate whether the displayed image is a still image or a moving image. The timing controller 11 can generate the image information MI based on information of multiple image frames. For example, when the gray-level value for each pixel in multiple image frames changes by more than a threshold, the timing controller 11 can generate the image information MI indicating that the displayed image is a moving image. On the other hand, when the gray-level value for each pixel in multiple image frames remains below the threshold, the timing controller 11 can generate the image information MI indicating that the displayed image is a still image. In another embodiment, an external processor can provide information about whether the displayed image is a moving image or a still image to the timing controller 11.

[0048] The back-gate voltage determiner 16 can provide a fixed back-gate voltage Vref. In another embodiment, the fixed back-gate voltage Vref can be provided from a separate voltage source.

[0049] The back-gate voltage determiner 16 can be a hardware (e.g., an integrated circuit) separate from the timing controller 11. On the other hand, the back-gate voltage determiner 16 can be a hardware integrated with the timing controller 11. Additionally, the back-gate voltage determiner 16 can be programmed into the timing controller 11 to be implemented as software.

[0050] The scan driver 13 can receive a clock signal CLKs, a scan start signal STV, etc. from the timing controller 11 to generate scan signals provided to scan lines S1, S2, and Sm. For example, the scan driver 13 can sequentially provide scan signals having pulses with a conductive level to the scan lines S1, S2, and Sm. For example, the scan stage of the scan driver 13 can include a shift register and can generate scan signals under the control of the clock signal CLKs in a manner including sequentially transmitting the scan start signal STV, which is a pulse with a conductive level, to the next scan stage. The "m" in "Sm" can be an integer greater than zero.

[0051] The scan driver 13 can also receive a high voltage VGH and a low voltage VGL from the timing controller 11. In another embodiment, the scan driver 13 can receive the high voltage VGH and the low voltage VGL from another voltage source.

[0052] According to an embodiment, the scan driver 13 can include a back-gate voltage supplier 132. The back-gate voltage supplier 132 can include back-gate stages. The back-gate stages can be respectively connected to corresponding back-gate lines B1, B2, and Bm. Each back-gate stage can apply a variable back-gate voltage or a fixed back-gate voltage to the back-gate line.

[0053] The data driver 12 can generate data voltages to be provided to data lines D1, D2, D3, and Dn using the received gray-scale values and control signals. For example, the data driver 12 can sample the gray-scale values using a clock signal and can apply data voltages (e.g., one or more analog voltages) corresponding to the gray-scale values (e.g., digital values) to the data lines D1, D2, D3, and Dn for each scan line. "n" in "Dn" can be an integer greater than zero.

[0054] The emission driver 14 can receive a clock signal, an emission stop signal, etc. from the timing controller 11 to generate emission signals provided to emission lines E1, E2, and Eo. For example, the emission driver 14 can sequentially provide emission signals of pulses having a cut-off level to the emission lines E1, E2, and Eo. For example, the light-emitting stage of the emission driver 14 can include a shift register and can generate emission signals under the control of the clock signal to sequentially transmit the emission stop signal of pulses as the cut-off level to the next light-emitting stage. "o" in "Eo" can be an integer greater than zero.

[0055] The display unit 15 includes pixels. Each pixel (e.g., pixel PXij) can be connected to a corresponding data line, a corresponding scan line, a corresponding emission line, and a corresponding back-gate line. "i" and "j" in "PXij" can be integers greater than zero. For an example of the configuration and driving method of the pixel PXij, see Figure 4 and Figure 5 .

[0056] Figure 2 is a diagram for showing a scan driver according to an embodiment of the present disclosure.

[0057] Refer to Figure 2 , the scan driver 13 according to an embodiment of the present disclosure can include a scan signal supplier 131 and a back-gate voltage supplier 132.

[0058] The scan signal supplier 131 can include scan stages SST1, SST2, and SST3. Each of the scan stages SST1, SST2, and SST3 can include a substantially equivalent circuit structure.

[0059] Each of the scan stages SST1, SST2, and SST3 can receive a clock signal CLKs, a high voltage VDD, and a low voltage VSS. In addition, the scan stages SST2 and SST3 except for the first scan stage SST1 can receive corresponding carry signals CR1 and CR2 from their respective previous scan stages. Since the first scan stage SST1 does not have a previous scan stage, the first scan stage SST1 can receive a scan start signal STV (e.g., instead of the carry signal) from the timing controller 11.

[0060] Each of the scan stages SST1, SST2, and SST3 can supply scan signals to the scan lines S1, S2, and S3 based on the clock signals CLKs and the carry signals CR1, CR2, and CR3 / scan start signal STV. Thus, the scan stages SST1, SST2, and SST3 can sequentially supply scan signals of a conductive level.

[0061] The conductive level can refer to such a voltage level at which a transistor receiving a corresponding signal at its gate electrode can conduct. For example, when the corresponding transistor is an N-type transistor (e.g., NMOS), the conductive level can be a logic high level. When the corresponding transistor is a P-type transistor (e.g., PMOS), the conductive level can be a logic low level. Hereinafter, it is assumed that the transistor is configured as a P-type transistor, and the conductive level can be a logic low level.

[0062] The back gate voltage supplier 132 can include back gate stages BST1, BST2, and BST3. Each of the back gate stages BST1, BST2, and BST3 can include a circuit structure substantially equivalent to that of the other back gate stages.

[0063] Each of the back gate stages BST1, BST2, and BST3 can receive a variable back gate voltage VB and a fixed back gate voltage Vref. The variable back gate voltage VB can be a voltage whose level can change according to the type of the displayed image (e.g., according to whether the displayed image is a moving image or a still image). The fixed back gate voltage Vref can be a voltage whose level can be fixed regardless of the type of the displayed image.

[0064] In addition, the back gate stages BST1, BST2, and BST3 can receive a first control signal C11, C21, and C31 and a second control signal C12, C22, and C32 from the corresponding scan stages SST1, SST2, and SST3.

[0065] The back gate stages BST1, BST2, and BST3 can supply one of the variable back gate voltage VB and the fixed back gate voltage Vref to the back gate lines B1, B2, and B3 according to the levels of the first control signals C11, C21, and C31 and the levels of the second control signals C12, C22, and C32.

[0066] Figure 3 is a diagram for showing a scan stage and a back gate stage according to an embodiment of the present disclosure.

[0067] Reference Figure 3 , shows the i-th scan stage SSTi and the i-th back gate stage BSTi. Since the other scan stages and back gate stages can respectively have substantially the same circuit structure as theirs, the repeated description will be omitted.

[0068] The scan stage SSTi may include a driver SDi and a buffer SBi.

[0069] The driver SDi may be controlled by a previous carry signal CR(i - 1) and a clock signal CLKs to generate a first control signal Ci1 and a second control signal Ci2. According to an embodiment, the driver SDi may generate a carry signal CRi, but according to another embodiment, the driver SDi may use the scan signal of the scan line Si as the carry signal CRi. Since the driver SDi may use the circuit structure of a conventional scan stage, repeated descriptions will be omitted.

[0070] The buffer SBi may include a first scan transistor ST1 and a second scan transistor ST2.

[0071] The gate electrode of the first scan transistor ST1 may be connected to the driver SDi. The first electrode of the first scan transistor ST1 may receive a high voltage VGH or a first clock signal CLK1, and the second electrode of the first scan transistor ST1 may be connected to the scan line Si. When a first control signal Ci1 with a conductive level (e.g., low level) is applied to the gate electrode of the first scan transistor ST1, the first scan transistor ST1 may apply a scan signal with a cut-off level (e.g., high level) to the scan line Si. The scan signal with the cut-off level may correspond to the high voltage VGH or the first clock signal CLK1. The first scan transistor ST1 may be referred to as a pull-up transistor.

[0072] The gate electrode of the second scan transistor ST2 may be connected to the driver SDi. The first electrode of the second scan transistor ST2 may be connected to the scan line Si, and the second electrode of the second scan transistor ST2 may receive a low voltage VGL or a second clock signal CLK2. When a second control signal Ci2 with a conductive level (e.g., low level) is applied to the gate electrode of the second scan transistor ST2, the second scan transistor ST2 may apply a scan signal with a conductive level (e.g., low level) to the scan line Si. The scan signal with the conductive level may correspond to the low voltage VGL or the second clock signal CLK2. The second scan transistor ST2 may be referred to as a pull-down transistor.

[0073] The clock signal CLKs may include a first clock signal CLK1 and a second clock signal CLK2.

[0074] The buffer SBi may use the circuit structure of a conventional scan stage. However, even if other control signals may be provided in the back-gate stage BSTi, the scan transistors ST1 and ST2 are still shown to illustrate Figure 3 an example electrical connection between the scan stage SSTi and the back-gate stage BSTi therein.

[0075] The back-gate stage BSTi may include a first back-gate transistor BT1 and a second back-gate transistor BT2.

[0076] The gate electrode of the first back-gate transistor BT1 may be connected to the gate electrode of the first scan transistor ST1. The first electrode of the first back-gate transistor BT1 may receive a variable back-gate voltage VB, and the second electrode of the first back-gate transistor BT1 may be connected to the back-gate line Bi. When a first control signal Ci1 at a conductive level is applied to the gate electrode of the first back-gate transistor BT1, the first back-gate transistor BT1 may apply the variable back-gate voltage VB to the back-gate line Bi.

[0077] The gate electrode of the second back-gate transistor BT2 may be connected to the gate electrode of the second scan transistor ST2. The first electrode of the second back-gate transistor BT2 may be connected to the back-gate line Bi, and the second electrode of the second back-gate transistor BT2 may receive a fixed back-gate voltage Vref. When a second control signal Ci2 at a conductive level is applied to the gate electrode of the second back-gate transistor BT2, the second back-gate transistor BT2 may apply the fixed back-gate voltage Vref to the back-gate line Bi.

[0078] According to an embodiment, the back-gate stage BSTi may apply the variable back-gate voltage VB to the back-gate line Bi while the scan stage SSTi applies a scan signal at a cut-off level to the scan line Si. Additionally, the back-gate stage BSTi may apply the fixed back-gate voltage Vref to the back-gate line Bi while the scan stage SSTi applies a scan signal at a conductive level to the scan line Si.

[0079] The fixed back-gate voltage Vref may have a third level, which is a level between the first level and the second level. For example, the fixed back-gate voltage Vref may be a ground voltage. The second level may be a positive voltage level. The first level may be a negative voltage level. In another embodiment, when a transistor having a back-gate electrode is configured as an N-type transistor, the first level may be a positive voltage level, and the second level may be a negative voltage level.

[0080] Figure 4 is a diagram for showing a pixel according to an embodiment of the present disclosure.

[0081] Reference Figure 4 , a pixel PXij according to an embodiment of the present disclosure may include pixel transistors M1, M2, M3, M4, M5, M6, and M7, a storage capacitor Cst, and a light-emitting diode LD.

[0082] The first pixel transistor M1 may have a gate electrode connected to a first node N1, a back gate electrode connected to a back gate line Bi, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The back gate electrode may be referred to as a bottom gate electrode, and the gate electrode may be referred to as a top gate electrode. The first pixel transistor M1 may be referred to as a driving transistor. The first pixel transistor M1 determines the amount of driving current flowing between a first power supply line ELVDD and a second power supply line ELVSS based on the potential difference between the gate electrode and the source electrode (e.g., the first electrode).

[0083] The second pixel transistor M2 may have a gate electrode connected to a scan line Si, a first electrode connected to a data line Dj, and a second electrode connected to the second node N2. The second pixel transistor M2 may be referred to as a switching transistor. When a scan signal of a conductive level is applied to the scan line Si, the second pixel transistor M2 pulls and inputs the data voltage of the data line Dj into the pixel PXij.

[0084] The third pixel transistor M3 has a gate electrode connected to the scan line Si, a first electrode connected to the first node N1, and a second electrode connected to the third node N3. When a scan signal of a conductive level is applied to the scan line Si, the third pixel transistor M3 connects the first pixel transistor M1 in the form of a diode.

[0085] The fourth pixel transistor M4 has a gate electrode connected to a previous scan line S(i - 1), a first electrode connected to the first node N1, and a second electrode connected to an initialization voltage line VINT. In another embodiment, the gate electrode of the fourth pixel transistor M4 may be connected to another scan line (e.g., one or more of the (i - 2)-th scan line and the (i - 3)-th scan line, etc.). When a scan signal of a conductive level is applied to the previous scan line S(i - 1), the fourth pixel transistor M4 transfers an initialization voltage to the gate electrode of the first pixel transistor M1, thereby initializing the charge amount of the gate electrode of the first pixel transistor M1.

[0086] The fifth pixel transistor M5 has a gate electrode connected to an emission line Ei, a first electrode connected to the first power supply line ELVDD, and a second electrode connected to the second node N2. The sixth pixel transistor M6 has a gate electrode connected to the emission line Ei, a first electrode connected to the third node N3, and a second electrode connected to the anode of a light-emitting diode LD. The fifth pixel transistor M5 and the sixth pixel transistor M6 may be referred to as light-emitting transistors. When an emission signal of a conductive level is applied to the fifth pixel transistor M5 and the sixth pixel transistor M6, the fifth pixel transistor M5 and the sixth pixel transistor M6 form a path for driving current between the first power supply line ELVDD and the second power supply line ELVSS to turn on the light-emitting diode LD.

[0087] The seventh pixel transistor M7 has a gate electrode connected to the scan line Si, a first electrode connected to the initialization voltage line VINT, and a second electrode connected to the anode of the light-emitting diode LD. In another embodiment, the gate electrode of the seventh pixel transistor M7 may be connected to another scan line. For example, the gate electrode of the seventh pixel transistor M7 may be connected to the previous scan line S(i-1), may be connected to a scan line before the previous scan line, may be connected to the next scan line (e.g., the (i + 1)-th scan line), or may be connected to a scan line after the next scan line. In this embodiment, when a scan signal of a conductive level is applied to the scan line Si, the seventh pixel transistor M7 transfers the initialization voltage to the anode of the light-emitting diode LD, thereby initializing the amount of charge stored in the light-emitting diode LD.

[0088] The first electrode of the storage capacitor Cst may be connected to the first power supply line ELVDD, and the second electrode of the storage capacitor Cst may be connected to the gate electrode of the first pixel transistor M1.

[0089] The light-emitting diode LD may have an anode connected to the second electrode of the sixth pixel transistor M6, and may have a cathode connected to the second power supply line ELVSS. The light-emitting diode LD may be an organic light-emitting diode OLED, an inorganic light-emitting diode, a quantum dot light-emitting diode, etc.

[0090] Figure 5 is a diagram for illustrating a driving method of a pixel according to an embodiment of the present disclosure.

[0091] First, the data voltage DATA(i-1)j for the previous pixel row is applied to the data line Dj, and a scan signal of a conductive level (e.g., a low level) is applied to the previous scan line S(i-1).

[0092] At this time, since a scan signal of a cut-off level (e.g., a high level) is applied to the scan line Si, the second pixel transistor M2 is in a cut-off state, and the data voltage DATA(i-1)j for the previous pixel row is prevented from being pulled and input into the pixel PXij.

[0093] At this time, since the fourth pixel transistor M4 is turned on, an initialization voltage is applied to the gate electrode of the first pixel transistor M1 to initialize the amount of charge. Since an emission signal of a cut-off level is applied to the emission line Ei, the transistors M5 and M6 are in a cut-off state. Therefore, according to the application process of the initialization voltage, the undesired light emission from the light-emitting diode LD is reduced or prevented.

[0094] Next, the data voltage DATAij for the current pixel row is applied to the data line Dj, and a scan signal at a conductive level is applied to the scan line Si. As a result, the transistors M2, M1, and M3 are turned on, and the data line Dj and the gate electrode of the first pixel transistor M1 are electrically connected. Therefore, a compensation voltage obtained by subtracting the threshold voltage of the first pixel transistor M1 from the data voltage DATAij is applied to the second electrode of the storage capacitor Cst (i.e., applied to the first node N1), and the storage capacitor Cst stores an electric charge corresponding to the difference between the first power supply voltage and the compensation voltage. This period can be referred to as a compensation period.

[0095] At this time, since the seventh pixel transistor M7 is turned on, the anode of the light-emitting diode LD is connected to the initialization voltage line VINT, and the light-emitting diode LD is pre-charged or initialized with an electric charge corresponding to the voltage difference between the initialization voltage and the second power supply voltage.

[0096] Thereafter, a emission signal at a conductive level is applied to the emission line Ei, and the transistors M5 and M6 are turned on, and the amount of the drive current flowing through the first pixel transistor M1 is controlled according to the electric charge stored in the storage capacitor Cst, so that the drive current flows to the light-emitting diode LD. The light-emitting diode LD emits light until an emission signal at a cut-off level is applied to the emission line Ei.

[0097] In this embodiment, a fixed back-gate voltage Vref can be applied to the back-gate line Bi while the compensation voltage is applied to the first node N1. Therefore, the threshold voltage of the first pixel transistor M1 can be accurately compensated. During the remaining periods other than the compensation period, a variable back-gate voltage VB can be applied to the back-gate line Bi.

[0098] Figure 6 FIG. is a diagram for showing changes in the variable back-gate voltage according to an embodiment of the present disclosure when a still image is displayed after displaying a moving image / movie image.

[0099] When the display device 10 displays a still image STILL IMAGE after displaying a moving image MOVIE, the back-gate voltage determiner 16 can change the variable back-gate voltage VB from the first level VBL to the second level VBH during the first transition period TP1 (as described above, it is assumed that the first pixel transistor M1 having a back-gate electrode is configured as a P-type transistor).

[0100] However, conventionally, when the level of the variable back-gate voltage VB is instantaneously changed, the amount of the drive current of the first pixel transistor M1 can be changed, so that the change in brightness can be visible to the user. Therefore, according to the embodiment, the level of the variable back-gate voltage VB can be gradually changed during the first transition period TP1 corresponding to several tens of image frame periods.

[0101] Figure 7 It is a diagram for showing the mitigation of transient afterimage according to the magnitude of a variable back-gate voltage.

[0102] The hysteresis characteristic means that the source-drain current curve with respect to the gate-source voltage of the first pixel transistor M1 is different when the data voltage of the current image frame is higher than the data voltage of the previous image frame from when the data voltage of the current image frame is lower than the data voltage of the previous image frame. Thus, when the hysteresis characteristic is strong, even if the same gate-source voltage is applied to the first pixel transistor M1, the amount of drive current flowing through the first pixel transistor M1 can still change, such that the light-emitting diode LD may not emit light at an appropriate brightness corresponding to the gray-scale value.

[0103] When the display device 10 displays a still image, the first pixel transistor M1 of the pixel PXij receives the same gate-source voltage during several tens to several hundreds of image frame periods. Thus, when the hysteresis characteristic of the (multiple) first pixel transistors M1 is maximized in the still image, and when the display device 10 switches an image on the screen, the pixel PXij does not emit light at an appropriate brightness corresponding to the gray-scale value, and an afterimage of the previous still image remains. This afterimage problem can be referred to as a transient afterimage problem. Such a transient afterimage persists for several seconds and may be visible to the user.

[0104] Reference Figure 7 shows the hysteresis voltage Vhys measured according to the back-gate-source voltage Vbs of the first pixel transistor M1. The hysteresis voltage Vhys refers to the voltage difference between the threshold voltage values when the hysteresis characteristic appears in the first pixel transistor M1. When the hysteresis voltage Vhys is zero, the hysteresis characteristic does not appear.

[0105] According to Figure 7 the graph of, it is generally visible that the higher the back-gate-source voltage Vbs of the first pixel transistor M1, the lower the hysteresis voltage Vhys. That is, if the source voltage of the first pixel transistor M1 is constant, the higher the back-gate voltage, the smaller the hysteresis characteristic, and the transient afterimage problem can be mitigated.

[0106] Thus, according to an embodiment of the present disclosure, when the display device 10 displays a still image, the transient afterimage problem can be mitigated by converging (e.g., gradually adjusting) the variable back-gate voltage VB to the second level VBH.

[0107] Figure 8 It is a diagram for showing the change of the variable back-gate voltage according to an embodiment of the present disclosure when a moving image is displayed after displaying a still image.

[0108] When the display device 10 displays a moving image MOVIE after displaying a still image STILL IMAGE, the back gate voltage determiner 16 may change the variable back gate voltage VB from the second level VBH to the first level VBL during the second transition period TP2.

[0109] However, conventionally, when the level of the variable back gate voltage VB instantaneously changes, the amount of the driving current of the first pixel transistor M1 may change, such that a change in brightness may be visible to the user. Therefore, according to an embodiment, the level of the variable back gate voltage VB may be gradually changed during the second transition period TP2 corresponding to several tens of image frame periods.

[0110] Compared with a still image, a moving image gives the user less chance to see a change in brightness. That is, compared with a still image, it is more difficult to detect a change in brightness in a moving image. Therefore, according to an embodiment, the second transition period TP2 may be set to be shorter than the first transition period TP1 (for example, see Figure 6 ).

[0111] Figure 9 and Figure 10 are diagrams for showing alleviating a step efficiency problem according to the magnitude of a variable back gate voltage.

[0112] The step efficiency problem refers to a problem of emitting light having a brightness corresponding to an intermediate gray level that is not a target gray level, which is imposed by a hysteresis characteristic and a charge trapping phenomenon, where the gray level changes rapidly for each image frame (for example, when the gray level changes from a white gray level in a previous image frame to a black gray level in the current image frame).

[0113] As perceived by the user, the step efficiency problem may be a major problem in displaying a moving image such as a screen scroll.

[0114] Figure 9 shows a graph of the gate-source voltage Vgs of the first pixel transistor M1 when a variable back gate voltage VB of +7.6V is applied to the back gate line Bi and the back gate-source voltage Vbs of the first pixel transistor M1 is +3V.

[0115] In the first image frame, it can be seen that a step efficiency problem occurs, where the gate-source voltage Vgs does not immediately change to 100% corresponding to the target gray level, but changes to 67.3%.

[0116] Figure 10A graph showing the gate-source voltage Vgs of the first pixel transistor M1 when a variable back-gate voltage VB of -2.4V is applied to the back-gate line Bi and the back-gate-source voltage Vbs of the first pixel transistor M1 is -7V.

[0117] In the first image frame, it can be seen that the gate-source voltage Vgs immediately changes to 100.5%, which is almost the same as the target gray level, thus alleviating the step efficiency problem. That is, by reducing the level of the variable back-gate voltage VB, it can be seen that the step efficiency problem can be alleviated.

[0118] Therefore, according to an embodiment of the present disclosure, when the display device 10 displays a moving image, the step efficiency problem can be alleviated by converging (e.g., gradually adjusting) the variable back-gate voltage to the first level VBL.

[0119] The accompanying drawings and detailed description of the present disclosure referred to above are only for descriptive purposes and are only for illustrative purposes, and are not intended to limit its meaning or the scope of the present disclosure. Therefore, those of ordinary skill in the art will understand through the above content that various modifications and other equivalent embodiments are also possible. Therefore, the actual protection scope of the present disclosure should be determined by the technical scope of the present disclosure that includes its functional equivalents therein.

Claims

1. A display device, wherein, The display device includes: Pixels, where each pixel includes a first pixel transistor. The gate electrode of the first pixel transistor is connected to a first node, the back gate electrode of the first pixel transistor is connected to a back gate line, the first electrode of the first pixel transistor is connected to a second node, and the second electrode of the first pixel transistor is connected to a third node; A back gate voltage determiner configured to converge a variable back gate voltage to a first level when the display device displays a moving image, and to converge the variable back gate voltage to a second level when the display device displays a still image; and A back gate stage configured to apply the variable back gate voltage to the back gate line, wherein the display device further includes a scan stage configured to apply a scan signal to a scan line, wherein the back gate stage is configured to apply the variable back gate voltage to the back gate line while the scan stage applies the scan signal at a cut-off level to the scan line, wherein the back gate stage is configured to apply a fixed back gate voltage at a third level between the first level and the second level to the back gate line while the scan stage applies the scan signal at a conductive level to the scan line.

2. The display device according to claim 1, Among them, wherein the pixel further includes a second pixel transistor. The gate electrode of the second pixel transistor is connected to the scan line, the first electrode of the second pixel transistor is connected to a data line, and the second electrode of the second pixel transistor is connected to the second node.

3. The display device according to claim 2, wherein, The scan stage includes: A first scan transistor configured to apply the scan signal at a cut-off level to the scan line when a first control signal at a conductive level is applied to the gate electrode of the first scan transistor; and A second scan transistor configured to apply the scan signal at a conductive level to the scan line when a second control signal at a conductive level is applied to the gate electrode of the second scan transistor, and wherein the back gate stage is configured to apply the variable back gate voltage or the fixed back gate voltage to the back gate line according to the first control signal or the second control signal.

4. The display device according to claim 3, wherein, The back gate stage includes: A first back gate transistor configured to apply the variable back gate voltage to the back gate line when a first control signal at a conductive level is applied to the gate electrode of the first back gate transistor; and A second back gate transistor configured to apply the fixed back gate voltage to the back gate line when a second control signal at a conductive level is applied to the gate electrode of the second back gate transistor.

5. The display device according to claim 4, wherein, The pixel further includes: a third pixel transistor. The gate electrode of the third pixel transistor is connected to the scan line, the first electrode of the third pixel transistor is connected to the first node, and the second electrode of the third pixel transistor is connected to the third node.

6. The display device according to claim 1, wherein, The back gate voltage determiner is configured to change the variable back gate voltage from the first level to the second level during a first transition period when the display device displays the still image after displaying the moving image, wherein the back gate voltage determiner is configured to change the variable back gate voltage from the second level to the first level during a second transition period when the display device displays the moving image after displaying the still image, and wherein the first transition period is longer than the second transition period.

7. A driving method of a display device, the display device including pixels, the pixels including: A first pixel transistor, having a gate electrode connected to a first node, a back gate electrode connected to a back gate line, a first electrode connected to a second node, and a second electrode connected to a third node; and a second pixel transistor, having a gate electrode connected to a scan line, a first electrode connected to a data line, and a second electrode connected to the second node, the driving method comprising: applying a variable back gate voltage to the back gate line while applying a scan signal of a cut-off level to the scan line; and applying a fixed back gate voltage to the back gate line while applying a scan signal of a conductive level to the scan line, wherein the fixed back gate voltage has a third level between the first level and the second level, wherein the driving method further comprises: converging the variable back gate voltage to the first level when the display device displays a moving image; and converging the variable back gate voltage to the second level when the display device displays a still image.

8. The driving method of the display device according to claim 7, wherein, The driving method further comprises: changing the variable back gate voltage from the first level to the second level during a first transition period when the display device displays the still image after displaying the moving image; and changing the variable back gate voltage from the second level to the first level during a second transition period when the display device displays the moving image after displaying the still image, wherein the first transition period is longer than the second transition period.

9. A driving method of a display device, wherein, The driving method comprises: applying a variable back gate voltage to a back gate electrode of a first pixel transistor of a pixel; converging the variable back gate voltage to the first level when the display device displays a moving image; and converging the variable back gate voltage to the second level when the display device displays a still image, The driving method further comprises: changing the variable back gate voltage from the first level to the second level during a first transition period when the display device displays the still image after displaying the moving image; and changing the variable back gate voltage from the second level to the first level during a second transition period when the display device displays the moving image after displaying the still image, wherein the first transition period is longer than the second transition period, The driving method further comprises: applying a fixed back gate voltage to the back gate electrode, wherein the fixed back gate voltage has a third level between the first level and the second level, Among them, the first pixel transistor includes: a gate electrode connected to a first node, a back gate electrode connected to a back gate line, a first electrode connected to a second node, and a second electrode connected to a third node. Among them, the pixel further includes: a second pixel transistor, the gate electrode of the second pixel transistor is connected to a scan line, the first electrode of the second pixel transistor is connected to a data line, and the second electrode of the second pixel transistor is connected to the second node. Among them, while applying a scan signal of a cut-off level to the scan line, a variable back gate voltage is applied to the back gate line, and Among them, while applying a scan signal of a conductive level to the scan line, a fixed back gate voltage is applied to the back gate line.

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