Virtual wafer technology for manufacturing semiconductor devices

Abstract

A virtual wafer technique for fabricating semiconductor devices is disclosed, and more particularly, a method for fabricating semiconductor devices includes epitaxially depositing a heavily doped substrate layer substantially free of crystal defects on a lightly doped virtual substrate. A device region of a semiconductor device can be fabricated around the heavily doped substrate layer prior to removal of the lightly doped virtual substrate.

Description

Background Technology

[0001] Computing systems have made significant contributions to the progress of modern society and are utilized in numerous applications to achieve advantageous results. A multitude of devices, such as desktop personal computers (PCs), laptop PCs, tablet PCs, netbooks, smartphones, and servers, have facilitated increased productivity and reduced costs in data communication and analysis across most fields of entertainment, education, business, and science. A common aspect of computing systems is the power transistor. A power transistor can comprise a single transistor occupying most of a semiconductor die. Power transistors are used to conduct relatively large currents, and therefore utilize heavily doped semiconductor substrates, which reduces the bulk resistance of the semiconductor substrate.

[0002] In the fabrication of semiconductor ingots or crystals, donor impurity atoms such as boron (B) or phosphorus (P) can be added in precise amounts to molten intrinsic semiconductor material (e.g., silicon (Si)) to produce n-type or p-type intrinsic semiconductors, respectively. The resulting ingot can then be diced into multiple semiconductor wafers. During semiconductor ingot growth, trace amounts of oxygen (O) may be present in the reaction chamber or introduced by a phosphorus doping source. Oxygen atoms can aggregate with excess phosphorus, thereby forming defects in the semiconductor lattice structure.

[0003] Referring to Figures 1A and 1B, an exemplary semiconductor device fabrication process according to conventional techniques is illustrated. The semiconductor device fabrication process may require the use of an n-type heavily doped semiconductor substrate 110, such as heavily phosphorus-doped silicon. As shown in Figure 1A, the heavily phosphorus-doped silicon substrate used in the commercial fabrication of semiconductor devices may have one or more types of point defects 120, 130 within the lattice structure of the semiconductor substrate 110. For example, phosphorus and oxygen can combine to form phosphorus pentoxide (P₂O₅) and generate point defects in the semiconductor substrate 110. Then, as shown in Figure 1B, various semiconductor fabrication techniques are used to fabricate one or more regions of one or more devices around the surface of the heavily doped semiconductor substrate 110. Point defects at or near the surface of the semiconductor substrate 110 can lead to reduced breakdown voltage and / or excessive leakage current in one or more devices fabricated on the substrate. Other dopants (e.g., arsenic (As)) may cause voltage breakdown failure mechanisms and / or excessive leakage current based on similar point defects. Breakdown voltage failure mechanisms and / or increased leakage current can degrade the performance of low on-resistance semiconductor devices, such as trench metal-oxide-semiconductor field-effect transistors (TMOSFETs), vertical MOSFETs (VMOS), vertically diffused MOSFETs (VDMOS), double-diffused (DMOS), and power MOSFETs (UMOS). Therefore, continuous improvement in semiconductor manufacturing technology is necessary. Summary of the Invention

[0004] The present technology can be best understood by referring to the following description and accompanying drawings, which illustrate embodiments of the present technology, which is directed to a technique for manufacturing substantially defect-free heavily doped substrates for use in the manufacture of semiconductor devices.

[0005] In one embodiment, a method of manufacturing a semiconductor device may include: depositing a heavily doped crystal substrate on a lightly doped crystal dummy substrate. One or more regions of one or more devices may be formed in and on the heavily doped crystal substrate. The lightly doped crystal dummy substrate may then be removed, leaving one or more regions of one or more devices formed in and on the heavily doped crystal substrate.

[0006] In another embodiment, a method of manufacturing a semiconductor device may include: epitaxially depositing an n-type heavily doped substrate layer on an n-type lightly doped dummy substrate. One or more regions of one or more devices may be formed around the surface of the n-type heavily doped substrate layer. After forming one or more regions of one or more devices, the n-type lightly doped dummy substrate may be removed from the n-type heavily doped substrate.

[0007] In another embodiment, a method of manufacturing a semiconductor device may include depositing a buffer layer on a crystalline dummy substrate. A heavily doped crystalline substrate may then be deposited on the buffer layer. The buffer layer may be configured to prevent defects from propagating from the crystalline dummy substrate to the heavily doped crystalline substrate. Before removing the crystalline dummy substrate and optionally the buffer layer, one or more regions of one or more devices may be formed around the surface of the heavily doped crystalline substrate.

[0008] This summary provides a simplified overview of some concepts that will be further described in the detailed description below. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. Attached Figure Description

[0009] In the accompanying drawings, embodiments of the present technology are illustrated by way of example and not limitation, and similar reference numerals refer to similar elements, wherein:

[0010] Figures 1A and 1B illustrate exemplary semiconductor device manufacturing processes according to conventional techniques.

[0011] Figure 2 A method for manufacturing a semiconductor device according to aspects of the present technology is shown.

[0012] Figure 3A , Figure 3B and Figure 3C An exemplary semiconductor device manufacturing process according to aspects of the present technology is illustrated.

[0013] Figure 4A and Figure 4B A method for manufacturing a vertical power device according to aspects of the present technology is shown.

[0014] Figures 5A to 5K A manufacturing process for an exemplary vertical power device according to aspects of this technology is illustrated.

[0015] Figure 6A and Figure 6B A method for manufacturing a vertical power device according to aspects of the present technology is shown.

[0016] Figures 7A to 7K A manufacturing process for an exemplary vertical power device according to aspects of this technology is illustrated. Detailed Implementation

[0017] Reference will now be made in detail to embodiments of the present technology, examples of which are illustrated in the accompanying drawings. Although the present technology will be described in conjunction with these embodiments, it should be understood that they are not intended to limit the invention to these embodiments. Rather, the invention is intended to cover alternatives, modifications, and equivalents that may be included within the scope of the invention as defined by the appended claims. Furthermore, numerous specific details are set forth in the following detailed description of the present technology to provide a thorough understanding of the technology. However, it should be understood that the present technology may be practiced without these specific details. In other instances, well-known methods, processes, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present technology.

[0018] The following embodiments of the present technology are presented using routines, modules, logic blocks, and other symbolic representations of operations on data within one or more electronic devices. Description and representation are means by which those skilled in the art most effectively communicate the essence of their work to others skilled in the art. Here, routines, modules, logic blocks, etc., are generally considered as a self-consistent sequence of processes or instructions that lead to a desired result. These processes are those that involve the physical manipulation of physical quantities. Typically, but not necessarily, these physical manipulations take the form of electrical or magnetic signals that can be stored, transmitted, compared, and otherwise manipulated within an electronic device. For convenience and with reference to general usage, and with reference to embodiments of the present technology, these signals are referred to as data, bits, values, elements, symbols, characters, items, numbers, strings, etc.

[0019] However, it should be remembered that all these terms should be interpreted as referring to physical manipulation and physical quantities, and are merely convenient labels, and should be further interpreted according to the terminology commonly used in the art. Unless otherwise explicitly stated from the discussion below, it should be understood that, through the discussion of this art, the use of terms such as “receiving” and / or similar terms refers to the actions and processes of electronic devices such as electronic computing devices that manipulate and convert data. Data is represented as physical (e.g., electronic) quantities in the logic circuits, registers, memories, and / or similar elements of electronic devices, and is converted into other data similarly represented as physical quantities in electronic devices.

[0020] In this application, the use of anticonnectives is intended to include conjunctions. The use of definite or indefinite articles is not intended to indicate cardinality. In particular, references to "the" object or "one" object are also intended to indicate one of a possible plurality of such objects. It should also be understood that the wording and terminology used herein are for descriptive purposes and should not be considered restrictive.

[0021] Now for reference Figure 2 This illustrates a method for manufacturing a semiconductor device according to aspects of the present technology. (Refer to...) Figure 3A , Figure 3B and Figure 3C The manufacturing method is further described below. At 210, the method of manufacturing a semiconductor device may include: optionally depositing a barrier layer (not shown) on a lightly doped crystalline dummy substrate 310. This barrier layer may be configured to reduce doping diffusion from the heavily doped crystalline substrate layer 310, as described subsequently, to the lightly doped crystalline dummy substrate 320. At 220, a heavily doped crystalline substrate layer 320 may be deposited on the lightly doped crystalline dummy substrate 310, or, if a barrier layer is included, the heavily doped crystalline substrate layer 320 may be deposited on a barrier layer. The term dummy substrate is used herein to express a dummy substrate on which a heavily doped crystalline substrate layer is deposited, and which is then subsequently removed prior to the completion of the manufacturing of the semiconductor device, as further described below. The lightly doped crystalline dummy substrate 310 may be substantially free of point defects.

[0022] In one implementation, the lightly doped crystalline virtual substrate 310 can be a lightly phosphorus-doped silicon wafer. The lightly phosphorus-doped silicon wafer can have a wafer thickness of approximately 625 micrometers (μm) and a resistivity of approximately a few milliohms-cm (mΩ·cm) or less. The lightly phosphorus-doped silicon wafer can have a very low point defect density. In contrast, heavily phosphorus-doped silicon wafers, with resistivity below 1 mΩ·cm, used in conventional techniques at comparable cost, have a significantly higher point defect density due to the precipitation of oxygen atoms with abundant phosphorus in the substrate.

[0023] In one implementation, a heavily doped crystal substrate 320 can be formed by epitaxially depositing silicon in the presence of phosphorus doping using chemical vapor deposition, vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), molecular beam epitaxy (MBE), or other similar epitaxial processes. For example, gases such as silicon tetrachloride (SiCl4), silane (SiH4), dichlorosilane (SiH2Cl2), and trichlorosilane (SiHCl3) can be used in a VPE at a temperature of approximately 1200 degrees Celsius (°C) along with impurity gases such as phosphine (PH3) to deposit a heavily phosphorus-doped silicon epitaxial layer on the silicon of a lightly phosphorus-doped dummy substrate. An epitaxial process can be performed to deposit a heavily phosphorus-doped silicon epitaxial layer on the silicon of the lightly phosphorus-doped dummy substrate, having a resistivity of less than 1 mΩ·cm and a thickness of approximately 20-50 μm.

[0024] Optionally, at 230, the heavily doped crystal substrate layer 320 deposited on the lightly doped crystal dummy substrate 310 may be annealed to reduce one or more types of defects in the heavily doped crystal substrate layer 320. In one implementation, the lightly phosphorus-doped silicon dummy substrate and the heavily phosphorus-doped epitaxially deposited silicon may be subjected to thermal cycling at approximately 1000°C to reduce one or more types of defects in the deposited heavily phosphorus-doped silicon substrate layer.

[0025] At 240, one or more regions of one or more devices 330 may be formed around the exposed surface of the heavily doped crystalline substrate 320. In one implementation, one or more semiconductor manufacturing techniques, such as epitaxial deposition, photolithography, etching, implantation, deposition, etc., may be performed to form one or more regions of one or more devices 330 in and on the deposited heavily phosphorus-doped silicon substrate, such as drain regions, drift regions, body regions, source regions, gate regions, gate dielectric regions, contacts, vias, etc., of one or more transistors or other similar devices.

[0026] At 250°, the lightly doped crystalline dummy substrate 310 can be removed from the heavily doped crystalline substrate 320, leaving one or more regions of one or more devices 330 formed around the heavily doped crystalline substrate 320. In one implementation, the lightly doped crystalline dummy substrate 3310 can be removed by back grinding and polishing processes. At 260°, optionally, the heavily doped crystalline substrate 320 can be thinned. In one implementation, a portion of the heavily doped crystalline substrate 320 can also be removed from the exposed surface opposite one or more regions of one or more devices 330 using back grinding and polishing processes. The heavily doped crystalline substrate 320 can be thinned to a final thickness of approximately 20-50 μm.

[0027] At 270, the method of manufacturing a semiconductor device may continue to form one or more additional regions of one or more devices 330 around the exposed surface of the heavily doped crystal substrate layer 320. In one implementation, one or more additional semiconductor manufacturing techniques, such as photolithography, etching, implantation, deposition, etc., may be performed to form one or more regions of one or more devices 330, such as packaging layers, leads, etc., of one or more transistors or other similar devices, in and on the heavily doped crystal substrate layer.

[0028] Now for reference Figure 4A and Figure 4B This illustrates a method for manufacturing an exemplary vertical power device according to aspects of the present technology. (Refer to...) Figures 5A to 5K Further description of the manufacturing method, Figures 5A to 5K Exemplary vertical power devices are shown in portions during various stages of fabrication. In one implementation, the vertical power device may be a trench metal-oxide-semiconductor field-effect transistor (TMOSFET). At 405, a method of fabricating the vertical power device may include: optionally depositing a barrier layer (not shown) on an n-type lightly doped dummy substrate 502. This barrier layer may be configured to reduce doping diffusion from a heavily doped crystalline substrate layer 504, described later, to the lightly doped crystalline dummy substrate 502. In one implementation, the barrier layer may be a thin layer of arsenic (As) or phosphorus (P). At 410, an n-type heavily doped substrate layer 504 may be epitaxially deposited on the n-type lightly doped crystalline dummy substrate 502 or an optional buffer layer. The term dummy substrate is used herein to express that the dummy substrate is used to epitaxially grow a heavily doped crystalline substrate layer thereon and then remove it from the finished semiconductor device as further described below. The n-type lightly doped crystalline dummy substrate 502 may be substantially free of point defects.

[0029] In one implementation, the lightly doped n-type crystalline virtual substrate 502 can be a lightly phosphorus-doped silicon wafer. The lightly phosphorus-doped silicon wafer can have a wafer thickness of approximately 625 μm and a resistivity of approximately a few milliohms-cm (mΩ·cm) or less. In contrast, a heavily phosphorus-doped silicon wafer with a resistivity below 1 mΩ·cm at comparable cost exhibits a significantly higher point defect density due to the precipitation of oxygen atoms with abundant phosphorus in the substrate.

[0030] In one implementation, an n-type heavily doped crystal substrate 504 can be formed by epitaxially depositing silicon in the presence of phosphorus doped by chemical vapor deposition, vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), molecular beam epitaxy (MBE), or other similar epitaxial processes. For example, gases such as silicon tetrachloride (SiCl4), silane (SiH4), dichlorosilane (SiH2Cl2), and trichlorosilane (SiHCl3) can be used in VPE at a temperature of approximately 1200°C along with impurity gases such as phosphine (PH3) to deposit a heavily phosphorus-doped silicon epitaxial layer on a lightly phosphorus-doped silicon virtual substrate. In one implementation, before epitaxially depositing the heavily n-type doped crystal substrate 504, an arsenic (As) buffer layer can be deposited on the lightly n-type doped crystal dummy substrate 502 to control the outward diffusion of n-type dopant from the heavily n-type doped crystal substrate 504 to the lightly n-type doped crystal dummy substrate 502, thereby improving control over the doping concentration and / or doping distribution in the heavily n-type doped crystal substrate 504. An epitaxial process can be performed to deposit a heavily phosphorus-doped silicon epitaxial layer with a resistivity of less than 1 mΩ·cm and a thickness of approximately 20-50 μm on the lightly phosphorus-doped silicon dummy substrate.

[0031] At position 415, an n-type moderately doped crystal layer 506 can be epitaxially deposited on the n-type heavily doped substrate layer 504. The n-type moderately doped crystal layer can be configured as a drift region. In one implementation, the n-type moderately doped crystal layer can be a moderately phosphorus (P) epitaxially deposited silicon layer.

[0032] At 420°C, the heavily doped n-type crystal substrate 504 and the moderately doped n-type drift region 506 may optionally be annealed to reduce one or more types of defects in the heavily doped n-type crystal substrate 504 and the moderately doped n-type drift region 506. In one implementation, the lightly phosphorus-doped silicon dummy substrate 502, the heavily phosphorus-doped epitaxially deposited silicon substrate 504, and the moderately phosphorus-doped epitaxially deposited silicon drift region 506 may be subjected to thermal cycling at approximately 1000°C to reduce one or more types of defects in the heavily doped phosphorus-doped silicon substrate 504 and the moderately phosphorus-doped epitaxially deposited silicon drift region 506.

[0033] At position 425, multiple trenches 508 can be formed in the n-type moderately doped drift region 506. In one implementation, a photolithography process can be used to deposit and pattern the mask layer. The n-type moderately doped crystal drift layer 506 exposed by the patterned mask layer 510 can be etched to form multiple trenches 508, such as... Figure 5B As shown. Then, after the multiple trenches 508 have been etched, the patterned mask layer 510 can be removed.

[0034] At 430, multiple gate dielectric regions can be formed on the walls of the multiple trenches 508. At 435, multiple gate regions can also be formed in the multiple trenches 508. The multiple gate dielectric regions can be disposed between the n-type moderately doped crystal drift region 506 and the multiple gate regions. In one implementation, a gate dielectric layer 512 can be grown on the exposed surface of the n-type moderately doped crystal drift region 506 using a thermal oxidation process for forming a silicon oxide layer. A conformal n-type doped semiconductor layer 514 can be deposited in the trench 506 and on top of the gate dielectric layer 512. The n-type doped semiconductor layer 514 can be a phosphorus-doped polysilicon layer. Then, the n-type doped semiconductor layer 514 and gate dielectric layer 512 can be etched back until the n-type doped semiconductor and gate dielectric are removed from the surface of the n-type moderately doped crystal drift region 506, leaving a gate dielectric and n-type doped semiconductor-filled trench 508 to form a plurality of gate regions 516, and leaving a plurality of gate dielectric regions 518 disposed between the n-type moderately doped crystal drift region 506 and the plurality of gate regions 516, such as Figure 5E As shown.

[0035] At 440, a plurality of p-type doped body regions 520 may be formed in a portion of an n-type moderately doped drift region 506 opposite to the n-type heavily doped crystal substrate layer 504. In one implementation, a mask layer may be deposited and patterned using a photolithography process. The plurality of p-type doped body regions 520 may be formed by implanting a p-type dopant, such as boron (B), into the upper portion of the n-type moderately doped crystal drift region 506 exposed by the patterned mask 522. The patterned mask 522 may then be removed after implantation of the plurality of p-type doped body regions 520. In one implementation, the plurality of p-type doped body regions 520 may extend to the bottom of a plurality of gate regions 516.

[0036] At position 445, multiple n-type doped source regions 526 can be formed in portions of multiple p-type doped body regions 520 opposite to the n-type moderately doped crystal drift region 506. In one implementation, a mask layer 528 can be deposited and patterned using a photolithography process. The multiple n-type doped source regions 526 can be formed by implanting an n-type dopant 530, such as phosphorus, into the upper portion of the p-type doped body region 520 exposed by the patterned mask 528. After implanting the multiple n-type doped source regions 526, the patterned mask 528 can be removed.

[0037] At 450°, source-body contacts coupled to multiple n-type doped source regions 526 and multiple p-type doped body regions 520 can be formed. In one implementation, a dielectric layer 532 can be deposited on the surfaces of multiple gate regions 516, multiple gate dielectric regions 518, multiple source regions 526, and multiple body regions 520. A mask layer 534 can be deposited and patterned using a photolithography process. The portions of the dielectric layer 532 exposed by the patterned mask layer 534 can be selectively etched to form multiple source-body contact openings 536 in the dielectric layer 530. After forming the source-body contact openings 536 in the dielectric layer 532, the patterned mask 534 can then be removed. A source-body contact layer 538 can be deposited in the source-body contact openings 536 and on the surface of the patterned dielectric layer 532. The source-body contact layer 538 can be patterned to form multiple source-body contacts 540 coupled to multiple n-type doped source regions 526 and multiple p-type doped body regions 520.

[0038] At 455, the lightly doped n-type dummy substrate 502 can be removed from the heavily doped n-type crystal substrate layer 504, leaving a plurality of gate regions 516, a plurality of gate dielectric regions 518, a plurality of p-type doped body regions 520, and a plurality of source-body contacts 540 formed around the moderately doped n-type crystal drift region 506. In one implementation, the lightly doped n-type dummy substrate 502 can be removed by a back-grinding and polishing process. At 460, the heavily doped n-type crystal substrate layer 504 can optionally be thinned. In one implementation, a portion of the heavily doped n-type crystal substrate layer 504 can also be removed from the exposed surface opposite the plurality of gate regions 516, the plurality of gate dielectric regions 518, the plurality of p-type doped body regions 520, and the plurality of source-body contacts 540 formed around the moderately doped n-type crystal drift region 506 using a back-grinding and polishing process. The heavily doped crystal substrate layer 504 can be thinned to a final thickness of approximately 25-50 micrometers (μm). The heavily doped crystal substrate 504 can be thinned to achieve a resistivity of about 1 milliohm / cm or less.

[0039] At 465, the method of manufacturing a semiconductor device may continue to form one or more additional regions of one or more devices around the heavily n-type doped crystal substrate layer 504. In one implementation, one or more additional semiconductor manufacturing techniques, such as photolithography, etching, implantation, deposition, etc., may be performed to form one or more regions of one or more devices, such as encapsulation layers, leads, etc., of one or more transistors or other similar devices in and on the epitaxially deposited heavily n-type doped crystal substrate layer. For example, a drain contact layer 542 may be deposited on the heavily n-type doped crystal substrate layer 504 opposite to multiple gate regions 516, multiple gate dielectric regions 518, multiple source regions 526, and multiple body regions 520. Additional processes may be performed to form gate contacts, encapsulation layers, etc.

[0040] This article includes references. Figures 4A-4B and Figures 5A-5K Exemplary semiconductor devices and methods of manufacturing thereof are described and illustrated to teach the implementation of various aspects of the present technology. However, the present technology is not limited thereto and can be readily applied to any number of different semiconductor devices and methods of manufacturing such semiconductor devices.

[0041] Now for reference Figure 6A and Figure 6B This illustrates a method for manufacturing another exemplary vertical power device according to aspects of the present technology. (Refer to...) Figures 7A to 7K Further description of the manufacturing method, Figures 7A to 7K Exemplary vertical power devices are shown in portions during various stages of fabrication. In one implementation, the vertical power device may be a trench metal-oxide-semiconductor field-effect transistor (TMOSFET). A method of fabricating a vertical power device may include: at 605, depositing a barrier layer 702 on a crystalline dummy substrate 704. The crystalline dummy substrate 704 may be of any type and may contain defects. The barrier layer 702 may be configured to prevent defects from propagating from the dummy substrate 704 to the heavily doped crystalline substrate layer 706, which is described subsequently. In one implementation, the barrier layer may be a thin layer of arsenic (As) or phosphorus (P). At 610, an n-type heavily doped substrate layer 706 may be epitaxially deposited on the buffer layer 702. The term dummy substrate is used herein to express the dummy substrate used to epitaxially grow a heavily doped crystalline substrate layer thereon, and then the dummy substrate is removed from the completed semiconductor device as further described below.

[0042] In one implementation, the crystalline virtual substrate 704 can be a phosphorus-doped silicon wafer. The phosphorus-doped silicon wafer can have a wafer thickness of approximately 625 μm and a resistivity of approximately a few milliohms-cm (mΩ·cm) or less. In one implementation, the n-type heavily doped crystalline substrate 706 can be formed by epitaxially depositing silicon in the presence of phosphorus doped using chemical vapor deposition, vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), molecular beam epitaxy (MBE), or other similar epitaxial processes. For example, a gas such as silicon tetrachloride (SiCl4), silane (SiH4), dichlorosilane (SiH2Cl2), or trichlorosilane (SiHCl3) can be used in VPE at a temperature of approximately 1200°C along with an impurity gas such as phosphine (PH3) to deposit a heavily phosphorus-doped silicon epitaxial layer on the buffer layer 702. Epitaxial processes can be performed on buffer layer 702 to deposit a heavily phosphorus-doped silicon epitaxial layer with a resistivity of less than 1 mΩ·cm and a thickness of approximately 20-50 μm.

[0043] At position 615, an n-type moderately doped crystal layer 708 can be epitaxially deposited on the n-type heavily doped substrate layer 706. The n-type moderately doped crystal layer can be configured as a drift region. In one implementation, the n-type moderately doped crystal layer can be a moderately phosphorus (P)-doped epitaxially deposited silicon layer.

[0044] At 620°C, the heavily n-type doped crystal substrate 706 and the moderately n-type doped drift region 708 may optionally be annealed to reduce one or more types of defects in the heavily n-type doped crystal substrate 706 and the moderately n-type doped drift region 708. In one implementation, the phosphorus-doped silicon dummy substrate 704, the buffer layer 702, the heavily phosphorus-doped epitaxially deposited silicon substrate 706, and the moderately phosphorus-doped epitaxially deposited silicon drift region 708 may be subjected to thermal cycling at approximately 1000°C to reduce one or more types of defects in the heavily phosphorus-doped epitaxially deposited silicon substrate 706 and the moderately phosphorus-doped epitaxially deposited silicon drift region 708.

[0045] At position 625, multiple trenches 710 can be formed in the n-type moderately doped drift region 708. In one implementation, a mask layer can be deposited and patterned using a photolithography process. The n-type moderately doped crystal drift layer 708 exposed by the patterned mask layer 712 can be etched to form the multiple trenches 710, as shown below. Figure 7B As shown. After the multiple trenches 710 have been etched, the patterned mask layer 712 can then be removed.

[0046] At 630, multiple gate dielectric regions can be formed on the walls of the multiple trenches 710. At 635, multiple gate regions can also be formed in the multiple trenches 710. The multiple gate dielectric regions can be disposed between the n-type moderately doped crystal drift region 708 and the multiple gate regions. In one implementation, a gate dielectric layer 714 can be grown on the exposed surface of the n-type moderately doped crystal drift region 708 using a thermal oxidation process for forming a silicon oxide layer. A conformal n-type doped semiconductor layer 716 can be deposited in the trenches 708 and on top of the gate dielectric layer 714. The n-type doped semiconductor layer 716 can be a phosphorus-doped polysilicon layer. Then, the n-type doped semiconductor layer 716 and the gate dielectric layer 714 can be etched back until the n-type doped semiconductor and gate dielectric are removed from the surface of the n-type moderately doped crystal drift region 708, leaving a gate dielectric and n-type doped semiconductor-filled trench 710 to form a plurality of gate regions 718, and leaving a plurality of gate dielectric regions 720 disposed between the n-type moderately doped crystal drift region 708 and the plurality of gate regions 718, such as Figure 7E As shown.

[0047] At 640, a plurality of p-type doped body regions 722 can be formed in a portion of the n-type moderately doped drift region 708 opposite the n-type heavily doped crystal substrate layer 706. In one implementation, a mask layer can be deposited and patterned using a photolithography process. The plurality of p-type doped body regions 722 can be formed by implanting a p-type dopant 726, such as boron (B), into the upper portion of the n-type moderately doped crystal drift region 708 exposed by the patterned mask 724. After implanting the plurality of p-type doped body regions 722, the mask 724 can then be removed. In one implementation, the plurality of p-type doped body regions 722 can extend to the bottom of the plurality of gate regions 718.

[0048] At position 645, multiple n-type doped source regions 728 can be formed in portions of multiple p-type doped body regions 722 opposite to the n-type moderately doped crystal drift region 708. In one implementation, a mask layer 730 can be deposited and patterned using a photolithography process. The multiple n-type doped source regions 728 can be formed by implanting an n-type dopant 732, such as phosphorus, into the upper portion of the p-type doped body region 722 exposed by the patterned mask 730. After implanting the multiple n-type doped source regions 728, the patterned mask 730 can then be removed.

[0049] At 650, source-body contacts coupled to multiple n-type doped source regions 728 and multiple p-type doped body regions 722 can be formed. In one implementation, a dielectric layer 734 can be deposited on the surfaces of multiple gate regions 718, multiple gate dielectric regions 720, multiple source regions 728, and multiple body regions 722. A mask layer 736 can be deposited and patterned using a photolithography process. The portion of the dielectric layer 734 exposed by the patterned mask layer 736 can be selectively etched to form multiple source-body contact openings 738 in the dielectric layer 732. After forming the source-body contact openings 738 in the dielectric layer 734, the patterned mask 736 can then be removed. A source-body contact layer 740 can be deposited in the source-body contact openings 738 and on the surface of the patterned dielectric layer 734. The source-body contact layer 740 can be patterned to form multiple source-body contacts 742 coupled to multiple n-type doped source regions 728 and multiple p-type doped body regions 722.

[0050] At 655, the crystal dummy substrate 704 can be removed. Optionally, the buffer layer 702 can also be removed from the n-type heavily doped crystal substrate layer 706, leaving a plurality of gate regions 718, a plurality of gate dielectric regions 720, a plurality of p-type doped body regions 722, and a plurality of source-body contacts 742 formed around the n-type moderately doped crystal drift region 708. In one implementation, the crystal dummy substrate 704 and the buffer layer 702 can be removed by a back-grinding and polishing process. At 660, the n-type heavily doped crystal substrate layer 706 can be optionally thinned. In one implementation, a portion of the n-type heavily doped crystal substrate layer 706 can also be removed from the exposed surface opposite the plurality of gate regions 718, the plurality of gate dielectric regions 720, the plurality of p-type doped body regions 722, and the plurality of source-body contacts 742 formed around the n-type moderately doped crystal drift region 708 using a back-grinding and polishing process. The heavily doped crystal substrate 706 can be thinned to a final thickness of approximately 25 to 50 micrometers (μm). The heavily doped crystal substrate 706 can be thinned to achieve a resistivity of approximately 1 mΩ·cm or less.

[0051] At 665, the method of manufacturing a semiconductor device can continue to form one or more additional regions of one or more devices around the heavily n-type doped crystal substrate 706. In one implementation, one or more additional semiconductor manufacturing techniques, such as photolithography, etching, implantation, deposition, etc., can be performed to form one or more regions of one or more devices, such as encapsulation layers, leads, etc., of one or more transistors or other similar devices in and on the epitaxially deposited heavily n-type doped crystal substrate 706. For example, a drain contact layer 744 can be deposited on the heavily n-type doped crystal substrate 706 opposite to multiple gate regions 718, multiple gate dielectric regions 720, multiple source regions 728, and multiple body regions 722. Additional processes can be performed to form gate contacts, encapsulation layers, etc.

[0052] refer to Figures 6A-6B and Figures 7A to 7K Exemplary semiconductor devices and methods of manufacturing thereof are described and illustrated herein to teach implementation of various aspects of the present technology. However, the present technology is not limited thereto and can be readily applied to any number of different semiconductor devices and methods of manufacturing such semiconductor devices.

[0053] Heavily doped crystal substrates 320, 504, and 706 are characterized by low bulk resistivity and low point defect concentration. The low bulk resistivity is particularly advantageous for trench MOSFETs (TMOSFETs), vertical MOSFETs (VMOS), vertically diffused MOSFETs (VDMOS), double-diffused (DMOS), power MOSFETs (UMOS), and other similar devices that conduct substantial currents through the substrate. The low bulk resistivity of the heavily doped crystal substrates 320, 502, and 706 results in relatively low on-resistivity for such trench MOSFETs (TMOSFETs), vertical MOSFETs (VMOS), vertically diffused MOSFETs (VDMOS), double-diffused (DMOS), power MOSFETs (UMOS), and other similar devices. The active regions of trench MOSFETs (TMOSFETs), vertical MOSFETs (VMOS), vertically diffused MOSFETs (VDMOS), double-diffused (DMOS), power MOSFETs (UMOS), and other similar devices extend down into the heavily doped crystal substrates 320, 502, and 706. Therefore, point defects distributed across the entire substrate are more likely to be located near the active regions of trench MOSFETs (TMOSFETs), vertical MOSFETs (VMOS), vertically diffused MOSFETs (VDMOS), double-diffused (DMOS), power MOSFETs (UMOS), and other similar devices. Conversely, lateral transistor structures, where the conductive channels run along the surface of the substrate, are typically only affected by point defects near the substrate surface, and not by point defects located below the substrate, away from the active regions of the lateral transistor structures. Thus, for trench MOSFETs (TMOSFETs), vertical MOSFETs (VMOS), vertically diffused MOSFETs (VDMOS), double-diffused (DMOS), power MOSFETs (UMOS), and other similar devices, the low point defect concentration of heavily doped crystal substrates 320, 504, and 706 leads to lower breakdown voltage failure rates and / or lower leakage currents.

[0054] The technique of epitaxially depositing a heavily doped crystal substrate layer on a lightly doped crystal dummy substrate advantageously allows the use of lightly doped crystal wafers, which are less expensive than heavily doped crystal wafers. Furthermore, for wafers with roughly the same cost, the point defect density in lightly doped crystal wafers is significantly lower than that in heavily doped crystal wafers. It has been found that there is a one-to-one correspondence between point defect density and breakdown voltage failure modes in devices fabricated in wafers. Therefore, compared to fabricating devices in heavily doped crystal substrate wafers, the process of epitaxially depositing a heavily doped crystal substrate layer on a lightly doped crystal dummy substrate advantageously reduces the breakdown voltage failure modes of devices fabricated in wafers. Subsequent removal of the lightly doped crystal dummy substrate also advantageously allows devices fabricated in the epitaxially deposited heavily doped crystal substrate layer to achieve on-resistance values ​​comparable to those of heavily doped crystal substrate wafers. In addition, epitaxial deposition of heavily doped crystal substrates advantageously enables increased control over the doping distribution and / or thickness of the heavily doped crystal substrate and / or additional regions formed in or on the heavily doped crystal substrate.

[0055] The following examples relate to specific technical embodiments and indicate specific features, elements, or steps that may be used or otherwise combined in implementing such embodiments.

[0056] Example 1 includes a method of manufacturing a semiconductor device, the method comprising: depositing a heavily doped crystal substrate on a lightly doped crystal dummy substrate; forming one or more regions of one or more devices around a surface of the heavily doped crystal substrate; and removing the lightly doped crystal dummy substrate from the heavily doped crystal substrate, thereby leaving one or more regions of one or more devices formed around the heavily doped crystal substrate.

[0057] Example 2 includes the method of manufacturing a semiconductor device of Example 1, the method further comprising: annealing a heavily doped crystal substrate deposited on a lightly doped crystal dummy substrate prior to forming one or more regions of one or more devices to reduce one or more types of defects in the heavily doped crystal substrate.

[0058] Example 3 includes the method of manufacturing a semiconductor device of Example 1, the method further comprising: thinning a heavily doped crystal substrate after removing a lightly doped crystalline dummy substrate.

[0059] Example 4 includes the method of manufacturing a semiconductor device of Example 1, the method further comprising: forming one or more additional regions of one or more devices around a heavily doped crystal substrate.

[0060] Example 5 includes the method of manufacturing a semiconductor device of Example 1, the method further comprising: depositing a barrier layer on the lightly doped crystal dummy substrate before depositing a heavily doped crystal substrate on the lightly doped crystal dummy substrate, wherein the barrier layer is configured to reduce doping diffusion from the heavily doped crystal substrate to the lightly doped crystal dummy substrate.

[0061] Example 6 includes the method of manufacturing a semiconductor device of Example 1, wherein the lightly doped crystalline dummy substrate is substantially free of crystal defects.

[0062] Example 7 includes the method of manufacturing a semiconductor device of Example 6, wherein a lightly doped crystalline virtual substrate with virtually no crystal defects is cheaper than a heavily doped crystalline wafer with virtually no crystal defects.

[0063] Example 8 includes the method of manufacturing a semiconductor device of Example 6, wherein the epitaxially deposited heavily doped crystal substrate is substantially free of crystal defects because the lightly doped crystalline dummy substrate is substantially free of crystal defects.

[0064] Example 9 includes a method of manufacturing a semiconductor device, the method comprising: epitaxially depositing an n-type heavily doped substrate layer on an n-type lightly doped dummy substrate; forming one or more regions of one or more devices around a first surface of the n-type heavily doped substrate layer; and removing the n-type lightly doped dummy substrate from the n-type heavily doped substrate layer.

[0065] Example 10 includes the method of manufacturing a semiconductor device of Example 9, wherein forming one or more regions of one or more devices includes: forming a plurality of gate trenches in an n-type heavily doped substrate layer; forming a plurality of gate dielectric regions in the plurality of gate trenches; forming a plurality of gate regions in the plurality of gate trenches, wherein the plurality of gate dielectric regions are disposed between the n-type heavily doped substrate layer and the plurality of gate regions; forming a plurality of p-type doped body regions in a portion of the n-type heavily doped substrate layer opposite to a lightly doped n-type dummy substrate; and forming a plurality of n-type doped source regions in a portion of the plurality of p-type doped body regions opposite to the n-type heavily doped substrate layer.

[0066] Example 11 includes the method of manufacturing a semiconductor device of Example 10, wherein forming one or more regions of one or more devices further includes forming a plurality of source-body contacts coupled to a plurality of n-type doped source regions and a plurality of p-type doped body regions.

[0067] Example 12 includes the method of manufacturing a semiconductor device of Example 9, wherein: the n-type lightly doped dummy substrate comprises lightly phosphorus-doped silicon (Si); and the n-type heavily doped substrate layer comprises heavily phosphorus-doped silicon.

[0068] Example 13 includes the method of manufacturing a semiconductor device of Example 12, the method further comprising: depositing a barrier layer comprising arsenic (As) on a lightly doped dummy substrate of n-type prior to epitaxially depositing an n-type heavily doped substrate layer.

[0069] Example 14 includes the method of manufacturing a semiconductor device of Example 12, wherein an n-type lightly doped substrate is removed by a back grinding and polishing process.

[0070] Example 15 includes the method of manufacturing a semiconductor device of Example 14, the method further comprising: an n-type heavily doped substrate layer surrounding a surface that is thinned to the surface of one or more regions of one or more devices.

[0071] Example 16 includes the method of manufacturing a semiconductor device of Example 15, wherein an n-type heavily doped substrate layer is thinned by back grinding and polishing processes.

[0072] Example 17 includes the method of manufacturing a semiconductor device of Example 9, the method further comprising: annealing an n-type heavily doped substrate layer deposited on an n-type lightly doped dummy substrate to reduce one or more types of defects in the n-type heavily doped substrate layer.

[0073] Example 18 includes the method of manufacturing a semiconductor device of Example 9, wherein the n-type lightly doped dummy substrate is substantially free of crystal defects.

[0074] Example 19 includes the method of manufacturing a semiconductor device of Example 18, wherein a lightly doped n-type dummy substrate with virtually no crystal defects is cheaper than a heavily doped crystal wafer with virtually no crystal defects.

[0075] Example 20 includes the method of manufacturing a semiconductor device of Example 18, wherein the epitaxially deposited n-type heavily doped substrate layer is substantially free of crystal defects because the n-type lightly doped dummy substrate is substantially free of crystal defects.

[0076] Example 21 includes a method of manufacturing a semiconductor device, the method comprising: depositing a buffer layer on a crystalline dummy substrate; depositing a heavily doped crystalline substrate on the buffer layer, wherein the buffer layer is configured to prevent defects from propagating from the crystalline dummy substrate to the heavily doped crystalline substrate; and forming one or more regions of one or more devices around a surface of the heavily doped crystalline substrate.

[0077] Example 22 includes the method of manufacturing a semiconductor device of Example 21, the method further comprising: removing a crystal dummy substrate from a buffer layer, thereby leaving one or more regions of one or more devices formed around a heavily doped crystal substrate.

[0078] Example 23 includes the method of manufacturing a semiconductor device of Example 22, the method further comprising: removing a buffer layer from a heavily doped crystal substrate.

[0079] Example 24 includes the method of manufacturing a semiconductor device of Example 23, the method further comprising: thinning a heavily doped crystal substrate after removing a buffer layer.

[0080] Example 25 includes the method of manufacturing a semiconductor device of Example 21, wherein the deposition of a buffer layer includes: epitaxially depositing a semiconductor heavily doped with arsenic (Ar) or phosphorus (P).

[0081] For purposes of illustration and description, the foregoing description of specific embodiments of the present technology has been given. These descriptions are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and many modifications and variations will be apparent from the foregoing teachings. The embodiments were chosen and described in order to best explain the principles of the present technology and its practical application, thereby enabling others skilled in the art to best utilize the present technology and various embodiments with various modifications suited to their intended particular use. It is intended that the scope of the invention be defined by the appended claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, comprising: An n-type heavily doped crystal substrate is epitaxially deposited directly on the surface of an n-type lightly doped crystal virtual substrate, wherein the n-type lightly doped crystal virtual substrate is a silicon (Si) substrate and the n-type heavily doped crystal substrate is a silicon (Si) substrate, wherein the doping concentration of the n-type lightly doped crystal virtual silicon (Si) substrate is less than the doping concentration of the n-type heavily doped crystal silicon (Si) substrate, and wherein the n-type lightly doped crystal virtual silicon (Si) substrate is substantially free of crystal defects, and since the n-type lightly doped crystal virtual silicon (Si) substrate is substantially free of crystal defects, the epitaxially deposited n-type heavily doped crystal silicon (Si) substrate is substantially free of crystal defects. One or more regions of one or more devices are formed around the surface of the epitaxially deposited n-type heavily doped crystalline silicon (Si) substrate; The n-type lightly doped crystalline silicon (Si) substrate is removed from the epitaxially deposited n-type heavily doped crystalline silicon (Si) substrate, leaving the one or more regions of the one or more devices formed around the epitaxially deposited n-type heavily doped crystalline silicon (Si) substrate.

2. The method for manufacturing a semiconductor device according to claim 1, further comprising: Prior to forming the one or more regions of the one or more devices, the n-type heavily doped crystalline silicon (Si) substrate deposited on the n-type lightly doped crystalline virtual silicon (Si) substrate is annealed to reduce one or more types of defects in the n-type heavily doped crystalline silicon (Si) substrate.

3. The method for manufacturing a semiconductor device according to claim 1, further comprising: After removing the lightly doped n-type crystalline dummy silicon (Si) substrate, the heavily doped n-type crystalline silicon (Si) substrate is thinned.

4. The method for manufacturing a semiconductor device according to claim 1, further comprising: One or more additional regions of the one or more devices are formed around the n-type heavily doped crystalline silicon (Si) substrate.

5. The method for manufacturing a semiconductor device according to claim 1, further comprising: Before depositing the n-type heavily doped crystalline silicon (Si) substrate on the n-type lightly doped crystalline virtual silicon (Si) substrate, a barrier layer is deposited on the n-type lightly doped crystalline virtual silicon (Si) substrate, wherein the barrier layer is configured to reduce doping diffusion from the n-type heavily doped crystalline silicon (Si) substrate to the n-type lightly doped crystalline virtual silicon (Si) substrate.

6. The method of manufacturing a semiconductor device according to claim 1, wherein forming the one or more regions of the one or more devices comprises: Multiple gate trenches are formed in an n-type heavily doped substrate layer; Multiple gate dielectric regions are formed in the plurality of gate trenches; A plurality of gate regions are formed in the plurality of gate trenches, wherein the plurality of gate dielectric regions are disposed between the n-type heavily doped substrate layer and the plurality of gate regions; Multiple p-type doped regions are formed in a portion of the n-type heavily doped substrate layer, which is opposite to the n-type lightly doped dummy substrate. as well as A plurality of n-type doped source regions are formed in a portion of the plurality of p-type doped body regions opposite to the n-type heavily doped substrate layer.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The n-type lightly doped virtual substrate comprises lightly phosphorus (P)-doped silicon (Si); and The n-type heavily doped substrate layer includes silicon heavily doped with phosphorus.

8. A method for manufacturing a semiconductor device, comprising: A buffer layer of arsenic (Ar) or phosphorus (P) is directly deposited on the surface of an n-type lightly doped crystal virtual substrate. An n-type heavily doped crystal substrate is epitaxially deposited directly on the surface of the buffer layer opposite to the n-type lightly doped crystalline dummy substrate, wherein the buffer layer is configured to prevent defects from propagating from the crystalline dummy substrate to the n-type heavily doped crystal substrate, wherein the buffer layer is deposited to control the outward diffusion of n-type doping from the n-type heavily doped crystal substrate to the n-type lightly doped crystalline dummy substrate, wherein the n-type lightly doped crystalline dummy substrate is a silicon (Si) substrate, the n-type heavily doped crystal substrate is a silicon (Si) substrate, and wherein the n-type lightly doped crystalline dummy substrate is substantially free of crystal defects, and since the n-type lightly doped crystalline dummy substrate is substantially free of crystal defects, the epitaxially deposited n-type heavily doped crystal substrate is substantially free of crystal defects; and One or more regions of one or more devices are formed around the surface of the n-type heavily doped crystal substrate.

9. The method for manufacturing a semiconductor device according to claim 8, further comprising: The crystal dummy substrate is removed from the buffer layer, leaving the one or more regions of the one or more devices formed around the n-type heavily doped crystal substrate.

10. The method for manufacturing a semiconductor device according to claim 9, further comprising: Remove the buffer layer from the heavily doped n-type crystal substrate.

11. The method for manufacturing a semiconductor device according to claim 10, further comprising: After removing the buffer layer, the n-type heavily doped crystal substrate is thinned.

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