Electronic panel and electronic device including the same

Abstract

An electronic panel and an electronic device including the electronic panel are provided. The electronic panel may include a plurality of sensing electrodes and a plurality of sensing lines. The sensing lines may include a plurality of first-group sensing lines and a plurality of second-group sensing lines, and the plurality of first-group sensing lines and the plurality of second-group sensing lines are spaced apart from each other in a specific direction and are alternately arranged with respect to each other. Each of the first-group sensing lines and the second-group sensing lines may include a first pattern layer and a second pattern layer, the first pattern layer and the second pattern layer are spaced apart from each other and an insulating layer is disposed therebetween and they are bonded to each other through the insulating layer. Each of the first-group sensing lines may include the first pattern layer in a specific area, and each of the second-group sensing lines may include the second pattern layer in a specific area.

Description

[0001] This application claims the priority and benefit of Korean Patent Application No. 10-2019-0040674, filed on Apr. 8, 2019, which is hereby incorporated by reference in its entirety for all purposes as if fully set forth herein. TECHNICAL FIELD

[0002] Exemplary embodiments of the invention generally relate to an electronic panel and an electronic device including the electronic panel, and more particularly, to an electronic panel including a display unit and an input sensing unit and an electronic device including the electronic panel. BACKGROUND ART

[0003] An electronic device may be activated by an electrical signal. The electronic device can include various electronic components, such as a display unit for displaying an image or an input sensing unit for sensing an external input. The electronic components are electrically connected to each other through signal lines, and the signal lines may be arranged in various configurations.

[0004] The display unit may include emitting devices configured to generate an image. The input sensing unit may include sensing electrodes for sensing an external input. In the case where the electronic device includes a single panel in which both the display unit and the input sensing unit are provided, the assembly process may be simplified due to its simple structure. However, since the display unit and the input sensing unit are formed in a single panel, the process suffers from problems of high complexity and low reliability.

[0005] The above information disclosed in this background art section is only for understanding the background of the inventive concept, and thus, it may include information that does not constitute the prior art. SUMMARY OF THE INVENTION

[0006] An apparatus constructed according to an exemplary embodiment of the invention can provide a highly reliable electronic panel including a sensing unit and a display unit and an electronic device including the electronic panel.

[0007] Additional features of the inventive concept will be set forth in the description below, and will be apparent in part from the description, or may be learned by practice of the inventive concept.

[0008] According to an exemplary embodiment of the inventive concept, an electronic device may include: a display unit including a substrate base, a plurality of emitting devices, and a encapsulation layer, the substrate base including an active area and a peripheral area adjacent to the active area, the plurality of emitting devices being disposed in the active area, and the encapsulation layer covering the emitting devices; and an input sensing unit including a plurality of sensing electrodes and a plurality of sensing lines, the sensing electrodes being disposed on the display unit and overlapping with the active area, and the sensing lines being disposed in the peripheral area, electrically connected to the sensing electrodes respectively, and arranged in a specific direction in a specific area. Each sensing line may include a first pattern layer and a second pattern layer, the second pattern layer being disposed on a different layer from the first pattern layer and the second pattern layer being bonded to the first pattern layer. The sensing lines may include a first group of sensing lines and a second group of sensing lines, each first group of sensing lines having a single-layer structure in which the first pattern layer of the first pattern layer and the second pattern layer is selectively disposed in a specific area, and each second group of sensing lines having a single-layer structure in which the second pattern layer of the first pattern layer and the second pattern layer is selectively disposed in a specific area. The first group of sensing lines and the second group of sensing lines may be alternately arranged in a specific direction.

[0009] In an embodiment, the first pattern layer of each first group of sensing lines may extend in a direction crossing the specific direction to pass through the specific area, and the second pattern layer of each first group of sensing lines may include a first end portion cut in the specific area. The second pattern layer of each second group of sensing lines may extend in a direction crossing the specific direction to pass through the specific area, and the first pattern layer of each second group of sensing lines may include a second end portion cut in the specific area.

[0010] In an embodiment, the first end portion and the second end portion may be aligned in the specific direction.

[0011] In an embodiment, the first end portion may be arranged to be misaligned with the second end portion in the specific direction.

[0012] In an embodiment, the display unit may further include a structure pattern disposed in the specific area, and the structure pattern may include a recessed area or a protruding portion.

[0013] In an embodiment, the display unit may provide a non-flat surface corresponding to the shape of the structure pattern to the specific area.

[0014] In an embodiment, the encapsulation layer may cover the structure pattern to provide a flat surface to the specific area.

[0015] In an embodiment, the first pattern layer and the second pattern layer may have substantially the same width in the specific direction.

[0016] In an embodiment, the first pattern layer and the second pattern layer may have different widths from each other in the specific direction.

[0017] In an embodiment, the first pattern layer and the second pattern layer may have substantially the same resistance.

[0018] In an embodiment, when viewed in a plan view, the first pattern layer of the first group of sensing lines and the second pattern layer of the second group of sensing lines may be spaced apart from each other.

[0019] In an embodiment, when viewed in a plan view, the first pattern layer of the first group of sensing lines and the second pattern layer of the second group of sensing lines may be partially overlapped with each other.

[0020] In an embodiment, each sensing electrode may include a first sensing electrode and a second sensing electrode. The first sensing electrode includes a plurality of first sensing patterns and a plurality of first connection patterns that connect the first sensing patterns to each other. The second sensing electrode includes a plurality of second sensing patterns and a plurality of second connection patterns. The second sensing patterns are spaced apart from the first sensing patterns. The second connection patterns are spaced apart from the first connection patterns and an insulating layer is disposed therebetween, and the second connection patterns connect the second sensing patterns to each other. The first pattern layer and the second pattern layer may be spaced apart from each other, and an insulating layer is disposed between the first pattern layer and the second pattern layer.

[0021] According to an exemplary embodiment of the inventive concept, an electronic panel may include: a substrate layer including a plurality of emitting devices disposed in an active area and a structural pattern disposed in a peripheral area adjacent to the active area and including an insulating material; a plurality of sensing electrodes disposed on the substrate layer and in the active area; and a plurality of sensing lines disposed on the substrate layer and in the peripheral area and electrically connected to the sensing electrodes respectively. The sensing lines may include a plurality of first groups of sensing lines and a plurality of second groups of sensing lines. The first groups of sensing lines are spaced apart from each other in a specific direction. The second groups of sensing lines are respectively disposed between the first groups of sensing lines and are spaced apart from each other in a specific direction. Each of the first groups of sensing lines and the second groups of sensing lines may include a first pattern layer and a second pattern layer. The first pattern layer and the second pattern layer are spaced apart from each other and are bonded to each other through an insulating layer disposed between the first pattern layer and the second pattern layer. Each of the first groups of sensing lines may include only the first pattern layer among the first pattern layer and the second pattern layer in a specific area. Each of the second groups of sensing lines may include only the second pattern layer among the first pattern layer and the second pattern layer in a specific area.

[0022] In an embodiment, the structural pattern may include a recessed area or a protruding portion extending in a specific direction, and the substrate layer may provide a non-planar surface to a specific area.

[0023] In an embodiment, the substrate layer may further include an organic layer covering the structural pattern, and the organic layer may provide a planar surface to a specific area.

[0024] In an embodiment, when observed in a plan view, the first pattern layer and the second pattern layer may be spaced apart from each other in a specific region.

[0025] In an embodiment, when observed in a plan view, the first pattern layer and the second pattern layer may be partially overlapped with each other in a specific region.

[0026] In an embodiment, the bonding portion between the first pattern layer and the second pattern layer may be spaced apart from the specific region.

[0027] In an embodiment, each sensing electrode may include a first sensing electrode and a second sensing electrode. The first sensing electrode includes a plurality of first sensing patterns and a plurality of first connection patterns. The first connection patterns are disposed between the first sensing patterns to connect adjacent patterns in the first sensing patterns to each other. The second sensing electrode includes a plurality of second connection patterns and a plurality of second sensing patterns. The second connection patterns are spaced apart from the first connection patterns and an insulating layer is disposed therebetween. The second sensing patterns are spaced apart from the first sensing patterns and the second sensing patterns are connected to each other through the second connection patterns.

[0028] It will be understood that the foregoing general description and the following detailed description are both exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings illustrate exemplary embodiments of the invention and are used in conjunction with the description to explain the inventive concept, wherein the drawings are included to provide a further understanding of the invention and are incorporated into and constitute a part of this specification.

[0030] Figure 1A is a perspective view of an electronic device showing an exemplary embodiment according to the inventive concept.

[0031] Figure 1B is Figure 1A an exploded perspective view of the electronic device.

[0032] Figure 2A and Figure 2B are perspective views showing some elements of the electronic device constituting Figure 1B the electronic device.

[0033] Figure 2C is an exploded perspective view of an electronic panel according to an exemplary embodiment of the inventive concept.

[0034] Figure 3 is Figure 2A a cross-sectional view taken along line I-I' of

[0035] Figure 4A is a plan view showing a part of an electronic device according to an exemplary embodiment of the inventive concept.

[0036] Figure 4B is a cross-sectional view taken along line II-II' Figure 4A thereof.

[0037] Figure 4C is a cross-sectional view taken along line III-III' Figure 4A thereof.

[0038] Figure 5A is a cross-sectional view showing a part of an electronic device according to an exemplary embodiment of the inventive concept.

[0039] Figure 5B is a cross-sectional view showing a part of an electronic device according to an exemplary embodiment of the inventive concept.

[0040] Figure 6A is a plan view showing a part of an electronic device according to an exemplary embodiment of the inventive concept.

[0041] Figure 6B is a cross-sectional view taken along line IV-IV' Figure 6A thereof.

[0042] Figure 7A is a plan view showing a part of an electronic device according to an exemplary embodiment of the inventive concept.

[0043] Figure 7B is a cross-sectional view showing a part of an electronic device according to an exemplary embodiment of the inventive concept.

[0044] Figure 8A , Figure 8B , Figure 8C , Figure 8D and Figure 8E are cross-sectional views showing a method of manufacturing an electronic device according to an exemplary embodiment of the inventive concept.

[0045] It should be noted that these figures are intended to illustrate the general characteristics of the methods, structures, and / or materials used in specific example embodiments and are intended to supplement the written description provided below. However, these drawings are not drawn to scale and may not precisely reflect the exact structure or performance characteristics of any given embodiment, and should not be construed as defining or limiting the scope of values or properties covered by the example embodiments. For example, for clarity, the relative thicknesses and positions of molecules, layers, regions, and / or structural elements may be reduced or enlarged. The use of like or identical reference numerals in the various drawings is intended to indicate the presence of like or identical elements or features. Detailed Description

[0046] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various exemplary embodiments or implementations of the invention. As used herein, "embodiment" and "implementation" are interchangeable terms and are non-limiting examples of a device or method that employs one or more inventive concepts disclosed herein. However, it is apparent that the various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. Additionally, the various exemplary embodiments may be different but not necessarily exclusive. For example, without departing from the inventive concept, the specific shape, configuration, and characteristics of an exemplary embodiment may be used or implemented in another exemplary embodiment.

[0047] Unless otherwise stated, the exemplary embodiments shown are to be understood as providing exemplary features of the details of variations of some ways in which the inventive concept may be implemented in practice. Thus, unless otherwise stated, the features, components, modules, layers, films, panels, regions, and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of the various embodiments may be combined, separated, interchanged, and / or repositioned otherwise without departing from the inventive concept.

[0048] The use of cross-hatching and / or shading is generally provided in the drawings to clarify the boundaries between adjacent elements. Thus, unless stated otherwise, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement regarding the specific materials, material properties, dimensions, proportions, commonality between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements. Additionally, in the drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. When the exemplary embodiments may be implemented differently, a specific process order may be performed differently from the order described. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to the order described. Additionally, like reference numerals denote like elements.

[0049] When a layer or an element is referred to as being "on", "connected to", or "coupled to" another element or layer, the element can be directly on, directly connected to, or directly coupled to the other element or layer, or there can be intervening elements or layers. However, when an element or layer is referred to as being "directly on", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. For this reason, the term "connected" can mean a physical connection, an electrical connection, and / or a fluid connection with or without intervening elements. In addition, the DR1 axis, the DR2 axis, and the DR3 axis are not limited to the three axes of a rectangular coordinate system (such as the x-axis, the y-axis, and the z-axis), and can be interpreted in a broader sense. For example, the DR1 axis, the DR2 axis, and the DR3 axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as by way of example XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0050] Although terms such as "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, the first element discussed below could be termed a second element without departing from the teachings of the disclosure.

[0051] For descriptive purposes, spatial relative terms such as "beneath", "below", "under", "lower", "above", "upper", "on top of", "higher", "side" (e.g., as in "sidewall") etc. may be used herein to describe the relationship of one element to another (other) element as shown in the figures. Spatial relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as "beneath" or "below" another element or feature would then be oriented "above" the other element or feature. Thus, the exemplary term "beneath" can include both an orientation of above and below. In addition, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatial relative descriptors used herein would be interpreted accordingly.

[0052] The terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms as well. Further, when the terms "comprises", "comprising", and / or their variants are used in this specification, it is specified that there are the stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It is also noted that, as used herein, the terms "substantially", "about", and other similar terms are used as approximate terms and not as terms of degree, so as to be used to explain the inherent deviations of measured, calculated, and / or provided values that would be recognized by a person of ordinary skill in the art.

[0053] Various exemplary embodiments are described herein with reference to cross-sectional views and / or exploded views that are schematic diagrams of idealized exemplary embodiments and / or intermediate structures. As such, variations in the shapes illustrated, for example due to manufacturing techniques and / or tolerances, can be expected. Accordingly, the exemplary embodiments disclosed herein should not necessarily be construed as limited to the specifically shown shapes of the regions, but will include deviations in shapes due to, for example, manufacturing. In this manner, the regions shown in the figures can be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and thus are not necessarily intended to be limiting.

[0054] As is conventional in the art, some exemplary embodiments are described and illustrated in the figures in terms of functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc.) that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where the blocks, units, and / or modules are implemented by a microprocessor or other similar hardware, they can be programmed and controlled using software (e.g., microcode) that performs the various functions discussed herein, and can optionally be driven by firmware and / or software. It is also contemplated that each block, unit, and / or module can be implemented by dedicated hardware, or can be implemented as a combination of dedicated hardware that performs certain functions and a processor (e.g., one or more programmed microprocessors and associated circuits) that performs other functions. Further, without departing from the scope of the inventive concept, each block, unit, and / or module of some exemplary embodiments can be physically separated into two or more interacting and discrete blocks, units, and / or modules. Additionally, without departing from the scope of the inventive concept, the blocks, units, and / or modules of some exemplary embodiments can be physically combined into more complex blocks, units, and / or modules.

[0055] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains as a part thereof. Terms (such as those defined in a general dictionary) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless explicitly so defined herein.

[0056] Figure 1A is a perspective view showing an electronic device according to an embodiment of the inventive concept. Figure 1B is Figure 1A an exploded perspective view of the electronic device. Figure 2A and Figure 2B are perspective views showing some elements of the electronic device constituting Figure 1B the electronic device. Figure 2C is an exploded perspective view of an electronic panel according to an embodiment of the inventive concept. Hereinafter, embodiments of the inventive concept will be described with reference to Figures 1A to 2C the drawings.

[0057] As Figure 1A and Figure 1B shown in the drawings, the electronic device EA may include a front surface FS for displaying an image IM. The front surface FS may be defined as being parallel to a plane defined by a first direction DR1 and a second direction DR2. The front surface FS may include a transmissive area TA and a border area BZA adjacent to the transmissive area TA.

[0058] The electronic device EA may display the image IM in the transmissive area TA. The image IM may be at least one of a still image and a moving image. Figure 1A showing a clock and a plurality of icons as an example of the image IM.

[0059] The transmissive area TA is shown as having a rectangular shape having sides parallel to the first direction DR1 and the second direction DR2 and having rounded corners. However, the inventive concept is not limited to this example or a specific embodiment, and in an embodiment, various changes may be made to the shape of the transmissive area TA.

[0060] The border area BZA may be disposed adjacent to the transmissive area TA. The border area BZA may have a predetermined color. The border area BZA may surround the transmissive area TA. However, the inventive concept is not limited to this example, and in an embodiment, the border area BZA may be disposed adjacent to one of the side areas of the transmissive area TA or may be omitted. The inventive concept is not limited to a specific structure of the electronic device EA, and various changes may be made to the structure of the electronic device EA.

[0061] Hereinafter, the direction orthogonal to the front surface FS will be referred to as the thickness direction or the third direction DR3 of the electronic device EA. In this specification, based on the third direction DR3 or the display direction of the image IM, the front surface (or top surface) and the rear surface (or bottom surface) of each element or component can be distinguished from each other. For example, the front surface and the rear surface of each component can face away from each other in the third direction DR3. The directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 can be relative concepts, and in some embodiments, they can be used to indicate other directions. Hereinafter, the first direction, the second direction, and the third direction can be the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3, respectively, and the same reference numerals will be referred to.

[0062] The electronic device EA can sense a user input TC (which can also be referred to as an "external input TC") provided from the outside. The user input TC can include various types of external inputs such as a part of the user's body, light, heat, or pressure. In addition, the electronic device EA can sense an input in contact with or close to it.

[0063] In this embodiment, as Figure 1A shown, the user input TC can be input to the front surface FS through the user's hand. However, the inventive concept is not limited to this example, and in an embodiment, as described above, the user input TC can be provided in various forms. In addition, depending on the structure of the electronic device EA, the electronic device EA can sense the user input TC applied through the side surface or the rear surface of the electronic device EA, but the inventive concept is not limited to a specific embodiment.

[0064] As Figure 1B shown, the electronic device EA can include a window 100, an electronic panel 200, a circuit substrate 300, and a housing 400. The window 100 and the housing 400 can be combined with each other to define the appearance of the electronic device EA.

[0065] The window 100 can be disposed on the electronic panel 200 to cover the front surface IS of the electronic panel 200. The window 100 can include an optically transparent insulating material. For example, the window 100 can be formed of or include glass or plastic. The window 100 can have a multi-layer structure or a single-layer structure. For example, the window 100 can have a stacked structure including a plurality of plastic films bonded to each other through an adhesive layer, or can have a stacked structure including a glass substrate and a plastic film bonded to each other through an adhesive layer.

[0066] The window 100 can include a front surface FS exposed to the outside. The front surface FS of the electronic device EA can be substantially defined by the front surface FS of the window 100.

[0067] Specifically, the transmissive region TA may be an optically transparent region. The transmissive region TA may have a shape corresponding to the active region AA. For example, the transmissive region TA may overlap with the front surface or at least a part of the active region AA. An image IM displayed in the active region AA of the electronic panel 200 may be provided to a user through the transmissive region TA.

[0068] Compared with the transmissive region TA, the border region BZA may have a relatively low optical transmittance. The border region BZA may define the shape of the transmissive region TA. The border region BZA may be adjacent to the transmissive region TA and may surround the transmissive region TA.

[0069] The border region BZA may have a predetermined color. In the case where the window 100 is provided in the form of a glass substrate or a plastic substrate, the border region BZA may be a region formed by printing or depositing a color layer on the surface of the glass substrate or the plastic substrate. In some embodiments, the border region BZA may be formed by coloring a corresponding region of the glass substrate or the plastic substrate.

[0070] The border region BZA may cover the peripheral region NAA of the electronic panel 200 and may prevent the peripheral region NAA from being recognized by a user. However, the inventive concept is not limited to this example, and in an embodiment, the border region BZA may be omitted from the electronic device EA.

[0071] The electronic panel 200 may display an image IM and sense an external input TC. The electronic panel 200 may include an active region AA and a peripheral region NAA, which are separated from each other when observed in a plan view. The active region AA may be a region activated according to an electrical signal. In the present embodiment, the active region AA may be a region for displaying an image IM and for sensing an external input TC. However, the inventive concept is not limited to this example or a specific embodiment, and in an embodiment, the active region AA may be divided into a region for displaying an image IM and another region for sensing an external input TC.

[0072] The peripheral region NAA may be adjacent to the active region AA. The peripheral region NAA may surround the boundary of the active region AA. However, the inventive concept is not limited to this example or a specific embodiment, and in an embodiment, the peripheral region NAA may be adjacent to a part of the boundary of the active region AA.

[0073] Electronic components or various signal lines GL, DL, and PL or pads (or referred to as "bonding pads") PD for supplying electrical signals to the active region AA (see Figure 2C ) may be provided in the peripheral region NAA. The peripheral region NAA may be covered by the border region BZA and may not be recognized by a user.

[0074] In an embodiment, the electronic panel 200 may include a bendable portion or a foldable portion. For example, as Figure 2A and Figure 2B shown, the electronic panel 200 may include a non-bending portion NBR and a bending portion BR. Figure 2A shows the electronic panel 200 in a non-bent state, while Figure 2B shows the electronic panel 200 in a bent state.

[0075] The bending portion BR may be bent along a bending axis BX extending in a first direction DR1 by an external force. The bending axis BX may be defined on the rear surface of the electronic panel 200.

[0076] In an embodiment, the electronic panel 200 may further include a stress relief pattern SNP provided in the bending portion BR. The stress relief pattern SNP may be provided between the active area AA and a pad area PA in which pads PD are provided. The stress relief pattern SNP may include an organic material. The stress relief pattern SNP may prevent the bending portion BR from being damaged due to bending stress that may be generated when the bending portion BR is bent.

[0077] Since the bending portion BR is bent to surround the bending axis BX, the area of the peripheral area NAA seen from the front surface FS of the window 100 may be reduced. Accordingly, the bezel area BZA may be reduced, thereby improving the aesthetic quality of the electronic device EA. However, the inventive concept is not limited to this example, and in an embodiment, the bending portion BR may be omitted from the electronic panel 200.

[0078] As Figure 2C shown, the electronic panel 200 may include a display unit 210 and an input sensing unit 220. To provide a better understanding of the structure of the electronic panel 200, Figure 2C the display unit 210 and the input sensing unit 220 are shown separated from each other.

[0079] The display unit 210 may generate and display an image IM in the active area AA. The display unit 210 may include a substrate base BS, a plurality of signal lines GL, DL, PL, and RL, pixels PX, and a gate driving circuit (not shown).

[0080] The substrate base BS may have a planar shape corresponding to the planar shape of the electronic panel 200. Specifically, the substrate base BS may be an element that substantially provides the bending portion BR and the non-bending portion NBR. The substrate base BS may be flexible and thus may be bent. For example, the substrate base BS may be an insulating polymer film.

[0081] The signal lines GL, DL, PL, and RL may be disposed on the substrate base BS. The signal lines GL, DL, PL, and RL may include a gate line GL, a data line DL, a power line PL, and a routing line RL. The gate line GL, the data line DL, and the power line PL may be used to transmit different electrical signals from each other.

[0082] The gate line GL may extend in a first direction DR1. In an embodiment, a plurality of gate lines GL may be arranged to be spaced apart from each other in a second direction DR2. However, for ease of illustration, only one of the gate lines GL is exemplarily shown in Figure 2C . The gate line GL may be used to transmit a gate signal generated in a gate driving circuit (not shown) to the pixel PX.

[0083] The data line DL may extend in a second direction DR2. The data line DL may be electrically disconnected from the gate line GL. In an embodiment, a plurality of data lines DL may be arranged to be spaced apart from each other in a first direction DR1. However, for ease of illustration, only one of the data lines DL is exemplarily shown in Figure 2C . The data line DL may be used to transmit a data signal to the pixel PX.

[0084] The power line PL may extend in a second direction DR2. The power line PL may be electrically disconnected from the gate line GL and the data line DL. In an embodiment, a plurality of power lines PL may be arranged to be spaced apart from each other in a first direction DR1. However, for ease of illustration, only one of the power lines PL is exemplarily shown in Figure 2C . The power line PL may be used to transmit a power signal (hereinafter, a first power signal) to the pixel PX.

[0085] The routing line RL may be disposed in the peripheral area NAA. When viewed in a plan view, the routing line RL may overlap with the stress relief pattern SNP. The routing line RL may connect the pad PD to the corresponding signal line corresponding to the pad PD. The signal line may include a data line DL, a gate line GL, a line connected to the gate driving circuit, a line connected to the power line PL, and the like. However, the inventive concept is not limited to this example or a specific embodiment, and in an embodiment, at least one routing line RL and at least one signal line corresponding to the at least one routing line RL may be connected to form a single object.

[0086] The pixel PX may emit light constituting the image IM in response to an electrical signal. Figure 2C An example of an equivalent circuit diagram of one pixel PX is shown. In an embodiment, a plurality of pixels PX may be provided. However, for ease of illustration, only one of the pixels PX is exemplarily shown in Figure 2C . In some embodiments, various changes may be made to the circuit structure of the pixel PX, and the inventive concept is not limited to a specific embodiment.

[0087] A pixel PX may include a first thin-film transistor TR1, a second thin-film transistor TR2, a capacitor CPP, and an emitting device ELD. The first thin-film transistor TR1, the second thin-film transistor TR2, the capacitor CPP, and the emitting device ELD may be electrically connected to each other.

[0088] The first thin-film transistor TR1 may be a switching device configured to control the on / off operation of the pixel PX. The first thin-film transistor TR1 may be connected to a gate line GL and a data line DL. The first thin-film transistor TR1 may be turned on by a gate signal transmitted through the gate line GL, and in this case, a data signal transmitted through the data line DL may be provided to the capacitor CPP.

[0089] The capacitor CPP may be connected to the first thin-film transistor TR1 and a power line PL. The capacitor CPP may be used to store charge, and the amount of charge stored in the capacitor CPP may be determined by the voltage difference between the data signal transmitted from the first thin-film transistor TR1 and the first power voltage applied to the power line PL.

[0090] The second thin-film transistor TR2 may be connected to the first thin-film transistor TR1, the capacitor CPP, and the emitting device ELD. The second thin-film transistor TR2 may control the driving current flowing through the emitting device ELD according to the amount of charge stored in the capacitor CPP. The on-time of the second thin-film transistor TR2 may be determined according to the amount of charge stored in the capacitor CPP. During the on-time, the second thin-film transistor TR2 may provide the first power voltage transmitted through the power line PL to the emitting device ELD.

[0091] The emitting device ELD may generate light or control the amount of light according to an electrical signal. For example, the emitting device ELD may include an organic light-emitting device, a quantum dot light-emitting device, an electrophoretic device, or an electro-wetting device.

[0092] The emitting device ELD may be connected to the second thin-film transistor TR2 and a power terminal VSS. The emitting device ELD may emit light, and here, the intensity of the light emitted from the emitting device ELD may be determined by the voltage difference between the signal transmitted through the second thin-film transistor TR2 and the second power voltage received through the power terminal VSS. The light-emitting operation of the emitting device ELD may continue during the on-time of the second thin-film transistor TR2.

[0093] The emitting device ELD may include a light-emitting material. The color of the light to be emitted from the emitting device ELD may be determined according to the type of the light-emitting material. The color of the light to be emitted from the emitting device ELD may be one of red, green, blue, and white.

[0094] However, the inventive concept is not limited to this example or specific embodiments, and in an embodiment, the pixel PX may include a number of electronic components that can be configured and arranged in various ways.

[0095] The gate driving circuit may be disposed in the peripheral area NAA. The gate driving circuit may generate a gate driving signal. The gate line GL may be connected to the gate driving circuit to transmit the gate driving signal to the pixel PX. Meanwhile, in this embodiment, a gate driving circuit mounted on the substrate base BS may be provided. However, the inventive concept is not limited to this example, and in some embodiments, the gate driving circuit may be provided in the form of a chip, or may be mounted on an additional circuit substrate and then attached to the substrate base BS.

[0096] The input sensing unit 220 may be disposed on the display unit 210. The input sensing unit 220 may sense an external input TC and may obtain information about the position and intensity of the external input TC. The input sensing unit 220 may include a plurality of sensing electrodes TE1 and TE2, a plurality of sensing lines SL1 and SL2 (collectively, touch sensing lines TSL), and a plurality of terminal pads TP.

[0097] The sensing electrodes TE1 and TE2 may be disposed in the active area AA. The sensing electrodes TE1 and TE2 may include a first sensing electrode TE1 and a second sensing electrode TE2, and the first sensing electrode TE1 and the second sensing electrode TE2 receive different electrical signals from each other. The input sensing unit 220 may obtain information about the external input TC from a change in capacitance between the first sensing electrode TE1 and the second sensing electrode TE2.

[0098] The first sensing electrode TE1 may extend in the second direction DR2. In an embodiment, the first sensing electrodes TE1 may be arranged to be spaced apart from each other in the first direction DR1. The first sensing electrode TE1 may include a plurality of first sensing patterns SP1 and a plurality of first connection patterns BP1 arranged along the second direction DR2. The first sensing patterns SP1 and the first connection patterns BP1 may be alternately arranged in the second direction DR2. Each first connection pattern BP1 may connect two adjacent patterns among the first sensing patterns SP1.

[0099] The second sensing electrode TE2 may extend in the first direction DR1. In an embodiment, a plurality of second sensing electrodes TE2 may be arranged to be spaced apart from each other in the second direction DR2. The second sensing electrode TE2 may include a plurality of second sensing patterns SP2 and a plurality of second connection patterns BP2 arranged along the first direction DR1. The second sensing patterns SP2 and the second connection patterns BP2 may be alternately arranged in the first direction DR1. Each second connection pattern BP2 may connect two adjacent patterns among the second sensing patterns SP2.

[0100] In this embodiment, the first connection pattern BP1 and the second connection pattern BP2 may be disposed on different layers, while the first sensing pattern SP1 and the second sensing pattern SP2 may be disposed on the same layer. For example, the first connection pattern BP1 may be disposed on a layer different from the layer below the second connection pattern BP2, the first sensing pattern SP1, and the second sensing pattern SP2, while the second connection pattern BP2, the first sensing pattern SP1, and the second sensing pattern SP2 may be disposed on the same layer.

[0101] However, the inventive concept is not limited to this example or a specific embodiment. For example, in an embodiment, the first connection pattern BP1 may be disposed on the same layer as the layer below the first sensing pattern SP1 and the second sensing pattern SP2, or the first sensing electrode TE1 and the second sensing electrode TE2 may be disposed on different layers.

[0102] The sensing lines SL1 and SL2 and the terminal pads TP may be disposed in the peripheral area NAA. The terminal pads TP may be respectively connected to the sensing lines SL1 and SL2. The terminal pads TP may be electrically connected to the sensing pads PDT of the pads PD.

[0103] The sensing lines SL1 and SL2 may include a first sensing line SL1 and a second sensing line SL2. The first sensing line SL1 may connect one of the terminal pads TP corresponding to the first sensing electrode TE1 to the first sensing pattern SP1 and may transmit an electrical signal provided from the outside to the first sensing electrode TE1. The second sensing line SL2 may connect one of the terminal pads TP corresponding to the second sensing electrode TE2 to the second sensing pattern SP2 and may transmit an electrical signal provided from the outside to the second sensing electrode TE2.

[0104] Meanwhile, the pads PD may be disposed in the display unit 210. The pads PD may be disposed in the pad area PA of the peripheral area NAA. In this embodiment, the pad area PA is exemplarily shown as being disposed in the bending portion BR.

[0105] The pads PD may include display pads PDD and sensing pads PDT. The display pads PDD may provide electrical signals to the display unit 210. Specifically, the display pads PDD may provide electrical signals to the pixels PX and the gate driving circuit. For example, the display pads PDD may include pads respectively connected to the data lines DL, the power lines PL, the gate driving circuit, and the power terminal VSS.

[0106] The sensing pads PDT may provide electrical signals to the input sensing unit 220. For example, the sensing pads PDT may be respectively connected to the terminal pads TP of the input sensing unit 220. This will be described in more detail below.

[0107] According to an embodiment of the inventive concept, since the display pad PDD and the sensing pad PDT are disposed in a single pad area PA, the display unit 210 and the input sensing unit 220 can be driven simultaneously through one circuit substrate 300 and thus can be easily assembled. In addition, the entire process can be simplified. However, the inventive concept is not limited to this example or specific embodiments, and in the electronic panel 200 according to an embodiment, the sensing pad PDT may be disposed in the input sensing unit 220 and may be disposed in a space different from the display pad PDP.

[0108] Return reference Figure 1B , the circuit substrate 300 may be connected to the electronic panel 200. The circuit substrate 300 may include a flexible substrate CF and a main substrate MB. The flexible substrate CF may include an insulating film and conductive lines mounted on the insulating film. The conductive lines may be bonded to the pads PD to electrically connect the circuit substrate 300 to the electronic panel 200. Meanwhile, in this embodiment, the flexible substrate CF may be omitted, and in this case, the main substrate MB may be directly bonded to the electronic panel 200.

[0109] The main substrate MB may include signal lines (not shown) and electronic components (not shown). The electronic components may be bonded to the signal lines and may be electrically connected to the electronic panel 200. The electronic components may generate various electrical signals (e.g., electrical signals for generating an image IM or electrical signals for sensing an external input TC) or process the sensed signals. In an embodiment, the main substrate MB may include a plurality of electronic components, each of the plurality of electronic components being related to a corresponding signal to be generated or processed, but the inventive concept is not limited to this example or specific embodiments.

[0110] The housing 400 may be disposed under the electronic panel 200. Compared with the electronic panel 200, the housing 400 may include a material having a relatively high hardness. For example, the housing 400 may include a plurality of frames and / or plates, each of the frames and plates being formed of at least one of glass, plastic, and metal materials.

[0111] The housing 400 may provide a storage space. The electronic panel 200 and the circuit substrate 300 may be disposed in the storage space and may be protected from external impacts. According to an embodiment of the inventive concept, it may be possible to implement an electronic device EA providing a usage environment in which the electronic panel 200 is used not only for displaying an image IM but also for sensing an external input TC. In addition, it may be possible to reduce the thickness of the electronic device EA and more effectively assemble the electronic device EA.

[0112] Figure 3 is a cross-sectional view taken along Figure 2A the line I-I' of. Hereinafter, reference will be made to Figure 3Describe embodiments of the inventive concept. For the sake of brevity of description, elements previously described with reference to Figures 1A to 2C may be identified by the same reference numerals without repeating their repeated description.

[0113] As Figure 3 shown, the electronic panel 200 may include a display unit 210 and an input sensing unit 220. The display unit 210 may include a substrate base BS, a plurality of insulating layers 10, 20, 30, 40, 50, 60, 70, 80, and 90, thin film transistors TR, and emission devices ELD. The thin film transistors TR and the emission devices ELD may correspond to the second thin film transistors TR2 (e.g., see Figure 2C shown) and the emission devices ELD, respectively. Figure 2C )

[0114] The substrate base BS may include an insulating material. For example, the substrate base BS may include polyimide (PI). Thus, as Figure 2B shown, at least a part of the electronic panel 200 may be easily bent or folded. However, the inventive concept is not limited to this example, and in an embodiment, the substrate base BS may be provided as a rigid element. For example, the substrate base BS may be formed of at least one of various materials such as a glass material or a plastic material, but the inventive concept is not limited to a specific embodiment.

[0115] The first insulating layer 10 may be disposed on the substrate base BS to cover the front surface of the substrate base BS. The first insulating layer 10 may include a barrier layer and / or a buffer layer. Thus, the first insulating layer 10 may prevent oxygen or moisture entering through the substrate base BS from entering the pixel PX, or may reduce the surface energy of the substrate base BS to stably form the pixel PX on the substrate base BS. However, the inventive concept is not limited to this example or a specific embodiment, and in the electronic panel 200 according to an embodiment, at least one of the barrier layer and the buffer layer may be omitted or may have a structure in which a plurality of layers are stacked.

[0116] The thin film transistor TR may be disposed on the first insulating layer 10. The thin film transistor TR may include a semiconductor pattern SP, a control electrode CE, an input electrode IE, and an output electrode OE. The semiconductor pattern SP may be disposed on the first insulating layer 10. The semiconductor pattern SP may include a semiconductor material.

[0117] The control electrode CE may be spaced apart from the semiconductor pattern SP, and the second insulating layer 20 is disposed between the control electrode CE and the semiconductor pattern SP. The control electrode CE may be connected to one electrode of the first thin film transistor TR1 (e.g., see Figure 2C ) and the capacitor CPP (e.g., see Figure 2C ).

[0118] The third insulating layer 30 may be disposed on the control electrode CE to cover the control electrode CE. The fourth insulating layer 40 may be disposed on the third insulating layer 30 to cover the third insulating layer 30.

[0119] The input electrode IE and the output electrode OE may be disposed on the fourth insulating layer 40 and may be spaced apart from each other when viewed in a plan view. The input electrode IE and the output electrode OE of the thin film transistor TR may penetrate the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40 and may be respectively coupled to two opposite portions of the semiconductor pattern SP.

[0120] Each of the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40 may include an inorganic material and / or an organic material. For example, each of the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40 may include silicon nitride, silicon oxide, or a mixture thereof. Although each of the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40 is shown as having a single-layer structure, it may have a multi-layer structure, and the inventive concept is not limited to these examples or specific embodiments.

[0121] Meanwhile, in the present embodiment, the thin film transistor TR may further include an upper electrode UE. The upper electrode UE may be disposed between the third insulating layer 30 and the fourth insulating layer 40. When viewed in a plane, the upper electrode UE may be disposed such that it overlaps with the control electrode CE. The upper electrode UE may receive a voltage different from the voltage of the control electrode CE to generate an electric field together with the control electrode CE, or may receive the same voltage as the voltage of the control electrode CE to affect the mobility of the channel region of the thin film transistor TR. In the thin film transistor TR according to an embodiment of the inventive concept, the upper electrode UE may be omitted.

[0122] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 to cover the input electrode IE and the output electrode OE. The fifth insulating layer 50 may include an organic material and / or an inorganic material and may have a single-layer structure or a stacked structure. In the present embodiment, the fifth insulating layer 50 is shown as an inorganic layer.

[0123] In the thin film transistor TR, the semiconductor pattern SP may be disposed on the control electrode CE. In an embodiment, the semiconductor pattern SP may be disposed on the input electrode IE and the output electrode OE. In an embodiment, the input electrode IE and the output electrode OE may be disposed on the same layer as the layer under the semiconductor pattern SP and may be directly coupled to the semiconductor pattern SP. According to an embodiment of the inventive concept, various changes may be made to the structure of the thin film transistor TR, and the inventive concept is not limited to a specific embodiment.

[0124] The sixth insulating layer 60 may be disposed on the fifth insulating layer 50. The seventh insulating layer 70 may be disposed on the sixth insulating layer 60 to cover the sixth insulating layer 60. Each of the sixth insulating layer 60 and the seventh insulating layer 70 may include an inorganic material and / or an organic material. In the present embodiment, each of the sixth insulating layer 60 and the seventh insulating layer 70 is shown as an organic layer.

[0125] The emission device ELD may be disposed on the seventh insulating layer 70. In an embodiment, the electronic panel 200 may further include a connection electrode CN. The connection electrode CN may be disposed between the sixth insulating layer 60 and the seventh insulating layer 70. The connection electrode CN may connect the emission device ELD to the thin film transistor TR. In the electronic panel 200 according to an embodiment of the inventive concept, the connection electrode CN may be omitted, and in this case, the emission device ELD may be directly connected to the thin film transistor TR.

[0126] The emission device ELD may include a first electrode E1, an emission layer EL, and a second electrode E2. The first electrode E1 may penetrate the seventh insulating layer 70 and may be bonded to the connection electrode CN. The first electrode E1 may receive a voltage output from the thin film transistor TR through the connection electrode CN.

[0127] The eighth insulating layer 80 may be disposed on the seventh insulating layer 70. An opening 80_OP may be defined in the eighth insulating layer 80. The opening 80_OP may expose at least a portion of the first electrode E1. The eighth insulating layer 80 may include an organic material and / or an inorganic material. In the present embodiment, the eighth insulating layer 80 is shown as an organic layer. In the present embodiment, the eighth insulating layer 80 may serve as a pixel defining layer.

[0128] The emission layer EL may be disposed in the opening 80_OP and may be disposed on the first electrode E1 exposed by the opening 80_OP. The emission layer EL may include a light emitting material. For example, the emission layer EL may be formed of at least one of light emitting materials that emit red, green, and blue light, and may include at least one of a fluorescent material and a phosphorescent material. The emission layer EL may be formed of an organic light emitting material or an inorganic light emitting material such as a quantum dot or a quantum rod or may include an organic light emitting material or an inorganic light emitting material such as a quantum dot or a quantum rod. The emission layer EL may emit light in response to a potential difference between the first electrode E1 and the second electrode E2.

[0129] The second electrode E2 may be disposed on the emission layer EL. The second electrode E2 may be opposite to the first electrode E1. The second electrode E2 may be disposed as a single object continuously extending from the active region AA to the peripheral region NAA. The second electrode E2 may be commonly disposed in a plurality of pixels PX. The emission devices ELD respectively disposed in the pixels PX may receive a common second power voltage through the second electrode E2.

[0130] The second electrode E2 may be formed of a transparent conductive material or a transmissive reflective conductive material, or include a transparent conductive material or a transmissive reflective conductive material. Thus, the light generated by the emission layer EL can easily pass through the second electrode E2 and can propagate in the third direction DR3. However, the inventive concept is not limited to this example, and in an embodiment, the emission device ELD may be designed to have a backside emission structure or a double-sided emission structure, in the backside emission structure, the first electrode E1 includes a transparent material or a transmissive reflective material, and in the double-sided emission structure, light is emitted through its top surface and bottom surface.

[0131] Although not shown, the emission device ELD may further include a charge control layer disposed between the first electrode E1 and the emission layer EL or between the second electrode E2 and the emission layer EL. The charge control layer may include a hole transport material / hole injection material or an electron transport material / electron injection material. Optionally, the emission device ELD may further include a charge generation layer disposed between the first electrode E1 and the emission layer EL or between the second electrode E2 and the emission layer EL. In this case, the emission layer EL may be provided in multiple layers. Various changes may be made to the structure of the emission device ELD, and the inventive concept is not limited to a specific structure of the emission device ELD.

[0132] The ninth insulating layer 90 may be provided on the emission device ELD to encapsulate the emission device ELD. In this embodiment, the ninth insulating layer 90 may be an encapsulation layer. The ninth insulating layer 90 may be provided as a single object continuously extending from the active region AA to the peripheral region NAA. The ninth insulating layer 90 may be commonly provided in a plurality of pixels PX. Although not shown, a cover layer may also be provided between the second electrode E2 and the ninth insulating layer 90 to cover the second electrode E2.

[0133] The ninth insulating layer 90 may include a first inorganic layer 91, an organic layer 92, and a second inorganic layer 93 sequentially stacked in the third direction DR3. In this embodiment, each of the first inorganic layer 91, the organic layer 92, and the second inorganic layer 93 is shown as a single layer. However, the inventive concept is not limited to this example or a specific embodiment, and in an embodiment, at least one of the first inorganic layer 91, the organic layer 92, and the second inorganic layer 93 may be provided as a multi-layer structure or may be omitted.

[0134] The first inorganic layer 91 may cover the second electrode E2. The first inorganic layer 91 may prevent external moisture or oxygen from entering the emission device ELD. For example, the first inorganic layer 91 may include silicon nitride, silicon oxide, or a mixture thereof. The first inorganic layer 91 may be formed by a deposition process.

[0135] The organic layer 92 may be disposed on the first inorganic layer 91 and may be in contact with the first inorganic layer 91. The organic layer 92 may provide a flat surface on the first inorganic layer 91. Specifically, the organic layer 92 may provide a flat surface in the active region AA.

[0136] The organic layer 92 may cover uneven structures, particles, etc. present on the first inorganic layer 91. Thus, it is possible to prevent elements formed on the organic layer 92 from being affected by the surface state of the top surface of the first inorganic layer 91. In addition, the organic layer 92 may relieve stress between layers in contact with each other. The organic layer 92 may include an organic material and may be formed by a solution process such as a spin coating process, a slit coating process, and an inkjet process.

[0137] The second inorganic layer 93 may be disposed on the organic layer 92 to cover the organic layer 92. Compared with the case where the second inorganic layer 93 is formed on the first inorganic layer 91, due to the organic layer 92 having a relatively flat top surface, it may be possible to form the second inorganic layer 93 more stably. The second inorganic layer 93 may encapsulate the organic layer 92 and may prevent moisture in the organic layer 92 from leaking to the outside. The second inorganic layer 93 may include silicon nitride, silicon oxide, or a mixture thereof. The second inorganic layer 93 may be formed by a deposition process.

[0138] In an embodiment, the display unit 210 may further include thin film transistors (also referred to as driving transistors) disposed in the peripheral region NAA, a plurality of signal patterns VSS and E-CNT, a plurality of dam portions DM1 and DM2, a plurality of signal lines CL1, CL2, CL3, and CL4, a routing line RL, a stress relief pattern SNP, a cover pattern CVL, and a plurality of pads PDD.

[0139] The signal patterns VSS and E-CNT may include a power pattern VSS (hereinafter, referred to as “power terminal VSS”) and a connection electrode E-CNT. The power pattern VSS may be disposed between the fourth insulating layer 40 and the fifth insulating layer 50. In the present embodiment, the power pattern VSS is exemplarily shown as being disposed on the same layer as the layer below the input electrode IE or the output electrode OE of the thin film transistor TR. The power pattern VSS may be connected to one of the pads PDD to which a second power signal is applied through one of the routing lines RL and may receive the second power signal.

[0140] The connection electrode E-CNT may be disposed between the seventh insulating layer 70 and the eighth insulating layer 80. The connection electrode E-CNT and the first electrode E1 may be disposed on the same layer. The connection electrode E-CNT may be coupled to the power pattern VSS. The connection electrode E-CNT may cover the power pattern VSS exposed from the dam portions DM1 and DM2 and may extend to overlap the dam portions DM1 and DM2.

[0141] The connection electrode E-CNT can be coupled to the second electrode E2. The second electrode E2 can be coupled to the power pattern VSS through the connection electrode E-CNT and can receive a second power voltage.

[0142] A hole E-H can be defined in the connection electrode E-CNT. The hole E-H can be formed to penetrate the connection electrode E-CNT. In the case where gas is generated from the sixth insulating layer 60 or the seventh insulating layer 70 disposed under the connection electrode E-CNT during the process of forming the display unit 210, the gas can be easily degassed through the hole E-H. Accordingly, the connection electrode E-CNT or the second electrode E2 can be stably formed on the seventh insulating layer 70. However, the inventive concept is not limited to this example or a specific embodiment, and in an embodiment, the hole E-H may be omitted depending on the material of the sixth insulating layer 60 or the seventh insulating layer 70 or according to the forming process.

[0143] In an embodiment, a recessed region 80_V can be defined in the eighth insulating layer 80. The recessed region 80_V can be formed by removing a part of the eighth insulating layer 80 and can be formed to correspond to the opening 80_OP of the active area AA. In the present embodiment, the connection electrode E-CNT can be exposed through the recessed region 80_V. The second electrode E2 can be coupled to the connection electrode E-CNT through the recessed region 80_V. However, the inventive concept is not limited to this example. For example, in an embodiment, the recessed region 80_V can be formed in a region that does not overlap with the connection electrode E-CNT, and in this case, the second electrode E2 can be coupled to the connection electrode E-CNT at other positions.

[0144] In the present embodiment, the recessed region 80_V can provide a curved surface to the upper element. The recessed region 80_V can be a possible example of a structural pattern RP to be described below. The curved surface formed through the recessed region 80_V can be covered with the organic layer 92 and flattened. Accordingly, the input sensing unit 220 can be formed on the flattened surface.

[0145] However, the inventive concept is not limited to this example or a specific embodiment, and in an embodiment, depending on the coating amount of the organic layer 92, a curved surface formed through the recessed region 80_V can be provided to the input sensing unit 220. This will be described in more detail below.

[0146] The signal lines CL1, CL2, CL3, and CL4 can include at least one of a data line, a gate line, and various control signal lines electrically connected to the active area AA. The signal lines CL1, CL2, CL3, and CL4 can transmit corresponding voltages in an independent manner.

[0147] The signal lines CL1, CL2, CL3, and CL4 may constitute a gate driving circuit, or the signal lines CL1, CL2, CL3, and CL4 may include a first signal line CL1, a second signal line CL2, a third signal line CL3, and a fourth signal line CL4. The first signal line CL1 may be disposed between the sixth insulating layer 60 and the seventh insulating layer 70. In other words, the first signal line CL1 may be disposed on the same layer as the layer below the connection electrode CN.

[0148] As described above, the routing line RL may connect the pad PDD (e.g., see Figure 2C ) to a device or component disposed in the active area AA. The routing line RL may include at least one of a signal line connecting the first pad PD1 to the display unit 210 and a signal line connecting the second pad PD2 to the input sensing unit 220. In the present embodiment, one of the routing lines RL is exemplarily shown.

[0149] The routing line RL may electrically connect the first pattern PP1 constituting the second pad PD2 to the conductive line CL. Accordingly, even when a part of the electronic panel 200 is bent, the electrical signal received through the second pad PD2 may be provided to the active area AA through the routing line RL and the conductive line CL.

[0150] The stress relief pattern SNP may include an organic material. The stress relief pattern SNP may be disposed in the opening OP defined in the insulating layer. For example, the opening OP_1 penetrating the first insulating layer 10 and the second insulating layer 20 may be connected to the opening OP_2 penetrating the third insulating layer 30 and the fourth insulating layer 40 to form the opening OP.

[0151] According to an embodiment of the inventive concept, the insulating layers 10, 20, 30, 40, and 50 having relatively low flexibility may be removed from the region corresponding to the bending portion BR (e.g., see Figure 2C ), and the stress relief pattern SNP having relatively high flexibility may be disposed in the region. Accordingly, when the bending portion BR is bent, the bending stress applied to the electronic panel 200 may be reduced. Accordingly, when the bending portion BR is bent, the routing line RL may be prevented from being damaged, and the reliability of the electronic panel 200 may be improved. In the electronic panel 200 according to an embodiment of the inventive concept, the bending portion BR or the stress relief pattern SNP may be omitted, but the inventive concept is not limited to this example or a specific embodiment.

[0152] The covering pattern CVL can be disposed on the stress relief pattern SNP. The routing line RL can be covered by the covering pattern CVL. The covering pattern CVL can include a first layer I1, a second layer I2, and a third layer I3. The covering pattern CVL is shown as having a stacked structure. The covering pattern CVL can protect the stress relief pattern SNP and the routing line RL.

[0153] The dam portions DM1 and DM2 can include a first dam portion DM1 and a second dam portion DM2. The first dam portion DM1 and the second dam portion DM2 can be sequentially arranged in a direction away from the active area AA.

[0154] The dam portions DM1 and DM2 can prevent the organic layer 92 from overflowing. Each of the dam portions DM1 and DM2 can include two layers P1 and P2 or can include three layers P1, P2, and P3. Various changes can be made to the structure of each of the dam portions DM1 and DM2, but the inventive concept is not limited to a specific embodiment.

[0155] The pads PD1 and PD2 can include a first pad PD1 and a second pad PD2. The first pad PD1 can be disposed on the fourth insulating layer 40. The first pad PD1 is shown as having a single-layer structure, but this is only an example. In an embodiment, the first pad PD1 can have a stacked structure including multiple layers, but the inventive concept is not limited to a specific embodiment.

[0156] At least a portion of the first pad PD1 can be exposed by the insulating pattern IPP. The insulating pattern IPP can be disposed on the fourth insulating layer 40. The opening IPP_OP defined in the insulating pattern IPP can expose at least a portion of the first pad PD1. The circuit substrate 300 (e.g., see Figure 1B ) can be bonded to the exposed portion of the first pad PD1 and can be electrically connected to the electronic panel 200.

[0157] As shown, the second pad PD2 can have a stacked structure. For example, the second pad PD2 can include a first pattern PP1 disposed on the third insulating layer 30 and a second pattern PP2 disposed on the fourth insulating layer 40. The second pattern PP2 can penetrate the fourth insulating layer 40 and can be bonded to the first pattern PP1. The circuit substrate 300 can be electrically connected to the electronic panel 200 through the second pattern PP2.

[0158] The first pad PD1 and the second pad PD2 can receive substantially different electrical signals from each other. For example, the first pad PD1 can be one of the display pads PDD (e.g., see Figure 2C ), and the second pad PD2 can be the sensing pad PDT (e.g., see Figure 2C) among them. In an embodiment, the pads for driving the input sensing unit 220 and the pads for sensing the display unit 210 may be provided in a single electronic panel 200. Accordingly, it may be possible to increase the integration density of the electronic panel 200 and reduce the thickness of the electronic device EA (e.g., see Figure 1A )).

[0159] The input sensing unit 220 may include a first insulating sensing layer TIS1, a second insulating sensing layer TIS2, a plurality of first patterns MT1, and a plurality of second patterns MT2. The first patterns MT1 and the second patterns MT2 may be provided on different layers from each other. The first patterns MT1 may be provided between the first insulating sensing layer TIS1 and the second insulating sensing layer TIS2, and the second patterns MT2 may be provided on the second insulating sensing layer TIS2. In the present embodiment, at least a part of the first patterns MT1 is shown to be bonded to the second patterns MT2.

[0160] The first patterns MT1 and the second patterns MT2 may constitute a first sensing electrode TE1 (e.g., see Figure 2C ) and a second sensing electrode TE2 (e.g., see Figure 2C ). For example, the first patterns MT1 may constitute a first connection pattern BP1 (e.g., see Figure 2C ), and the second patterns MT2 may constitute a first sensing pattern SP1 and a second sensing pattern SP2 (e.g., see Figure 2C ) and a second connection pattern BP2 (e.g., see Figure 2C ). In some embodiments, for example, the first patterns MT1 may constitute the second connection pattern BP2, and the second patterns MT2 may constitute the first sensing pattern SP1 and the second sensing pattern SP2 and the first connection pattern BP1. In some embodiments, the first patterns MT1 may constitute the first sensing pattern SP1 and the second sensing pattern SP2 and the first connection pattern BP1, and the second patterns MT2 may constitute the second connection pattern BP2.

[0161] In some embodiments, the first patterns MT1 may constitute the first sensing electrode TE1, and the second patterns MT2 may constitute the second sensing electrode TE2. Here, the first patterns MT1 and the second patterns MT2 may not be bonded to each other. The electronic device EA according to an embodiment of the inventive concept may include the input sensing unit 220 having various structures, but the inventive concept is not limited to this example.

[0162] Each of the first insulating sensing layer TIS1 and the second insulating sensing layer TIS2 may include an insulating material. Each of the first insulating sensing layer TIS1 and the second insulating sensing layer TIS2 may include an organic material and / or an inorganic material. In the present embodiment, the first insulating sensing layer TIS1 is exemplarily shown as an inorganic layer. Accordingly, the first insulating sensing layer TIS1 may provide a surface to the first pattern MT1 that reflects the shape of the top surface provided by the display unit 210 (specifically, the second inorganic layer 93). This will be described in more detail below.

[0163] In an embodiment, the input sensing unit 220 may further include a first pattern layer L1 and a second pattern layer L2. The first pattern layer L1 and the second pattern layer L2 may be disposed in the peripheral area NAA. The first pattern layer L1 and the second pattern layer L2 may be disposed on different layers from each other. In the present embodiment, the first pattern layer L1 may be disposed on the same layer as the layer below the first pattern MT1, and the second pattern layer L2 may be disposed on the same layer as the layer below the second pattern MT2. The first pattern layer L1 and the second pattern layer L2 may form Figure 2C the sensing lines SL1 and SL2 shown in. This will be described in more detail below.

[0164] According to an embodiment of the inventive concept, at least a portion of the sensing lines SL1 and SL2 may include the first pattern layer L1 and the second pattern layer L2 that are alternately arranged. The first pattern layer L1 and the second pattern layer L2 may be electrically disconnected from each other, and the second insulating sensing layer TIS2 may be disposed between the first pattern layer L1 and the second pattern layer L2. Accordingly, it may be possible to effectively prevent a short circuit problem from occurring between adjacent sensing lines in the sensing lines SL1 and SL2. This will be described in more detail below.

[0165] Figure 4A is a plan view showing a part of an electronic device according to an embodiment of the inventive concept. Figure 4B is a cross-sectional view taken along the line Figure 4A II-II'. Figure 4C is a cross-sectional view taken along the line Figure 4A III-III'. Hereinafter, embodiments of the inventive concept will be described with reference to Figures 4A to 4C For the sake of brevity of description, the elements previously described with reference to Figures 1A to 3 may be identified by the same reference numerals without repeating their repeated description.

[0166] For ease of explanation and description, Figure 4ATen sensing lines SLn1, SLn2, SLn3, SLn4, SLn5, SLm1, SLm2, SLm3, SLm4, and SLm5 are shown. Each of the sensing lines SLn1, SLn2, SLn3, SLn4, SLn5, SLm1, SLm2, SLm3, SLm4, and SLm5 can correspond to one of the sensing lines SL1 and SL2 shown in Figure 2C For example, all ten sensing lines SLn1, SLn2, SLn3, SLn4, SLn5, SLm1, SLm2, SLm3, SLm4, and SLm5 can be the first sensing line SL1 or can be the second sensing line SL2. Optionally, some of the ten sensing lines SLn1, SLn2, SLn3, SLn4, SLn5, SLm1, SLm2, SLm3, SLm4, and SLm5 can be the first sensing line SL1, while the other sensing lines can be the second sensing line SL2.

[0167] The ten sensing lines SLn1, SLn2, SLn3, SLn4, SLn5, SLm1, SLm2, SLm3, SLm4, and SLm5 can include a first group of sensing lines SLn1, SLn2, SLn3, SLn4, and SLn5 (which can be referred to as the first group of sensing lines SLn) and a second group of sensing lines SLm1, SLm2, SLm3, SLm4, and SLm5 (which can be referred to as the second group of sensing lines SLm). The sensing lines SLn1, SLn2, SLn3, SLn4, and SLn5 of the first group and the sensing lines SLm1, SLm2, SLm3, SLm4, and SLm5 of the second group can be arranged alternately with respect to each other. Thus, two adjacent lines among the sensing lines can be included in different first and second groups respectively.

[0168] Each of the sensing lines SLn1, SLn2, SLn3, SLn4, and SLn5 of the first group and the sensing lines SLm1, SLm2, SLm3, SLm4, and SLm5 of the second group can extend along a flat region FA, a non-flat region NFA, and a flat region FA.

[0169] Compared with the flat region FA, the non-flat region NFA can be a region that provides a relatively uneven surface to the input sensing unit 220. The non-flat region NFA can be formed by the recessed region 80_V or the dam portions DM1 and DM2 described above, or can be a region where less organic layer 92 is coated thereon.

[0170] In the present embodiment, for ease of illustration or description, the structural pattern RP is shown with a hatched pattern. The structural pattern RP may be disposed in the non-flat area NFA to provide a curved surface to the input sensing unit 220. The structural pattern RP may extend in a direction crossing the arrangement direction of the sensing lines SLn1, SLn2, SLn3, SLn4, SLn5, SLm1, SLm2, SLm3, SLm4, and SLm5. The structural pattern RP may be a convex pattern or a concave pattern.

[0171] Each of the sensing lines SLn1, SLn2, SLn3, SLn4, and SLn5 of the first group and the sensing lines SLm1, SLm2, SLm3, SLm4, and SLm5 of the second group may have a stacked structure including multiple layers in the flat area FA and may have a single-layer structure in the non-flat area NFA. Specifically, each of the sensing lines SLn1, SLn2, SLn3, SLn4, and SLn5 of the first group and the sensing lines SLm1, SLm2, SLm3, SLm4, and SLm5 of the second group may include a first pattern layer L1 and a second pattern layer L2. The first pattern layer L1 and the second pattern layer L2 may be disposed on different layers from each other.

[0172] The first pattern layer L1 may be disposed between the base layer BSL and the second insulating sensing layer TIS2. The first pattern layer L1 may substantially correspond to the first pattern layer L1 shown in Figure 3 . The base layer BSL may be a layer including the display unit 210 and the first insulating sensing layer TIS1.

[0173] The second pattern layer L2 may be disposed on the second insulating sensing layer TIS2. The second pattern layer L2 may extend along the first pattern layer L1. The second pattern layer L2 may be coupled to the first pattern layer L1 through a contact portion CNT formed to penetrate the second insulating sensing layer TIS2.

[0174] When observed in a cross-sectional view, the first pattern layer L1 and the second pattern layer L2 constituting each of the sensing lines SLn1, SLn2, SLn3, SLn4, and SLn5 of the first group and the sensing lines SLm1, SLm2, SLm3, SLm4, and SLm5 of the second group may be stacked, and the second insulating sensing layer TIS2 may be disposed between the first pattern layer L1 and the second pattern layer L2. The first pattern layer L1 and the second pattern layer L2 may be sequentially stacked in the flat area FA, while only one of the first pattern layer L1 and the second pattern layer L2 may be disposed in the non-flat area NFA.

[0175] Specifically, each of the sensing lines SLn1, SLn2, SLn3, SLn4, and SLn5 in the first group may have a structure in which the first pattern layer L1 and the second pattern layer L2 are stacked in the flat area FA, and may have a structure including only the second pattern layer L2 in the non-flat area NFA. A portion of the first pattern layer L1 corresponding to the non-flat area NFA may be removed to form an end portion EG in the first pattern layer L1.

[0176] Similarly, each of the sensing lines SLm1, SLm2, SLm3, SLm4, and SLm5 in the second group may have a structure in which the first pattern layer L1 and the second pattern layer L2 are stacked in the flat area FA, and may have a structure including only the first pattern layer L1 in the non-flat area NFA. A portion of the second pattern layer L2 corresponding to the non-flat area NFA may be removed to form an end portion EG in the second pattern layer L2.

[0177] Accordingly, the first pattern layer L1 and the second pattern layer L2 of each of the sensing lines SLn1, SLn2, SLn3, SLn4, and SLn5 in the first group and the sensing lines SLm1, SLm2, SLm3, SLm4, and SLm5 in the second group may be alternately arranged in a certain direction in the non-flat area NFA. In other words, the pattern adjacent to the first pattern layer L1 disposed in the non-flat area NFA may be the second pattern layer L2.

[0178] The first width W1 of the first pattern layer L1 and the second width W2 of the second pattern layer L2 may be designed in an independent manner from each other. In the present embodiment, as shown, the first width W1 and the second width W2 may be equal to each other.

[0179] The second pattern layer L2 may be disposed in a space SS between a pair of first pattern layers L1. In the present embodiment, the distance DT between the first pattern layer L1 and the second pattern layer L2 is shown to be uniform. In the present embodiment, the distance DT between the first pattern layer L1 and the second pattern layer L2 may be equal to or greater than approximately 19 μm. According to an embodiment of the inventive concept, even when the distance DT between the first pattern layer L1 and the second pattern layer L2 is relatively small, since the first pattern layer L1 and the second pattern layer L2 may be disposed on different layers, it may also be possible to effectively prevent a short circuit problem from occurring.

[0180] According to an embodiment of the inventive concept, the first pattern layer L1 and the second pattern layer L2 may be spatially separated from each other and electrically separated from each other, and the second insulating sensing layer TIS2 is disposed between the first pattern layer L1 and the second pattern layer L2. Accordingly, it may be possible to effectively prevent a short circuit problem from occurring between the second set of sensing lines SLm1, SLm2, SLm3, SLm4, and SLm5 and the first set of sensing lines SLn1, SLn2, SLn3, SLn4, and SLn5. Each of the second set of sensing lines SLm1, SLm2, SLm3, SLm4, and SLm5 has the first pattern layer L1 in the non-flat area NFA, and each of the first set of sensing lines SLn1, SLn2, SLn3, SLn4, and SLn5 has the second pattern layer L2 in the non-flat area NFA.

[0181] In addition, since the first set of sensing lines SLn1, SLn2, SLn3, SLn4, and SLn5 and the second set of sensing lines SLm1, SLm2, SLm3, SLm4, and SLm5 are alternately arranged relative to each other, it may be possible to achieve a relatively large distance between the first pattern layers L1 or between the second pattern layers L2 provided on the same layer. Accordingly, it may be possible to effectively reduce the short circuit problem between the sensing lines SLn1, SLn2, SLn3, SLn4, SLn5, SLm1, SLm2, SLm3, SLm4, and SLm5 and improve the reliability of the electronic device EA.

[0182] Figure 5A is a cross-sectional view showing a part of an electronic device according to an embodiment of the inventive concept. Figure 5B is a cross-sectional view showing a part of an electronic device according to an embodiment of the inventive concept. Figure 5A and Figure 5B show the area Figure 4B substantially corresponding to. Hereinafter, embodiments of the inventive concept will be described with reference to Figure 5A and Figure 5B Description of embodiments of the inventive concept.

[0183] As Figure 5A shown, the electronic panel 200-1 may include a substrate layer BSL, a first pattern layer MTL1, a second insulating sensing layer TIS2, and a second pattern layer MTL2. The substrate layer BSL may include a substrate BSS, a structural pattern RP, a first inorganic layer 91, an organic layer 92, a second inorganic layer 93, and a first insulating sensing layer TIS1. The first inorganic layer 91, the organic layer 92, and the second inorganic layer 93 may correspond to the first inorganic layer 91, the organic layer 92, and the second inorganic layer 93 shown in Figure 3 respectively, and the substrate BSS and the structural pattern RP may include those provided in Figure 3The insulating layer and the device or component below the first inorganic layer 91 shown in. For example, the structural pattern RP may include a recessed region 80_V (e.g., see Figure 3 ) or dam portions DM1 and DM2. In the present embodiment, for ease of illustration or description, prominent patterns such as dam portions DM1 and DM2 are shown as the structural pattern RP.

[0184] The non-flat surface provided by the structural pattern RP may be covered with the organic layer 92 and planarized. When the coating amount of the organic layer 92 is sufficient, the organic layer 92 may fill the stepped structure AA' between the structural pattern RP and the substrate BSS and may provide a flat top surface. Accordingly, the second inorganic layer 93 may be formed on the flat surface to provide a flat surface to the input sensing unit 220.

[0185] In some embodiments, as Figure 5B shown, the organic layer 92 may be omitted from the electronic panel 200-2. The electronic panel 200-2 may be an embodiment in which the formation amount of the organic layer 92 is less than that of the organic layer 92 of the Figure 5A electronic panel 200-1. Accordingly, the stepped structure AA' between the structural pattern RP and the substrate BSS may be transcribed onto the second inorganic layer 93 to form a stepped structure BB' in the surface on which the input sensing unit 220 will be disposed.

[0186] The curved surface caused by the stepped structure BB' may cause a photoresist patterning failure during the process of patterning the second pattern layer L2, and thus photoresist residues or residues of the second pattern layer L2 may remain after the patterning process.

[0187] In the electronic panel 200-2 according to an embodiment of the inventive concept, even when the stepped structure BB' is formed by the structural pattern RP, the first pattern layer L1 having a single-layer structure may be used to form sensing lines in the curved surface, and thus, it may be possible to prevent or suppress the interference problem between the sensing lines caused by the residues of the second pattern layer L2. In addition, it may be possible to increase the distance between conductive patterns provided on the same layer. Accordingly, it may be possible to more effectively prevent a short-circuit problem between adjacent sensing lines near the stepped structure BB' and improve the reliability of the electronic panel 200-1 or 200-2.

[0188] Figure 6A is a plan view showing a part of an electronic device according to an embodiment of the inventive concept. Figure 6B is a cross-sectional view taken along the line Figure 6A IV-IV'. Figure 6B The region of Figure 4B may substantially correspond to the region shown in Figure 6Aand Figure 6B Describe embodiments of the inventive concept. For the sake of brevity of description, elements previously referred to Figures 1A to 5B described may be identified by the same reference numerals without repeating their repeated description.

[0189] As Figure 6A shown, the electronic panel 200-A may include a plurality of first-group sensing lines SLna and a plurality of second-group sensing lines SLma. Each of the first-group sensing lines SLna and the second-group sensing lines SLma may have a stacked structure composed of a first pattern layer L1a and a second pattern layer L2a in a flat area FA, and may have a single-layer structure composed of the first pattern layer L1a or the second pattern layer L2a in a non-flat area NFA.

[0190] Meanwhile, in the present embodiment, the first-group sensing lines SLna may include first pattern layers L1a and L1b having different widths from each other. Specifically, the first-group sensing lines SLna may be composed of the first pattern layer L1a having a first width W11a in the non-flat area NFA or the first pattern layer L1b having a second width W11b in the non-flat area NFA. The second width W11b may be larger than the first width W11a. When there is an unpatterned problem in the non-flat area NFA, the first pattern layer L1b having the second width W11b may be formed. For example, due to the structural pattern RP, the first pattern layer L1b may be formed in the non-flat area NFA to have a second width W11b that is larger than the first width W11a and is non-uniform.

[0191] The second-group sensing lines SLma may include second pattern layers L2a and L2b in the non-flat area NFA. In Figure 6B it, a pair of second pattern layers L2a and L2b spaced apart from each other are shown to have the same width (e.g., W21).

[0192] When observed in a plan view, some of the second-group sensing lines SLma may overlap with the first pattern layer L1b having the second width W11b. Specifically, the second-group sensing lines SLma may include the second pattern layer L2a disposed between the first-group sensing lines SLna and disposed in the non-flat area NFA, and the second pattern layer L2b overlapping with some of the first-group sensing lines SLna. Even if the distance between the second-group sensing lines SLma and the first-group sensing lines SLna is designed to have a constant value, due to process errors, some of the second-group sensing lines SLma may overlap with the first pattern layer L1b.

[0193] According to an embodiment of the inventive concept, the second group of sensing lines SLma may have a single-layer structure composed of second pattern layers L2a and L2b in the non-flat area NFA. Accordingly, even when the first pattern layer L1b and the second pattern layer L2b are stacked on each other, since the first pattern layer L1b and the second pattern layer L2b may be disposed at different layers and the second insulating sensing layer TIS2 is disposed between the first pattern layer L1b and the second pattern layer L2b, it is possible to prevent a short circuit from being formed between the first pattern layer L1b and the second pattern layer L2b.

[0194] According to an embodiment of the inventive concept, due to the structural pattern RP, even when there is an error in the process of patterning the sensing lines in the non-flat area NFA, it is possible to effectively prevent a short circuit from being formed between adjacent sensing lines. This can make it possible to improve the reliability of the electronic panel 200-A.

[0195] Figure 7A is a plan view showing a part of an electronic device according to an embodiment of the inventive concept. Figure 7B is a cross-sectional view showing a part of an electronic device according to an embodiment of the inventive concept. Figure 7A The area shown in Figure 4A may substantially correspond to the area shown in Figure 7B The area shown in Figure 4C may substantially correspond to the area shown in

[0196] Hereinafter, embodiments of the inventive concept will be described with reference to Figure 7A and Figure 7B For the sake of brevity of description, the elements previously described with reference to Figures 1A to 6B may be identified by the same reference numerals without repeating their repeated description.

[0197] As Figure 7A shown, in the electronic panel 200-B, the contact portions CNT1 of the first group of sensing lines SLnb and the contact portions CNT2 of the second group of sensing lines SLmb may be alternately arranged with respect to each other in a specific direction. Specifically, the contact portions CNT2 of the second group of sensing lines SLmb may be disposed farther from the non-flat area NFA than the contact portions CNT1 of the first group of sensing lines SLnb. Accordingly, the end portions EG1 of the first pattern layer L12 of the first group of sensing lines SLnb and the end portions EG2 of the second pattern layer L22 of the second group of sensing lines SLmb may be alternately arranged with respect to each other.

[0198] According to an embodiment of the inventive concept, since the contact portions CNT1 and CNT2 and the end portions EG1 and EG2 adjacent to each other in the flat region FA are alternately arranged with respect to each other, it is possible to effectively suppress or prevent a short circuit problem that may occur between adjacent patterns due to process errors or the like.

[0199] Optionally, as Figure 7B shown in, in the electronic panel 200-C, the first pattern layer L12 and the second pattern layer L22 may have different shapes from each other. The first pattern layer L12 may have a first width W12 and a first thickness T1, and the second pattern layer L22 may have a second width W22 and a second thickness T2.

[0200] The first width W12 may be larger than the second width W22, and the first thickness T1 may be smaller than the second thickness T2. According to an embodiment of the inventive concept, by increasing the width but decreasing the thickness, it is possible to achieve a desired or designed resistance of the first pattern layer L12. Similarly, by decreasing the width but increasing the thickness, it is possible to achieve a desired or designed resistance of the second pattern layer L22. According to an embodiment of the inventive concept, the first pattern layer L12 and the second pattern layer L22 may be designed in various shapes according to their desired resistance values, but the inventive concept is not limited to this example. In an embodiment, the first pattern layer L12 and the second pattern layer L22 may have the same resistance.

[0201] In addition, in the electronic panel 200-C, since the first width W12 of the first pattern layer L12 increases, the distance SS2 between the first pattern layers L12 provided in a given region may be decreased. According to an embodiment of the inventive concept, by increasing the second thickness T2 of the second pattern layer L22 but decreasing the second width W22, it is possible to stably form a pattern having a designed resistance in the region where the distance SS2 is decreased. Accordingly, the reliability of the electronic panel 200-C may be improved.

[0202] Figures 8A to 8E is a cross-sectional view showing a method of manufacturing an electronic device according to an embodiment of the present inventive concept. For convenience of description and illustration, Figures 8A to 8E shows a manufacturing process performed at a region corresponding to the region shown in Figure 4C . Hereinafter, embodiments of the inventive concept will be described with reference to Figures 8A to 8E . To make the description concise, the elements previously described with reference to Figures 1A to 7B may be identified by the same reference numerals without repeating their repeated description.

[0203] As Figure 8AAs shown in [Fig. 0], a conductive layer CLL and a photoresist layer PRL can be sequentially formed on a substrate layer BSL. The conductive layer CLL can be formed by depositing or coating a conductive material on the substrate layer BSL. The photoresist layer PRL can be formed by coating a photoresist material on the conductive layer CLL.

[0204] Next, as Figure 8B shown in [Fig. 1], the photoresist layer PRL can be patterned to form a photoresist pattern PR. The photoresist pattern PR can be formed by removing portions of the photoresist layer PRL using a mask (not shown). As a result, an opening PR_OP can be formed in the photoresist pattern PR.

[0205] Subsequently, as Figure 8C shown in [Fig. 2], the conductive layer CLL can be patterned to form a first pattern layer L1. The first pattern layer L1 can be formed by removing the portions of the conductive layer CLL exposed by the opening PR_OP of the photoresist pattern PR. The first pattern layer L1 can include patterns spaced apart from each other by a specific distance SS, and each pattern has a first width W1.

[0206] Next, as Figure 8D shown in [Fig. 3], a second insulating sensing layer TIS2 can be formed. The second insulating sensing layer TIS2 can be formed by depositing or coating an insulating material. The second insulating sensing layer TIS2 can be formed to cover the first pattern layer L1.

[0207] Subsequently, as Figure 8E shown in [Fig. 4], a second pattern layer L2 can be formed on the second insulating sensing layer TIS2. The second pattern layer L2 can be formed between the patterns of the first pattern layer L1 such that the second pattern layer L2 has a width smaller than the distance SS of the space between the patterns, but the inventive concept is not limited to this example. In an embodiment, the second pattern layer L2 can have a second width W2 and can be spaced apart from the first pattern layer L1 by a specific distance DT.

[0208] According to an embodiment of the inventive concept, the first pattern layer L1 and the second pattern layer L2 can be formed by different processes, and the first pattern layer L1 and the second pattern layer L2 can be disposed on different layers from each other. Accordingly, it can be possible to prevent a short circuit problem from occurring between the first pattern layer L1 and the second pattern layer L2 adjacent to each other and improve the reliability of the electronic device.

[0209] According to an embodiment of the inventive concept, in the input sensing unit, it is possible to effectively prevent a short circuit from being formed between adjacent sensing lines in the sensing lines for transmitting an electrical signal to the sensing electrodes. Accordingly, even if the display unit provides a non-flat surface, the input sensing unit can be stably formed on the display unit, and thus, it is possible to improve the reliability of an electronic device including the display unit and the input sensing unit.

[0210] Although specific exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, the inventive concept is not limited to such embodiments, but rather to the claims and the broader scope of various modifications and equivalent arrangements that will be apparent to those of ordinary skill in the art.

Claims

1. An electronic device, the electronic device comprising: A display unit, comprising: a substrate base including an active area and a peripheral area adjacent to the active area; a plurality of emitting devices disposed in the active area; and an encapsulation layer covering the plurality of emitting devices; and An input sensing unit, comprising: a plurality of sensing electrodes disposed on the display unit and overlapping with the active area; and a plurality of sensing lines disposed in the peripheral area, electrically connected to the plurality of sensing electrodes respectively, and arranged in a first direction intersecting with an extending direction of the plurality of sensing lines in a non-flat area of the peripheral area, Wherein each of the plurality of sensing lines includes: a first pattern layer; and a second pattern layer disposed on a different layer from the first pattern layer and bonded to the first pattern layer, and The plurality of sensing lines further includes: a first group of sensing lines, each of the first group of sensing lines having a single-layer structure in the non-flat area where the first pattern layer of the first pattern layer and the second pattern layer is selectively disposed; and a second group of sensing lines, each of the second group of sensing lines having a single-layer structure in the non-flat area where the second pattern layer of the first pattern layer and the second pattern layer is selectively disposed, and Wherein the first group of sensing lines and the second group of sensing lines are alternately arranged in the first direction.

2. The electronic device according to claim 1, wherein: The first pattern layer of each of the first group of sensing lines extends in the extending direction to pass through the non-flat area, The second pattern layer of each of the first group of sensing lines includes a first end portion cut in the non-flat area, The second pattern layer of each of the second group of sensing lines extends in the extending direction to pass through the non-flat area, and The first pattern layer of each of the second group of sensing lines includes a second end portion cut in the non-flat area.

3. The electronic device according to claim 2, wherein, The first end portion and the second end portion are aligned in the first direction.

4. The electronic device according to claim 2, wherein, The first end portion is arranged to be misaligned with the second end portion in the first direction.

5. The electronic device according to claim 1, wherein: The display unit further includes a structure pattern disposed in the non-flat area, and The structure pattern includes a recessed area or a protruding portion.

6. The electronic device according to claim 5, wherein, The display unit provides a non-flat surface corresponding to the shape of the structure pattern to the non-flat area.

7. The electronic device according to claim 5, wherein, The encapsulation layer covers the structure pattern to provide a flat surface to the non-flat area.

8. The electronic device according to claim 1, wherein, The first pattern layer and the second pattern layer have the same width in the first direction.

9. The electronic device according to claim 1, wherein, The first pattern layer and the second pattern layer have different widths from each other in the first direction.

10. The electronic device according to claim 9, wherein, The first pattern layer and the second pattern layer have the same resistance.

11. The electronic device according to claim 1, wherein, When observed in a plan view, the first pattern layer of the first group of sensing lines is spaced apart from the second pattern layer of the second group of sensing lines.

12. The electronic device according to claim 1, wherein, When observed in a plan view, the first pattern layer of the first set of sensing lines and the second pattern layer of the second set of sensing lines partially overlap each other.

13. The electronic device according to claim 1, wherein, Each of the plurality of sensing electrodes includes: a first sensing electrode including a plurality of first sensing patterns and a plurality of first connection patterns connecting the plurality of first sensing patterns to each other; and a second sensing electrode including a plurality of second sensing patterns and a plurality of second connection patterns, the plurality of second sensing patterns being spaced apart from the plurality of first sensing patterns, the plurality of second connection patterns connecting the plurality of second sensing patterns to each other, the plurality of second connection patterns being spaced apart from the plurality of first connection patterns, an insulating layer being disposed between the plurality of second connection patterns and the plurality of first connection patterns, and wherein the first pattern layer and the second pattern layer are spaced apart from each other, and the insulating layer is disposed between the first pattern layer and the second pattern layer.

14. An electronic panel, the electronic panel comprising: a substrate layer including: a plurality of emission devices disposed in an active area; and a structural pattern disposed in a peripheral area adjacent to the active area and including an insulating material; a plurality of sensing electrodes disposed on the substrate layer and in the active area; and a plurality of sensing lines disposed on the substrate layer and in the peripheral area and electrically connected to the plurality of sensing electrodes respectively, wherein the sensing lines include a plurality of first sets of sensing lines and a plurality of second sets of sensing lines, the plurality of first sets of sensing lines being spaced apart from each other in a first direction intersecting an extending direction of the plurality of sensing lines, the plurality of second sets of sensing lines being respectively disposed between the plurality of first sets of sensing lines and being spaced apart from each other in the first direction, each of the plurality of first sets of sensing lines and the plurality of second sets of sensing lines includes a first pattern layer and a second pattern layer, the first pattern layer and the second pattern layer being spaced apart from each other and bonded to each other through an insulating layer disposed between the first pattern layer and the second pattern layer, each of the plurality of first sets of sensing lines includes only the first pattern layer of the first pattern layer and the second pattern layer in a non-flat area of the peripheral area, and each of the plurality of second sets of sensing lines includes only the second pattern layer of the first pattern layer and the second pattern layer in the non-flat area.

15. The electronic panel according to claim 14, wherein: the structural pattern includes a recessed area or a protruding portion extending in the first direction, and the substrate layer provides a non-flat surface to the non-flat area.

16. The electronic panel according to claim 15, wherein: the substrate layer further includes an organic layer covering the structural pattern, and the organic layer provides a flat surface to the non-flat area.

17. The electronic panel according to claim 14, wherein, When observed in a plan view, the first pattern layer and the second pattern layer are spaced apart from each other in the non-flat area.

18. The electronic panel according to claim 14, wherein, When observed in a plan view, the first pattern layer and the second pattern layer partially overlap each other in the non-flat area.

19. The electronic panel according to claim 14, wherein, A bonding portion between the first pattern layer and the second pattern layer is spaced apart from the non-flat region.

20. The electronic panel according to claim 14, wherein, Each of the plurality of sensing electrodes includes: A first sensing electrode including a plurality of first sensing patterns and a plurality of first connection patterns disposed between the plurality of first sensing patterns to electrically connect adjacent patterns among the plurality of first sensing patterns to each other; and A second sensing electrode including a plurality of second connection patterns and a plurality of second sensing patterns, the plurality of second connection patterns being spaced apart from the plurality of first connection patterns, an insulating layer being disposed between the plurality of second connection patterns and the plurality of first connection patterns, the plurality of second sensing patterns being spaced apart from the plurality of first sensing patterns, and the plurality of second sensing patterns being electrically connected to each other through the plurality of second connection patterns.

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