Efficient matrix formats for neural networks

Abstract

The present invention discloses an efficient matrix format suitable for use in neural networks. Specifically, many computing systems process data organized in a matrix format. For example, artificial neural networks perform a large number of calculations on data organized into matrices using conventional matrix arithmetic operations. One such operation is the transposition operation. Techniques for storing matrices in a compressed format are described, which, for example, allow the transposition operation to be performed during decompression. Therefore, by utilizing the described techniques, transformations (e.g., transpositions) of compressed matrices can be implemented in a more efficient manner. Parallel processing can also be used to more efficiently perform compression and / or decompression.

Description

Technical Field

[0001] The technology relates to compression and decompression of data sets for compact storage and communication, and more specifically to compressing sparse matrix data for subsequent decompression in transposed and / or non-transposed form. The technology also relates to compression and decompression of sparse matrix data for use in, for example, deep learning, machine learning, and artificial intelligence systems. The technology also relates to a graphics processing unit (GPU) that generates, stores, and / or uses compressed and decompressed sparse matrix data in a deep neural network (DNN). Background Art

[0002] Massively parallel processing systems, such as GPUs (Graphics Processing Units), include many high-performance processing units that can perform arithmetic operations in parallel at the same time. The large number of parallel processing units makes them very suitable for parallel processing of large data sets. Although these systems can use parallel processing to speed up the processing of large data sets, the huge cost of performing calculations on large data sets is memory latency and bandwidth.

[0003] Data compression can be used to reduce memory latency and transmission latency. Data compressors reduce the size of data for storage and / or communication. Data decompressors can be used to recover the data for further processing and other uses. Data compression can be either lossy or lossless. Lossy encoding methods use inexact approximations and / or remove unwanted or unneeded data. MP3 audio, H.265 video, and JPEG images are examples of lossy encoding. This compression technique eliminates more detailed information that does not have as much impact on human perception (think of an "abridged version" of a longer story, for example), so that the data can be stored in a reduced memory space and transmitted faster with less bandwidth. In contrast, lossless encoding methods compress the data into a format from which all of the original data can be recovered without loss of information. Lossless ("unabridged") encoding is often used in applications where the data represents text or mathematical properties, where every detail is different. Lossless compression can be used using a variety of different techniques to represent the same amount of data in a smaller space.

[0004] One type of commonly used large datasets is the so-called "sparse matrix", which can benefit from lossless compression. Sparse matrices are widely used in many applications, such as machine learning, artificial intelligence, and deep neural networks. Basically, a matrix is ​​"sparse" when it contains many zero values ​​(e.g., there are many more zero values ​​than non-zero values). Since sparse matrices contain relatively few non-zero values, they are natural candidates for data compression.

[0005] In order to efficiently store and process sparse matrices, a compressed data structure (storage format) can be used that stores only non-zero entries. Various compressed storage formats have been proposed:

[0006] The coordinate (COO) format stores the row and column indices and the values ​​of all nonzero entries explicitly in the row array, column array, and data array, respectively.

[0007] The Compressed Sparse Row (CSR) format retains the same column array and data array as COO, but compresses the row index into a pointer element that is the starting position of all rows in the column / data.

[0008] The diagonal (DIA) format stores non-zero values ​​in the diagonal direction (from the upper left corner to the lower right corner). The array offset records the offset of each diagonal relative to the main diagonal.

[0009] See, e.g., Zhao et al., “Bridging the Gap between Deep Learning and Sparse Matrix Format Selection,” in Proceedings of the 18th PPoPP Conference, Vienna, Austria, February 24–28, 2018 (ACM 2018); Math Kernel Library<software.intel.com / en-us / mkl-developer-reference-c-sparse-blas-diagonal-matrix-storage-format> "Sparse BLAS Diagonal Matrix Storage Format" on .

[0010] For many compression / decompression techniques, there is a trade-off between compactness and time. Just as carefully packing a travel bag to fit as much as possible takes longer, compressing a sparse matrix data file to achieve maximum compression may also take longer. But unlike the travel bag analogy, a highly compressed sparse matrix data file may take much longer to decompress than a less compressed data file. As data sizes and analytical requirements increase, solutions are needed to efficiently decompress data on demand. For example, solutions are needed that provide compressed data in a format that can efficiently generate several different versions of the decompressed data depending on, for example, how the data will be used. Summary of the invention

[0011] Example embodiments provide a lossless data compressor and decompressor ("codec") for matrix data. Example embodiments provide a system and method for generating, storing and / or performing operations using matrix data that is compressed using a diagonal storage format. The diagonal storage format allows the original matrix, transposed matrix, compacted original matrix and / or compact transposed matrix to be easily generated from the diagonal storage format. Example embodiments of the diagonal storage format include an array of non-zero elements arranged in sequence along each diagonal of the matrix and the index of the non-zero elements. The index of the non-zero elements can be provided in a mapping, such as a bitmap indicating the position of the non-zero elements. In certain example embodiments, the rows of the mapping can be cyclically shifted, and the index of the non-zero element can be determined from the cyclically shifted bitmap.

[0012] Example embodiments provide a processing system (e.g., a GPU) configured to execute instructions for loading from a memory to retrieve matrix data stored in a diagonal storage format from a shared memory and decompress the data into another format. For example, the memory load instruction may include converting the matrix data stored in the diagonal storage format into a dense matrix or a dense transposed matrix, and writing the dense matrix or the dense transposed matrix and metadata into a register.

[0013] According to an embodiment, a data decompressor is provided. The decompressor includes an input circuit and a decoder, wherein the input circuit is configured to receive a compressed data file, which includes: (a) a stream of non-zero values ​​along a diagonal of a sparse matrix and (b) a mask indicating the sparse matrix positions of the non-zero values. The decoder is configured to use the mask to fill a transposed dense matrix with the non-zero values ​​in the stream.

[0014] According to some example embodiments, the decoder may be configured to populate a transposed dense matrix without storing intermediate matrix data.

[0015] According to another embodiment, a processing system is provided, configured to execute a load matrix instruction stored in a memory, and to generate a dense matrix and metadata based on a stream of non-zero values ​​and a mask. The instruction can retrieve compressed data, the compressed data comprising: (a) a stream of non-zero values ​​along a matrix diagonal and (b) a mask indicating the matrix positions of the non-zero values ​​in the stream. In some embodiments, the generated dense matrix is ​​a transposed matrix of a matrix represented by the stream of non-zero values ​​and the metadata, the generated dense matrix is ​​stored in a register, and / or is a matrix represented by a stream of non-zero values ​​and a mask comprising data with a sparsity greater than 0.5.

[0016] According to another embodiment, a method performed by at least one programmable multi-threaded processor is provided. The method includes: receiving compressed matrix data from a memory, the compressed matrix data including an array of continuous non-zero values ​​along a matrix diagonal and a mask indicating the position of the non-zero values; generating a dense matrix and / or a dense transposed matrix based on the array of continuous non-zero values ​​and the mask; and storing the generated matrix or transposed matrix in the memory.

[0017] According to another embodiment, a method is provided for execution by at least one processor that executes instructions stored in a memory. The method includes: receiving compressed matrix data from the memory, the compressed matrix data including (a) a stream of non-zero values ​​along a matrix diagonal and (b) index data indicating the matrix positions of the non-zero values ​​in the stream; and executing multiple threads to determine the matrix coordinates and / or transposed matrix coordinates of the non-zero values ​​based on the index data, wherein each thread determines the coordinates of a different non-zero value. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The following is an understanding of the specific implementation of exemplary non-limiting embodiments in conjunction with the accompanying drawings, in which:

[0019] Figure 1A Example non-limiting data compression and decompression are shown.

[0020] Figure 1B A block diagram of an example processing system including a compressor and a decompressor for compressing and / or decompressing a sparse matrix array according to various embodiments disclosed herein is shown.

[0021] Figure 2A An example of training a neural network to recognize certain animals is shown.

[0022] Figure 2B A neuron in a neural network is shown, which receives N inputs from other neurons and receives a bias value.

[0023] Figure 3A The matrix and the transposed matrix are shown.

[0024] Figure 3B and Figure 3C The corresponding diagonals of the matrix and the transposed matrix are shown.

[0025] Figure 4 The process for obtaining the bit mask of a matrix is ​​shown.

[0026] Figure 5A An example non-limiting method of representing a matrix with diagonal lines is shown.

[0027] Figure 5BAn example non-limiting schematic representation of an encoder that can generate compressed data in a diagonal storage format is shown.

[0028] Figure 6 An example non-limiting method of generating a matrix from a matrix stored by the diagonal is shown.

[0029] Figure 7 An example non-limiting parallel processing system is shown.

[0030] Figure 8 Example non-limiting methods of converting a diagonal format to an original matrix and / or a transposed matrix are shown.

[0031] Fig.9A and Fig. 9B An example non-limiting implementation of converting a diagonal format to an original matrix and / or a transposed matrix using multiple threads is shown.

[0032] Fig. 10A and Fig. 10B Another example non-limiting implementation of converting a diagonal format to an original matrix and / or a transposed matrix using multiple threads is shown.

[0033] Fig.11A An example, non-limiting use of diagonal matrices and metadata compression to perform a matrix multiplication instruction is shown.

[0034] Fig. 11B An example non-limiting schematic representation of a decoder is shown that can generate decompressed data from data in a diagonal storage format.

[0035] Figure 12A-12C A matrix representation with diagonal lines for a matrix with 4 elements and 2 non-zero values ​​for each row is shown.

[0036] Fig.13 A parallel processing unit according to an embodiment is shown.

[0037] Fig.14A It shows that according to the embodiment Fig.13 A general-purpose processing cluster within a parallel processing unit.

[0038] Fig. 14B It shows that according to the embodiment Fig.13 The memory partitioning unit of the parallel processing unit.

[0039] Fig.15A It shows that according to the embodiment Fig.14A Streaming multiprocessor.

[0040] Fig. 15B According to the use of the embodiment Fig.13Conceptual diagram of a processing system implemented with a parallel processing unit (PPU).

[0041] Fig. 15C An exemplary system is shown in which the various architectures and / or functionality of the various preceding embodiments may be implemented.

[0042] Fig.16 According to the embodiment, Fig.13 Conceptual diagram of the graphics processing pipeline implemented by the PPU. DETAILED DESCRIPTION

[0043] The example non-limiting technology of this paper provides a data compressor and a decompressor, which compress and decompress matrix data in a format that stores non-zero values ​​in diagonal order. This compression format allows lossless compression. The decompressor can use compressed data to effectively generate different versions of data. For example, the decompressor of an embodiment can selectively restore the original sparse matrix, or produce a transposed version of the sparse matrix. Therefore, the example non-limiting technology of this paper provides a data decompressor, which can decompress data to restore the original data, generate the original data of different compression formats, and / or provide a modified version of the original data. Different compression formats can be formats that enable a processing system to perform calculations on it efficiently. The modified version of the original data can include the original data provided in different orders. For example, the modified representation can include a transposed matrix, and the rows of the original matrix are reordered into the columns of the transposed matrix by the transposed matrix.

[0044] The example non-limiting techniques herein also provide compressed data in a format from which a decompressor can extract information for performing operations without reconstructing the original data represented by the compressed data. For example, for certain operations, the decompressor can selectively restore the indexes or non-zero values ​​and indexes of the original sparse matrix and / or the transposed version of the sparse matrix without generating the original matrix and / or the transposed matrix.

[0045] The example non-limiting techniques herein also provide a processing system (e.g., a GPU) that is configured to execute instructions loaded from memory that can decompress compressed data into a format required for the operation requesting the data. For example, for certain operations, the instructions loaded from memory can retrieve compressed matrix data, convert the data into one or more different formats (e.g., a compressed format, a decompressed format, and / or a format in which the data is rearranged), and store the converted data in a register.

[0046] Figure 1AAn example non-limiting data compression and decompression or "codec" system 100 is shown. The codec system 100 may include a compressor 10 and a plurality of different decompressors 20 (which may all be provided in the same "codec system" 100 or decompressor 20). The compressor 10 may be configured to compress a sparse matrix array into a compressed data file 102. The decompressors 20a-20d may be configured to generate different data sets of decompressed data from the same compressed data file 102.

[0047] The compressor 10 receives a sparse matrix array 104 and generates a compressed data file 102 in a diagonal storage format. In an example embodiment, the diagonal storage format includes a mask and a stream of diagonally ordered non-zero values. The mask provides data for determining the position of the non-zero values ​​in the decompressed data (such as the original sparse matrix array or the transposed sparse matrix array). In one example, the mask can be a bit mask, where 1 (or 0) indicates the position of the non-zero value in the sparse matrix array.

[0048] The mask and diagonally ordered non-zero values ​​may be stored in memory for retrieval by the decompressor 20a-20d and / or transmitted to the decompressor 20a-20d.

[0049] The decompressors 20a-20d may be configured to decompress the compressed data and generate a data set 106 corresponding to the sparse matrix array 104. In some example embodiments, operations (e.g., linear algebra operations) may be performed using the generated data set 106. In some example embodiments, operations (e.g., linear algebra operations) may be performed using information extracted from the compressed data (e.g., non-zero values ​​and / or matrix indices of non-zero values) without reconstructing the sparse matrix array 104.

[0050] like Figure 1A As shown, decompressor 20a receives compressed data file 102 (which includes masks and non-zero values) and generates a sparse matrix array 106a that is identical (or substantially identical) to the sparse matrix array 104 provided to compressor 10. Decompressor 20b uses the same compressed data file 102 to generate a compact matrix array 106b, which corresponds to the sparse matrix array 104 provided to compressor 10 but is represented in a "compact" form. Decompressor 20c uses the same compressed data file 102 to derive a transposed sparse matrix array 106c, which corresponds to a transposed version of the sparse matrix array 104 provided to compressor 10. Decompressor 20d uses the same compressed data file 102 to derive a compact transposed matrix array 106d, which corresponds to a transposed version of the sparse matrix array provided to compressor 10.

[0051] In some example embodiments, the data format provided by the "compact" version 106b, 106d of the matrix array is different from the diagonal storage format, but the data provided is still smaller than the original sparse matrix array 104. For example, the compact format can be a format that uses the data to perform calculations without completely decompressing the data. In one example, the compact version provides a "dense matrix array" (most elements are non-zero), which corresponds to the sparse matrix array. The dense matrix array can include non-zero values ​​and zero values ​​and / or store values ​​in row or column order.

[0052] In some example embodiments, the decompressor 20 may be configured to decompress the compressed data and generate a data set in a dense, coordinate, compressed sparse row, compressed sparse column, Ellpack-Itpack format (ELL), a hybrid storage format, and / or other formats. The dense matrix format may be stored in a column-major format in memory and may be represented by a row number, a column number, and a pointer to a data array including matrix elements. The coordinate matrix format (COO) may be represented by a number of non-zero elements in a matrix, a pointer to a data array that holds non-zero values ​​in a row-major format, a pointer to an integer array of row indices containing non-zero values, and a pointer to an integer array of column indices containing non-zero values. The compressed sparse row format (CSR) may be represented by a number of non-zero elements in a matrix, a pointer to a data array of non-zero values, a pointer to an integer array of compressed row indices containing non-zero values, and a pointer to an integer array of column indices containing non-zero values. The Compressed Sparse Column format (CSC) can be represented by a number of non-zero elements in the matrix, a pointer to a data array of non-zero values, a pointer to an integer array of row indices containing non-zero values, and a pointer to an integer array of compressed column indices containing non-zero values. The Ellpack-Itpack format (ELL) can represent an m×n sparse matrix A with up to k non-zero elements per row, stored using two dense arrays of dimension m×k, the first array containing the values ​​of the non-zero elements in the matrix and the second array containing the corresponding column indices. Other formats may include the Block Compressed Sparse Row format (BSR) or the Extended BSR format (BSRX).

[0053] Since the transpose operation maps the diagonals of the original matrix array to the diagonals of the transposed matrix array, an advantage of the system 100 using the diagonal storage format 104 is that it can efficiently reconstruct the original sparse matrix array 106a and the transposed version 106c of the sparse matrix array. Diagonal storage only requires one copy of the non-zero sum mask, from which different versions of the original matrix array and the transposed matrix array can be derived and / or reconstructed.

[0054] In certain embodiments, the decompressor may generate the compact sparse matrix array 106b, the transposed sparse matrix array 106c, and / or the compact transposed matrix array 106d without generating intermediate results that may include the original matrix arrays.

[0055] Example Non-Limiting Processing System

[0056] Figure 1B A block diagram of an example processing system 100 is shown, the processing system 100 includes a processor-implemented compressor 10 and a processor-implemented decompressor 20 for compressing and / or decompressing a sparse matrix array. The compressor 10 and / or the decompressor 20 may be provided in the form of a CPU and / or a GPU, executing instructions stored in a non-temporary memory. In some other examples, the compressor 10 and / or the decompressor 20 may be provided in hardware as part of a memory controller, such as a cache controller, which is operably coupled between a cache memory and the CPU and / or the GPU.

[0057] The memory 150 may store the sparse matrix array 104. The compressor 10 may be configured to access the sparse matrix array data 104 from the memory 150 and compress the sparse matrix array data into a compressed diagonal storage format 102 including, for example, masks and non-zero values ​​in diagonal order.

[0058] Compressed data 102 may be stored in memory and / or transmitted to a system capable of decompressing the compressed data to recover useful information therefrom.

[0059] For example, decompressor 20 (which may be located in the same or different location as compressor 10 and may include the same or different CPU, GPU and / or hardware for implementing the compressor) receives compressed data 102 (e.g., diagonal order of masks and non-zero values) and decompresses the data. The decompressed data may be stored in memory 150' and / or further provided to a processing system (e.g., in a CPU or GPU) for further processing. Figure 1B As shown, the decompressed data generated by the decompressor 20 may include a sparse matrix array 106a, a compact sparse matrix array 106b, a transposed sparse matrix array 106c, and / or a compact transposed matrix array 106d.

[0060] The command CPU / GPU 140' generates the requested decompressed data, which may indicate one or more different data formats that the decompressor 20 needs to generate. In some examples, multiple decompressors or decompression operations may operate in parallel to decompress compressed data into multiple different data formats 106a, 106b, 106c, 106d.

[0061] In some embodiments, the decompressor 20 may be provided within the memory 150' to the register file load path of the CPU / GPU 140'. In one example, the compressed data 102 may be stored in the memory 150', and when an instruction to perform an operation using matrix data is received, the decompressor 20 provided in the path between the memory 150' and the register file of the CPU / GPU 140' may provide one or more of the different data formats 106a, 106b, 106c, 106d required for the operation. The compressed data 102 may remain compressed until the last storage before the instruction, and one or more data formats required for the operation are generated in the register file as needed.

[0062] Deep Neural Networks

[0063] In some examples, according to various embodiments disclosed in this specification, implementations of the compressor 10 and / or decompressor 20 can be used in machine learning applications to store, transmit and / or process large amounts of data stored in matrices. The matrix data is compressed and decompressed at different stages to reduce system storage and / or communication resources and increase computational speed.

[0064] As an example, a deep neural network (DNN) model includes multiple layers of many connected nodes (such as perceptrons, Boltzmann machines, radial basis functions, convolutional layers, etc.), which can be trained with a large amount of input data to solve complex problems quickly and with high accuracy.

[0065] Figure 2AThe training of a neural network to recognize certain animals is shown. The neural network includes an input layer 42, a plurality of hidden layers 44, and an output layer 46. The training process adjusts the weights of the neuron connections in the neural network so that the output layer 46 makes the correct decision for the data provided to the input layer 42. The neural network shown can generate a sparse matrix during training (e.g., weights of coefficients) and can also generate a sparse matrix during operation (e.g., observations of recording the occurrence or count of activities, preparation of data, etc.). See, e.g., Brownlee, “A Gentle Introduction to Sparse Matrices for Machine Learning,” http: / / machinelearningmastery.com / sparse-matrices-for-machine-learning / ; “Sparse Linear Algebra” in the CuSPARSE library for CUDA (NVIDIA), http: / / developer.nvidia.com / cusparse; and Bell et al., “Efficient Sparse Matrix-Vector Multiplication on CUDA,” NVIDIA Technical Report NVR-2008-004 (December 2008).

[0066] In more detail, neurons are the basic units of neural networks. Figure 2B Neuron 48 is shown receiving N inputs and bias values ​​from other neurons. Each input to the neuron is multiplied by a corresponding weight value w. The weights represent the strength of the connection between neurons. Neurons may also include bias inputs that do not receive input from any other neurons. Weight value b is applied to the bias input. The weighted inputs and biases are added to provide The activation function g(z) used to provide nonlinearity to the neural network is applied to the weighted sum of the input and bias. The output of the neuron can be expressed as The weighted inputs and biases generated during the training process result in large amounts of sparse matrix data that must be properly represented, stored, and accessed.

[0067] For example, during training, data flows through the DNN in the forward propagation phase until a prediction is generated that indicates a label corresponding to the input. The operations in the forward propagation include multiplying the weight matrix by the activation matrix. The weight matrix models the weights applied to the connections between neurons in layer N and layer N+1. The activation matrix of layer N+1 is the output from the operations in layer N.

[0068] The error between the correct label and the predicted label is analyzed, and the weights are adjusted for each feature during the back-propagation phase until the DNN correctly labels the inputs in the training dataset and other inputs. Back-propagation minimizes the error between the correct label and the predicted label. Back-propagation involves propagating the error back through the layers of the network, adjusting the weights of the inputs to the individual neurons, and making another decision.

[0069] Backpropagation generates the gradient of the activations, which tells how wrong we are and which direction to move in order to generate the correct prediction. The higher the gradient, the steeper the slope of the function and the faster the network learns. When the slope is zero, the network stops learning. Generating gradients in backpropagation involves multiplying the activations by the transposed weight matrix. As will be discussed in more detail below, the transpose of matrix A is matrix AT, which is formed by transposing the rows of matrix A into the columns of matrix AT.

[0070] Forward and back propagation can be performed on thousands of images, with each iteration resulting in revised weights for the neural network.

[0071] Once a DNN is trained, it can be deployed and used to recognize and classify objects or patterns in a process called inference. Examples of inference (the process by which a DNN extracts useful information from a given input) include recognizing handwritten numbers on a check deposited into an ATM, identifying images of friends in photos, providing movie recommendations to over 50 million users, recognizing and classifying different types of cars, pedestrians, and road hazards in a self-driving car, or translating human speech in real time.

[0072] exist Figure 2A In the example of , many interconnected layers can be provided, including an input layer 42, an output layer 46, and multiple intermediate hidden layers 44. In an illustrative example, the first layer of the DNN model breaks down the input image into different parts and looks for edges. Additional layers 44 can assemble edges to find higher-level patterns, such as basic patterns like lines and angles, and identify certain parts of animals, such as wings, eyes, and tails. The last few layers can generate labels for the input image for identifying objects. The output layer 46 can generate output.

[0073] As discussed above, forward propagation and back propagation include performing matrix multiplication operations, involving matrix A and transposed matrix AT. It may take time to transpose matrix A into a transposed matrix. In addition, because the neural network is large, weights and activation matrices may be very large and exceed the available memory at some memory layers of the parallel processing system, such as L1 or L2 cache memory. Although there is more memory available on higher memory layers (such as main memory), accessing data from such higher memory layers consumes more time. In order to overcome these challenges and other challenges, an example non-limiting embodiment provides a method for representing a sparse matrix for storing and / or generating a matrix in a diagonal storage format, from which the original matrix and / or transposed matrix can be effectively extracted.

[0074] Sparse Matrix

[0075] As discussed above, the workload processed by a neural network can be very large and can include sparse data, meaning that many values ​​in the matrix are zero. Similarly, the matrices that represent the characteristics of a neural network during training and inference can include sparse matrix data.

[0076] Large sparse matrices are difficult to work with because they take up a lot of storage space and cause latency when performing operations designed for dense matrices. Therefore, when storing and performing operations with sparse matrices, specialized data representations can be used to exploit the sparsity of the matrices to reduce storage requirements and memory latency.

[0077] Example embodiments provide systems and techniques for generating, storing and / or performing operations using a diagonal format for storing sparse matrices. Example non-limiting diagonal storage formats include non-zero matrix elements and masks indicating the positions of non-zero elements in the original matrix. The data is continuous non-zero along the matrix diagonal. For example, the diagonal of an 8×8 matrix is ​​defined as a set element (i, j) such that ij=k (mod 8). For k=0,…,k=7, the matrix has 8 diagonals, where k=0 is the main diagonal. The advantage of the diagonal storage of the example non-limiting embodiment is that, since the transposition operation can be used to map the diagonals of the original matrix to the diagonals of the transposed matrix, it is quite efficient for the example non-limiting decoder to reconstruct the original version of the sparse matrix or the transposed version of the matrix.

[0078] Diagonal storage requires only one copy of the non-zero sum mask (e.g., 8 bytes for an 8×8 sparse matrix). Example non-limiting embodiments include applying diagonal storage to 8×8 matrices of 0.5 or greater sparsity, but diagonal storage is not limited to this. Example embodiments may be applied to matrices of 4:8 sparsity, which is a special case of 0.5 sparsity. Diagonal storage is not limited to any particular sparsity, sparsity pattern, and / or particular block size.

[0079] Existing methods either require two copies of the non-zeros or require a lot of metadata. Diagonal storage is optimal within 4 bits for a total of 8 bytes for the mask, and 64 bytes for the non-zeros (assuming half-precision data).

[0080] Diagonal storage will reduce the amount of data storage required for sparse weights in DNNs and other applications by almost 2x (2 times).

[0081] Although example non-limiting embodiments are described in conjunction with neural networks, the techniques herein are generally more applicable to any application using sparse matrices and / or transposed matrices. For example, the techniques herein can be used in the context of high performance computing (HPC) applications. As a specific example, the techniques herein can be used in the context of computational flows around an aircraft, where matrices include sparse data and / or transposed matrices.

[0082] Compression and Decompression Overview

[0083] For a two-dimensional N:M structured sparse matrix (where each column and each row of M elements has only N non-zero values), it is desirable to store a single version of the compact matrix using M×N storage space (plus metadata), but to be able to simply generate a compact+transposed version of the matrix and a compact+non-transposed version of the matrix from that storage. In addition to the appropriate metadata (generated or stored), these versions of the matrix can be directly fed to a sparse matrix multiply-accumulate (MMA) instruction.

[0084] Existing approaches to solving the problem of reducing gradients during the forward propagation step (fprop) and the backpropagation step (dgrad) require both non-transposed and transposed versions of the same compact weight matrix and do not provide the desired savings in storage or without expanding the matrix to be larger.

[0085] As an example, one approach is to store two copies of the compact matrix. The downside is that this requires twice as much storage space as a single copy, so after accounting for metadata, the net storage space savings is less than zero for a 50% dense matrix.

[0086] Another approach is to provide a lookup table, which exploits the fact that for a given block, there are a finite number of possible 2-dimensional structured sparse patterns. For example, there are only 90 possible 2-dimensional 2:4 4×4 blocks whose transpose information can be stored in a lookup table. The disadvantage is that this approach does not scale to larger blocks (such as for 2-dimensional 4:8 8×8 blocks, there are millions of possibilities).

[0087] Diagonal storage

[0088] In an exemplary non-limiting embodiment, the values ​​in the matrix diagonal remain unchanged during the transposition, and the transposition operation is equivalent to a reordering of the matrix diagonal. Figure 3A The shown square sparse matrix A of size m=8.

[0089] The transpose of matrix A is matrix AT, which is formed by transforming the rows of matrix A into the columns of matrix AT. Since matrix A is sparse, its transpose AT is also sparse. Figure 3A As shown, the rows of the matrix A are provided as columns of the transposed matrix AT.

[0090] Both the matrix A and the transposed matrix AT include eight diagonals starting from the first row of each matrix. Assume Figure 3A If the matrix is ​​a chess board, then the bishop and queen can move along these diagonals, except in the example non-limiting embodiment where both diagonals have the same number of entries and thus "wrap" to the opposite side of the matrix (these moves are not in accordance with the rules of chess). Figure 3A In the example, zero values ​​are shown as blanks for ease of illustration, but they actually include 00hex (i.e., in this case, each value is one byte long, consisting of two 4-bit binary nibbles). Figure 3B As shown in the following figures, Figure 3A The diagonal of the sparse matrix A (i.e., the paths that the bishop and queen can move on the chess board but will "switch") consists of:

[0091] d0 = [00, 00, 00, 00, 00, 00, 00]; (no need to transpose)

[0092] d1 = [00, 00, 00, 00, 00, 00, 00]; (transpose to the lowest square on the left)

[0093] d2 = [02, 00, 24, 35, 00, 00, 00, 00]; (e.g. Figure 3B Transposed as shown)

[0094] d3 = [00, 14, 00, 00, 00, 00, 00, 00]; (transpose to row 6)

[0095] d4 = [00, 15, 00, 00, 00, 00, 00, 00]; (transpose to row 5)

[0096] d5 = [05, 00, 27, 30, 41, 00, 00, 74]; (e.g. Figure 3C Transposed as shown)

[0097] d6 = [00, 00, 00, 00, 00, 00, 00]; (transpose to the third row)

[0098] d7 = [00, 10, 00, 00, 00, 00, 00, 00]; (transpose to the second row)

[0099] Figure 3A , Figure 3B , Figure 3C The diagonal of the transposed matrix AT shown on the right side includes:

[0100] d0=[00, 00, 00, 00, 00, 00, 00, 00];

[0101] d1=[10, 00, 00, 00, 00, 00, 00, 00];

[0102] d2=[00, 00, 00, 00, 00, 00, 00, 00];

[0103] d3=[30, 41, 00, 00, 74, 05, 00, 27];

[0104] d4=[00, 00, 00, 00, 00, 15, 00, 00];

[0105] d5=[00, 00, 00, 00, 14, 00, 00, 00];

[0106] d6 = [00, 00, 02, 00, 24, 35, 00, 00]; and

[0107] d7=[00, 00, 00, 00, 00, 00, 00, 00].

[0108] From this example, it can be seen that the diagonal d0 of matrix A and the transposed matrix AT is exactly the same, that is, all are zero. The other diagonals in matrix A are provided at other positions in the transposed matrix AT, but the order of zero-valued elements and non-zero-valued elements remains unchanged.

[0109] For example, Figure 3B As shown, the diagonal d2 = [02, 00, 24, 35, 00, 00, 00, 00] of matrix A corresponds to the diagonal d6 = [00, 00, 02, 00, 24, 35, 00, 00] of the transposed matrix AT. The diagonal d6 of the transposed matrix AT includes elements 02, 24 and 35 in the same order as in the original untransposed matrix (about the same zero value positions). The difference is that the diagonal d2 of matrix A now starts from the column (md)%m→(8-2)%8=d6, and its elements have been circularly shifted down d=2 positions.

[0110] As another example, Figure 3CAs shown, the diagonal d5 = [05, 00, 27, 30, 41, 00, 00, 74] of the matrix A corresponds to the diagonal d3 = [30, 41, 00, 00, 74, 05, 00, 27] of the transposed matrix AT. The diagonal d3 of the transposed matrix AT includes non-zero elements 05, 27, 30, 41 and 74, which are in the same order as in the non-transposed matrix (about the same zero value position). The diagonal d5 of the matrix A, in the transposed matrix AT, starting from the column (md)%m→(8-5)%8=3, its elements have been cyclically moved down by d=5 positions.

[0111] To store a sparse matrix in diagonal format, two data structures are used in the example non-limiting embodiment:

[0112] 1) A vector D that contains the non-zero values ​​that are compact along a series of diagonals (i.e., all zero values ​​on the diagonal are removed so that the data representation is "compact" in the sense that it is made more compact by removing zero values). The size of the vector depends on the number of non-zero values.

[0113] D=[02, 24, 35, 14, 15, 05, 27, 30, 41, 74, 10]

[0114] 2) A bit mask M of size m×m that indicates the zero / non-zero state of each position in each row of the matrix A (in other words, since the vector D does not include information from which the position of each non-zero element in the matrix can be unambiguously determined, an additional mask is used to specify the matrix position of each non-zero value). For example, a hexadecimal bit mask may include the following values:

[0115] M = 0x4213091220000001

[0116] Figure 4 An example non-limiting process for determining the hexadecimal representation of a bit mask M for a matrix A is shown. A bit is used to indicate whether each element position in the matrix is ​​a zero-valued element or a non-zero-valued element. In the mask, a "0" represents a zero-valued element and a "1" represents a non-zero-valued element. Each group of 4 bits is converted to a hexadecimal value, where the bits are read from right to left.

[0117] The prefix sum of the values ​​in the rows of the matrix can be computed (and stored with the above data, or generated from the above data at runtime) using the vector D and the bit mask M. This will indicate where the values ​​of each diagonal will be located in the compact output.

[0118] Using this stored or generated data, the example non-limiting decoder of the example non-limiting embodiment may generate any of four possible outputs depending on the use case (e.g., the needs of the application):

[0119] 1) Original matrix A;

[0120] 2) compact matrix AC and metadata Am;

[0121] 3) transpose matrix AT; and / or

[0122] 4) Transpose the compact matrix ATC and metadata ATm.

[0123] In certain example non-limiting implementations, the compact matrix and metadata may be ready to be input to a sparse matrix multiply-accumulate instruction.

[0124] The method disclosed in this application is not limited to structured sparsity or any specific block size. The method can be applied to 2:8 sparsity, 4:16 sparsity, 8:16 sparsity, and even in the absence of structure, with a general density of 25% or 50% density. In some embodiments, interactions with sparse matrix multiplication and accumulation may require a compliant sparse mode.

[0125] In some example non-limiting implementations, the storage format is not limited to sparse matrices, but can also be applied to matrices with densities greater than 50%. Matrices with these higher densities may require higher overhead to obtain the matrix or transpose the matrix from the stored data.

[0126] Method and system for representing matrices using diagonal lines

[0127] Figure 5A An example non-limiting method 50 for representing a matrix with diagonal lines is shown. The method may be performed by a processor (e.g., one or more CPUs and / or GPUs) that executes software instructions stored in non-transitory memory and / or hardware-based processing circuitry. In some example non-limiting implementations, the method may be performed by software and / or hardware encoders.

[0128] The method 50 includes receiving matrix data 52. The matrix data may be received in response to a command to access the matrix data from a memory. The matrix data may include a sparse matrix, wherein most elements are zero. In some embodiments, the matrix data may include a dense matrix, wherein most elements are non-zero. If the matrix data is compressed, the method may include decompressing the matrix data into a format required to perform the operation.

[0129] The method includes generating a diagonal storage format, specifically comprising: step 54, extracting a stream of non-zero values ​​from the received matrix data; step 56, indexing the data to determine the location of the non-zero values ​​in an array. The array lists the non-zero matrix values ​​along each diagonal of the matrix in turn. The size of the array will depend on the number of non-zero values ​​in the matrix.

[0130] The index data provides information required to specify and / or determine, for each non-zero value, the location of the non-zero value in: (1) a matrix, (2) a compact matrix, (3) a transposed matrix, and / or (4) a transposed compact matrix. In one example, a bit mask having a bit corresponding to each element of the matrix can indicate whether each position of the matrix is ​​a zero value or a non-zero value. The bit mask can be preprocessed to indicate the location of the non-zero value in a compressed format. The index data can be generated only for the non-zero values. A convention can be used so that the order of the bits in the bit mask has a predetermined correspondence with the position in the (or certain) matrix.

[0131] For example, the index data can indicate the diagonal number or other identifier of each non-zero value, and where the respective non-zero value is located in the identified diagonal. In one example, the index data indicates the diagonal number and matrix row number of each non-zero value. The index data can be used to reconstruct the original matrix, the compact matrix, the transposed matrix and / or the transposed compact matrix.

[0132] In some example non-limiting implementations, the bit mask is preprocessed into a function S and a function Q by a simple bitwise sum operation, where the function S indicates the number of non-zeros on each diagonal and the function Q indicates the starting point of the diagonal. Using these two functions, the positions of the non-zero elements of the original matrix, the compact matrix, the transposed matrix and / or the transposed compact matrix can be determined.

[0133] As will be discussed in more detail below, the function S is the column sum of the circularly shifted bit mask, S(k) is the number of nonzeros on the kth diagonal, and Q(k) is the prefix sum of S, which provides the starting point of the kth diagonal in the array of matrix values ​​D. The prefix sum is the cumulative sum of a sequence of quantities, represented by yi=yi-1+xi. Given an array of size n, the prefix sum of an array Arr[n] is another array of the same size, where the value of the prefix sum array is determined by Prefix_Arr[i]=Arr[0]+Arr[1]+Arr[2]+…+Arr[i]. Using the functions S and Q, a vector of length S(j) is formed for each column j in the bit mask, which provides the index of the row with nonzero elements.

[0134] In some example non-limiting implementations, the index data may indicate a row number for each non-zero element and a diagonal number for each non-zero element.

[0135] In certain example non-limiting implementations, the index data may include a mask of circularly shifted row number bits. The columns in the circularly shifted mask correspond to the diagonals in the matrix.

[0136] The method may include: step 58, storing array and index data and / or performing computing operations using array and index data. The array and index data may be stored in a shared memory / L1 cache, an L2 cache, and / or a local memory (e.g., a dynamic random access memory). Computing operations (e.g., matrix multiplication instructions) may be configured to perform these operations by directly using the array and index data without decompressing the data to generate the original matrix, the compact matrix, the transposed matrix, and / or the transposed compact matrix. For example, a first matrix stored in a diagonal storage format may be multiplied by a second matrix stored in a diagonal storage format without decompressing the data to generate a third matrix stored in a diagonal storage format. The operation may include, but is not limited to, a matrix multiplication operation.

[0137] Example schematic representation of an encoder

[0138] Figure 5B An example non-limiting schematic representation of a hardware-based encoder that can generate compressed data in a diagonal storage format is shown. Figure 5B The output of the system is a bit mask indicating the positions of non-zero elements in the input matrix, and an array of non-zero values ​​in diagonal order. In other examples, other metadata (rather than a bit mask) can be generated to specify the positions of non-zero elements of the original matrix and / or transposed matrix, and / or the positions of non-zero elements in the matrix and / or transposed matrix can be determined therefrom.

[0139] Figure 5B An example shift register is shown (eg, allocated in cache memory) that allows the hardware logic circuit to scan the matrix and generate an array of masks and non-zero values. Other more parallel circuits can be used to reduce the time to scan the matrix.

[0140] The stream of data includes matrix element values ​​(e.g., a, b, c) in row order. The comparator receives the stream of input data and generates a stream of bits indicating zero elements and non-zero elements in the stream of input data. In one example, the comparator may include a plurality of OR gates, each of which outputs "0" or "false" if the value of all bits of the element is zero, and each of which outputs "1" or "true" if the value of the element is non-zero (i.e., any bit in the value is set).

[0141] The stream of data is also provided to a sorter or selector configured to sort or select the elements of the matrix into respective diagonals (d0, d1, d2, ... dN). The non-zero extraction circuit can discard or suppress zero elements and send only non-zero values ​​to the multiplexer. The multiplexer can combine the non-zero values ​​on each diagonal in an appropriate order to produce a stream of non-zero values ​​in diagonal order. For example, the multiplexer can be controlled to output all non-zero values ​​on diagonal 0 first, then output the non-zero elements on the next diagonal, and so on, until all non-zero values ​​on the diagonal are output.

[0142] The compressed data file, including the generated bit mask and the array of non-zero values, can be stored in memory and / or transmitted to a processing system for further processing. If desired, further lossless compression techniques can be employed, such as by eliminating redundant information to further reduce the size of the compressed data file.

[0143] Decompression method and system

[0144] Figure 6 An example non-limiting method 60 for decompressing a compressed matrix representation is shown, to generate a matrix in any of several different formats, for example, from a matrix stored diagonally. The method can be performed by one or more processors (e.g., a CPU and / or GPU) that executes software instructions stored in non-temporary memory and / or hardware-based processing circuits. In some example non-limiting implementations, the method can be performed by software and / or hardware decoders. In some example embodiments, decompression can be performed using tensor cores in a parallel processing operating environment (such as CUDA). In some example embodiments, one or more operations of method 60 may be included in a load from a memory instruction and / or an arithmetic operation instruction.

[0145] The method comprises step 62 of receiving compressed matrix data stored by diagonal lines. The compressed matrix data stored by diagonal lines may comprise an array of non-zero values ​​and index data for determining the position or location of the non-zero values ​​in the array.

[0146] The compressed matrix data stored by the diagonal can be received in response to a request to perform a computational operation (such as a matrix multiplication operation) on a matrix or transposed matrix represented by the matrix data stored by the diagonal. Such a request can include a field or an operation code that specifies the format of the output matrix required or desired.

[0147] The method includes step 64: for each non-zero value in the array, determine the position in the matrix and / or the transposed matrix. Since the values ​​in the diagonal of the matrix are kept unchanged during the transposition, the same index data can be used to determine the position of each non-zero value in the matrix and the transposed matrix. In some example non-limiting implementations, for each non-zero value in the array, determine the position in the compact matrix and / or the transposed compact matrix. In some example non-limiting implementations, the matrix position of each non-zero value can be determined by function S and function Q, where function S indicates the number of non-zeros on each diagonal, and function Q indicates the starting point of the diagonal.

[0148] The method comprises step 66: generating a matrix and / or a transposed matrix. The matrix or transposed matrix is ​​generated by placing each non-zero value at a determined position and placing zeros at all other positions of the matrix. The generated matrix and / or transposed matrix may be an uncompressed matrix or a compact matrix with associated metadata.

[0149] The method comprises step 68: the generated matrix, the compact matrix with metadata, the transposed matrix and / or the transposed compact matrix with metadata can be stored in a memory, or can be used to perform a computational operation (such as a matrix multiplication operation). The computational operation can use the entire generated matrix, a portion of the matrix and / or the non-zero values ​​and their positions without generating the entire matrix.

[0150] In some example embodiments, generating the matrix and / or the transposed matrix in step 66 may include determining the positions of non-zero values ​​in the original matrix, the transposed matrix, the dense matrix (e.g., the non-transposed matrix), and / or the dense transposed matrix without generating the original matrix, the transposed matrix, the dense matrix, and / or the dense transposed matrix. The non-zero values ​​and the determined positions thereof in a particular matrix may be used to perform operations without generating a complete matrix.

[0151] In certain example embodiments, at least a portion of a transposed matrix, a dense matrix, and / or a dense transposed matrix may be determined without generating and / or storing an intermediate result, one or more intermediate matrices, and / or an entire matrix (e.g., an original matrix, a transposed matrix, and / or a dense original matrix).

[0152] In some examples, a dense matrix can be generated from matrix data stored diagonally without generating and / or storing the original matrix. In some examples, a transposed matrix can be generated from matrix data stored diagonally without generating and / or storing the original untransposed matrix. In some examples, a transposed dense matrix can be generated from matrix data stored diagonally without generating and / or storing the original untransposed matrix and / or transposed matrix.

[0153] Example implementation for allocating threads to compute destination indices for nonzero elements stored in diagonal format

[0154] In some example non-limiting implementations, the task of determining the destination index of each non-zero element may be assigned to different threads in a parallel processing system. Figure 7 An example non-limiting parallel processing system is shown. Figure 7 A specific arrangement of parallel processing system components is shown, but embodiments of the present disclosure are not limited to the arrangement of parallel processing systems shown. In some example embodiments, Figure 7 The parallel processing system shown is a streaming multiprocessor (SM) 440, which refers to Fig.14A and Fig.15A Have a discussion.

[0155] The parallel processing system can be configured to control the execution of multiple thread blocks, each of which has multiple thread warps. Each thread warp includes multiple threads (eg, 32 threads).

[0156] Each thread can independently process and store data using registers on the chip. Threads in a thread block can collaborate and exchange data through shared memory. The thread can exchange data with threads in other thread blocks and / or other processing systems (such as CPUs) through global memory.

[0157] Determining the destination index for each element in the array of non-zero matrix values ​​may be performed by different threads of the warp. Figure 7 As shown, each of threads 0 to K-1 of a warp can receive matrix data in a diagonal format. Each of threads 0 to K-1 can receive different elements of an array D, which includes non-zero matrix values ​​and index data along each diagonal of the matrix. The thread can determine the destination of the non-zero elements of the original matrix, the transposed matrix, the original dense matrix, and / or the transposed dense matrix without generating and / or storing intermediate results (e.g., untransposed sparse matrix, untransposed dense matrix, and / or transposed dense matrix).

[0158] The threads can determine the coordinates of the elements of array D based on the index data, and store the elements and coordinates of array D in respective registers. Coordinates can be determined for matrices or transposed matrices. The threads can perform calculations in parallel. The results in the registers can provide dense matrices or dense transposed matrices. In some examples, the determined matrix coordinates and / or transposed matrix coordinates of non-zero values ​​can be used to perform operations (e.g., linear algebra operations) without reconstructing the matrix or transposed matrix.

[0159] The index data provided to the register may include the row positions of the non-zero elements in the array S, array Q, and the shift bit mask of the matrix, the array S indicating the column sum of the shift bit mask of the matrix, and the array Q indicating the prefix sum of S. Each thread may calculate the diagonal number and row number of the assigned elements. In one example, the index data provided to the register may include index data providing the column position and row position of the non-zero elements in the bitmap, wherein the bitmap has a row cyclic shift row number bit greater than zero.

[0160] Each warp may be assigned to determine the destination index of non-zero elements stored in a diagonal format for different matrices or different blocks of a large matrix. Similarly, different thread blocks may be assigned to determine the destination index of non-zero elements stored in a diagonal format for different matrices or different blocks of a large matrix. Threads in one or more warps and / or one or more warps may execute in parallel.

[0161] A more detailed example of a matrix represented with a diagonal

[0162] Storing matrices with diagonals

[0163] The diagonal in a square matrix of size N is the set of a[i, j] elements such that ij=k mod N. The diagonal is invariant under matrix transposition, i.e., transposition maps the diagonal of the matrix to the diagonal of the transposed matrix. Specifically, a matrix of size N has N diagonals indexed by 0, ..., N-1. The kth diagonal of the transposed matrix is ​​the image of the (N-1-k)th diagonal of the original matrix. The elements on the kth diagonal are cyclically shifted by the k elements on the (N-1-k)th diagonal. In other words, the element A[j, (k+j)mod N] in the transposed matrix is ​​equal to the element A[(k+j)mod N, j] in the original matrix.

[0164] If the matrix is ​​sparse and each diagonal is represented by the indices of its elements, then to get the kth diagonal of the transposed matrix, add k (mod N) to the indices of the elements of the diagonal N-1-k.

[0165] Consider the example of an 8×8 matrix with at most 4 non-zero elements per row. The matrix can be represented by a vector D of 32 non-zeros and a 64-bit mask M that marks the non-zeros in the matrix. Each row can have one byte. This representation is close to optimal. There are 162 (= 8 + 28 + 56 + 70) possible rows with at most 4 non-zeros. The total number of 8×8 matrices with at most 4 non-zeros per row is 162^8. The logarithm of this number, 58, is the minimum number of bits required to uniquely identify this type of matrix.

[0166] In summary, for [4, 8] sparsity, the overhead is 8B or 12.5% ​​relative to 64(32×2)B of data. This overhead is 6 bits less than the optimal.

[0167] Convert the diagonal matrix to the original matrix and transpose

[0168] It will now be shown how to construct 8×8 matrices A and A∧T using an array D (which lists up to 32 non-zeros along the diagonal) and a matrix mask M. Figure 8 Example non-limiting methods of converting a diagonal format to an original matrix and / or a transposed matrix are shown.

[0169] Figure 8 The operations shown in the may be performed by one or more processors (e.g., CPU and / or GPU) executing software instructions stored in non-transitory memory and / or one or more hardware-based processing circuits. In certain example non-limiting implementations, the operations may be performed by software and / or hardware decoders. In some example embodiments, the operations may be performed using tensor cores in a parallel processing operating environment (e.g., CUDA). In some example embodiments, Figure 8 One or more of the operations shown may be included in a load from memory instruction and / or an arithmetic operation instruction.

[0170] The k-th element of the vector D listing the non-zero values ​​in the matrix is ​​assigned to thread k of the warp, and the computation of the destination index on that element is assigned to that thread (step 80).

[0171] First, the i-th row of M is cyclically shifted to the left by i positions (step 82). Then M[i, j] is 1 only when the j-th element of the i-th row in the original matrix A is non-zero.

[0172] Then, using M, the CIdx[i,j] function is calculated, which is equal to the jth non-zero column number of the i-th row of M, i=0, ..., 7, j=0, ..., 3 (step 84). Finally, it follows that there are at most 4 non-zero elements in each row. CIdx[I,j] will be used for the sparse matrix multiplication (HMM) instruction. Similarly, RIdx[i,j] will be calculated for the transposed matrix AT.

[0173] Then, the columns of M are summed as the row vector S (step 86). S[j] will be the number of non-zeros on the diagonal j, and let Q be the prefix sum of S, then Q[j] will be the starting point of the diagonal j in the vector D (step 88).

[0174] The method includes, for each column j in M, forming a vector of length S[j], where S[j] is the index of the row with entry 1, let it be R[j,i], i=0, ..., S[j]-1 (step 90).

[0175] Using Q and R, we can calculate the coordinates of the elements of A and / or AT that should be assigned the value of D (step 92):

[0176] A[R[j,i],j+R[j,i]]=D[Q[j]+i],i=0,...,S[j]-1; and

[0177] AT[R[j,i]+j,R[j,i]]=D[Q[j]+i],i=0,...,S[j]–1.

[0178] Calculation function R:

[0179] The function R[j,i] is computed for each column j of the mask M separately. A column of M can be represented as a byte. R of a byte B returns a list of the positions of the 1s in B. Since k=Q[j]+i can assume values ​​from 0 to 31 at most once, R[j,i] can be represented as Idx[k]. This means that each thread in the warp will compute J[k] and Idx[k], which are necessary to assign the correct value to A or AT.

[0180] A step function J[k] is introduced that performs one step on each segment of the diagonal in D. In other words, J(k) tells the diagonal number of the elements of D assigned to thread k. Idx[k] indicates the row number of the non-zero element k in D.

[0181] After calculating J(k) and Idx[k], the above permutation equation can be simplified to:

[0182] A[Idx[k], J[k]+Idx[k]]=D[k];

[0183] AT[Idx[k]+J[k], Idx[k]]=D[k].

[0184] This representation will be the basis for directly converting a pair of sparse matrices represented by the diagonal into dense 8×8 matrices and index functions, which are required for sparse matrix multiplication and accumulation (e.g., FP 16HMMA) or warp matrix multiply and accumulate (WMMA) instructions in CUDA 9 or other CUDA versions. WMMA allows values ​​to be loaded or initialized into a special format for a tensor core, performs a matrix multiply-accumulate (MMA) step, and stores the value back to memory. During program execution, multiple tensor cores can be used simultaneously by the entire warp. This allows the warp to perform 16×16×16 MMAs at very high throughput. In some embodiments, instructions for generating original matrices, transposed matrices, compact original matrices, and / or compact transposed matrices from diagonally stored matrix data can be placed into matrix multiplication instructions.

[0185] Fig.9A and Fig. 9B An example non-limiting implementation of converting a diagonal format to an original matrix and / or a transposed matrix using multiple threads is shown. Fig.9A and Fig. 9B Multiple threads of vectors D of compact non-zero values ​​received sequentially along each diagonal are shown, along with a matrix bit mask M indicating the zero / non-zero state of each position in each row of matrix A. In the example shown, it is assumed that vector D includes 32 elements, but embodiments of the present disclosure are not limited thereto.

[0186] The task of determining the destination index of each non-zero element in vector D is assigned to different threads. Each thread performs operations to determine the matrix A (such as Fig.9A As shown) or the transposed matrix AT (as Fig. 9B The coordinates of the non-zero elements in . Figure 8 The method operations discussed may be performed by each thread.In some examples, a single thread may provide coordinates for both the matrix A and the transposed matrix AT.

[0187] exist Fig.9A In the example above, thread 0 determines the row and column of the first element in vector D in matrix A. Thread 31 determines the row and column of the 32nd element in vector D in matrix A.

[0188] exist Fig. 9B In the example, thread 0 determines the row and column of the first element of vector D in the transposed matrix AT. Thread 31 determines the row and column of the 32nd element of vector D in the transposed matrix A.

[0189] Computations can be performed in parallel and the results can be stored in registers associated with the threads.

[0190] Fig. 10A and Fig. 10B Another example non-limiting implementation of converting a diagonal format to an original matrix and / or a transposed matrix using multiple threads is shown. Fig. 10A and Fig. 10B Multiple threads are shown receiving in turn a vector D of compact non-zero values ​​along each diagonal, a vector Idx[k] indicating the row numbers of the elements of D assigned to thread k, and a vector J[k] indicating the diagonal numbers of the elements of D assigned to thread k.

[0191] The task of determining the destination index of each non-zero element in vector D is assigned to different threads. Each thread performs operations to determine the matrix A (such as Fig. 10A As shown) or the transposed matrix AT (as Fig. 10BEach thread determines Idx(k), which indicates the row number of element k in D, and J(k), which indicates the diagonal number of element k in D. These values ​​are used to determine the coordinates of element k in matrix A and / or transposed matrix AT. In some examples, a single thread may provide coordinates to both matrix A and transposed matrix AT.

[0192] Convert to 8×4 dense matrix

[0193] Fig.11A An example non-limiting use of a matrix multiplication instruction performed by a diagonal matrix and metadata compression is shown. Matrix A is 16×16 in size, with each column and each row having at most N=8 non-zero values, and k=16 non-zero values. Matrix A is multiplied by matrix B to obtain matrix C. Matrix A can be represented by four blocks, and in this particular example, the density of each 8×8 block of matrix A is 4:8.

[0194] like Fig.11A As shown, matrix A can be compressed and stored using 288 bytes. Each of the four blocks uses 64 bytes to store non-zero values ​​and 8 bytes to store the mask. This compression saves 7 / 16 of the memory required to store the uncompressed matrix A using 512 bytes. Each block of matrix A stored in diagonal format can be decompressed into a dense 8×4 matrix corresponding to matrix A or a dense 4×8 matrix corresponding to the transposed matrix AT (see Fig.11A ACT00, ACT10, ACT01 and ACT11 in the .

[0195] A matrix multiply and accumulate (MMA) operation may be defined by C+=A*B. An MMA operation may include adding a matrix to A*B, which may be the result of a previous MMA operation (e.g., C+=A*B). C=A*B may be a special case of MMA. An MMA operation may include loading matrices A and B from memory into registers. Matrix C from a previous operation may be stored in a register from a previous operation. When the load operation is complete, the destination register in each thread holds a segment of the loaded matrix.

[0196] Loading matrices A and / or B may include decompressing data stored in memory into a format required for the MMA operation. For example, the load operation may include decompressing one or more matrices stored in a diagonal format into a dense matrix (e.g., a dense matrix AC or a transposed dense matrix ACT).

[0197] Next, matrix multiplication and addition (optionally) are performed on the loaded matrices. When the operation is completed, the destination register in each thread holds a segment of the resulting matrix C. Next, the resulting matrix C is stored back to memory. Alternatively, the resulting matrix C can be added to the multiplied matrix in the next MMA operation.

[0198] As discussed previously, for use with the sparse matrix multiply and accumulate (HMMA) instruction, D represented by the diagonal can be converted to a dense 8×4 matrix AC and a 4×8 ACT matrix.

[0199] Define two functions:

[0200] CIdx(i,j) = the number of non-zeros in the i-th row before the non-zero in the j-th column of the i-th row; and

[0201] RIdx(i,j) = the number of non-zeros in the jth column before the non-zeros in the i-th row of the jth column.

[0202] From the definition of RIdx and CIdx functions:

[0203] AC[Idx[k], CIdx[J[k]+Idx[k]]]=D[k]; and

[0204] ACT[RIdx[J[k]+Idx[k]], Idx[k]]=D[k].

[0205] The column index functions CIdxI and RIdxI are the inverse functions of CIdx and RIdx, and will be used to select the matching elements of B and C.

[0206] Expand to other dense

[0207] Diagonal-wise storage is not limited to 4:8 sparsity, it can be used for any type of sparsity. In some example embodiments, the sparsity can be limited to 0.5 sparsity. Only the size of array D is changed. For the case where each row of A has 3 or more non-zeros, the size of the metadata (mask M) is close to the minimum.

[0208] In some example embodiments, the diagonal storage can be extended to 2:8 sparsity. In the case of 2:8 sparsity, the 64-bit mask can be replaced by a 48-bit vector M2, but the calculation of S, Q, R and other functions requires another step. M2 is 8 pairs of vectors, one pair per row. The first and second elements of each pair represent the first non-zero and second non-zero columns in each row.

[0209] The mask M can be calculated from M2 using the formulas M[i, M2[i, 0] + i] = 1 and M[i, M2[i, 1]] = 1. All other operations to convert D to AC and ACT are the same as in the 0.5 sparsity case.

[0210] Extension to large matrices

[0211] For a 16×16 matrix, 8×8 blocks with sparsity 0.5, all operations will be done independently on each block by 4 warps.

[0212] DLSM instruction

[0213] In certain example embodiments, a memory load instruction may include converting the retrieved compressed matrix data into a desired format. For example, a memory load instruction may include retrieving matrix data stored in a diagonal storage format from a shared memory, decompressing the data into another format (e.g., a dense matrix or a dense transposed matrix), and writing the decompressed data to a register. A DLSM instruction is an example of a memory load instruction that can provide a dense matrix from compressed matrix data stored diagonally.

[0214] DLSM loads four 4:8 matrices stored diagonally from shared memory into the register file. The result of the instruction is a 16×8 dense matrix written into registers (similar to the LDSM instruction) and metadata pointing to the rows of matrix B corresponding to the elements of A, as described in the sHMMA instruction.

[0215] For each block of matrix A, assume that the block and metadata compressed by the diagonal are loaded into shared memory (SMEM). The DLSM instruction scatters each block into registers as an 8×4 matrix. All 4 matrices will form a 16×8 matrix. Each block is loaded independently of each other by 32 threads (thread warps), one thread for each non-zero in the block.

[0216] The address of the destination of the compressed element is calculated using the functions described in the previous section and summarized here.

[0217] M is an 8-byte mask (64 bits in total) representing the non-zeros in the block.

[0218] Calculate CIdx(i,j) = the number of ones in the i-th row before the non-zero at the j-th column of the i-th row. This function tells the column numbers of the non-zeros in A in the matrix AC (block numbers 00, ..., 11 are skipped here).

[0219] Then calculate CIdxI(i,j), the inverse function of CIdx. CIdxI(i,j) = the jth non-zero column number in the i-th row. The function CIdxI will be used as metadata for the sHMMA instruction.

[0220] If an AT matrix is ​​required, use the row variables RIdx and RIdxI of CIdx and CIdxI.

[0221] The index required to find the address of the element of vector D in AC is then calculated. The calculations include: rotating the i-th row of M to the left by i positions; calculating the function S(j) = the column sum of M; calculating the function Q(j) = the prefix sum of S; calculating the function R[i, j] = the i-th non-zero row number in the j-th column; and calculating the function J(k), which indicates the diagonal number of the element D[k].

[0222] Example schematic representation of a decoder

[0223] Fig. 11B An example non-limiting schematic representation of a decoder is shown that can generate decompressed data from data in a diagonal storage format. Fig. 11B The output of the system in generates the row and column values ​​of the nonzero elements in the original matrix and / or the transposed matrix.

[0224] like Fig. 11B As shown, the shift circuit receives a bit mask indicating the position of non-zero elements in the matrix and generates a cyclically shifted bit mask. The shift circuit is configured to cyclically shift the rows of the bit mask by the row number bits. The columns in the cyclically shifted bit mask correspond to the rows in the original matrix. In one example, a demultiplexer (de-mux) can receive a bit stream and send respective row shift circuits configured to shift the row number bits. The multiplexer can reconstruct the shifted rows into a bit stream representing the cyclically shifted bit mask.

[0225] The shifted mask is provided to a plurality of circuits configured to determine the row and diagonal numbers of the non-zero values. Fig. 11B As shown, each non-zero value can be provided to a different circuit, which determines the row number and column number of the non-zero value. The row number extraction circuit can determine the row corresponding to the non-zero value in the shifted mask, and the diagonal number extraction circuit can determine the column number corresponding to the non-zero value in the shifted mask. These values ​​are used to determine the row number and column number of the non-zero value in the original matrix and / or the transposed matrix.

[0226] The row number of the non-zero element in the original matrix is ​​provided by the row number determined by the row number extraction unit. The column number of the non-zero element in the original matrix is ​​provided by an adder that combines the row determined by the row number extraction unit and the diagonal determined by the diagonal number extraction circuit.

[0227] The row number of the non-zero element in the transposed matrix is ​​provided by an adder that combines the row determined by the row number extraction unit with the diagonal determined by the diagonal number extraction circuit. The column number of the non-zero element in the transposed matrix is ​​provided by the row determined by the row number extraction unit.

[0228] The row values ​​and column values ​​of the non-zero elements in the original matrix and / or the transposed matrix may be used to reconstruct the original matrix and / or the transposed matrix, and / or, a reconstructed compact version of the original matrix and / or the transposed matrix.

[0229] 2:4 Description of the situation

[0230] Figure 12A-12C A matrix representation of the diagonal of a matrix having 4 elements and 2 non-zero values ​​for each row is shown.

[0231] Fig. 12A A matrix A and a compact matrix AC with metadata are shown, where the metadata can be used for sparse matrix multiplication and accumulation instructions. The elements of the compact matrix AC include A, B / C, D / E, F / G, H, and the metadata of the compact matrix includes 2, 1 / 1, 2 / 2, 1 / 1, 2 = 6, 9, 6, 9.

[0232] The compact transposed matrix ACT can be represented by elements C, G / A, E / B, F / D, H. The metadata of the compact matrix includes 2, 0 / 3, 1 / 3, 1 / 2, 0.

[0233] Diagonal storage consists of extracting the array D of nonzero elements in matrix A, such as Fig. 12B As shown, the array D = [F, H, A, G, B, D, C, E] lists the non-zero elements of each matrix diagonal starting from the diagonal d0. Each diagonal of the matrix A, each diagonal starts from the 0th row of the matrix.

[0234] Fig. 12C The bit mask nnz_mask and the circularly shifted bit mask nnz_mask are shown. The bit mask nnz_mask is generated with 1s representing the positions of non-zero elements in the matrix A and 0s representing the zero-valued elements in the matrix A. The hexadecimal representation of the matrix bitmap is 0x6969.

[0235] Next, the rows of the bit mask nnz_mask are circularly shifted. Specifically, the i-th row of the bit mask nnz_mask is circularly shifted to the left by i bits. After the circular shift, the 0th row remains unchanged, the 1st row is 0011 after being shifted to the left by 1, the 2nd row is 1001 after being shifted to the left by 2, and the 3rd row is 1100 after being shifted to the left by 3. The hexadecimal representation of the matrix bitmap after the circular shift is 0x6C93. Each column of the shifted bit mask nnz_mask corresponds to the diagonal of the original matrix.

[0236] The column sum of the shifted nnz_mask is 2222, which is represented by the vector S = [2, 2, 2, 2]. S(j) represents the number of non-zeros on the diagonal j, so S(0) = 2 indicates that the number of non-zeros on the diagonal 0 is 2.

[0237] The prefix of the column sum is 2468, represented by the vector Q. Q(j) will be the starting point of diagonal j in vector D. Q[0]=0, Q[1]=2, Q[2]=4, Q[3]=6.

[0238] The index function format is: diagonal number (column number in the M mask), followed by the row number of the non-zero elements along that diagonal (column of the M mask). 0:2 3 1:0 3 2:0 1 3:1 2

[0243] According to the index function format, the calculation function R[i,j] = the i-th non-zero row number in the j-th column. R[0,0] = 2, R[0,1] = 3, R[1,0] = 0, R[1,1] = 3, R[2,0] = 0, R[2,1] = 1, R[3,0] = 1 and R[3,1] = 2.

[0244] Use Q and R to compute the coordinates of the elements in the matrix or transposed matrix assigned the value of D. The coordinates of the elements in the diagonal j of the original matrix are given by:

[0245] A[R[j,i], R[j,i]+j]=D[Q[j]+i], where j=column number, i=0,..., S[j]–1, and Q[j]+i=k.

[0246] ====Reconstruct the original matrix:

[0247] A[R[0,0], R[0,0]+0]=AC[Q[0]+0] or A[2,2]=D[0]=F

[0248] A[R[0,1], R[0,1]+0]=AC[Q[0]+1] or A[3,3]=D[1]=H

[0249] A[R[1,0], R[1,0]+1]=AC[Q[1]+0] or A[0,1]=D[2]=A

[0250] A[R[1,1], R[1,1]+1]=AC[Q[1]+1] or A[3,0]=D[3]=G

[0251] A[R[2,0], R[2,0]+2]=AC[Q[2]+0] or A[0,2]=D[4]=B

[0252] A[R[2,1], R[2,1]+2]=AC[Q[2]+1] or A[1,3]=D[5]=D

[0253] A[R[3,0], R[3,0]+3]=AC[Q[3]+0] or A[1,0]=D[6]=C

[0254] A[R[3,1], R[3,1]+3]=AC[Q[3]+1] or A[2,1]=D[7]=E

[0255] The coordinates of the elements in the original matrix are given by:

[0256] AT[R[j,i]+j, R[j,i]]=D[Q[j]+i], where j=column number, i=0,..., S[j]–1, and Q[j]+i=k.

[0257] ===Reconstruct the transposed matrix:

[0258] AT[R[0,0]+0,R[0,0]]=AC[Q[0]+0] or A[2,2]=D[0]=F

[0259] AT[R[0,1]+0,R[0,1]]=AC[Q[0]+1] or A[3,3]=D[1]=H

[0260] AT[R[1,0]+1,R[1,0]]=AC[Q[1]+0] or A[1,0]=D[2]=A

[0261] AT[R[1,1]+1,R[1,1]]=AC[Q[1]+1] or A[0,3]=D[3]=G

[0262] AT[R[2,0]+2,R[2,0]]=AC[Q[2]+0] or A[2,0]=D[4]=B

[0263] AT[R[2,1]+2,R[2,1]]=AC[Q[2]+1] or A[3,1]=D[5]=D

[0264] AT[R[3,0]+3,R[3,0]]=AC[Q[3]+0] or A[0,1]=D[6]=C

[0265] AT[R[3,1]+3,R[3,1]]=AC[Q[3]+1] or A[1,2]=D[7]=E

[0266] 4:8 Explanation of Sparsity

[0267] An implementation of the calculation of functions S, Q and R is shown for a matrix with 8 rows, 8 columns and 32 non-zero values.

[0268] . / spmm_by_diagonals

[0269] ====num_rows 8num_cols 8nnz 32

[0270] ====MakeRandomCsrMatrix:requested nnz:32assigned nnz:32dims:8×8

[0271] ====nnz_mask of the created sparse matrix: 3C743C3C5A6C1E56 0 1 0 1 0 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 1 1 0 0 0 1 0 1 1 0 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 1 1 1 0 0

[0280] ====nnz_mask after circular shift:1E1D87C3D2B13C56 0 1 0 1 0 1 1 0 0 0 1 1 1 1 0 0 1 0 1 1 0 0 0 1 1 1 0 1 0 0 1 0 1 1 0 0 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 0 1 0 0 0 1 1 1 1 0

[0289] === ...

[0290] === ...

[0291] Index function format: diagonal number followed by the row number of non-zero values ​​along that diagonal 0:2 3 4 5 1:0 3 4 2:1 2 3:0 1 2 3 6 7 4:1 6 7 5:0 1 5 6 7 6:0 3 4 5 7 7:2 4 5 6

[0300] ====Testing by row has been completed.

[0301] The index function format is provided in the matrix A:

[0302] Diagonal 0 has four non-zero elements, located in rows 2, 3, 4, and 5;

[0303] Diagonal 1 has three non-zero elements, located in rows 0, 3, and 4;

[0304] Diagonal 2 has two non-zero elements, located in rows 1 and 2;

[0305] Diagonal 3 has six non-zero elements, located in rows 0, 1, 2, 3, 6, and 7;

[0306] Diagonal 4 has three non-zero elements, located in rows 1, 6, and 7;

[0307] Diagonal 5 has five non-zero elements, located in rows 0, 1, 5, 6, and 7;

[0308] Diagonal 6 has five non-zero elements, located in rows 0, 3, 4, 5, and 7; and

[0309] Diagonal 7 has four non-zero elements, located in rows 2, 4, 5, and 6.

[0310] The index function format and array D (including nonzero elements) can be used to determine the matrix and / or transposed matrix using the following equations:

[0311] A[R[j,i], R[j,i]+j] = D[Q[j]+i], where j = column number, i = 0, ..., S[j] - 1, and Q[j]+i = k; and

[0312] AT[R[j,i]+j, R[j,i]]=D[Q[j]+i], where j=column number, i=0,..., S[j]–1, and Q[j]+i=k.

[0313] A parallel processing architecture for generating data using a diagonal storage format and / or deriving data from data using a diagonal storage format Extract matrices and / or transpose matrices from data in

[0314] Now, more illustrative information about various optional architectures and features that can be used to implement the above framework will be described, depending on the needs of the user. It should be strongly noted that the following information is described for illustrative purposes and should not be interpreted as limiting in any way. Any of the following features can be combined with other features described, or these features may not be excluded.

[0315] Fig.13A parallel processing unit (PPU) 300 is shown according to one embodiment. In one embodiment, the PPU 300 is a multi-threaded processor implemented on one or more integrated circuit devices. The PPU 300 is a latency-hiding architecture designed for processing many threads in parallel. A thread (i.e., an execution thread) is an instance of an instruction set configured to be executed by the PPU 300. In one embodiment, the PPU 300 is a graphics processing unit (GPU) configured to implement a graphics rendering pipeline for processing three-dimensional (3D) graphics data to generate two-dimensional (2D) image data for display on a display device (such as a liquid crystal display (LCD) device). In other embodiments, the PPU 300 can be used to perform general-purpose calculations. Although an exemplary parallel processor is provided herein for illustrative purposes, it should be specifically noted that the processor is described only for illustrative purposes and any processor can be used to supplement and / or replace the processor.

[0316] One or more PPUs 300 can be configured to accelerate thousands of high-performance computing (HPC), data center, and machine learning applications. PPU 300 can be configured to accelerate numerous deep learning systems and applications, including autonomous vehicle platforms, deep learning, high-precision speech, image, and text recognition systems, intelligent video analysis, molecular simulation, drug development, disease diagnosis, weather forecasting, big data analysis, astronomy, molecular dynamics simulation, financial modeling, robotics, factory automation, real-time language translation, online search optimization, and personalized user recommendations, among others.

[0317] like Fig.13 As shown, the PPU 300 includes an input / output (I / O) unit 305, a front-end unit 315, a scheduler unit 320, a work distribution unit 325, a hub 330, a crossbar switch (Xbar) 370, one or more general processing clusters (GPCs) 350, and one or more partition units 380. The PPU 300 can be connected to a host processor or other PPUs 300 via one or more high-speed NVLink 310 interconnects. The PPU 300 can be connected to a host processor or other peripheral devices via an interconnect 302. The PPU 300 can also be connected to a local memory including multiple memory devices 304. In one embodiment, the local memory can include multiple dynamic random access memory (DRAM) devices. The DRAM device can be configured as a high bandwidth memory (HBM) subsystem, in which multiple DRAM dies are stacked within each device.

[0318] The NVLink 310 interconnect enables the system to scale and include one or more PPUs 300 in conjunction with one or more CPUs, supporting cache coherency between the PPU 300 and the CPU, and CPU mastering. Data and / or commands may be sent by the NVLink 310 through the hub 330 to or from other units of the PPU 300, such as one or more copy engines, video encoders, video decoders, power management units, etc. (not explicitly shown). Fig. 15B NVLink 310 is described in more detail.

[0319] I / O unit 305 is configured to send and receive communications (e.g., commands, data, etc.) from a host processor (not shown) via interconnect 302. I / O unit 305 may communicate with the host processor directly via interconnect 302, or through one or more intermediate devices (such as a memory bridge). In one embodiment, I / O unit 305 may communicate with one or more other processors (e.g., one or more PPUs 300) via interconnect 302. In one embodiment, I / O unit 305 implements a peripheral component interconnect express (PCIe) interface for communicating over a PCIe bus, and interconnect 302 is a PCIe bus. In alternative embodiments, I / O unit 305 may implement other types of known interfaces for communicating with external devices.

[0320] The I / O unit 305 decodes packets received via the interconnect 302. In one embodiment, the packets represent commands configured to cause the PPU 300 to perform various operations. The I / O unit 305 sends the decoded commands to various other units of the PPU 300 as specified by the commands. For example, some commands may be sent to the front end unit 315. Other commands may be sent to the hub 330 or other units of the PPU 300, such as one or more copy engines, video encoders, video decoders, power management units, etc. (not explicitly shown). In other words, the I / O unit 305 is configured to route communications between and among the various logical units of the PPU 300.

[0321] In one embodiment, a program executed by a host processor encodes a command stream in a buffer that provides a workload to the PPU 300 for processing. The workload may include many instructions and data to be processed by those instructions. A buffer is an area in memory that is accessible (e.g., read / write) by both the host processor and the PPU 300. For example, the I / O unit 305 may be configured to access a buffer in a system memory connected to the interconnect 302 via a memory request transmitted through the interconnect 302. In one embodiment, the host processor writes a command stream to the buffer and then sends a pointer to the start of the command stream to the PPU 300. The front end unit 315 receives a pointer to one or more command streams. The front end unit 315 manages one or more streams, reads commands from the streams, and forwards the commands to the various units of the PPU 300.

[0322] The front end unit 315 is coupled to a scheduler unit 320, which configures the various GPCs 350 to process the tasks defined by one or more streams. The scheduler unit 320 is configured to track state information related to the various tasks managed by the scheduler unit 320. The state may indicate which GPC 350 the task is assigned to, whether the task is active or inactive, a priority associated with the task, etc. The scheduler unit 320 manages the execution of multiple tasks on one or more GPCs 350.

[0323] Scheduler unit 320 is coupled to work distribution unit 325, which is configured to dispatch tasks for execution on GPC 350. Work distribution unit 325 may keep track of a number of scheduled tasks received from scheduler unit 320. In one embodiment, work distribution unit 325 manages a pending task pool and an active task pool for each GPC 350. The pending task pool may include a number of time slots (e.g., 32 time slots) containing tasks assigned to be processed by a particular GPC 350. The active task pool may include a number of time slots (e.g., 4 time slots) for tasks that are being actively processed by GPC 350. When a GPC 350 completes execution of a task, the task is evicted from the active task pool of GPC 350, and one of the other tasks from the pending task pool is selected and scheduled for execution on GPC 350. If an active task on a GPC 350 has become idle, such as while waiting for a data dependency to be resolved, then the active task may be evicted from the GPC 350 and returned to the pending task pool, while another task in the pending task pool is selected and scheduled for execution on the GPC 350 .

[0324] Work distribution unit 325 communicates with one or more GPCs 350 via XBar (crossbar) 370. XBar 370 is an interconnect network that couples many units of PPU 300 to other units of PPU 300. For example, XBar 370 can be configured to couple work distribution unit 325 to a particular GPC 350. Although not explicitly shown, one or more other units of PPU 300 can also be connected to XBar 370 via hub 330.

[0325] Tasks are managed by a scheduler unit 320 and dispatched to GPCs 350 by a work distribution unit 325. GPCs 350 are configured to process tasks and generate results. Results can be consumed by other tasks within the GPC 350, routed to a different GPC 350 via XBar 370, or stored in memory 304. Results can be written to memory 304 via a partition unit 380, which implements a memory interface for reading data from and writing data to memory 304. Results can be sent to another PPU 304 or CPU via NVLink 310. In one embodiment, a PPU 300 includes a number U of partition units 380, which is equal to the number of independent and distinct memory devices 304 coupled to the PPU 300. This will be described below in conjunction with Fig. 14B The partition unit 380 is described in more detail.

[0326] In one embodiment, the host processor executes a driver kernel that implements an application programming interface (API) that enables one or more applications to be executed on the host processor to schedule operations for execution on the PPU 300. In one embodiment, multiple computing applications are executed simultaneously by the PPU 300, and the PPU 300 provides isolation, quality of service (QoS), and independent address spaces for multiple computing applications. The application can generate instructions (e.g., API calls) that cause the driver kernel to generate one or more tasks to be executed by the PPU 300. The driver kernel outputs the tasks to one or more streams being processed by the PPU 300. Each task can include one or more related thread groups, referred to herein as thread warps. In one embodiment, a thread warp includes 32 related threads that can execute in parallel. Collaborating threads can refer to multiple threads that include instructions to perform tasks and can exchange data through shared memory. In combination Figure 5A Describes threads and cooperative threads in more detail.

[0327] Fig.14A According to an embodiment Fig.13 PPU 300 GPC 350. Fig.14AAs shown, each GPC 350 includes multiple hardware units for processing tasks. In one embodiment, each GPC 350 includes a pipeline manager 410, a pre-raster operation unit (PROP) 415, a raster engine 425, a work distribution crossbar switch (WDX) 480, a memory management unit (MMU) 490, and one or more data processing clusters (DPCs) 420. It should be understood that Fig.14A The GPC 350 may include instead Fig.14A Other hardware units or units other than those shown in Fig.14A Other hardware units than those shown in .

[0328] In one embodiment, the operation of the GPC 350 is controlled by a pipeline manager 410. The pipeline manager 410 manages the configuration of one or more DPCs 420 for processing tasks assigned to the GPC 350. In one embodiment, the pipeline manager 410 may configure at least one of the one or more DPCs 420 to implement at least a portion of a graphics rendering pipeline. For example, a DPC 420 may be configured to execute a vertex shading program on a programmable streaming multiprocessor (SM) 440. The pipeline manager 410 may also be configured to route packets received from the work distribution unit 325 to appropriate logic units in the GPC 350. For example, some packets may be routed to fixed-function hardware units in the PROP 415 and / or the raster engine 425, while other packets may be routed to the DPC 420 for processing by the primitive engine 435 or the SM 440. In one embodiment, the pipeline manager 410 may configure at least one of the one or more DPCs 420 to implement a neural network model and / or a computational pipeline.

[0329] PROP unit 415 is configured to route data generated by raster engine 425 and DPC 420 to a raster operations (ROP) unit, in conjunction with Fig. 14B The PROP unit 415 may also be configured to perform optimization of color blending, organize pixel data, perform address translation, etc.

[0330] Raster engine 425 includes several fixed function hardware units configured to perform various raster operations. In one embodiment, raster engine 425 includes a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, and a tile aggregation engine. The setup engine receives the transformed vertices and generates plane equations associated with the geometric primitives defined by the vertices. The plane equations are sent to the coarse raster engine to generate coverage information (e.g., x, y coverage masks of tiles) of the primitives. The output of the coarse raster engine is sent to the culling engine, where fragments associated with primitives that fail the z-test are culled, and unculled fragments are sent to the clipping engine, where fragments outside the viewing cone are clipped. Those fragments that remain after clipping and culling can be passed to the fine raster engine to generate attributes of pixel fragments based on the plane equations generated by the setup engine. The output of raster engine 425 includes, for example, fragments to be processed by a fragment shader implemented in DPC 420.

[0331] Each DPC 420 included in the GPC 350 includes an M pipeline controller (MPC) 430, a primitive engine 435, and one or more SMs 440. The MPC 430 controls the operation of the DPC 420, routing packets received from the pipeline manager 410 to appropriate units in the DPC 420. For example, packets associated with vertices may be routed to the primitive engine 435, which is configured to fetch vertex attributes associated with the vertices from the memory 304. Conversely, packets associated with shading programs may be sent to the SM 440.

[0332] SM 440 includes a programmable stream processor configured to process tasks represented by multiple threads. Each SM440 is multithreaded and is configured to execute multiple threads (e.g., 32 threads) from a specific thread group simultaneously. In one embodiment, SM 440 implements a SIMD (single instruction, multiple data) architecture, wherein each thread in a thread group (e.g., warp) is configured to process different data sets based on the same instruction set. All threads in a thread group execute the same instruction. In another embodiment, SM 440 implements a SIMT (single instruction, multiple thread) architecture, wherein each thread in a thread group is configured to process different data sets based on the same instruction set, but wherein each thread in a thread group is allowed to diverge during execution. In one embodiment, a program counter, a call stack, and an execution state are maintained for each thread bundle, and when threads within a thread bundle diverge, concurrency between serial executions in the thread bundle and the thread bundle is made possible. In another embodiment, a program counter, a call stack, and an execution state are maintained for each individual thread, thereby achieving equal concurrency between all threads within and between thread bundles. When execution state is maintained for each individual thread, threads executing the same instructions can be converged and executed in parallel for maximum efficiency. Fig.15A SM 440 is described in more detail.

[0333] MMU 490 provides an interface between GPC 350 and partition unit 380. MMU 490 can provide virtual address to physical address translation, memory protection, and arbitration of memory requests. In one embodiment, MMU 490 provides one or more translation lookaside buffers (TLBs) for performing translations from virtual addresses to physical addresses in memory 304.

[0334] Fig. 14B According to an embodiment Fig.13 The memory partition unit 380 of the PPU 300. Fig. 14B As shown, the memory partition unit 380 includes a raster operation (ROP) unit 450, a second level (L2) cache 460, and a memory interface 470. The memory interface 470 is coupled to the memory 304. The memory interface 470 can implement a 32, 64, 128, 1024 bit data bus, etc. for high-speed data transmission. In one embodiment, the PPU 300 incorporates U memory interfaces 470, one for each pair of partition units 380, wherein each pair of partition units 380 is connected to a corresponding memory device 304. For example, the PPU 300 can be connected to up to Y memory devices 304, such as a high bandwidth memory stack or a graphics double data rate version 5 synchronous dynamic random access memory or other types of persistent memory.

[0335] In one embodiment, memory interface 470 implements an HBM2 memory interface, and Y is equal to half of U. In one embodiment, the HBM2 memory stack is located on the same physical package as PPU 300, providing significant power and area savings compared to conventional GDDR5 SDRAM systems. In one embodiment, each HBM2 stack includes four memory dies and Y is equal to 4, where the HBM2 stack includes two 128-bit channels per die, a total of 8 channels and a data bus width of 1024 bits.

[0336] In one embodiment, memory 304 supports single error correction double error detection (SECDED) error correction code (ECC) to protect data. ECC provides higher reliability for computing applications that are sensitive to data corruption. Reliability is particularly important in large cluster computing environments where PPU 300 processes very large data sets and / or long-running applications.

[0337] In one embodiment, the PPU 300 implements a multi-level memory hierarchy. In one embodiment, the memory partition unit 380 supports unified memory to provide a single unified virtual address space for the CPU and PPU 300 memory, enabling data sharing between virtual memory systems. In one embodiment, the frequency of PPU 300 accesses to memory located on other processors is tracked to ensure that memory pages are moved to the physical memory of the PPU 300 that accesses the page more frequently. In one embodiment, the NVLink 310 supports address translation services that allow the PPU 300 to directly access the CPU's page tables and provide full access to the CPU memory by the PPU 300.

[0338] In one embodiment, the copy engine transfers data between multiple PPUs 300 or between a PPU 300 and a CPU. The copy engine can generate a page fault for an address that is not mapped to a page table. The memory partition unit 380 can then service the page fault, map the address into a page table, and then the copy engine can perform the transfer. In conventional systems, fixed memory (e.g., non-pageable) is operated for multiple copy engines between multiple processors, which significantly reduces the available memory. Due to hardware paging faults, addresses can be passed to the copy engine without worrying about whether the memory page is resident, and the copy process is transparent.

[0339] Data from memory 304 or other system memory may be retrieved by memory partition unit 380 and stored in L2 cache 460, which is located on-chip and shared between various GPCs 350. As shown, each memory partition unit 380 includes a portion of L2 cache 460 associated with a corresponding memory device 304. Lower level caches may then be implemented in multiple units within a GPC 350. For example, each SM 440 may implement a level 1 (L1) cache. An L1 cache is a dedicated memory dedicated to a particular SM 440. Data from L2 cache 460 may be retrieved and stored in each L1 cache for processing in a functional unit of the SM 440. L2 cache 460 is coupled to a memory interface 470 and an XBar 370.

[0340] The ROP unit 450 performs graphics raster operations related to pixel color such as color compression, pixel blending, etc. The ROP unit 450 also implements depth testing in conjunction with the raster engine 425, receiving the depth of a sample position associated with a pixel fragment from the culling engine of the raster engine 425. The depth of the sample position associated with the fragment is tested relative to the corresponding depth in the depth buffer. If the fragment passes the depth test for the sample position, the ROP unit 450 updates the depth buffer and sends the result of the depth test to the raster engine 425. It will be understood that the number of partition units 380 may be different than the number of GPCs 350, and thus each ROP unit 450 may be coupled to each GPC 350. The ROP unit 450 tracks packets received from different GPCs 350 and determines to which GPC 350 the results generated by the ROP unit 450 are routed via the Xbar 370. Although in Fig. 14B In the embodiment shown, ROP unit 450 is included within memory partition unit 380, but in other embodiments, ROP unit 450 may be external to memory partition unit 380. For example, ROP unit 450 may reside in GPC 350 or another unit.

[0341] Fig.15A According to an embodiment Fig.14A The streaming multiprocessor 440. Fig.15A As shown, SM 440 includes an instruction cache 505, one or more scheduler units 510, a register file 520, one or more processing cores 550, one or more special function units (SFU) 552, one or more load / store units (LSU) 554, an interconnection network 580, and a shared memory / L1 cache 570.

[0342] As described above, the work distribution unit 325 schedules tasks to be executed on the GPC 350 of the PPU 300. Tasks are assigned to specific DPCs 420 within the GPC 350, and if the task is associated with a shader program, the task may be assigned to the SM 440. The scheduler unit 510 receives tasks from the work distribution unit 325 and manages the scheduling of instructions assigned to one or more thread blocks assigned to the SM 440. The scheduler unit 510 schedules the thread blocks to execute as warps of parallel threads, where each thread block is assigned at least one warp. In one embodiment, each warp executes 32 threads. The scheduler unit 510 can manage a plurality of different thread blocks, assign warps to different thread blocks, and then dispatch instructions from a plurality of different cooperative groups to various functional units (i.e., core 550, SFU 552, and LSU 554) during each clock cycle.

[0343] Cooperative Groups is a programming model for organizing groups of communicating threads that allows developers to express the granularity at which threads are communicating, enabling the expression of richer and more efficient decompositions of parallelism. The cooperative launch API supports synchronization between thread blocks to execute parallel algorithms. Conventional programming models provide a single simple structure for synchronizing cooperative threads: a barrier across all threads of a thread block (e.g., the syncthreads() function). However, programmers often want to define thread groups at a granularity smaller than the thread block granularity and synchronize within the defined group, enabling higher performance, design flexibility, and software reuse in the form of a collective group-wide function interface.

[0344] Cooperative Groups enables programmers to explicitly define thread groups at sub-block (e.g., as small as a single thread) and multi-block granularity and perform collective operations such as synchronization on threads in a cooperative group. The programming model supports clean composition across software boundaries so that libraries and utility functions can safely synchronize in their local environment without making assumptions about convergence. Cooperative Groups primitives enable new patterns of cooperative parallelism, including producer-consumer parallelism, opportunistic parallelism, and global synchronization across the entire grid of thread blocks.

[0345] The dispatch unit 515 is configured to transmit instructions to one or more functional units. In this embodiment, the scheduler unit 510 includes two dispatch units 515, which enables two different instructions from the same thread warp to be scheduled during each clock cycle. In alternative embodiments, each scheduler unit 510 may include a single dispatch unit 515 or additional dispatch units 515.

[0346] Each SM 440 includes a register file 520 that provides a set of registers for the functional units of the SM 440. In one embodiment, the register file 520 is divided between each functional unit so that each functional unit is assigned a dedicated portion of the register file 520. In another embodiment, the register file 520 is divided between different warps executed by the SM 440. The register file 520 provides temporary storage for operands connected to the data paths of the functional units.

[0347] Each SM 440 includes L processing cores 550. In one embodiment, SM 440 includes a large number (e.g., 128, etc.) of different processing cores 550. Each core 550 may include a fully pipelined, single-precision, double-precision, and / or mixed-precision processing unit, including a floating-point arithmetic logic unit and an integer arithmetic logic unit. In one embodiment, the floating-point arithmetic logic unit implements the IEEE 754-2008 standard for floating-point operations. In one embodiment, core 550 includes 64 single-precision (32-bit) floating-point cores, 64 integer cores, 32 double-precision (64-bit) floating-point cores, and 8 tensor cores.

[0348] The tensor cores are configured to perform matrix operations, and in one embodiment, one or more tensor cores are included in core 550. Specifically, the tensor cores are configured to perform deep learning matrix operations, such as convolution operations for neural network training and inference. In one embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiplication and accumulation operation D=A×B+C, where A, B, C, and D are 4×4 matrices.

[0349] In one embodiment, the matrix multiplication inputs A and B are 16-bit floating point matrices, while the accumulation matrices C and D can be 16-bit floating point or 32-bit floating point matrices. The tensor cores operate on 16-bit floating point input data as well as 32-bit floating point accumulations. The 16-bit floating point multiplication requires 64 operations, producing full-precision products, which are then accumulated using 32-bit floating point additions with other intermediate products of the 4×4×4 matrix multiplication. In practice, tensor cores are used to perform larger two-dimensional or higher dimensional matrix operations built from these smaller elements. APIs (such as the CUDA 9 C++ API) expose specialized matrix loads, matrix multiplications and accumulations, and matrix storage operations to efficiently use tensor cores from CUDA-C++ programs. At the CUDA level, the warp-level interface assumes that the 16×16 size matrix spans all 32 threads of the warp.

[0350] In some embodiments, the transposition hardware is included in the processing core 550 or another functional unit (e.g., SFUs 552 or LSUs 554) and is configured to generate matrix data stored by diagonals and / or generate original matrices and / or transposed matrices from matrix data stored by diagonals. The transposition hardware can provide a load path to the register file 520 of the SM 440 within the shared memory 570.

[0351] In one example, the matrix data stored by the diagonal can be taken from the DRAM and stored in the shared memory 570. When the instruction to perform processing using the matrix data stored by the diagonal is processed, the transposition hardware provided in the path of the shared memory 570 and the register file 520 can provide the original matrix, the transposed matrix, the compact original matrix and / or the compact transposed matrix. The single matrix data stored by the diagonal can be maintained until the last storage before the instruction, and the matrix type specified by the instruction is generated in the register file 520 as needed.

[0352] Each SM 440 also includes M SFUs 552 that perform special functions (e.g., attribute evaluation, reciprocal square root, etc.). In one embodiment, the SFUs 552 may include a tree traversal unit configured to traverse a hierarchical tree data structure. In one embodiment, the SFUs 552 may include a texture unit configured to perform texture map filtering operations. In one embodiment, the texture unit is configured to load a texture map (e.g., a 2D array of texture pixels) from memory 304 and sample the texture map to produce sampled texture values ​​for use in a shader program executed by the SM 440. In one embodiment, the texture map is stored in a shared memory / L1 cache 470. The texture unit implements texture operations, such as filtering operations using mip maps (i.e., texture maps of different levels of detail). In one embodiment, each SM 440 includes two texture units.

[0353] Each SM 440 also includes N LSUs 554 that implement load operations and store operations between the shared memory / L1 cache 570 and the register file 520. Each SM 440 includes an interconnect network 580 that connects each functional unit to the register file 520 and connects the LSUs 554 to the register file 520 and the shared memory / L1 cache 570. In one embodiment, the interconnect network 580 is a crossbar switch that can be configured to connect any functional unit to any register in the register file 520 and to connect the LSUs 554 to memory locations in the register file and the shared memory / L1 cache 570.

[0354] The shared memory / L1 cache 570 is an on-chip memory array that allows data storage and communication between the SM 440 and the primitive engine 435, as well as between threads in the SM 440. In one embodiment, the shared memory / L1 cache 570 includes 128KB of storage capacity and is in the path from the SM 440 to the partition unit 380. The shared memory / L1 cache 570 can be used to cache reads and writes. One or more of the shared memory / L1 cache 570, the L2 cache 460, and the memory 304 is a backing store.

[0355] Combining the data cache and shared memory functions into a single memory block provides the best overall performance for both types of memory accesses. This capacity can be used by programs as a cache that does not use the shared memory. For example, if the shared memory is configured to use half of the capacity, texture and load / store operations can use the remaining capacity. Integration within the shared memory / L1 cache 570 enables the shared memory / L1 cache 570 to function as a high throughput pipeline for streaming data, while providing high bandwidth and low latency access to frequently reused data.

[0356] When configured for general parallel computing, a simpler configuration can be used compared to graphics processing. Specifically, the fixed-function graphics processing unit shown in Figure 3 is bypassed, creating a simpler programming model. In the general parallel computing configuration, the work distribution unit 325 assigns and distributes thread blocks directly to the DPC 420. The threads in the block execute the same program, use unique thread IDs in the calculation to ensure that each thread generates a unique result, use SM 440 to execute the program and perform calculations, use shared memory / L1 cache 570 to communicate between threads, and use LSU 554 to read and write global memory through shared memory / L1 cache 570 and memory partition unit 380. When configured for general parallel computing, SM 440 can also write commands that the scheduler unit 320 can use to start new work on DPC 420.

[0357] The PPU 300 may be included in a desktop computer, a laptop computer, a tablet computer, a server, a supercomputer, a smartphone (e.g., wireless, handheld device), a personal digital assistant (PDA), a digital camera, a vehicle, a head-mounted display, a handheld electronic device, etc. In one embodiment, the PPU 300 is included on a single semiconductor substrate. In another embodiment, the PPU 300 is included on a system on a chip (SoC) along with one or more other devices (such as an additional PPU 300, a memory 304, a reduced instruction set computer (RISC) CPU, a memory management unit (MMU), a digital-to-analog converter (DAC), etc.).

[0358] In one embodiment, PPU 300 may be included on a graphics card that includes one or more memory devices 304. The graphics card may be configured to interface with a PCIe slot on a motherboard of a desktop computer. In yet another embodiment, PPU 300 may be an integrated graphics processing unit (iGPU) or parallel processor included in a chipset of a motherboard.

[0359] Exemplary Computing System

[0360] Systems with multiple GPUs and CPUs are used in a variety of industries as developers expose and exploit more parallelism in applications such as artificial intelligence computing. High-performance GPU-accelerated systems with tens to thousands of computing nodes are deployed in data centers, research institutions, and supercomputers to solve larger problems. As the number of processing devices within high-performance systems increases, communication and data transmission mechanisms need to scale to support this increased bandwidth.

[0361] Fig. 15B According to one embodiment, the use Fig.13 The exemplary system 500 may be configured to implement the method disclosed in the present application (eg, FIG. 5 , Figure 6 or Figure 8 The processing system 500 includes a CPU 530, a switch 555, and each of the plurality of PPUs 300 and a corresponding memory 304. NVLink 310 provides a high-speed communication link between each PPU 300. Fig. 15B 302 connections, but the number of connections connected to each PPU 300 and CPU 530 may vary. Switch 555 interfaces between interconnect 302 and CPU 530. PPU 300, memory 304, and NVLink 310 may be located on a single semiconductor platform to form parallel processing module 525. In one embodiment, switch 555 supports two or more protocols that interface between various different connections and / or links.

[0362] In another embodiment (not shown), NVLink 310 provides one or more high-speed communication links between each PPU 300 and CPU 530, and switch 555 interfaces between interconnect 302 and each PPU 300. PPU 300, memory 304, and interconnect 302 may be located on a single semiconductor platform to form parallel processing module 525. In yet another embodiment (not shown), interconnect 302 provides one or more communication links between each PPU 300 and CPU 530, and switch 555 interfaces between each PPU 300 using NVLink 310 to provide one or more high-speed communication links between PPU 300. In another embodiment (not shown), NVLink 310 provides one or more high-speed communication links between PPU 300 and CPU 530 through switch 555. In yet another embodiment (not shown), interconnect 302 provides one or more communication links directly between each PPU 300. One or more NVLink 310 high-speed communication links may be implemented as a physical NVLink interconnect or as an on-chip or on-die interconnect using the same protocol as NVLink 310.

[0363] In the context of this specification, a single semiconductor platform may refer to a unique single semiconductor-based integrated circuit manufactured on a bare die or chip. It should be noted that the term single semiconductor platform may also refer to a multi-chip module with increased connectivity that simulates on-chip operations and is substantially improved by utilizing conventional bus implementations. Of course, various circuits or devices may also be placed separately or in various combinations of semiconductor platforms, depending on the needs of the user. Optionally, the parallel processing module 525 may be implemented as a circuit board substrate, and each of the PPU 300 and / or memory 304 may be a packaged device. In one embodiment, the CPU 530, the switch 555, and the parallel processing module 525 are located on a single semiconductor platform.

[0364] In one embodiment, the signaling rate of each NVLink 310 is 20 to 25 Gbit / s, and each PPU 300 includes six NVLink 310 interfaces (e.g., Fig. 15B Each NVLink 310 provides a data transfer rate of 25 Gbit / s in each direction, with six links providing 300 Gbit / s. When the CPU 530 also includes one or more NVLink 310 interfaces, the NVLink 310 can be used exclusively for, for example, Fig. 15B PPU to PPU communication as shown, or some combination of PPU to PPU and PPU to CPU.

[0365] In one embodiment, NVLink 310 allows direct load / store / atomic access from CPU 530 to memory 304 of each PPU 300. In one embodiment, NVLink 310 supports coherency operations, allowing data read from memory 304 to be stored in the cache hierarchy of CPU 530, reducing cache access latency of CPU 530. In one embodiment, NVLink 310 includes support for address translation services (ATS), allowing PPU 300 to directly access page tables within CPU 530. One or more NVLink 310 can also be configured to operate in a low power mode.

[0366] Fig. 15C An exemplary system 565 is shown in which various architectures and / or functions of various previous embodiments can be implemented. The exemplary system 565 can be configured to implement the methods disclosed in the present application (e.g., FIG. 5, Figure 6 or Figure 8 method shown).

[0367] As shown, a system 565 is provided that includes at least one central processing unit 530 connected to a communication bus 575. The communication bus 575 can be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect), PCI-Express, AGP (Accelerated Graphics Port), HyperTransport, or any other bus or one or more point-to-point communication protocols. The system 565 also includes a main memory 540. Control logic (software) and data are stored in the main memory 540, which can take the form of a random access memory (RAM).

[0368] The system 565 also includes an input device 560, a parallel processing system 525, and a display device 545, such as a conventional CRT (cathode ray tube), LCD (liquid crystal display), LED (light emitting diode), plasma display, etc. User input can be received from the input device 560 (e.g., keyboard, mouse, touch pad, microphone, etc.). Each of the aforementioned modules and / or devices can even be located on a single semiconductor platform to form the system 565. Optionally, the modules can also be placed separately or in various combinations of semiconductor platforms according to the needs of the user.

[0369] Furthermore, system 565 may be coupled to a network (e.g., a telecommunications network, a local area network (LAN), a wireless network, a wide area network (WAN) such as the Internet, a peer-to-peer network, a cable network, etc.) through network interface 535 for communication purposes.

[0370] The system 565 may also include auxiliary storage (not shown). The auxiliary storage 610 includes, for example, a hard disk drive and / or a removable storage drive, representative of a floppy disk drive, a tape drive, an optical disk drive, a digital versatile disk (DVD) drive, a recording device, a universal serial bus (USB) flash memory. The removable storage drive reads from and / or writes to a removable storage unit in a well-known manner.

[0371] Computer programs or computer control logic algorithms may be stored in the main memory 540 and / or the secondary storage. These computer programs, when executed, enable the system 565 to perform various functions. The memory 540, storage and / or any other storage are possible examples of computer-readable media.

[0372] The architecture and / or functionality of the various prior figures may be implemented in the context of a general purpose computer system, a circuit board system, a game console system dedicated to entertainment purposes, a dedicated system, and / or any other desired system. For example, system 565 may take the form of a desktop computer, a laptop computer, a tablet computer, a server, a supercomputer, a smartphone (e.g., a wireless, handheld device), a personal digital assistant (PDA), a digital camera, a vehicle, a head mounted display, a handheld electronic device, a mobile telephone device, a television, a workstation, a game console, an embedded system, and / or any other type of logic.

[0373] Although various embodiments have been described above, it should be understood that they are presented by way of example only and not limitation. Thus, the breadth and scope of a preferred embodiment should not be limited by any of the above-described exemplary embodiments, but should be limited only in accordance with the following claims and their equivalents.

[0374] Graphics Processing Pipeline

[0375] In one embodiment, the PPU 300 includes a graphics processing unit (GPU). The PPU 300 is configured to receive commands specifying a shader for processing graphics data. The graphics data may be defined as a set of primitives, such as points, lines, triangles, quadrilaterals, triangle strips, etc. Typically, a primitive includes data specifying a plurality of vertices of the primitive (e.g., in a model space coordinate system) and attributes associated with each vertex of the primitive. The PPU 300 may be configured to process the primitives to generate a frame buffer (e.g., pixel data for each of the pixels of a display).

[0376] The application writes the model data (e.g., a collection of vertices and attributes) of the scene to a memory (such as system memory or memory 304). The model data defines each of the objects that may be visible on the display. The application then makes an API call to the driver kernel, which requests the model data to be rendered and displayed. The driver kernel reads the model data and writes commands to one or more streams to perform operations to process the model data. These commands may refer to different shading programs to be implemented on the SM440 of the PPU 300, including one or more of vertex shading, hull shading, domain shading, geometry shading, and pixel shading. For example, one or more of the SMs 440 may be configured to execute a vertex shading program that processes multiple vertices defined by the model data. In one embodiment, different SMs 440 may be configured to execute different shading programs simultaneously. For example, a first subset of SMs 440 may be configured to execute a vertex shading program, and a second subset of SMs 440 may be configured to execute a pixel shading program. The first subset of SMs 440 processes the vertex data to generate processed vertex data, and writes the processed vertex data to the L2 cache 460 and / or the memory 304. After the processed vertex data is rasterized (e.g., converted from three-dimensional data to two-dimensional data in screen space) to generate fragment data, a second subset of SMs 440 performs pixel shading to generate processed fragment data, which is then blended with other processed fragment data and written to a frame buffer in memory 304. Vertex shading programs and pixel shading programs can be executed simultaneously, processing different data from the same scene in a pipelined manner until all model data for the scene has been rendered to the frame buffer. The contents of the frame buffer are then transmitted to a display controller for display on a display device.

[0377] Fig.16 According to one embodiment, Fig.13 300 of FIG. 1 . Graphics processing pipeline 600 is an abstract flow chart of processing steps implemented to generate a 2D computer-generated image from 3D geometric data. As is well known, pipeline architectures can perform long latency operations more efficiently by breaking the operations into multiple stages, where the output of each stage is coupled to the input of the next consecutive stage. Thus, graphics processing pipeline 600 receives input data 601 that is passed from one stage of graphics processing pipeline 600 to the next stage to generate output data 602. In one embodiment, graphics processing pipeline 600 may represent a graphics processing pipeline composed of API-defined graphics processing pipeline. Alternatively, graphics processing pipeline 600 can be implemented in the functional and architectural context of the previous figures and / or one or more of any subsequent figures.

[0378] like Fig.16As shown, the graphics processing pipeline 600 includes a pipeline architecture including multiple stages. These stages include, but are not limited to, a data assembly stage 610, a vertex shading stage 620, a primitive assembly stage 630, a geometry shading stage 640, a viewport scale, cull, and clip (VSCC) stage 650, a rasterization stage 660, a fragment shading stage 670, and a raster operation stage 680. In one embodiment, input data 601 includes commands that configure a processing unit to implement the stages of the graphics processing pipeline 600 and configure geometric primitives (e.g., points, lines, triangles, quadrilaterals, triangle strips or fans, etc.) to be processed by these stages. Output data 602 may include pixel data (i.e., color data), which is copied to a frame buffer or other type of surface data structure in memory.

[0379] The data assembly stage 610 receives input data 601, which specifies vertex data for high-order surfaces, primitives, etc. The data assembly stage 610 collects the vertex data in temporary storage or queues, such as by receiving a command from a host processor including a pointer to a buffer in memory and reading the vertex data from the buffer. The vertex data is then passed to the vertex shading stage 620 for processing.

[0380] The vertex shading stage 620 processes vertex data by executing a set of operations (e.g., a vertex shader or program) once for each vertex. A vertex may be specified, for example, as a 4-coordinate vector (e.g.,<x,y,z,w> ). The vertex shading stage 620 can manipulate various vertex attributes, such as position, color, texture coordinates, etc. In other words, the vertex shading stage 620 performs operations on vertex coordinates or other vertex attributes associated with the vertex. These operations typically include lighting operations (e.g., modifying the color attribute of the vertex) and transformation operations (e.g., modifying the coordinate space of the vertex). For example, a vertex can be specified using coordinates in an object coordinate space, which is transformed by multiplying the coordinates by a matrix that converts the coordinates from the object coordinate space to world space or normalized-device-coordinate (NCD) space. The vertex shading stage 620 generates transformed vertex data that is transmitted to the primitive assembly stage 630.

[0381] The primitive assembly stage 630 collects the vertices output by the vertex shading stage 620 and groups the vertices into geometric primitives for processing by the geometry shading stage 640. For example, the primitive assembly stage 630 may be configured to group every three consecutive vertices into geometric primitives (e.g., triangles) for transmission to the geometry shading stage 640. In some embodiments, particular vertices may be reused for consecutive geometric primitives (e.g., two consecutive triangles in a triangle strip may share two vertices). The primitive assembly stage 630 transmits the geometric primitives (e.g., a collection of associated vertices) to the geometry shading stage 640.

[0382] The geometry shading stage 640 processes geometric primitives by performing a set of operations (e.g., geometry shaders or programs) on the geometric primitives. A tessellation operation can generate one or more geometric primitives from each geometric primitive. In other words, the geometry shading stage 640 can subdivide each geometric primitive into a finer grid of two or more geometric primitives for processing by the rest of the graphics processing pipeline 600. The geometry shading stage 640 transmits the geometric primitives to the viewport SCC stage 650.

[0383] In one embodiment, the graphics processing pipeline 600 can operate within a streaming multiprocessor and vertex shading stage 620, primitive assembly stage 630, geometry shading stage 640, fragment shading stage 670 and / or hardware / software associated therewith, and can perform processing operations sequentially. Once the sequential processing operations are completed, in one embodiment, the viewport SCC stage 650 can utilize the data. In one embodiment, primitive data processed by one or more stages in the graphics processing pipeline 600 can be written to a cache (e.g., an L1 cache, a vertex cache, etc.). In this case, in one embodiment, the viewport SCC stage 650 can access the data in the cache. In one embodiment, the viewport SCC stage 650 and the rasterization stage 660 are implemented as fixed function circuits.

[0384] The viewport SCC stage 650 performs viewport scaling, culling, and clipping of geometric primitives. Each surface being rendered is associated with an abstract camera position. The camera position represents the position of the viewer who is viewing the scene and defines a view cone that surrounds the objects of the scene. The view cone may include a viewing plane, a back plane, and four clipping planes. Any geometric primitives that are completely outside the view cone may be culled (e.g., discarded) because they will not contribute to the final rendered scene. Any geometric primitives that are partially within the view cone and partially outside the view cone may be clipped (e.g., converted to new geometric primitives that are enclosed within the view cone). In addition, each geometric primitive may be scaled based on the depth of the view cone. All potentially visible geometric primitives are then transferred to the rasterization stage 660.

[0385] The rasterization stage 660 converts 3D geometric primitives into 2D fragments (e.g., capable of being used for display, etc.). The rasterization stage 660 can be configured to use the vertices of the geometric primitives to set a set of plane equations from which various attributes can be interpolated. The rasterization stage 660 can also calculate a coverage mask for multiple pixels, which indicates whether one or more sample positions of a pixel intercept the geometric primitive. In one embodiment, a z test can also be performed to determine whether the geometric primitive is occluded by other geometric primitives that have been rasterized. The rasterization stage 660 generates fragment data (e.g., interpolated vertex attributes associated with a specific sample position of each covered pixel), which is transmitted to the fragment shading stage 670.

[0386] The fragment shading stage 670 processes the fragment data by executing a set of operations (e.g., a fragment shader or program) on each of the fragments. The fragment shading stage 670 may generate pixel data (e.g., color values) for the fragments, such as by performing lighting operations or sampling a texture map using interpolated texture coordinates of the fragments. The fragment shading stage 670 generates pixel data, which is sent to the raster operations stage 680.

[0387] Raster operations stage 680 may perform various operations on the pixel data, such as performing alpha tests, stencil tests, and blending the pixel data with other pixel data corresponding to other fragments associated with the pixel. When raster operations stage 680 has completed processing the pixel data (e.g., output data 602), the pixel data may be written to a render target, such as a frame buffer, a color buffer, etc.

[0388] It should be appreciated that one or more additional stages may be included in the graphics processing pipeline 600 in addition to or in place of one or more of the above-described stages. Various implementations of the abstract graphics processing pipeline may implement different stages. Furthermore, in some embodiments, one or more of the above-described stages may be excluded from the graphics processing pipeline (such as the geometry shading stage 640). Other types of graphics processing pipelines are considered to be contemplated within the scope of the present disclosure. Furthermore, any stage of the graphics processing pipeline 600 may be implemented by one or more dedicated hardware units within a graphics processor (such as PPU 300). Other stages of the graphics processing pipeline 600 may be implemented by programmable hardware units (such as SM 440 of PPU 300).

[0389] The graphics processing pipeline 600 may be implemented via an application program executed by a host processor (such as a CPU). In one embodiment, a device driver may implement an application programming interface (API) that defines various functions that can be utilized by an application program to generate graphics data for display. A device driver is a software program that includes a plurality of instructions that control the operation of the PPU 300. The API provides an abstraction for programmers that allows programmers to utilize dedicated graphics hardware (such as the PPU 300) to generate graphics data without requiring the programmer to utilize a specific instruction set of the PPU 300. An application program may include an API call that is routed to a device driver of the PPU 300. The device driver interprets the API call and performs various operations in response to the API call. In some cases, the device driver may perform operations by executing instructions on the CPU. In other cases, the device driver may perform operations at least in part by initiating operations on the PPU 300 using an input / output interface between the CPU and the PPU 300. In one embodiment, the device driver is configured to implement the graphics processing pipeline 600 using the hardware of the PPU 300.

[0390] Various programs may be executed within the PPU 300 to implement the various stages of the graphics processing pipeline 600. For example, a device driver may launch a kernel on the PPU 300 to execute the vertex shading stage 620 on one SM 440 (or multiple SMs 440). The device driver (or the initial kernel executed by the PPU 400) may also launch other kernels on the PPU 400 to execute other stages of the graphics processing pipeline 600, such as the geometry shading stage 640 and the fragment shading stage 670. In addition, some of the stages of the graphics processing pipeline 600 may be implemented on fixed unit hardware, such as a rasterizer or data assembler implemented within the PPU 400. It should be appreciated that the results from one kernel may be processed by one or more intermediate fixed function hardware units before being processed by subsequent kernels on the SM 440.

[0391] Example Technical Advantages of Some Embodiments

[0392] Certain example embodiments provide improved generation of original matrices and / or transposed matrices from compressed matrix data.

[0393] Compared to conventional methods of storing matrices and generating transposed matrices, example embodiments of the methods and systems of the present invention use less storage, improve transmission time and / or reduce computation time. Unlike conventional methods, when using the diagonal storage format, both the original matrix and the transposed matrix do not need to be stored and / or transmitted, because the original matrix, the transposed matrix, the compact original matrix and / or the compact transposed matrix can be easily generated from the diagonal storage format. In addition, the advantages of the diagonal storage format are also applicable to large matrices.

[0394] Numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the present invention may be practiced otherwise than as specifically described herein.

Claims

1. A data decompressor system, comprising: An input circuit configured to receive a compressed data file comprising: (a) a stream of non-zero values ​​along a diagonal of a sparse matrix and (b) a mask indicating the sparse matrix locations of the non-zero values; and A decoder configured to use the mask to fill a transposed dense matrix with the non-zero values ​​in the stream, wherein the decoder is configured to fill the transposed dense matrix based on the compressed data without writing intermediate result matrix data back to memory.

2. The data decompressor system according to claim 1, wherein: The sparsity of the sparse matrix is ​​greater than 0.

5.

3. The data decompressor system according to claim 1, wherein: The intermediate result matrix data includes a non-transposed sparse matrix and / or a non-transposed dense matrix.

4. The data decompressor system of claim 1, wherein: The decoder is configured to selectively fill a non-transposed matrix, a non-transposed dense matrix, a transposed sparse matrix, or the transposed dense matrix with the non-zero values ​​in the stream based on the mask.

5. The data decompressor system of claim 1, wherein: The mask comprises a bit mask indicating the position of each non-zero value in the sparse matrix, the decoder being further configured to: Circularly shifting the i-th row of the bit mask left by i bits; Determining rows having non-zero values ​​in each column of the cyclically shifted bit mask; as well as For each non-zero value, a transposed dense matrix coordinate of the non-zero value is determined based on the row and column indicating the non-zero value in the cyclically shifted bit mask.

6. The data decompressor system of claim 1, wherein: The mask comprises a bit mask indicating the position of each non-zero value in the sparse matrix, and the decoder is further configured to: Circularly shifting the i-th row of the bit mask left by i bits; Determine an array S including column sums of the cyclically shifted bit masks; Determine an array that includes the prefix sum of array S; For each column j of the cyclically shifted bit mask, generate a vector of length S(j) indicating the rows with non-zero values ​​in column j; as well as For each non-zero value, determine the transposed matrix coordinates based on the rows with non-zero values ​​and the array comprising the prefix sum of array S.

7. A data decompressor system according to claim 1, wherein the compressed data file includes neural network data.

8. A processing system configured to execute a load matrix instruction stored in a memory to: Retrieving compressed data, the compressed data comprising: (a) a stream of non-zero values ​​along a matrix diagonal and (b) a mask indicating the matrix positions of the non-zero values ​​in the stream; as well as A dense matrix and metadata are generated based on the stream of non-zero values ​​and the mask without writing intermediate result matrix data back to the memory, the dense matrix including zero values ​​and the non-zero values ​​in the stream. 9 . The processing system of claim 8 , wherein the generated dense matrix is ​​a transposed matrix of a matrix represented by the stream of non-zero values ​​and the metadata.

10. The processing system of claim 8, the generated dense matrix is ​​stored in a register.

11. The processing system of claim 8, wherein a matrix represented by the stream of non-zero values ​​and the mask comprises data having a sparsity greater than 0.

5.

12. A method performed by at least one programmable processor, the method comprising: receiving compressed matrix data from a memory, the compressed matrix data comprising an array of consecutive non-zero values ​​along a diagonal of the matrix and a mask indicating locations of the non-zero values; generating a dense matrix and / or a dense transposed matrix based on the array of consecutive non-zero values ​​and the mask without writing intermediate result matrix data back to the memory, the dense matrix and / or the dense transposed matrix including zero values ​​and the non-zero values ​​in the array; as well as The generated dense matrix or dense transposed matrix is ​​stored in the memory.

13. The method of claim 12, wherein the dense transposed matrix is ​​generated, the method further comprising performing a matrix multiplication operation using the generated transposed matrix.

14. The method of claim 12, wherein the mask comprises a bit mask, generating the transposed matrix comprises: Circularly shifting the i-th row of the bit mask left by i bits; Determining rows having non-zero values ​​in each column of the cyclically shifted bit mask; as well as For each non-zero value, matrix coordinates and / or transposed matrix coordinates of the non-zero value are generated based on the row and column indicating the non-zero value in the cyclically shifted bit mask.

15. The method according to claim 14, wherein: The programmable processor is a multi-threaded processor, the matrix coordinates and / or transposed matrix coordinates of the non-zero values ​​are determined by a plurality of threads in a warp, and each thread determines coordinates of different non-zero values.

16. A method performed by at least one processor, the at least one processor executing instructions stored in a memory, the method comprising: Receiving compressed matrix data from a memory, the compressed matrix data comprising: (a) a stream of non-zero values ​​along a matrix diagonal and (b) a mask indicating matrix positions of the non-zero values ​​in the stream; and A plurality of threads are executed to determine matrix coordinates and / or transposed matrix coordinates of the non-zero value based on the value of the mask, and the non-zero value and the matrix coordinates and / or the transposed matrix coordinates are stored in registers associated with the plurality of threads without writing intermediate result matrix data back to the registers, wherein each of the threads determines the coordinates of a different non-zero value.

17. The method of claim 16, wherein the mask comprises a bit mask indicating locations of non-zero values ​​in the matrix, each thread being executed to: Circularly shifting the i-th row of the bit mask left by i bits; determining the column and row indicating the position of non-zero values ​​in each column of the cyclically shifted bit mask; and Real-time matrix coordinates and / or transposed matrix coordinates are generated based on the determined rows and columns.

18. The method of claim 16, wherein the transposed matrix coordinates are determined, the method further comprising: A matrix multiplication operation is performed using the determined transposed matrix coordinates.

19. The method of claim 16, wherein the matrix is ​​a sparse matrix, the method further comprising: A dense matrix and / or a dense transposed matrix is ​​generated based on the determined matrix coordinates and / or transposed matrix coordinates.

20. A system comprising: An input circuit configured to receive a compressed data file comprising: (a) a stream of non-zero values ​​along a diagonal of a sparse matrix and (b) a mask comprising a plurality of rows indicating sparse matrix locations of the non-zero values; and A decoder is configured to: circularly shift multiple rows of the mask based on row numbers of corresponding rows, determine rows in each column of the circularly shifted mask having non-zero values, and based on the stream of non-zero values ​​and the rows and columns indicating non-zero values ​​in the circularly shifted mask, fill the transposed dense matrix with zero values ​​and the non-zero values ​​in the stream without writing intermediate result matrix data back to the memory.

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