Packaging structure, stacked packaging structure and manufacturing method thereof

Abstract

A packaging structure includes a first semiconductor die, a second semiconductor die, an insulating encapsulation body and a redistribution layer. The first semiconductor die has a first conductive rod and a first protective layer laterally surrounding the first conductive rod. The second semiconductor die is embedded in the first protective layer of the first semiconductor die and surrounded by the first conductive rod, wherein the second semiconductor die includes a second conductive rod. The insulating encapsulation body encapsulates the first semiconductor die and the second semiconductor die. The redistribution layer is disposed on the insulating encapsulation body and connected to the first conductive rod and the second conductive rod, wherein the first semiconductor die and the second semiconductor die are electrically connected through the first conductive rod, the redistribution layer and the second conductive rod.

Description

Technical Field

[0001] The present disclosure relates to a packaging structure, a stacked packaging structure and a manufacturing method thereof. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically made by sequentially depositing layers of insulating or dielectric material, conductive material, and semiconductor material on a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements thereon. Many semiconductor integrated circuits are typically manufactured on a single semiconductor wafer. The die of the wafer can be processed and packaged at the wafer level, and various technologies have been developed for wafer-level packaging. Summary of the invention

[0003] Some embodiments of the present disclosure provide a packaging structure, which includes: a first semiconductor die, at least one second semiconductor die, an insulating encapsulant, and a redistribution layer. The first semiconductor die has a plurality of first conductive rods and a first protective layer laterally surrounding the plurality of first conductive rods. The at least one second semiconductor die is embedded in the first protective layer of the first semiconductor die and surrounded by the plurality of first conductive rods, wherein the at least one second semiconductor die includes a plurality of second conductive rods. The insulating encapsulant encapsulates the first semiconductor die and the at least one second semiconductor die. The redistribution layer is disposed on the insulating encapsulant and connected to the plurality of first conductive rods and the plurality of second conductive rods, wherein the first semiconductor die and the at least one second semiconductor die are electrically connected through the plurality of first conductive rods, the redistribution layer, and the plurality of second conductive rods.

[0004] Some embodiments of the present disclosure provide a stacked package structure, which includes a first package and a second package. The second package includes a plurality of conductive balls electrically connected to the first package. The first package includes at least one stacked die unit, an insulating encapsulation body, and a redistribution layer. The at least one stacked die unit includes a first semiconductor die and at least one second semiconductor die. The first semiconductor die has: a plurality of first conductive pads; a first passivation layer covering some portions of the plurality of first conductive pads; a plurality of through-holes disposed on the first passivation layer and electrically connected to the plurality of first conductive pads; and a protective layer disposed on the first passivation layer and covering the plurality of through-holes. The at least one second semiconductor die is stacked on the first semiconductor die, wherein the at least one second semiconductor die includes: a plurality of second conductive pads; a second passivation layer covering some portions of the plurality of second conductive pads; and a plurality of conductive rods disposed on the second passivation layer and electrically connected to the plurality of second conductive pads, wherein the protective layer of the first semiconductor die covers the at least one second semiconductor die. The insulating encapsulation has a first surface and a second surface opposite to the first surface, wherein the insulating encapsulation encapsulates the at least one stacked die unit. The redistribution layer is disposed on the first surface of the insulating encapsulation and is electrically connected to the plurality of through-holes and the plurality of conductive rods.

[0005] Some embodiments of the present disclosure describe a method for manufacturing a package structure. The method includes the following steps. A stacked die unit is formed. The step of forming the stacked die unit includes the following steps. A semiconductor wafer having a plurality of first semiconductor die is provided, wherein each of the plurality of first semiconductor die includes a first passivation layer and a plurality of first conductive rods formed on the first passivation layer. A second semiconductor die is fixed to the first passivation layer of each of the plurality of first semiconductor die in an area surrounded by the plurality of first conductive rods, wherein the second semiconductor die includes a plurality of second conductive rods. A first protective layer is formed on the surface of the first passivation layer of each of the plurality of first semiconductor die to cover the plurality of first conductive rods and the second semiconductor die. The semiconductor wafer is divided to separate the plurality of first semiconductor die to form the stacked die unit. The stacked die unit is bonded to a carrier. An insulating encapsulation is formed to encapsulate the stacked die unit. A redistribution layer is formed on the insulating encapsulation and the stacked die unit, wherein the redistribution layer is electrically connected to the plurality of first conductive rods and the plurality of second conductive rods. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the embodiments of the present invention are best understood from the following detailed description, which is read in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the key dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figures 1A to 1F are schematic cross-sectional views of various stages of a method of making a stacked die unit according to some exemplary embodiments of the present disclosure.

[0008] Figure 2A to Figure 2G are schematic cross-sectional views of various stages of a method for manufacturing a package structure according to some exemplary embodiments of the present disclosure.

[0009] Figure 3 is a schematic cross-sectional view of a packaging structure according to some other exemplary embodiments of the present disclosure.

[0010] Figure 4 is a schematic cross-sectional view of a packaging structure according to some other exemplary embodiments of the present disclosure.

[0011] Figure 5 is a schematic cross-sectional view of a packaging structure according to some other exemplary embodiments of the present disclosure.

[0012] Figure 6 is a schematic cross-sectional view of a packaging structure according to some other exemplary embodiments of the present disclosure.

[0013] Figure 7 is a schematic cross-sectional view of a packaging structure according to some other exemplary embodiments of the present disclosure.

[0014] Figure 8 is a schematic cross-sectional view of a packaging structure according to some other exemplary embodiments of the present disclosure.

[0015] Fig. 9 is a schematic cross-sectional view of a packaging structure according to some other exemplary embodiments of the present disclosure.

[0016] Fig.10 is a schematic cross-sectional view of a packaging structure according to some other exemplary embodiments of the present disclosure.

[0017] Fig.11 is a schematic cross-sectional view of a package-on-package (PoP) structure according to some exemplary embodiments of the present disclosure.

[0018] Fig.12 is a schematic cross-sectional view of a package-on-package (PoP) structure according to some other exemplary embodiments of the present disclosure.

[0019] [Explanation of Symbols]

[0020] 30: The third semiconductor die

[0021] 31: The third conductive rod

[0022] 32: Third semiconductor substrate

[0023] 33: The third protection layer

[0024] 34, 104, 204: Inner connection layer

[0025] 36: The third conductive pad

[0026] 38: The third passivation layer

[0027] 100: First semiconductor die

[0028] 102: First semiconductor substrate

[0029] 106: First conductive pad

[0030] 108: First passivation layer

[0031] 110: First conductive rod

[0032] 110-TS, 210-TS: Top

[0033] 112: Protective materials

[0034] 112': Protective layer

[0035] 112-TS, 212-TS, 306-TS, 308-TS: Top surface

[0036] 200: Second semiconductor die

[0037] 202: Second semiconductor substrate

[0038] 206: Second conductive pad

[0039] 208: Second passivation layer

[0040] 210: Second conductive rod

[0041] 212: Second protection layer

[0042] 302: Carrier

[0043] 304: Peeling layer

[0044] 306: Insulator perforation

[0045] 308: Insulation material

[0046] 308', 560: Insulation enclosure

[0047] 310, 550: Conductive pads

[0048] 312: Conductive ball

[0049] 401: Stripe

[0050] 402: Framework

[0051] 510: Substrate

[0052] 520: Semiconductor chips

[0053] 530: Bonding

[0054] 540: Pad

[0055] 570: Conductive ball

[0056] 580: Filling primer

[0057] CD1, CD2: Conductive layer

[0058] DAF: Die Attach Film

[0059] DI1, DI2: Dielectric layer

[0060] DL: Dividing Line

[0061] IPD: Integrated Passive Devices

[0062] PK1A, PK1B, PK1C, PK1D, PK1E, PK1F, PK1G, PK1H, PK1I: Package structure

[0063] PK2: Second package / package structure

[0064] POP1, POP2: stacked package structure

[0065] RDL1, RDL2: redistribution layer

[0066] S1: First surface

[0067] S2: Second surface

[0068] SU1, SU2: Stacked die units

[0069] WF1, WF2: semiconductor wafers DETAILED DESCRIPTION

[0070] The following disclosure provides many different embodiments or examples to implement the different features of the provided subject matter. Specific examples of components and arrangements are described below to make this disclosure concise. Of course, these are only examples and are not intended to be limiting. For example, in the following description, a second feature formed on or formed on a first feature may include an embodiment in which the second feature and the first feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the second feature and the first feature so that the second feature and the first feature cannot be directly contacted. In addition, this disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not essentially specify the relationship between the various embodiments and / or configurations described.

[0071] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "on," "over," "overlying," "above," and the like, may be used herein to describe the relationship of one element or feature to another element or feature, as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0072] Other features and processes may also be included. For example, a test structure may be included to assist in verification testing of a three-dimensional (3D) package or a three-dimensional integrated circuit (3DIC) device. The test structure may include, for example, a test pad formed in a redistribution layer or formed on a substrate, which allows the use of a probe and / or a probe card to test the 3D package or 3DIC. Verification testing may be performed on intermediate structures and final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method that includes verifying a known good die at an intermediate stage to improve yield and reduce cost.

[0073] Figures 1A to 1F are schematic cross-sectional views of various stages of a method of making a stacked die unit according to some exemplary embodiments of the present disclosure. Figure 1A , a semiconductor wafer WF1 having a plurality of first semiconductor dies 100 is provided. Figure 1AAs described in the figure, each of the first semiconductor dies 100 includes a first semiconductor substrate 102, an interconnect layer 104, a plurality of first conductive pads 106, a first passivation layer 108, and a plurality of first conductive rods 110 (or vias). In some embodiments, the first semiconductor substrate 102 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate, and active components (e.g., transistors, etc.) and passive components (e.g., resistors, capacitors, inductors, etc.) are also formed in the first semiconductor substrate 102. The interconnect layer 104 is disposed on the first semiconductor substrate 102 and may include, for example, a plurality of metallization layers and interlayer dielectrics stacked alternately. The first conductive pad 106 may be an aluminum pad, a copper pad, or other suitable metal pads. The first conductive pad 106 is, for example, electrically connected to the interconnect layer 104. The first passivation layer 108 may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed of any suitable dielectric material. The first passivation layer 108 covers the first conductive pad 106 and has a plurality of contact openings, wherein the contact openings of the first passivation layer 108 partially expose the first conductive pad 106. In some embodiments, the first conductive rods 110 (through holes) are formed on the first conductive pad 106 by plating.

[0074] refer to Figure 1B , another semiconductor wafer WF2 having a plurality of second semiconductor dies 200 is provided. In an exemplary embodiment, each of the second semiconductor dies 200 includes a second semiconductor substrate 202, an interconnect layer 204, a plurality of second conductive pads 206, a second passivation layer 208, a plurality of second conductive rods 210, and a second protection layer 212. The size or dimension of each of the second semiconductor dies 200 is less than Figure 1A The size or dimensions of each of the first semiconductor dies 100 illustrated in .

[0075] In an exemplary embodiment, the second semiconductor substrate 202 may be a bulk silicon substrate or a silicon on insulator (SOI) substrate, and active components (e.g., transistors, etc.) and passive components (e.g., resistors, capacitors, inductors, etc.) are also formed in the second semiconductor substrate 202. The interconnect layer 204 is disposed on the second semiconductor substrate 202, and may, for example, include a plurality of metallization layers and interlayer dielectrics stacked alternately. The second conductive pad 206 may be an aluminum pad, a copper pad, or other suitable metal pads. The second conductive pad 206 is, for example, electrically connected to the interconnect layer 204. The second passivation layer 208 may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed of any suitable dielectric material. The second passivation layer 208 covers the second conductive pad 206 and has a plurality of contact openings, wherein the contact openings of the second passivation layer 208 partially expose the second conductive pad 206. In some embodiments, the second conductive rod 210 is formed on the second conductive pad 206 by plating. In some embodiments, the second protection layer 212 is formed on the second passivation layer 208 and covers the second conductive rods 210 to protect the second conductive rods 210. In some embodiments, the semiconductor wafer WF2 may be divided along the dividing lines DL to separate the plurality of second semiconductor dies 200 from each other. Although the description of the second semiconductor die 200 is similar to the description of the first semiconductor die 100, it should be noted that the materials used therein may be the same or different based on design requirements.

[0076] refer to Figure 1C , after the second semiconductor dies 200 are separated, at least one of the second semiconductor dies 200 is stacked on the first semiconductor die 100. For example, the back side of the second semiconductor die 200 is fixed or bonded to the first passivation layer 108 of each of the first semiconductor dies 100 in the area surrounded by the plurality of first conductive rods 110 (perforations). In an exemplary embodiment, the second semiconductor die 200 is fixed to the first passivation layer 108 by fusion bonding. In some embodiments, fusion bonding is performed at a temperature range of 100° C. to 300° C. to generate a chemical bond that bonds the second semiconductor die 200 to the first passivation layer 108 of each of the first semiconductor dies 100. In certain embodiments, a chemical bond is formed between a surface of the first passivation layer 108 and a surface of the second semiconductor substrate 202 (the back side of the second semiconductor die 200). In some exemplary embodiments, the chemical bond formed is a covalent bond. In some alternative embodiments, the second semiconductor die 200 is fixed or bonded onto the first passivation layer 108 of each of the first semiconductor dies 100 by a die attach film (not shown).

[0077] refer to Figure 1DAfter bonding the second semiconductor die 200, a protective material 112 is formed on the surface of the first passivation layer 108 to cover the plurality of first conductive rods 110 (perforations) and the second semiconductor die 200. In some embodiments, the protective material 112 also covers the second protective layer 212 of the second semiconductor die 200. In certain embodiments, the protective material 112 fills the gaps between the adjacent first conductive rods 110 and fills the gaps between the second semiconductor die 200 and the first conductive rods 110. In other words, the protective material 112 is embedded between the first conductive rods 110 and the second semiconductor die 200 and is well protected by the protective material 112. In some embodiments, the protective material 112 includes a polymer, a dielectric material, a molding compound, a resin material, etc. However, the present disclosure is not limited thereto, and other suitable protective materials may be used. In one embodiment, the protective material 112 (used to form the first protective layer) is different from the material of the second protective layer 212. In another embodiment, the protective material 112 and the second protective layer 212 include the same material. The present disclosure is not limited thereto.

[0078] refer to Figure 1E In the next step, the protective material 112 and the second protective layer 212 of the second semiconductor die 200 are ground or polished by a mechanical grinding process and / or a chemical mechanical polishing (CMP) process until the top 110-TS of the first conductive rod 110 (through hole) and the top 210-TS of the second conductive rod 210 are exposed. In some embodiments, the first conductive rod 110 (through hole) and the second conductive rod 210 are partially polished so that the top 110-TS of the first conductive rod 110 (through hole) and the top 210-TS of the second conductive rod 210 are flush with the top surface 212-TS of the second protective layer 212. In some embodiments, the protective material 112 is polished to form a protective layer 112' (first protective layer). After the polishing process, the top surface 112-TS of the protection layer 112' is coplanar with the top 110-TS of the first conductive rod 110 (through hole), the top 210-TS of the second conductive rod 210, and the top surface 212-TS of the second protection layer 212. In addition, since the protection layer 112' and the second protection layer 212 are formed in different steps, it should be noted that no matter whether the same material or different materials are used, there will be an interface between the surface of the protection layer 112' and the surface of the second protection layer 212.

[0079] refer to Figure 1F , after the polishing process, along the dividing line DL ( Figure 1E) is divided into the semiconductor wafer WF1 to separate the plurality of first semiconductor dies 100 from each other, thereby forming a stacked die unit SU1. In an exemplary embodiment, the stacked die unit SU1 includes at least one second semiconductor die 200 stacked on the first semiconductor die 100. In certain embodiments, the second semiconductor die 200 is embedded in the protective layer 112' of the first semiconductor die 100 and is laterally surrounded by the plurality of first conductive rods 110 (perforations). Although only one second semiconductor die 200 is shown stacked on the first semiconductor die 100, the present disclosure is not limited thereto. In some other embodiments, the number of semiconductor dies stacked on the first semiconductor die 100 can be adjusted based on design requirements. At this point, the stacked die unit SU1 according to some exemplary embodiments of the present disclosure is realized.

[0080] Figure 2A to Figure 2G Schematic cross-sectional views of various stages of a method for manufacturing a package structure according to some exemplary embodiments of the present disclosure. Figure 2A , providing a carrier 302. In some embodiments, the carrier 302 may be a glass carrier or any suitable carrier that carries a semiconductor wafer or a reconstructed wafer for performing a packaging structure manufacturing method. In some embodiments, the carrier 302 is coated with a peeling layer 304. The material of the peeling layer 304 may be any material suitable for bonding the carrier 302 and peeling the carrier 302 from an upper layer or any wafer disposed on the carrier 302.

[0081] In some embodiments, the release layer 304 may include a dielectric material layer made of a dielectric material, including any suitable polymer-based dielectric material (e.g., benzocyclobutane ("BCB"), polybenzoxazole ("PBO")). In an alternative embodiment, the release layer 304 may include a dielectric material layer made of an epoxy-based thermal release material that loses adhesion when heated, such as a light-to-heat-conversion (LTHC) release coating film. In another embodiment, the release layer 304 may include a dielectric material layer made of an ultraviolet (UV) glue that loses adhesion when exposed to UV light. In certain embodiments, the release layer 304 may be dispensed in liquid form and cured, or may be a laminated film laminated to the carrier 302, or may be a material such as the like. The top surface of the release layer 304, opposite to the bottom surface contacting the carrier 302, may be flush and may have a high degree of coplanarity. In some embodiments, the release layer 304 is, for example, a LTHC layer having good chemical resistance, and this layer enables room temperature release from the carrier 302 by applying laser irradiation, but the present disclosure is not limited thereto.

[0082] In an alternative embodiment, a buffer layer (not shown) may be coated on the peeling layer 304, wherein the peeling layer 304 is sandwiched between the buffer layer and the carrier 302, and the top surface of the buffer layer may also have a high degree of coplanarity. In some embodiments, the buffer layer may be a dielectric material layer. In some embodiments, the buffer layer may be a polymer layer made of polyimide, PBO, BCB, or any other suitable polymer-based dielectric material. In some embodiments, the buffer layer may be Ajinomoto Buildup Film (ABF), Solder Resist (SR), etc. In other words, the buffer layer is optional and may be omitted based on demand, so the present disclosure is not limited thereto.

[0083] like Figure 2A As further described in the figure, a redistribution layer RDL1 is formed on the carrier 302. For example, the redistribution layer RDL1 is formed on the peeling layer 304, and the formation of the redistribution layer RDL1 includes sequentially and alternately forming one or more dielectric layers DI1 and one or more conductive layers CD1. In some embodiments, the redistribution layer RDL1 includes two dielectric layers DI1 and one conductive layer CD1, such as Figure 2A As shown in FIG. , the conductive layer CD1 is sandwiched between the dielectric layers DI1. However, the present disclosure is not limited thereto. The number of the dielectric layers DI1 and the conductive layers CD1 included in the redistribution layer RDL1 is not limited thereto, and can be determined and selected based on requirements. For example, the number of the dielectric layers DI1 and the conductive layers CD1 can be one or more.

[0084] In some embodiments, the material of the dielectric layer DI1 may be polyimide, polybenzoxazole (PBO), benzocyclobutane (BCB), nitride (e.g., silicon nitride), oxide (e.g., silicon oxide), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or a combination thereof, and the material of the dielectric layer DI1 may be patterned using photolithography and / or etching processes. In some embodiments, the material of the dielectric layer DI1 may be formed using a suitable fabrication technique, such as spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), etc. The present disclosure is not limited thereto.

[0085] In some embodiments, the material of the conductive layer CD1 may be made of a conductive material (e.g., aluminum, titanium, copper, nickel, tungsten, and / or alloys thereof) formed by electroplating or deposition, and the material of the conductive layer may be patterned using photolithography and etching processes. In some embodiments, the conductive layer CD1 may be a patterned copper layer or other suitable patterned metal layer. Throughout this specification, the term "copper" is intended to include substantially pure elemental copper, copper containing unavoidable impurities, and copper alloys containing trace elements (e.g., tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum, or zirconium, etc.).

[0086] refer to Figure 2B After forming the redistribution layer RDL1, a substrate 302 is disposed on the redistribution layer RDL1 and on the carrier 302. Figure 1F at least one stacked die unit SU1 obtained therein, and a plurality of insulator through-holes 306. In some embodiments, the insulator through-holes 306 are integrated fan-out ("InFO") through-holes. In one embodiment, the formation of the insulator through-holes 306 includes: forming a mask pattern (not shown) having an opening, then forming a metal material (not shown) by electroplating or deposition to fill the opening, and removing the mask pattern to form the insulator through-holes 306 on the redistribution layer RDL1. In certain embodiments, the insulator through-holes 306 are filled into the through-hole openings of the conductive layer CD1 exposing the redistribution layer RDL1, so that the insulator through-holes 306 can be electrically connected to the redistribution layer RDL1. In some embodiments, the material of the mask pattern may include a positive photoresist or a negative photoresist. In one embodiment, the material of the insulator through-holes 306 may include a metal material, such as copper or a copper alloy. However, the present disclosure is not limited thereto.

[0087] In an alternative embodiment, the insulator through-hole 306 may be formed by the following steps: forming a seed layer (not shown) on the redistribution layer RDL1; forming a mask pattern having openings that expose portions of the seed layer; forming a metal material on the exposed portions of the seed layer by plating to form the insulator through-hole 306; removing the mask pattern; and then removing the portion of the seed layer exposed by the insulator through-hole 306. For example, the seed layer may be a titanium / copper composite layer. For simplicity, Figure 2B Only two insulator through-holes 306 are shown in FIG. However, it should be noted that the number of insulator through-holes 306 is not limited thereto and can be selected based on requirements.

[0088] In addition, in some embodiments, at least one stacked die unit SU1 is picked up and placed on the redistribution layer RDL1. In certain embodiments, the stacked die unit SU1 is placed on the redistribution layer RDL1 by bonding the first semiconductor substrate 102 of the first semiconductor die 100 to the dielectric layer DI1 of the redistribution layer RDL1. For example, the first semiconductor substrate 102 is bonded to the redistribution layer RDL1 by a die bonding film (not shown). Good adhesion between the stacked die unit SU1 and the redistribution layer RDL1 is ensured by using a die bonding film. In an exemplary embodiment, only one stacked die unit SU1 is shown. However, it should be noted that the number of stacked die units SU1 placed on the redistribution layer RDL1 is not limited thereto, and this can be adjusted based on design requirements.

[0089] In some embodiments, when more than one stacked die units SU1 are placed on the redistribution layer RDL1, the stacked die units SU1 may be arranged in an array, and when the stacked die units SU1 are arranged in an array, the insulator through-vias 306 may be classified into groups. The number of stacked die units SU1 may correspond to the number of groups of insulator through-vias 306. In an exemplary embodiment, the stacked die units SU1 may be picked up and placed on the redistribution layer RDL1 after the insulator through-vias 306 are formed. However, the present disclosure is not limited thereto. In some alternative embodiments, the stacked die units SU1 may be picked up and placed on the redistribution layer RDL1 before the insulator through-vias 306 are formed.

[0090] In addition, in an exemplary embodiment, the stacked die unit SU1 includes at least a second semiconductor die 200 stacked on the first semiconductor die 100. For example, the first semiconductor die 100 and the second semiconductor die 200 may be selected from: an application-specific integrated circuit (ASIC) chip, an analog chip (e.g., a wireless radio frequency chip), a digital chip (e.g., a baseband chip), an integrated passive device (IPD), a voltage regulator chip, a sensor chip, a memory chip, etc. The present disclosure is not limited thereto.

[0091] refer to Figure 2CIn the next step, an insulating material 308 is formed on the redistribution layer RDL1 and above the stacked die unit SU1. In some embodiments, the insulating material 308 is formed by, for example, a molding process, which fills the gap between the stacked die unit SU1 and the insulating through-hole 306 to encapsulate the stacked die unit SU1. The insulating material 308 also fills the gap between adjacent insulator through-holes 306 to encapsulate the insulator through-holes 306. At this stage, the first conductive rod 110 (through-hole), the protective layer 112', the second conductive rod 210 and the second protective layer 212 are encapsulated by the insulating material 308 and are well protected by the insulating material 308. In other words, the first conductive rod 110 (through-hole), the protective layer 112' of the first semiconductor die 100, and the second conductive rod 210, the second protective layer 212 of the second semiconductor die 200 are not exposed and are not well protected by the insulating material 308.

[0092] In some embodiments, the insulating material 308 includes a polymer (e.g., epoxy resin, phenolic resin, silicone resin, or other suitable resin), a dielectric material with low permittivity (Dk) and low loss tangent (Df) properties, or other suitable materials. In alternative embodiments, the insulating material 308 may include an acceptable insulating encapsulation material. In some embodiments, the insulating material 308 may also include an inorganic filler or an inorganic compound (e.g., silicon dioxide, clay, etc.), which may be added to the insulating material 308 to optimize the coefficient of thermal expansion (CTE) of the insulating material 308. The present disclosure is not limited thereto.

[0093] refer to Figure 2D In some embodiments, the insulating material 308 is partially removed to expose the insulator through-hole 306, the first conductive rod 110 (through-hole), and the second conductive rod 210. In some embodiments, the insulating material 308 is ground or polished by a planarization step. For example, the planarization step is performed by a mechanical grinding process and / or a chemical mechanical polishing (CMP) process until the top 110-TS of the first conductive rod 110 (through-hole) and the top 210-TS of the second conductive rod 210 are exposed. In some embodiments, the insulator through-hole 306 may be partially polished so that the top surface 306-TS of the insulator through-hole 306 is flush with the top 110-TS of the first conductive rod 110 (through-hole) and the top 210-TS of the second conductive rod 210. In other words, the insulator through-hole 306, the first conductive rod 110 (through-hole), and the second conductive rod 210 may also be slightly ground / polished.

[0094] In the illustrated embodiment, the insulating material 308 is polished to form an insulating encapsulation 308'. In some embodiments, the top surface 308-TS of the insulating encapsulation 308', the top surface 306-TS of the insulating through-hole 306, the top 110-TS of the first conductive rod 110 (through-hole), the top surface 112-TS of the protective layer 112', the top 210-TS of the second conductive rod 210, and the top surface 212-TS of the second protective layer 212 are coplanar and flush with each other. In some embodiments, after performing the mechanical grinding or chemical mechanical polishing (CMP) step, a cleaning step may be performed as appropriate. For example, a cleaning step is performed to clean and remove the residues generated by the planarization step. However, the present disclosure is not limited thereto, and the planarization step may be performed by any other suitable method.

[0095] refer to Figure 2E , after the grinding / polishing step is performed, a redistribution layer RDL2 is formed on the insulating encapsulation 308', the insulator through-hole 306, and the stacked die unit SU1. For example, the insulating encapsulation 308' has a first surface S1 and a second surface S2 opposite to the first surface S1, wherein the redistribution layer RDL2 is formed on the first surface S1 of the insulating encapsulation 308', and the redistribution layer RDL1 is formed on the second surface S2. In some embodiments, the redistribution layer RDL2 is electrically connected to the insulator through-hole 306 and electrically connected to the first semiconductor die 100 and the second semiconductor die 200 through the first conductive rod 110 and the second conductive rod 210, respectively. In certain embodiments, the redistribution layer RDL2 electrically connects the first conductive rod 110 of the first semiconductor die 100 to the second conductive rod 210 of the second semiconductor die 200. In other words, the first semiconductor die 100 and the second semiconductor die 200 are electrically connected through the first conductive rod 110, the redistribution layer RDL2, and the second conductive rod 210. In some embodiments, the stacked die unit SU1 is electrically connected to the through-insulator via 306 through the redistribution layer RDL2 .

[0096] In addition, in some embodiments, the formation of the redistribution layer RDL2 includes sequentially and alternately forming one or more dielectric layers DI2 and one or more conductive layers CD2. In some embodiments, the conductive layer CD2 is sandwiched between the dielectric layers DI2. Although only three conductive layers CD2 and four dielectric layers DI2 are shown herein, the scope of the present disclosure is not limited by the embodiments. In other embodiments, the number of conductive layers CD2 and dielectric layers DI2 can be adjusted based on product requirements. In some embodiments, the conductive layer CD2 is electrically connected to the first conductive rod 110 (perforation) of the first semiconductor die 100, and is electrically connected to the second conductive rod 210 of the second semiconductor die 200. In addition, the conductive layer CD2 is electrically connected to the insulator perforation 306. In some embodiments, the materials of the dielectric layer DI2 and the conductive layer CD2 of the redistribution layer RDL2 are similar to the materials of the dielectric layer DI1 and the conductive layer CD1 described with respect to the redistribution layer RDL1. Therefore, the dielectric layer DI2 and the conductive layer CD2 will not be described in detail herein.

[0097] After forming the redistribution layer RDL2, a plurality of conductive pads 310 may be disposed on the exposed top surface of the topmost layer of the conductive layer CD2 for electrical connection with the conductive balls. In some embodiments, the conductive pads 310 are, for example, under-ball metallurgy (UBM) patterns for ball mounting. Figure 2E As shown in , the conductive pad 310 is formed on the redistribution layer RDL2 and is electrically connected to the redistribution layer RDL2. In some embodiments, the material of the conductive pad 310 may include copper, nickel, titanium, tungsten or alloys thereof, and may be formed, for example, by an electroplating process. The number of the conductive pads 310 is not limited to the present disclosure, and may be selected based on the design layout. In some alternative embodiments, the conductive pad 310 may be omitted. In other words, the conductive ball 312 formed in a subsequent step may be directly disposed on the redistribution layer RDL2.

[0098] After forming the conductive pad 310, a plurality of conductive balls 312 are disposed on the conductive pad 310 and on the redistribution layer RDL2. In some embodiments, the conductive balls 312 may be disposed on the conductive pad 310 by a ball implantation process or a reflow process. In some embodiments, the conductive balls 312 are, for example, solder balls or ball grid array (BGA) balls. In some embodiments, the conductive balls 312 are connected to the redistribution layer RDL2 through the conductive pad 310. In certain embodiments, some of the conductive balls 312 may be electrically connected to the stacked die unit SU1 through the redistribution layer RDL2. In addition, some of the conductive balls 312 may be electrically connected to the insulator through-via 306 through the redistribution layer RDL2. The number of the conductive balls 312 is not limited to the present disclosure, and may be determined and selected based on the number of the conductive pads 310.

[0099] refer to Figure 2F After forming the redistribution layer RDL2 and placing the conductive balls 312, Figure 2E The structure shown in FIG. 4 is inverted and attached to a strip 401 (eg, a split strip) supported by a frame 402. Figure 2F As described in , the carrier 302 and the redistribution layer RDL1 are peeled off and separated. In some embodiments, the peeling process includes projecting light (e.g., laser or UV light) onto the peeling layer 304 (e.g., LTHC release layer) so that the carrier 302 can be easily removed together with the peeling layer 304. During the peeling step, the package structure is first stabilized using a tape 401, and then the carrier 302 and the peeling layer 304 are peeled off. After the peeling process, the back side surface of the redistribution layer RDL1 is revealed or exposed. In some embodiments, the dielectric layer DI1 of the redistribution layer RDL1 is revealed or exposed.

[0100] refer to Figure 2G , after the stripping process, along the dividing line DL ( Figure 2F 308' and the redistribution layer RDL1 and the redistribution layer RDL2) are cut into a plurality of package structures PK1A. In an exemplary embodiment, the cutting process is a wafer cutting process including mechanical sawing or laser cutting. In subsequent processes, the separated package structures PK1A can be set on a circuit substrate or placed on other components based on requirements.

[0101] Figure 3 is a schematic cross-sectional view of a packaging structure according to some other exemplary embodiments of the present disclosure. Figure 3 The package structure shown in PK1B is Figure 2G The package structure PK1A shown in FIG. 1 is similar to the package structure PK1A shown in FIG. 1 , and therefore the same reference numerals are used to refer to the same or similar components, and they will not be described in detail herein. The difference between the embodiments is that in the package structure PK1B, the second semiconductor die 200 is fixed to the first semiconductor die 100 in the stacked die unit SU1. In the previous embodiment, the second semiconductor die 200 is fixed to the first passivation layer 108 by fusion bonding. However, the present disclosure is not limited thereto. Reference Figure 3 In some embodiments, the second semiconductor die 200 may be fixed to the first passivation layer 108 of the first semiconductor die 100 using a die attach film DAF. In other words, the die attach film DAF is located between the second semiconductor substrate 202 of the second semiconductor die 200 and the first passivation layer 108 of the first semiconductor die 100.

[0102] Figure 4is a schematic cross-sectional view of a packaging structure according to some other exemplary embodiments of the present disclosure. Figure 4 The package structure shown in PK1C is Figure 2G The package structure PK1A shown in FIG. 1 is similar to the package structure PK1A shown in FIG. 1 , and therefore the same reference numerals are used to refer to the same or similar components, and they will not be described in detail herein. The difference between the embodiments is that the second semiconductor die 200 of the package structure PK1C omits the second protective layer 212. Figure 4 , the second semiconductor die 200 has the second conductive rod 210 exposed or revealed. Therefore, after the second semiconductor die 200 is fixed to the first semiconductor die 100 and the protective layer 112' is formed, the protective layer 112' will cover and physically contact the second conductive rod 210 of the second semiconductor die 200. In other words, the protective layer 112' is sufficient to protect both the first conductive rod 110 (through hole) and the second conductive rod 210. In addition, since the second protective layer 212 is omitted, there will be no interface between the surface of the protective layer 112' and the surface of the second protective layer 212 in the package structure PK1C.

[0103] Figure 5 is a schematic cross-sectional view of a packaging structure according to some other exemplary embodiments of the present disclosure. Figure 5 The package structure shown in PK1D is Figure 2G The package structure PK1A shown in FIG. 1 is similar to that shown in FIG. 1 , and therefore the same reference numerals are used to refer to the same or similar components, and they will not be described in detail herein. The difference between the embodiments described is the number of second semiconductor dies 200 fixed to the first semiconductor die 100. Figure 5 , two second semiconductor dies 200 are fixed on the first passivation layer 108 of the first semiconductor die 100. In some embodiments, the two second semiconductor dies 200 are embedded in the protection layer 112' of the first semiconductor die 100. In addition, each of the second semiconductor dies 200 is surrounded by the plurality of first conductive rods 110 (perforations). In some embodiments, since the first conductive rods 110 are located between the second semiconductor dies 200, one of the second semiconductor dies 200 is separated from the other of the second semiconductor dies 200. In addition, the two second semiconductor dies 200 are located on the same plane and on the same surface of the first semiconductor die 100, and are substantially coplanar with each other.

[0104] Figure 6 is a schematic cross-sectional view of a packaging structure according to some other exemplary embodiments of the present disclosure. Figure 6 The package structure shown in PK1E is Figure 2GThe package structure PK1E is similar to the package structure PK1A shown in FIG. 1 , and therefore the same reference numerals are used to refer to the same or similar components, and they will not be described in detail herein. The difference between the embodiments is that the package structure PK1E further includes a third semiconductor die 30. Figure 6 In some embodiments, the third semiconductor die 30 is disposed on the first passivation layer 108 of the first semiconductor die 100 adjacent to the second semiconductor die 200. In some embodiments, the size of the third semiconductor die 30 is smaller than the size of the second semiconductor die 200 and the first semiconductor die 100. However, the present disclosure is not limited thereto, and the size of the third semiconductor die 30 may be selected based on requirements. In certain embodiments, the third semiconductor die 30, the second semiconductor die 200, and the first semiconductor die 100 are different types of semiconductor dies. However, the present disclosure is not limited thereto. In alternative embodiments, the third semiconductor die 30 may be the same type of semiconductor die as either the first semiconductor die 100 or the second semiconductor die 200, with only a different size or dimension.

[0105] In an exemplary embodiment, the third semiconductor die 30 includes a third semiconductor substrate 32, an interconnect layer 34, a plurality of third conductive pads 36, a third passivation layer 38, a plurality of third conductive rods 31, and a third protective layer 33. The third semiconductor substrate 32 may be a bulk silicon substrate or a silicon on insulator (SOI) substrate, and active components (e.g., transistors, etc.) are also formed in the third semiconductor substrate 32 and passive components (e.g., resistors, capacitors, inductors, etc.) are optionally included. The interconnect layer 34 is disposed on the third semiconductor substrate 32 and may, for example, include a plurality of metallization layers and interlayer dielectrics stacked alternately. The third conductive pad 36 may be an aluminum pad, a copper pad, or other suitable metal pads. The third conductive pad 36 is, for example, electrically connected to the interconnect layer 34. The third passivation layer 38 may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed of any suitable dielectric material. The third passivation layer 38 covers the third conductive pad 36 and has a plurality of contact openings, wherein the contact openings of the third passivation layer 38 partially expose the third conductive pad 36. In some embodiments, the third conductive rod 31 is formed on the third conductive pad 36 by plating. In some embodiments, the third protective layer 33 is formed on the third passivation layer 38 and covers the third conductive rod 31 to protect the third conductive rod 31. In addition, as shown in FIG. Figure 6 As illustrated in FIG. 1 , the third semiconductor die 30 is embedded in the protection layer 112′ of the first semiconductor die 100 and is surrounded by the plurality of first conductive rods 110 (vias). In addition, the redistribution layer RDL2 is electrically connected to the third conductive rods 31 of the third semiconductor die 30. In some embodiments, the third semiconductor die 30 is electrically connected to the first semiconductor die 100 and / or the second semiconductor die through the redistribution layer RDL2.

[0106] Figure 7 is a schematic cross-sectional view of a packaging structure according to some other exemplary embodiments of the present disclosure. Figure 7 The package structure shown in PK1F is Figure 6 The package structure PK1E shown in FIG. 1 is similar to that shown in FIG. 1 , and therefore the same reference numerals are used to refer to the same or similar components, and they will not be described in detail herein. The difference between the embodiments described is the position of the third semiconductor die 30. Figure 7 In the stacked die unit SU1, the third semiconductor die 30 is disposed on the second semiconductor die 200. The size of the third semiconductor die 30 is smaller than the size of the second semiconductor die 200 and the first semiconductor die 100. In addition, in some embodiments, the third semiconductor die 30 is disposed on the second passivation layer 208 of the second semiconductor die 200 and is surrounded by the second conductive rod 210. On the other hand, the second semiconductor die 200 is also disposed on the first passivation layer 108 of the first semiconductor die 100 and is surrounded by the first conductive rod 110 (through hole).

[0107] Figure 8 is a schematic cross-sectional view of a packaging structure according to some other exemplary embodiments of the present disclosure. Figure 8 The package structure shown in PK1G is Figure 7 The package structure PK1F shown in FIG. 1 is similar to the package structure PK1F shown in FIG. 1 , and therefore the same reference numerals are used to refer to the same or similar components, and they will not be described in detail herein. The difference between the embodiments is that in the package structure PK1G two stacked die units (SU1 / SU2) are included in the package structure PK1G. Figure 8 , in an exemplary embodiment, includes a stacked die unit SU1 and a stacked die unit SU2. The number of stacked semiconductor dies in the stacked die unit SU1 is different from the number of stacked semiconductor dies in the stacked die unit SU2. For example, the stacked die unit SU1 includes a first semiconductor die 100, a second semiconductor die 200, and a third semiconductor die 30 stacked together, and the stacked die unit SU2 includes a first semiconductor die 100 and a second semiconductor die 200. Although only two stacked die units (SU1 / SU2) are described herein, it should be noted that the number of stacked die units in each of the packaging structures is not limited thereto. For example, in an alternative embodiment, the packaging structure may include two or more stacked die units. In addition, the number and arrangement of semiconductor dies in each of the stacked die units may be the same or different based on design requirements.

[0108] Fig. 9 is a schematic cross-sectional view of a packaging structure according to some other exemplary embodiments of the present disclosure. Fig. 9The package structure shown in PK1H is Figure 2G The package structure PK1A shown in FIG. 1 is similar to the package structure PK1A shown in FIG. 1 , and therefore the same reference numerals are used to refer to the same or similar components, and they will not be described in detail herein. The difference between the embodiments is that the package structure PK1H further includes an integrated passive device IPD. Fig. 9 In some embodiments, the integrated passive device IPD may be disposed on the first passivation layer 108 of the first semiconductor die 100 and embedded in the protection layer 112'. The integrated passive device IPD may be disposed on the same surface and on the same plane as the second semiconductor die 200 of the first semiconductor die 100, and may be electrically connected to the redistribution layer RDL2. In addition, the first conductive rod 110 surrounds both the second semiconductor die 200 and the integrated passive device IPD.

[0109] Fig.10 is a schematic cross-sectional view of a packaging structure according to some other exemplary embodiments of the present disclosure. Fig.10 The package structure shown in PK1I is Figure 2G The package structure PK1A shown in FIG. 1 is similar to the package structure PK1A shown in FIG. 1 , and therefore the same reference numerals are used to refer to the same or similar components, and they will not be described in detail herein. The difference between the embodiments is that the package structure PK1I omits the redistribution layer RDL1. Fig.10 In some embodiments, the dielectric layer DL is disposed on the second surface S2 of the insulating encapsulation 308' instead of the redistribution layer RDL1. In some embodiments, the dielectric layer DL has an opening that exposes the insulator through-hole 306, and a conductive terminal 120 is further disposed in the opening of the dielectric layer DL, and the conductive terminal 120 is connected to the insulator through-hole 306. In other words, a package structure PK1I having double-sided terminals without the redistribution layer RDL1 is realized. In an alternative embodiment, the conductive terminal 120 may be omitted, and the dielectric layer DL may cover the back side (second surface S2) of the insulating encapsulation 308' and the back side of the stacked die unit SU1.

[0110] Fig.11 is a schematic cross-sectional view of a package-on-package (PoP) structure according to some exemplary embodiments of the present disclosure. Fig.11 , when making the first package (for example, Figure 2G After the package structure PK1A described in the above, the second package PK2 can be stacked on the package structure PK1A (first package) to form a package-on-package (PoP) structure. Fig.11As shown in , the second package PK2 is electrically connected to the conductive layer CD1 of the package structure PK1A (first package). In some embodiments, the second package PK2 has a substrate 510, a plurality of semiconductor chips 520, and the plurality of semiconductor chips 520 are mounted on a surface (e.g., the top surface) of the substrate 510 and stacked on each other. In some embodiments, a bonding wire 530 is used to make an electrical connection between the semiconductor chip 520 and the pad 540 (e.g., a bonding pad). In some embodiments, an insulating encapsulation 560 is formed to encapsulate the semiconductor chip 520 and the bonding wire 530 to protect these components. In some embodiments, an insulator perforation (not shown) can be used to electrically connect the pad 540 to a conductive pad 550 (e.g., a bonding pad) located on another surface (e.g., the bottom surface) of the substrate 510. In some embodiments, the conductive pad 550 is electrically connected to the semiconductor chip 520 through these insulator perforations (not shown). In some embodiments, the conductive pad 550 of the package structure PK2 is electrically connected to the conductive ball 570. In addition, the conductive balls 570 are electrically connected to the conductive layer CD1 of the redistribution layer RDL1 (back side redistribution layer) in the package structure PK1A (first package). In some embodiments, a filling primer 580 is also provided to fill the space between the conductive balls 570 to protect the conductive balls 570. After the second package PK2 is stacked on the package structure PK1A (first package) and an electrical connection is provided therebetween, a stacked package structure POP1 can be manufactured.

[0111] Fig.12 is a schematic cross-sectional view of a package-on-package (PoP) structure according to some other exemplary embodiments of the present disclosure. Fig.12 The stacked package structure POP2 shown in Fig.11 The stacked package structure POP1 shown in FIG. 1 is similar to the stacked package structure POP2, so the same reference numerals are used to refer to the same or similar components, and they will not be described in detail herein. The difference between the embodiments is that the stacked package structure POP2 omits the redistribution layer RDL1. Fig.12 In some embodiments, since the redistribution layer RDL1 is omitted, the conductive balls 570 of the second package PK2 can be directly connected to the insulator through-vias 306 of the package structure PK1A (first package) to form a stacked package structure POP2.

[0112] In the above embodiments, the package structure or the stacked package structure includes at least one stacked die unit. The stacked die unit includes at least one second semiconductor die embedded in the protective layer of the first semiconductor die, wherein the first conductive rod surrounds the second semiconductor die. In addition, the redistribution layer is electrically connected to the first conductive rod of the first semiconductor die and the second conductive rod of the second semiconductor die, respectively. Since the second semiconductor die is stacked on the first semiconductor die and embedded in the first semiconductor die, the communication path (through the redistribution layer) between the semiconductor dies can be shortened. In general, the performance and efficiency of the package structure can be improved.

[0113] According to some embodiments of the present disclosure, a packaging structure is provided, the packaging structure comprising: a first semiconductor die, at least one second semiconductor die, an insulating encapsulant and a redistribution layer. The first semiconductor die has a plurality of first conductive rods and a first protective layer laterally surrounding the plurality of first conductive rods. The at least one second semiconductor die is embedded in the first protective layer of the first semiconductor die and surrounded by the plurality of first conductive rods, wherein the at least one second semiconductor die comprises a plurality of second conductive rods. The insulating encapsulant encapsulates the first semiconductor die and the at least one second semiconductor die. The redistribution layer is disposed on the insulating encapsulant and connected to the plurality of first conductive rods and the plurality of second conductive rods, wherein the first semiconductor die and the at least one second semiconductor die are electrically connected through the plurality of first conductive rods, the redistribution layer and the plurality of second conductive rods.

[0114] In some embodiments, the tops of the plurality of first conductive rods are flush with the tops of the plurality of second conductive rods. In some embodiments, the packaging structure further comprises a plurality of insulator through-holes penetrating the insulating enclosure, and a back side rewiring layer is disposed on the insulating enclosure and connected to the plurality of insulator through-holes.

[0115] According to some other embodiments of the present disclosure, a stacked package structure is provided, the stacked package structure comprising a first package and a second package. The second package comprises a plurality of conductive balls electrically connected to the first package. The first package comprises at least one stacked die unit, an insulating encapsulation body and a redistribution layer. The at least one stacked die unit comprises a first semiconductor die and at least one second semiconductor die. The first semiconductor die has: a plurality of first conductive pads; a first passivation layer covering some portions of the plurality of first conductive pads; a plurality of through-holes arranged on the first passivation layer and electrically connected to the plurality of first conductive pads; and a protective layer arranged on the first passivation layer and covering the plurality of through-holes. The at least one second semiconductor die is stacked on the first semiconductor die, wherein the at least one second semiconductor die comprises: a plurality of second conductive pads; a second passivation layer covering some portions of the plurality of second conductive pads; and a plurality of conductive rods arranged on the second passivation layer and electrically connected to the plurality of second conductive pads, wherein the protective layer of the first semiconductor die covers the at least one second semiconductor die. The insulating encapsulation has a first surface and a second surface opposite to the first surface, wherein the insulating encapsulation encapsulates the at least one stacked die unit. The redistribution layer is disposed on the first surface of the insulating encapsulation and is electrically connected to the plurality of through-holes and the plurality of conductive rods.

[0116] In some embodiments, two of the second semiconductor dies are disposed on the first passivation layer, and the plurality of perforations surround the two second semiconductor dies. In some embodiments, the stacked package structure further comprises a passive device, which is disposed on the first passivation layer of the first semiconductor die and embedded in the protective layer. In some embodiments, the back side of the at least one second semiconductor die is bonded to the first passivation layer of the first semiconductor die by fusion bonding. In some embodiments, the first package comprises at least two stacked die units, and the number of stacked semiconductor dies in one of the stacked die units is different from the number of stacked semiconductor dies in the other of the stacked die units.

[0117] In another embodiment of the present disclosure, a method for making a package structure is described. The method includes the following steps. A stacked die unit is formed. The step of forming the stacked die unit includes the following steps. A semiconductor wafer having a plurality of first semiconductor die is provided, wherein each of the plurality of first semiconductor die includes a first passivation layer and a plurality of first conductive rods formed on the first passivation layer. A second semiconductor die is fixed to the first passivation layer of each of the plurality of first semiconductor die in an area surrounded by the plurality of first conductive rods, wherein the second semiconductor die includes a plurality of second conductive rods. A first protective layer is formed on the surface of the first passivation layer of each of the plurality of first semiconductor die to cover the plurality of first conductive rods and the second semiconductor die. The semiconductor wafer is divided to separate the plurality of first semiconductor die to form the stacked die unit. The stacked die unit is bonded to a carrier. An insulating encapsulation is formed to encapsulate the stacked die unit. A redistribution layer is formed on the insulating encapsulation and the stacked die unit, wherein the redistribution layer is electrically connected to the plurality of first conductive rods and the plurality of second conductive rods.

[0118] In some embodiments, fixing the second semiconductor die to the first passivation layer of each of the plurality of first semiconductor dies includes: melt-bonding the second semiconductor die to the first passivation layer at a temperature range of 100°C to 300°C to generate a chemical bond between the back side of the second semiconductor die and the first passivation layer. In some embodiments, the second semiconductor die is fixed to the first passivation layer of each of the plurality of first semiconductor dies by a die bonding film. In some embodiments, the method for making a package structure also includes performing a grinding process on the stacked die unit so that the top surface of the first protective layer, the top surface of the plurality of first conductive rods, and the top surface of the plurality of second conductive rods are flush with each other. In some embodiments, the method for making a package structure also includes forming a second protective layer on the second passivation layer of the second semiconductor die to cover the plurality of second conductive rods, wherein the first protective layer covers the second protective layer.

[0119] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they may easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A packaging structure, comprising: A first semiconductor die having a plurality of first conductive rods and a first protection layer laterally surrounding the plurality of first conductive rods; at least one second semiconductor die embedded in the first protection layer of the first semiconductor die and surrounded by the plurality of first conductive rods, wherein the at least one second semiconductor die comprises a plurality of second conductive rods and a second protection layer laterally surrounding the plurality of second conductive rods, and the second protection layer of the at least one second semiconductor die is located between the plurality of second conductive rods and the first protection layer of the first semiconductor die; an insulating encapsulation body encapsulating the first semiconductor die and the at least one second semiconductor die; as well as A redistribution layer is disposed on the insulating package and connected to the plurality of first conductive rods and the plurality of second conductive rods, wherein the first semiconductor die is electrically connected to the at least one second semiconductor die through the plurality of first conductive rods, the redistribution layer and the plurality of second conductive rods. 2 . The package structure of claim 1 , wherein the at least one second semiconductor die comprises two or more second semiconductor dies embedded in the first protection layer of the first semiconductor die, and the plurality of first conductive rods surround the two or more second semiconductor dies.

3. The packaging structure according to claim 1 further includes a die bonding film, wherein the die bonding film is located between the back side of the at least one second semiconductor die and the passivation layer of the first semiconductor die, and the at least one second semiconductor die is bonded to the passivation layer of the first semiconductor die through the die bonding film. 4 . The package structure of claim 1 , wherein a back side of the at least one second semiconductor die is attached to the passivation layer of the first semiconductor die by fusion bonding. 5 . The package structure according to claim 1 , wherein tops of the plurality of first conductive bars are flush with tops of the plurality of second conductive bars. 6 . The packaging structure according to claim 1 , further comprising a plurality of insulator through-holes penetrating through the insulating encapsulation body, and a back side redistribution layer is disposed on the insulating encapsulation body and connected to the plurality of insulator through-holes. 7 . The package structure according to claim 1 , wherein the first semiconductor die further comprises a first semiconductor substrate and a first interconnect layer disposed on the first semiconductor substrate, and the plurality of first conductive rods are electrically connected to the first interconnect layer.

8. The packaging structure according to claim 7, wherein the at least one second semiconductor die further includes a second semiconductor substrate and a second internal wiring layer arranged on the second semiconductor substrate, the plurality of second conductive rods are electrically connected to the second internal wiring layer, and the first protective layer laterally surrounds the second semiconductor substrate and the second internal wiring layer.

9. A stacked package structure, comprising: a first package and a second package stacked on the first package, wherein the second package includes a plurality of conductive balls electrically connected to the first package, The first package comprises: At least one stacked die unit comprising: A first semiconductor die having: a plurality of first conductive pads; a first passivation layer covering some portions of the plurality of first conductive pads; a plurality of through-holes disposed on the first passivation layer and electrically connected to the plurality of first conductive pads; and a protection layer disposed on the first passivation layer and covering the plurality of through-holes; and At least one second semiconductor die stacked on the first semiconductor die, wherein the at least one second semiconductor die comprises a plurality of second conductive pads; a second passivation layer covering some portions of the plurality of second conductive pads; a plurality of conductive rods disposed on the second passivation layer and electrically connected to the plurality of second conductive pads; and a second protective layer, the second protective layer laterally surrounding the plurality of conductive rods, and the second protective layer of the at least one second semiconductor die is located between the plurality of conductive rods and the protective layer of the first semiconductor die, wherein the protective layer of the first semiconductor die covers the at least one second semiconductor die; an insulating encapsulation having a first surface and a second surface opposite to the first surface, wherein the insulating encapsulation encapsulates the at least one stacked die unit; and A redistribution layer is disposed on the first surface of the insulating enclosure and is electrically connected to the plurality of through holes and the plurality of conductive rods.

10. The package-on-package structure according to claim 9, wherein the first package further comprises: a plurality of insulator perforations embedded in the insulation enclosure; as well as A backside redistribution layer is disposed on the second surface of the insulating package, and the plurality of conductive balls of the second package are electrically connected to the backside redistribution layer of the first package through the plurality of insulator through-holes. 11 . The stacked package structure according to claim 9 , wherein two of the second semiconductor dies are disposed on the first passivation layer, and the plurality of through holes surround the two of the second semiconductor dies.

12. The package-on-package structure according to claim 9, further comprising: A third semiconductor die is stacked on the at least one second semiconductor die, wherein the third semiconductor die includes a plurality of third conductive pads, a third passivation layer covering some portions of the plurality of third conductive pads, and the plurality of conductive rods of the at least one second semiconductor die surround the third semiconductor die.

13. The package-on-package structure according to claim 9, further comprising: A third semiconductor die is disposed on the first semiconductor die adjacent to the at least one second semiconductor die, wherein the third semiconductor die includes a plurality of third conductive pads, a third passivation layer covering portions of the plurality of third conductive pads, and wherein the plurality of through-holes of the first semiconductor die surround the third semiconductor die. 14 . The package-on-package structure according to claim 9 , further comprising a passive device disposed on the first passivation layer of the first semiconductor die and embedded in the protection layer. 15 . The package-on-package structure of claim 9 , wherein a back side of the at least one second semiconductor die is attached to the first passivation layer of the first semiconductor die by fusion bonding. 16 . The package-on-package structure of claim 9 , wherein the first package comprises at least two stacked die units, and the number of stacked semiconductor dies in one of the stacked die units is different from the number of stacked semiconductor dies in another of the stacked die units.

17. A method for manufacturing a packaging structure, comprising: Forming a stacked die unit, comprising: providing a semiconductor wafer having a plurality of first semiconductor dies, wherein each of the plurality of first semiconductor dies comprises a first passivation layer and a plurality of first conductive rods formed on the first passivation layer; affix a second semiconductor die to the first passivation layer of each of the plurality of first semiconductor dies in a region surrounded by the plurality of first conductive rods, wherein the second semiconductor die comprises a plurality of second conductive rods and a second protective layer laterally surrounding the plurality of second conductive rods; forming a first protection layer on a surface of the first passivation layer of each of the plurality of first semiconductor dies to laterally cover the plurality of first conductive rods and the second semiconductor die, wherein the second protection layer of the second semiconductor die is located between the plurality of second conductive rods and the first protection layer of each of the plurality of first semiconductor dies; and Slicing the semiconductor wafer to separate the plurality of first semiconductor dies from each other to form the stacked die unit having one of the plurality of first semiconductor dies and the second semiconductor die; bonding the stacked die unit to a carrier; forming an insulating encapsulation body to encapsulate the stacked die unit; and A redistribution layer is formed on the insulating package and the stacked die unit, wherein the redistribution layer is electrically connected to the plurality of first conductive rods and the plurality of second conductive rods, and each of the plurality of first semiconductor die is electrically connected to the second semiconductor die through the plurality of first conductive rods, the redistribution layer and the plurality of second conductive rods.

18. The method of making a package structure according to claim 17, wherein fixing the second semiconductor die to the first passivation layer of each of the plurality of first semiconductor dies comprises: The second semiconductor die is melt bonded onto the first passivation layer at a temperature ranging from 100° C. to 300° C. to create a chemical bond between a back side of the second semiconductor die and the first passivation layer. 19 . The method for manufacturing a package structure according to claim 17 , wherein the second semiconductor die is fixed to the first passivation layer of each of the plurality of first semiconductor dies by a die attach film. 20 . The method for manufacturing a package structure according to claim 17 , further comprising performing a grinding process on the stacked die unit to make a top surface of the first protection layer, top surfaces of the first conductive rods, and top surfaces of the second conductive rods flush with each other.

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