Display device and method of manufacturing the same

Abstract

The present invention relates to a display device and a manufacturing method thereof. The display device includes: a substrate; and a driving pad arranged on the substrate, wherein the driving pad includes a first pad portion and a second pad portion alternately arranged along a first direction, wherein each of the first pad portion and the second pad portion includes a first data pad and a signal pad, wherein the first data pad of the first pad portion and the first data pad of the second pad portion include a first side and a second side different from the first side, wherein the signal pad of the first pad portion is arranged on a first side of the first data pad of the first pad portion, and the signal pad of the second pad portion is arranged on a second side of the first data pad of the second pad portion, and wherein the first data pad provides a data signal to a pixel, and the signal pad provides a driving voltage to the pixel.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0052172, filed on May 3, 2019, the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present invention relates to a display device and a method for manufacturing the same, and more particularly, to a display device including a pad electrode and a conductive film connected to the pad electrode and a method for manufacturing the same. Background Art

[0004] As information is increasingly distributed throughout society, display devices for displaying images and information are becoming increasingly popular. For example, display devices are applied to various electronic devices such as smart phones, digital cameras, notebook computers, navigation, and smart TVs. Display devices may be flat panel display devices such as liquid crystal display (LCD) devices, field emission display (FED) devices, and organic light emitting display (OLED) devices.

[0005] Typically, a display device may include a plurality of pixels for displaying an image and a display driver for controlling the pixels. In the case of a display driver, the display driver may typically be manufactured in the form of a chip and may be mounted on the display device in the form of a chip on film (COF). Summary of the invention

[0006] According to an exemplary embodiment of the present invention, a display device includes: a first substrate including a plurality of pixels; and a driving pad arranged on the first substrate, wherein the driving pad includes a first pad portion and a second pad portion alternately arranged along a first direction, wherein each of the first pad portion and the second pad portion includes a first data pad and a signal pad, wherein the first data pad of the first pad portion and the first data pad of the second pad portion include a first side and a second side different from the first side, wherein the signal pad of the first pad portion is arranged on a first side of the first data pad of the first pad portion, and the signal pad of the second pad portion is arranged on a second side of the first data pad of the second pad portion, and wherein the first data pad provides a data signal to the plurality of pixels, and the signal pad provides a driving voltage to the plurality of pixels.

[0007] In an exemplary embodiment of the present inventive concept, a plurality of bonding regions are provided on a first substrate, wherein the driving pads are arranged in the plurality of bonding regions, wherein each of the plurality of bonding regions includes a data region and a signal region, wherein the signal pad is disposed in the signal region, wherein the first data pad is disposed in the data region, and wherein an area of ​​the data region is greater than an area of ​​the signal region.

[0008] In an exemplary embodiment of the present inventive concept, each of the first pad portion and the second pad portion further includes a second data pad, wherein the data region includes a first row data region and a second row data region arranged along a second direction crossing the first direction, and wherein the first data pad is arranged in the first row data region and the second data pad is arranged in the second row data region.

[0009] In an exemplary embodiment of the present invention, the first pad portion and the second pad portion form a pad pair, the shape of the first pad portion and the shape of the second pad portion are symmetrical to each other relative to a line extending in the second direction between the first pad portion and the second pad portion, and the driving pad includes a plurality of pad pairs arranged along the first direction.

[0010] In an exemplary embodiment of the inventive concept, a signal pad of the first pad part or a signal pad of the second pad part provides a gate signal to a plurality of pixels.

[0011] In an exemplary embodiment of the inventive concept, the driving voltage is at least one of a common voltage, a storage voltage, and a divided reference voltage.

[0012] In an exemplary embodiment of the present inventive concept, the display device further includes a driving film electrically coupled to the driving pad, wherein the driving film includes a flexible film and a source driving circuit disposed on the flexible film.

[0013] In an exemplary embodiment of the present inventive concept, the driving film includes first and second driving film portions alternately disposed along a first direction, and wherein the first driving film portion is coupled to the first pad portion and the second driving film portion is coupled to the second pad portion.

[0014] In an exemplary embodiment of the present inventive concept, the first driving film portion includes a first lead portion, and the second driving film portion includes a second lead portion, wherein each of the first lead portion and the second lead portion includes a first data lead and a signal lead, wherein the first data lead of the first lead portion and the first data lead of the second lead portion include a first side and a second side different from the first side, and wherein the signal lead of the first lead portion is arranged only on a first side of the first data lead of the first lead portion, and the signal lead of the second lead portion is arranged only on a second side of the first data lead of the second lead portion.

[0015] In an exemplary embodiment of the inventive concept, the first data pad is electrically coupled to the first data lead line to receive a data signal, and the signal pad is electrically coupled to the signal lead line to receive a driving voltage.

[0016] In an exemplary embodiment of the inventive concept, the signal lead line of the first driving film portion or the signal lead line of the second driving film portion receives a gate signal from the source driving circuit.

[0017] In an exemplary embodiment of the present inventive concept, the driving pad further includes a third pad portion disposed between the first pad portion and the second pad portion, and wherein the first pad portion, the second pad portion and the third pad portion form one pad pair.

[0018] In an exemplary embodiment of the inventive concept, the third pad portion includes the first data pad and does not include the signal pad.

[0019] In an exemplary embodiment of the inventive concept, the third pad portion further includes a second data pad arranged in the second row data region.

[0020] In an exemplary embodiment of the present inventive concept, the display device further includes: a second substrate facing the first substrate; and a liquid crystal layer disposed between the first substrate and the second substrate.

[0021] In an exemplary embodiment of the present invention, the signal area includes a first row signal area and a second row signal area arranged along a second direction, wherein the first row signal area overlaps with the first row data area in the first direction, and the second row signal area overlaps with the second row data area in the first direction, and wherein the signal pad is arranged in the first row signal area and not arranged in the second row signal area.

[0022] According to an exemplary embodiment of the present invention, a method for manufacturing a display device includes: exposing a first exposure area of ​​an exposure mask; exposing a second exposure area of ​​the exposure mask; and exposing a third exposure area of ​​the exposure mask, wherein the exposure mask includes a first pad opening area, a second pad opening area, a third pad opening area, and a fourth pad opening area arranged along a first direction, wherein each of the first pad opening area and the third pad opening area includes a first pad slit portion, wherein each of the second pad opening area and the fourth pad opening area includes a second pad slit portion, and the second pad slit portion is symmetrical to the first pad slit portion relative to a line extending between the second pad slit portion and the first pad slit portion in a second direction intersecting the first direction, wherein the first exposure area includes the first pad opening area, the second pad opening area, and the third pad opening area, wherein the second exposure area includes the second pad opening area and the third pad opening area, and wherein the third exposure area includes the second pad opening area, the third pad opening area, and the fourth pad opening area.

[0023] According to an exemplary embodiment of the present invention, a display device includes: a first substrate; and a driving pad, which is arranged on the first substrate and includes a first pad portion and a second pad portion alternately arranged along a first direction, wherein each of the first pad portion and the second pad portion includes a first pad area and a second pad area, wherein the first pad area of ​​the first pad portion and the first pad area of ​​the second pad portion include a first side and a second side opposite to the first side, wherein the second pad area of ​​the first pad portion is arranged at a first side of the first pad area of ​​the first pad portion, and the second pad area of ​​the second pad portion is arranged at a second side of the first pad area of ​​the second pad portion, and wherein each first pad area is wider than each second pad area.

[0024] In an exemplary embodiment of the present inventive concept, each first pad area includes a first pad, and each second pad area includes a second pad, wherein the first pad is configured to provide a data signal to a plurality of pixels arranged on a first substrate, and the second pad is configured to provide a driving voltage to the plurality of pixels.

[0025] In an exemplary embodiment of the present inventive concept, the second pad is not arranged at the second side of the first pad region of the first pad part and at the first side of the first pad region of the second pad part. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other features of the present invention will become more apparent by describing in detail exemplary embodiments of the present invention with reference to the accompanying drawings, in which:

[0027] Figure 1 is a perspective view of a display device according to an exemplary embodiment of the present invention;

[0028] Figure 2 is a perspective view of a display panel according to an exemplary embodiment of the present invention;

[0029] Figure 3 It is a graphic Figure 2 A circuit diagram of a pixel shown in ;

[0030] Figure 4 It is a graphic Figure 2 A plan view of a display panel;

[0031] Figure 5 It is one of the display panels Figure 4 An enlarged plan view in which region Q1 is enlarged;

[0032] Figure 6 yes Figure 5 An enlarged plan view of region Q2 in FIG.

[0033] Figure 7 It is the driving membrane Figure 4 An enlarged plan view in which region Q1 is enlarged;

[0034] Figure 8 yes Figure 7 An enlarged plan view of region Q3 in FIG.

[0035] Fig. 9 is a plan view illustrating a display panel according to an exemplary embodiment of the present invention;

[0036] Fig.10 It is one of the display panels Fig. 9 An enlarged plan view of an area Q1' where the area Q1' is enlarged;

[0037] Fig.11 It is the driving membrane Fig. 9 An enlarged plan view of an area Q1' where the area Q1' is enlarged;

[0038] Fig.12 is an enlarged plan view of a display panel according to an exemplary embodiment of the present invention;

[0039] Fig.13 yes Fig.12 An enlarged plan view of area Q2" in FIG.

[0040] Fig.14 is an enlarged plan view of a driving film of a display panel according to an exemplary embodiment of the present invention;

[0041] Fig.15 yes Fig.14 an enlarged plan view of area Q3″ in FIG.

[0042] Fig.16 is a plan view of an exposure mask for manufacturing a display device according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0043] Exemplary embodiments of the present invention will be described more fully hereinafter with reference to the accompanying drawings. However, the present invention is not limited to the following exemplary embodiments and may be implemented in various different forms.

[0044] It will be understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element or layer, or intervening elements or layers may be present. Throughout this specification, the same reference numerals may refer to the same elements, and thus repeated descriptions may be omitted.

[0045] Although the terms "first", "second", etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another component. Therefore, without departing from the spirit and scope of the present invention, the first component discussed below may be referred to as the second component.

[0046] Hereinafter, exemplary embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

[0047] Figure 1 is a perspective view of a display apparatus according to an exemplary embodiment of the present invention. Figure 2 is a perspective view of a display panel according to an exemplary embodiment of the present invention.

[0048] refer to Figure 1 and Figure 2 The display device 10 according to an exemplary embodiment of the present invention may include a display panel 100, a driving film 200, a source circuit board 300, a cable 400, a control circuit board 500, a timing control circuit 600, and an integrated cover 700. Each of the driving films 200 may include a flexible film 210 and a source driving circuit 220.

[0049] The collection cover 700 may be arranged to surround the boundary of the display panel 100. The collection cover 700 may cover the non-display area of ​​the display panel 100 without covering the display area. The collection cover 700 may include a top collection cover covering the edge of the upper surface of the display panel 100 and a bottom collection cover covering the lower surface and side surfaces of the display panel 100. The top collection cover and the bottom collection cover may be coupled to each other by a fixing member such as a screw or an adhesive member such as a double-sided tape or an adhesive. The collection cover 700 may be made of plastic and / or metal.

[0050] The display panel 100 may have a quadrilateral shape in a plan view. Figure 2 As shown in , the display panel 100 may have a rectangular shape having a long side extending in a first direction D1 and a short side extending in a second direction D2 intersecting the first direction D1. The angle at which the long side in the first direction D1 and the short side in the second direction D2 intersect may be formed to be approximately 90 degrees, or may be rounded to have a predetermined curvature. The planar shape of the display panel 100 is not limited to a rectangle. For example, the display panel 100 may have a polygonal shape, a circular shape, or an elliptical shape. In addition, the third direction D3 may be a direction perpendicular to the first direction D1 and the second direction D2, for example, a normal direction of the display panel 100.

[0051] Figure 2 An example is shown in which the display panel 100 is flat, but the present invention is not limited thereto. The display panel 100 may be curved with a predetermined curvature.

[0052] The display panel 100 may include a first substrate 101 and a second substrate 102. The first substrate 101 and the second substrate 102 may be rigid or flexible. The first substrate 101 and the second substrate 102 may be formed of glass or plastic. The second substrate 102 may be disposed on the first substrate 101.

[0053] The display panel 100 may include a liquid crystal layer between the first substrate 101 and the second substrate 102 to control light transmittance of the liquid crystal layer according to a driving signal applied to the display panel 100. Therefore, the display panel 100 may display an image of a desired grayscale.

[0054] One end of each of the driving films 200 may be attached to one surface of the first substrate 101 of the display panel 100, and the other end of each of the driving films 200 may be attached to one surface of the source circuit board 300. For example, since the size of the first substrate 101 is larger than that of the second substrate 102, one side of the first substrate 101 may be exposed without being covered by the second substrate 102. The driving film 200 may be attached to the side of the first substrate 101 that is exposed without being covered by the second substrate 102. Each of the driving films 200 may be attached to one surface of the first substrate 101 and one surface of the source circuit board 300 by using an anisotropic conductive film (ACF).

[0055] Each of the drive films 200 may be a COF structure. In addition, the drive film 200 may be bendable. For example, the drive film 200 may be bent to the lower surface of the first substrate 101. When the drive film 200 is bent, the source circuit board 300, the cable 400, and the control circuit board 500 may be arranged on the lower surface of the first substrate 101.

[0056] Figure 2An example is shown in which eight driving films 200 are attached to the first substrate 101 of the display panel 100 . However, the number of the driving films 200 is not limited thereto. For example, 24 driving films 200 may be attached to the first substrate 101 .

[0057] Each of the driving films 200 may include a flexible film 210 and a source driving circuit 220. For example, the source driving circuit 220 may be disposed on one surface of the flexible film 210. The source driving circuit 220 may be formed of an integrated circuit (IC). The source driving circuit 220 may convert digital video data into an analog data voltage according to a source control signal of the timing control circuit 600, and supply the analog data voltage to the data line of the display panel 100 through the flexible film 210.

[0058] Each of the source circuit boards 300 may be coupled to the control circuit board 500 via a cable 400. The source circuit board 300 may be a flexible printed circuit board (FPCB) or a printed circuit board (PCB). The cable 400 may be a flexible cable.

[0059] The control circuit board 500 may be coupled to the source circuit board 300 via the cable 400. The control circuit board 500 may be an FPCB or a PCB.

[0060] Figure 2 An example is shown in which four cables 400 connect the source circuit board 300 and the control circuit board 500. However, the number of cables 400 is not limited thereto. Figure 2 There are shown two source circuit boards 300. However, the number of the source circuit boards 300 is not limited thereto.

[0061] The timing control circuit 600 may be arranged on one surface of the control circuit board 500. For example, the timing control circuit 600 may be formed by an integrated circuit (IC). The timing control circuit 600 may receive digital video data and a timing signal such as a gate signal from a system-on-chip of the system circuit board, and may generate a source control signal for controlling the timing of the source driving circuit 220 according to the timing signal.

[0062] The system on chip may be mounted on a system circuit board coupled to the control circuit board 500 via another flexible cable, and may be formed by an integrated circuit. For example, the system on chip may be a processor of a smart TV, a central processing unit (CPU) or a graphics processing unit (GPU) of a computer or notebook, or an application processor of a smart phone or a tablet computer. The system circuit board may be a flexible printed circuit board or a printed circuit board.

[0063] The power supply circuit may be further attached to one surface of the control circuit board 500. The power supply circuit may generate a voltage for driving the display panel 100 using the main power supplied from the system circuit board, and supply the voltage to the display panel 100. For example, the power supply circuit may generate a storage voltage, a common voltage, and a reference voltage for driving a liquid crystal display device, and supply these voltages to the display panel 100. In addition, the power supply circuit may generate and supply a driving voltage for driving the source drive circuit 220, the timing control circuit 600, and the like. The power supply circuit may be formed by an integrated circuit. In addition, the power supply circuit may be arranged on a power supply circuit board formed separately from the control circuit board 500. The power supply circuit board may be a flexible printed circuit board or a printed circuit board.

[0064] Figure 1 and Figure 2 An example of a medium or large display device 10 including a plurality of source drive circuits 220 is shown. However, the present invention is not limited thereto. In an exemplary embodiment of the present invention, the display device 10 may be a small display device including one source drive circuit 220. In this case, the flexible film 210, the source circuit board 300, and the cable 400 may be omitted. In addition, the source drive circuit 220 and the timing control circuit 600 may be integrated into one integrated circuit and bonded to one flexible circuit board connected to the first substrate 101, or the source drive circuit 220 and the timing control circuit 600 may be bonded to the first substrate 101 of the display panel 100. Examples of medium or large display devices may include monitors and televisions, and examples of small display devices may include smart phones and tablet computers.

[0065] Figure 3 It is a graphic Figure 2 Circuit diagram of a pixel shown in .

[0066] refer to Figure 3 , a pixel PX of the display panel may include a plurality of signal lines and a first thin film transistor TFT1, a second thin film transistor TFT2, a third thin film transistor TFT3, a high liquid crystal capacitor HClc, a low liquid crystal capacitor LClc, a high storage capacitor HCST and a low storage capacitor LCST electrically coupled to the plurality of signal lines.

[0067] The signal lines may include a gate line GL, a data line DL, and a divided reference voltage line RDL. A gate signal GATE may be applied to the gate line GL, a data signal DATA may be applied to the data line DL, and a divided reference voltage VRD may be supplied to the divided reference voltage line RDL.

[0068] A common voltage Vcom may be supplied to the common electrode VCL, and a high liquid crystal capacitor HClc may be formed between the common electrode VCL and one electrode of the first thin film transistor TFT1. A low liquid crystal capacitor LClc may be formed between the common electrode VCL and one electrode of the second thin film transistor TFT2.

[0069] A storage voltage Vcst may be applied to the storage electrode VSL, and a high storage capacitor HCST may be formed between the storage electrode VSL and one electrode of the first thin film transistor TFT1. A low storage capacitor LCST may be formed between the storage electrode VSL and one electrode of the second thin film transistor TFT2.

[0070] When the gate signal GATE is applied to the gate line GL, the first thin film transistor TFT1, the second thin film transistor TFT2 and the third thin film transistor TFT3 may be turned on. Therefore, when the first thin film transistor TFT1 is turned on, the data voltage applied to the data line DL (for example, the data voltage of the data signal DATA) may be applied to the high liquid crystal capacitor HClc through the first thin film transistor TFT1. At this time, the high liquid crystal capacitor HClc may be charged with a voltage corresponding to the difference between the common voltage Vcom applied to the common electrode VCL and the data voltage. At the same time, the data voltage may be transmitted to the second thin film transistor TFT2 when the second thin film transistor TFT2 is turned on, and may be transmitted to the third thin film transistor TFT3 when the third thin film transistor TFT3 is turned on. In addition, the low liquid crystal capacitor LClc may be charged with the data voltage. The voltage charged in the low liquid crystal capacitor LClc may be lower than the voltage charged in the high liquid crystal capacitor HClc.

[0071] For example, the data voltage that has passed through the first thin film transistor TFT1 may be fully charged into the high liquid crystal capacitor HClc, but the data voltage that has passed through the second thin film transistor TFT2 may be partially charged into the low liquid crystal capacitor LClc due to the third thin film transistor TFT3. Therefore, the brightness of the area where the high liquid crystal capacitor HClc is located is higher than the brightness of the area where the low liquid crystal capacitor LClc is located.

[0072] The display device including the pixel PX according to the present embodiment can adjust the voltage charged into the upper liquid crystal capacitor HClc and the lower liquid crystal capacitor LClc so that the image viewed from the side is as close as possible to the image viewed from the front. As a result, the side visibility can be increased.

[0073] Figure 4 It is a graphic Figure 2 For ease of explanation, Figure 2 Different, in Figure 4The source circuit board 300, the cable 400, the control circuit board 500, and the timing control circuit 600 may be omitted, and the first substrate 101, the second substrate 102, and the driving film 200 may be illustrated.

[0074] refer to Figure 4 , the display panel 100 may include a first substrate 101 , a second substrate 102 , and a driving film 200 attached to one side of the first substrate 101 .

[0075] As described above, each of the driving films 200 may include a flexible film 210 and a source driving circuit 220 disposed on one surface of the flexible film 210. The source driving circuit 220 may supply various driving signals and driving power (e.g., voltage) for driving the display device, and the driving signal and driving power may be supplied to the pixel PX in the display panel 100 through the flexible film 210.

[0076] The first substrate 101 may include signal lines for transmitting a driving signal and driving power provided from the driving film 200 to electrodes inside the display panel 100 .

[0077] The area on the first substrate 101 to which each of the driving films 200 is attached may be a bonding area BA. The flexible film 210 may contact the first substrate 101 at the bonding area BA to transmit a driving signal and driving power for driving the display device. For example, the first substrate 101 may include a plurality of bonding areas BA. The plurality of bonding areas BA may be disposed adjacent to one side of the first substrate 101 in the first direction D1.

[0078] In addition, the driving film 200 may include a plurality of first driving film portions 201 and a plurality of second driving film portions 202. Figure 4 As shown in FIG. 1 , the first driving film portions 201 and the second driving film portions 202 may be alternately disposed along the first direction D1 .

[0079] The driving film 200 may include a plurality of film pairs 200p. One film pair 200p may include a first driving film portion 201 and a second driving film portion 202 that are sequentially disposed. The plurality of film pairs 200p may be disposed along a first direction D1.

[0080] In the following, reference will be made to Figures 5 to 8 The driving pad 110 of the first substrate 101 and the driving film 200 connected to the driving pad 110 are described in detail.

[0081] Figure 5 It is one of the display panels Figure 4 An enlarged plan view in which area Q1 is enlarged. Figure 6 yes Figure 5 For example, Figure 5 A first pad portion 111 and a second pad portion 112 of the first substrate 101 are shown. Figure 6 The first data pad PA1, the second data pad PA2, and the signal pad PA3 of the first pad portion 111 are shown. For convenience of explanation, Figure 5 and Figure 6 Only the first substrate 101 is shown without the driving film 200 .

[0082] refer to Figure 3 , Figure 4 , Figure 5 and Figure 6 , the driving pad 110 and various signal lines PL1 , PL2 , and PL3 electrically coupled to the driving pad 110 may be formed on a surface of one side of the first substrate 101 .

[0083] The driving pad 110 may include a first pad portion 111 and a second pad portion 112. Figure 5 As shown in FIG. 1 , the first pad portions 111 and the second pad portions 112 may be alternately disposed along the first direction D1 .

[0084] The driving pad 110 may include a plurality of pad pairs 110p. One pad pair 110p may include a first pad portion 111 and a second pad portion 112 that are sequentially disposed, and the plurality of pad pairs 110p may be disposed along the first direction D1.

[0085] The first pad portion 111 and the second pad portion 112 may be symmetrical to each other with respect to a symmetry line SML between the first pad portion 111 and the second pad portion 112. Therefore, the signal lines PL1, PL2, and PL3 connected to the first pad portion 111 and the second pad portion 112 may be formed in a symmetrical shape. For example, the signal lines PL1, PL2, and PL3 connected to the first pad portion 111 may be symmetrical to the signal lines PL1, PL2, and PL3 connected to the second pad portion 112 with respect to the symmetry line SML.

[0086] The first pad portion 111 and the second pad portion 112 may be formed in the bonding area BA. As described above, the bonding area BA may be connected to the driving film 200. The bonding area BA may include a data area BA1 and a signal area BA2. According to an exemplary embodiment of the present invention, the bonding area BA may include the data area BA1 or the signal area BA2.

[0087] The area of ​​the data area BA1 may be wider than the area of ​​the signal area BA2. For example, the widths of the data area BA1 and the signal area BA2 in the first direction D1 may be different from each other, and the widths of the data area BA1 and the signal area BA2 in the second direction D2 may be substantially equal to each other. For example, the width of the data area BA1 in the first direction D1 may be wider than the width of the signal area BA2 in the first direction D1.

[0088] The data area BA1 and the signal area BA2 may be areas where different signals are transmitted. For example, the data area BA1 may be an area where the data signal DATA is transmitted, and the signal area BA2 may be an area where the gate signal GATE and various driving voltages VRD, Vcst, and Vcom other than the data signal DATA are transmitted. The types of signals transmitted through the data area BA1 and the signal area BA2 are not limited thereto.

[0089] Each of the first pad portion 111 and the second pad portion 112 may include a plurality of first data pads PA1, a plurality of second data pads PA2, and a plurality of third pads PA3. The first data pads PA1 and the second data pads PA2 may be arranged in the data area BA1, and the third pads (eg, signal pads) PA3 may be arranged in the signal area BA2.

[0090] like Figure 6 As shown in , the first data pad PA1 may include a first pad PA11, a second pad PA12, a third pad PA13, and a fourth pad PA14. The first pad PA11, the second pad PA12, the third pad PA13, and the fourth pad PA14 may be arranged along the first direction D1. The second data pad PA2 may include a fifth pad PA21, a sixth pad PA22, a seventh pad PA23, and an eighth pad PA24. The fifth pad PA21, the sixth pad PA22, the seventh pad PA23, and the eighth pad PA24 may be arranged along the first direction D1. For example, the first data pad PA1 and the second data pad PA2 may each include a pad row. The pad row of the first data pad PA1 and the pad row of the second data pad PA2 may be spaced apart from each other in the second direction D2.

[0091] The data area BA1 may be divided into a first row data area BA11 and a second row data area BA12 along the second direction D2. The first data pad PA1 may be disposed in the first row data area BA11 of the data area BA1, and the second data pad PA2 may be disposed in the second row data area BA12 of the data area BA1.

[0092] The first data pad PA1 and the second data pad PA2 may not overlap each other in the second direction D2. For example, the first data pad PA1 and the second data pad PA2 may be arranged to be staggered with each other. For example, in the first direction D1, the second pad PA12 of the first data pad PA1 may be arranged between the fifth pad PA21 of the second data pad PA2 and the sixth pad PA22 adjacent to the fifth pad PA21. For example, the pads PA11, PA12, PA13 and PA14 of the first data pad PA1 and the pads PA21, PA22, PA23 and PA24 of the second data pad PA2 may be alternately arranged along the first direction D1.

[0093] The signal pad PA3 may be repeatedly disposed in the signal area BA2 along the first direction D1. The signal area BA2 may be adjacent to the data area BA1 in the first direction D1 or in a direction opposite to the first direction D1. For example, the signal area BA2 may be located on the left or right side of the data area BA1 on a plane. In an exemplary embodiment of the present invention, the signal area BA2 of the first pad portion 111 may be located on the left side of the data area BA1, and the signal area BA2 of the second pad portion 112 may be located on the right side of the data area BA1.

[0094] Signal lines PL1, PL2, and PL3 may be formed on the first substrate 101. The signal lines PL1, PL2, and PL3 may receive a driving signal and a driving power from the first data pad PA1, the second data pad PA2, and the signal pad PA3, respectively, and may transmit the received driving signal and the received driving power to the pixel PX. For example, the first signal line PL1 may be coupled to the first data pad PA1, the second signal line PL2 may be coupled to the second data pad PA2, and the third signal line PL3 may be coupled to the signal pad PA3. Each of the pads PA1, PA2, and PA3 and each of the signal lines PL1, PL2, and PL3 may be connected to correspond to each other. However, according to an exemplary embodiment of the inventive concept, some pads may be set as dummy pads that are not coupled to the signal lines.

[0095] The signals transmitted by the signal lines PL1, PL2 and PL3 may be different from each other. In an exemplary embodiment of the present inventive concept, the first data pad PA1 and the second data pad PA2 may receive the data signal DATA from the driving film 200. The first signal line PL1 and the second signal line PL2 may be coupled to the data line DL to transmit the data signal DATA to each pixel PX. In addition, the signal pad PA3 may receive a signal other than the data signal DATA from the driving film 200. For example, the signal pad PA3 may be provided with a gate signal GATE and a driving power. The driving power provided to the signal pad PA3 may include at least one of a voltage-dividing reference voltage VRD, a storage voltage Vcst and a common voltage Vcom. For example, the third signal line PL3 may be coupled to the gate line GL, the voltage-dividing reference voltage line RDL, the common electrode VCL and the storage electrode VSL to transmit the driving signal and the driving power to each of the pixels PX. The driving signal and the driving power transmitted by each of the signal lines PL1, PL2 and PL3 are not limited to those described above, and other types of signals may be transmitted.

[0096] The gate signal GATE provided by the driving film 200 may be transmitted to a portion of the signal pad PA3. In an exemplary embodiment of the present invention, the gate signal GATE may be transmitted only to the outermost pad portion of the driving pad 110 formed on the first substrate 101. For example, the signal pad PA3 of the leftmost first pad portion 111 of the driving pad 110 and the signal pad PA3 of the rightmost second pad portion 112 of the driving pad 110 may be provided with the gate signal GATE, and the other signal pads PA3 may be provided with the driving power VRD, Vcom, and Vcst in addition to the data signal DATA and the gate signal GATE.

[0097] As described above, the driving pad 110 may be formed on one side of the first substrate 101, and the driving pad 110 may include a plurality of first pad portions 111 and a plurality of second pad portions 112 that are alternately arranged. The first pad portions 111 and the second pad portions 112 may be symmetrical to each other with respect to the symmetry line SML, and constitute a pad pair 110p. When the first pad portions 111 and the second pad portions 112 constitute the pad pair 110p, even if the size of the mask used in the exposure process for forming the driving pad 110 is smaller than the size of the driving pad 110, a full-sized driving pad 110 may be formed by repeating the exposure process multiple times.

[0098] Each of the first pad portion 111 and the second pad portion 112 may include pads PA1, PA2, and PA3 arranged in the data area BA1 and the signal area BA2, and receive different signals from the driving film 200. For example, the first pad portion 111 may include a first data pad PA1 and a second data pad PA2 arranged in the data area BA1 to receive the data signal DATA. The first pad portion 111 may further include a signal pad PA3 arranged in the signal area BA2 to receive various signals including a gate signal GATE, a divided reference voltage VRD, a storage voltage Vcst, and a common voltage Vcom.

[0099] Each of the various signal lines PL1, PL2, and PL3 formed on the first substrate 101 may be coupled to the driving pad 110 to transmit the signal and voltage supplied to the driving pad 110 to the pixel PX. The first signal line PL1 and the second signal line PL2 may be coupled to the first data pad PA1 and the second data pad PA2, respectively, to transmit the data signal DATA to the pixel PX, and the third signal line PL3 may be coupled to the signal pad PA3 to provide various signals including the gate signal GATE to the pixel PX.

[0100] In the following, reference will be made to Figure 7 and Figure 8 The driving film bonded to the above-mentioned pad portion is described in detail.

[0101] Figure 7 It is the driving membrane Figure 4 An enlarged plan view in which area Q1 is enlarged. Figure 8 yes Figure 7 An enlarged plan view of region Q3 in FIG. For example, Figure 7 The first driving film portion 201 and the second driving film portion 202 of the driving film 200 are shown, and Figure 8 A first data lead line LD1 , a second data lead line LD2 , and a signal lead line LD3 of the first driving film portion 201 are shown.

[0102] refer to Figures 3 to 8 , the driving film 200 may be attached to one side of the first substrate 101 to correspond to the driving pad 110 .

[0103] As described above, the driving film 200 may include a first driving film portion 201 and a second driving film portion 202. The first driving film portion 201 and the second driving film portion 202 may be alternately arranged along the first direction D1. The driving film 200 may include a plurality of film pairs 200p. One film pair 200p may include a first driving film portion 201 and a second driving film portion 202 arranged sequentially, and a plurality of film pairs 200p may be arranged in the first direction D1.

[0104] The first driving film portion 201 and the second driving film portion 202 may be symmetrical to each other with respect to a symmetry line SML. Figure 7 The symmetry line SML shown in Figure 5 The symmetry line SML shown in is the same.

[0105] The first driving film portion 201 may include a first lead portion 211, and the second driving film portion 202 may include a second lead portion 212. The first lead portion 211 and the second lead portion 212 may be a plurality of wirings formed on one surface of the flexible film 210.

[0106] The bonding area BA may be an area on the first substrate 101 where the driving pad 110 and the driving film 200 are coupled to each other. The bonding area BA may include a data area BA1 and a signal area BA2. In an exemplary embodiment of the present invention, the bonding area BA may include a data area BA1 or a signal area BA2.

[0107] The first and second lead portions 211 and 212 may include a plurality of first data leads LD1, a plurality of second data leads LD2, and a plurality of signal leads LD3. The first and second data leads LD1 and LD2 may overlap the data area BA1, and the signal leads LD3 may overlap the signal area BA2.

[0108] like Figure 8 As shown in , each of the first data leads LD1 may include a first lead LD11, a second lead LD12, a third lead LD13, and a fourth lead LD14, and the first lead LD11, the second lead LD12, the third lead LD13, and the fourth lead LD14 may be arranged on one surface of the flexible film 210 along the first direction D1. Each of the second data leads LD2 may include a fifth lead LD21, a sixth lead LD22, a seventh lead LD23, and an eighth lead LD24, and the fifth lead LD21, the sixth lead LD22, the seventh lead LD23, and the eighth lead LD24 may be arranged on one surface of the flexible film 210 along the first direction D1. In addition, the first data leads LD1 and the second data leads LD2 may be alternately arranged along the first direction D1. For example, the fifth lead LD21 of the second data lead LD2 may be arranged between the first lead LD11 and the second lead LD12 of the first data lead LD1. For example, the length of each of the first lead LD11, the second lead LD12, the third lead LD13 and the fourth lead LD14 of the first data lead LD1 may have a length smaller than the length of the fifth lead LD21, the sixth lead LD22, the seventh lead LD23 and the eighth lead LD24 of the second data lead LD2 in the second direction D2.

[0109] The first data lead LD1 , the second data lead LD2 , and the signal lead LD3 may be wirings having a substantially uniform width extending in the second direction D2 .

[0110] The data area BA1 may be divided into a first row data area BA11 and a second row data area BA12 along the second direction D2. The first data lead LD1 may overlap the first row data area BA11 of the data area BA1 and may not overlap the second row data area BA12. The second data lead LD2 may overlap the first row data area BA11 and the second row data area BA12 of the data area BA1.

[0111] The signal lead LD3 may overlap the signal area BA2. The signal lead LD3 may be disposed along the first direction D1. The signal area BA2 may be adjacent to the data area BA1 in the first direction D1 or in a direction opposite to the first direction D1.

[0112] Each of the first data lead LD1, the second data lead LD2, and the signal lead LD3 may be electrically coupled to the source driving circuit 220 and the driving pad 110. One end of each of the first data lead LD1, the second data lead LD2, and the signal lead LD3 may be coupled to the source driving circuit 220, and the other ends of the first data lead LD1, the second data lead LD2, and the signal lead LD3 may be coupled to the first data pad PA1, the second data pad PA2, and the signal pad PA3 of the driving pad 110, respectively.

[0113] The first data lead LD1 , the second data lead LD2 , and the signal lead LD3 may be supplied with driving signals DATA and GATE and driving powers VRD, Vcom, and Vcst from the source driving circuit 220 , and may transmit the received driving signals and the received driving power to the driving pad 110 .

[0114] The signals transmitted by the first data lead LD1, the second data lead LD2 and the signal lead LD3 may be different from each other. In an exemplary embodiment of the present invention, the first data lead LD1 and the second data lead LD2 may be provided with a data signal DATA from the source drive circuit 220. In addition, the first data lead LD1 and the second data lead LD2 may be coupled to the first data pad PA1 and the second data pad PA2, respectively, to transmit the data signal DATA. The signal lead LD3 may be provided with a signal other than the data signal DATA from the source drive circuit 220. For example, the signal lead LD3 may be provided with a gate signal GATE and various driving powers VRD, Vcom and Vcst. The driving power provided to the signal lead LD3 may include at least one of a voltage-divided reference voltage VRD, a storage voltage Vcst and a common voltage Vcom. The signal lead LD3 may be electrically coupled to the signal pad PA3 to transmit various signals and voltages. The signals and voltages transmitted by the first data lead LD1, the second data lead LD2 and the signal lead LD3 are not limited to those described above, and other types of signals may be transmitted.

[0115] According to an exemplary embodiment of the present invention, only a portion of the signal lead LD3 may transmit the gate signal GATE to the signal pad PA3. In an exemplary embodiment of the present invention, only the outermost driving film portion of the driving film 200 attached to the first substrate 101 may transmit the gate signal GATE. For example, the signal lead LD3 of the leftmost first driving film portion 201 of the driving film 200 and the signal lead LD3 of the rightmost second driving film portion 202 of the driving film 200 may transmit the gate signal GATE, and the other signal leads LD3 between the leftmost first driving film portion 201 and the rightmost second driving film portion 202 may transmit the driving power VRD, Vcom and Vcst in addition to the data signal DATA and the gate signal GATE.

[0116] As described above, the driving film 200 may be attached to one side of the first substrate 101, and the driving film 200 may include a plurality of first driving film portions 201 and a plurality of second driving film portions 202 that are alternately arranged. The first driving film portion 201 and the second driving film portion 202 may be symmetrical to each other with respect to the symmetry line SML, and may constitute a film pair 200p. When the first driving film portion 201 and the second driving film portion 202 constitute a film pair 200p, the film pair 200p of the driving film 200 may be attached to the pad pair 110p of the driving pad 110 in a one-to-one correspondence.

[0117] The first driving film portion 201 may include a first lead portion 211 formed on the flexible film 210 , and the second driving film portion 202 may include a second lead portion 212 formed on the flexible film 210 .

[0118] Each of the first lead portion 211 and the second lead portion 212 may include leads LD1, LD2, and LD3 disposed in the data area BA1 and the signal area BA2, and the leads LD1, LD2, and LD3 may receive different signals from the source driving circuit 220. For example, the first lead portion 211 may include first and second data leads LD1 and LD2 disposed in the data area BA1 to receive the data signal DATA, and a signal lead LD3 disposed in the signal area BA2 to receive various signals including a gate signal GATE, a divided reference voltage VRD, a storage voltage Vcst, and a common voltage Vcom.

[0119] Each of the first data lead LD1, the second data lead LD2, and the signal lead LD3 may be coupled to the driving pad 110 to transmit a signal and a voltage provided to the driving film 200. The first data lead LD1 and the second data lead LD2 may be coupled to the first data pad PA1 and the second data pad PA2, respectively, to transmit a data signal DATA, and the signal lead LD3 may be coupled to the signal pad PA3 to transmit various signals including a gate signal GATE.

[0120] In a conventional display device, a signal pad is formed on the left and right sides of a data pad. In contrast, the display device according to the present embodiment forms a signal area BA2 only in one of the left and right sides of the data area BA1, so that the data pads PA1 and PA2 can be formed in a wider space. For example, the distance between the data pads PA1 and PA2 can be fully ensured. When the distance between the data pads PA1 and PA2 is not fully ensured, in an external lead bonding (OLB) process for connecting the driving pad 110 and the driving film 200 to each other, a short circuit may be generated between the pads PA1, PA2 and PA3 and the leads LD1, LD2 and LD3, and the display device may not operate normally. For example, the distance between the data pads PA1 and PA2 can be ensured to increase the reliability of the OLB process.

[0121] Typically, a film on which a first row of data leads is formed and a film on which a second row of data leads is formed are separately manufactured and attached to each other. In contrast, in the present embodiment, the first data leads LD1 and the second data leads LD2 may be formed on one driving film 200 and coupled to the driving pad 110. Therefore, the number of driving films 200 connected to the driving pad 110 may be reduced, thereby reducing manufacturing costs.

[0122] Hereinafter, a display device according to an exemplary embodiment of the present invention will be described. In the following description, components identical or similar to those previously described may be referred to by the same reference numerals, and their description may be omitted or simplified; therefore, the differences between the previously described embodiment and the present embodiment will be mainly described.

[0123] Fig. 9 is a plan view illustrating a display panel according to an exemplary embodiment of the present invention. Fig.10 It is one of the display panels Fig. 9 An enlarged plan view in which the region Q1' is enlarged. Fig.11 It is the driving membrane Fig. 9 The area Q1' is enlarged in the enlarged plan view. For example, Fig.10 The first pad portion 111, the second pad portion 112 and the third pad portion 113 of the first substrate 101_1 are shown, and Fig.11 A first drive membrane portion 201 , a second drive membrane portion 202 and a third drive membrane portion 203 are shown.

[0124] and Figures 4 to 8 Different from the embodiment shown in Figures 9 to 11 The embodiment shown in may further include a third pad portion and a third driving film portion. The first pad portion, the second pad portion and the third pad portion may constitute a pad pair, and the first driving film portion, the second driving film portion and the third driving film portion may constitute a film pair.

[0125] refer to Figures 9 to 11 , the display panel 100_1 may include a first substrate 101_1, a second substrate 102, and a driving film 200_1. The first substrate 101_1 may be electrically coupled to the driving film 200_1 through a driving pad 110_1 provided adjacent to one side of the first substrate 101_1 and along a first direction D1. The first substrate 101_1 may include various signal lines PL1, PL2, and PL3 connected to the driving pad 110_1. A driving signal and a driving power may be provided to the pixel PX through the signal lines PL1, PL2, and PL3.

[0126] like Fig.10 As shown in FIG. 1 , driving pad 110_1 may include first pad portion 111, second pad portion 112, and third pad portion 113 disposed between first pad portion 111 and second pad portion 112. Areas of first pad portion 111, second pad portion 112, and third pad portion 113 may be substantially the same.

[0127] The driving pad 110_1 may include a plurality of pad pairs 110p_1. One pad pair 110p_1 may include a first pad portion 111, a third pad portion 113, and a second pad portion 112 that are sequentially arranged. The plurality of pad pairs 110p_1 may be arranged along the first direction D1. For example, the driving pad 110_1 may include a plurality of pad portions 111, 112, and 113 that are sequentially arranged in the order of the first pad portion 111, the third pad portion 113, and the second pad portion 112.

[0128] Each of the first pad portion 111 and the second pad portion 112 may include a first data pad PA1, a second data pad PA2, and a signal pad PA3. The first data pad PA1, the second data pad PA2, and the signal pad PA3 may be connected to Figures 4 to 8 The first data pad PA1, the second data pad PA2, and the signal pad PA3 described in the embodiment of FIG. 1 are the same as or similar, and thus a detailed description thereof will be omitted.

[0129] The third pad portion 113 may be arranged in the bonding area BA. The third pad portion 113 may include a first data pad PA1 and a second data pad PA2. Unlike the first pad portion 111 and the second pad portion 112 described above, the third pad portion 113 may not include a signal pad PA3. For example, the area where the third pad portion 113 is arranged may be a data area BA3 for transmitting a data signal DATA.

[0130] The first data pad PA1 of the third pad portion 113 may be coupled to the first signal line PL1 to provide the transmitted data signal DATA to the pixel PX, and the second data pad PA2 may be coupled to the second signal line PL2 to provide the data signal DATA to the pixel PX.

[0131] like Fig.11 As shown in FIG. 1 , the driving film 200_1 may include a first driving film portion 201 , a second driving film portion 202 , and a third driving film portion 203 disposed between the first driving film portion 201 and the second driving film portion 202 .

[0132] The driving film 200_1 may include a plurality of film pairs 200p_1. One film pair 200p_1 may include a first driving film portion 201, a third driving film portion 203, and a second driving film portion 202 that are sequentially arranged. The plurality of film pairs 200p_1 may be arranged along the first direction D1. For example, the driving film 200_1 may include a plurality of driving film portions 201, 202, and 203 that are sequentially arranged in the order of the first driving film portion 201, the third driving film portion 203, and the second driving film portion 202.

[0133] The first driving film portion 201 may include a first lead portion 211, and the second driving film portion 202 may include a second lead portion 212. The first lead portion 211 and the second lead portion 212 may be a plurality of wirings formed on one surface of the flexible film 210. Each of the first lead portion 211 and the second lead portion 212 may include a first data lead LD1, a second data lead LD2, and a signal lead LD3. The first data lead LD1, the second data lead LD2, and the signal lead LD3 are connected to the first data lead LD1, the second data lead LD2, and the signal lead LD3. Figures 4 to 8 The first data lead LD1, the second data lead LD2, and the signal lead LD3 described in the embodiment of FIG. 1 are the same as or similar to each other, and thus a detailed description thereof will be omitted.

[0134] The third driving film portion 203 may be formed on one surface of the flexible film 210, and may include a third lead portion 213 disposed between the first lead portion 211 and the second lead portion 212. The third lead portion 213 may be disposed in the bonding area BA.

[0135] Unlike the first lead portion 211 and the second lead portion 212, the third lead portion 213 may include the first data lead LD1 and the second data lead LD2 and may not include the signal lead LD3. For example, the area where the third lead portion 213 of the third driving film portion 203 is arranged may be a data area BA3 for transmitting a data signal DATA.

[0136] Each of the first data lead LD1 and the second data lead LD2 of the third driving film portion 203 may be electrically coupled to the source driving circuit 220 and the driving pad 110_1. For example, one end of each of the first data lead LD1 and the second data lead LD2 may be coupled to the source driving circuit 220, and the other ends of the first data lead LD1 and the second data lead LD2 may be coupled to the first data pad PA1 and the second data pad PA2 of the driving pad 110_1, respectively.

[0137] The first and second data leads LD1 and LD2 of the third driving film portion 203 may receive the data signal DATA from the source driving circuit 220 and transmit the data signal DATA to the driving pad 110_1 .

[0138] In reference Figures 9 to 11 In the described embodiment, one pad pair 110p_1 may include one third pad portion 113, and one film pair 200p_1 may include one third lead portion 213. However, the present invention is not limited thereto. One pad pair 110p_1 may include a plurality of third pad portions 113, and one film pair 200p_1 may include a plurality of third lead portions 213.

[0139] The display device according to an exemplary embodiment of the present invention may include a third pad portion 113 on which no signal pad PA3 is formed. For example, the third pad portion 113 may include more data pads PA1 and PA2 than the first and second pad portions 111 and 112 within the same area.

[0140] Fig.12 is an enlarged plan view of a display panel according to an exemplary embodiment of the present invention. Fig.13 yes Fig.12 An enlarged plan view of area Q2" in FIG. Fig.14 is an enlarged plan view of a driving film of a display panel according to an exemplary embodiment of the present invention. Fig.15 yes Fig.14 An enlarged plan view of area Q3" in FIG.

[0141] Figures 12 to 15 Examples and Figures 4 to 8 The difference between the embodiments is that the signal pad PA3_2 of the signal area BA2 overlaps the first data pad PA1 in the first direction D1 and does not overlap the second data pad PA2 in the first direction D1. The differences between the embodiments are explained below.

[0142] refer to Figures 12 to 15 , the first substrate 101_2 may be electrically coupled to the driving film 200_2 through the driving pad 110_2 provided adjacent to one side of the first substrate 101_2 and along the first direction D1.

[0143] The driving pad 110_2 may include a first pad portion 111_2 and a second pad portion 112_2 formed in the bonding area BA. The first pad portion 111_2 and the second pad portion 112_2 may include a first data pad PA1, a second data pad PA2, and a signal pad PA3_2. The first data pad PA1 and the second data pad PA2 are arranged in the data area BA1, and the signal pad PA3_2 is arranged in the signal area BA2.

[0144] According to Figure 5 and Figure 6 The signal pad PA3 of the embodiment is different, according to Fig.12 and Fig.13The signal pad PA3_2 of the embodiment may not overlap with the second data pad PA2 in the first direction D1. For example, the signal area BA2 may be divided into a first row signal area BA21 and a second row signal area BA22 along the second direction D2. The first row signal area BA21 may overlap with the first row data area BA11 in the first direction D1, and the second row signal area BA22 may overlap with the second row data area BA12 in the first direction D1. The signal pad PA3_2 may be arranged in the first row signal area BA21 of the signal area BA2, and may not be arranged in the second row signal area BA22.

[0145] The driving film 200_2 may include a first driving film portion 201_2 and a second driving film portion 202_2. The first driving film portion 201_2 and the second driving film portion 202_2 may respectively include a first lead portion 211_2 and a second lead portion 212_2 formed on one surface of the flexible film 210. Each of the first lead portion 211_2 and the second lead portion 212_2 may include a first data lead line LD1, a second data lead line LD2, and a signal lead line LD3_2. The first data lead line LD1 and the second data lead line LD2 may be arranged in the data area BA1, and the signal lead line LD3_2 may be arranged in the signal area BA2.

[0146] According to Figure 7 and Figure 8 The signal lead LD3 of the embodiment is different, according to Fig.14 and Fig.15 The signal lead LD3_2 of the embodiment may not overlap with the second data lead LD2 in the first direction D1. For example, the signal area BA2 may be divided into a first row signal area BA21 and a second row signal area BA22 along the second direction D2. The signal lead LD3_2 may be arranged in the first row signal area BA21 of the signal area BA2, and may not be arranged in the second row signal area BA22.

[0147] When the signal pad PA3_2 is Figures 12 to 15 When the third signal line PL3 is arranged only in the first row signal area BA21 of the bonding area BA and not in the second row signal area BA22 as in the embodiment of FIG. 1 , a space in which the third signal line PL3 is to be arranged can be sufficiently provided.

[0148] For example, Fig.13As shown in , the leftmost signal pad PA3_2 can receive the gate signal GATE from the driving film 200_2 and provide the received gate signal GATE to each pixel PX. By using the space of the second row signal area BA22 where the signal pad PA3_2 is not formed, the third signal line PL3 for transmitting the gate signal GATE is formed closer to the edge side of the first substrate 101_2, so that the size of the frame of the display device can be reduced.

[0149] In addition, the contact area between the signal pad PA3_2 and the signal lead LD3_2 can be reduced, and the resistance caused thereby can be reduced. For example, the heat generated by the wiring resistance in the display device can be reduced.

[0150] Fig.16 is a plan view of an exposure mask for manufacturing a display device according to an exemplary embodiment of the present invention. For example, Fig.16 The exposure mask shown in FIG. 1 may be used to form Figures 4 to 6 The exposure mask of the first substrate 101 is provided. The repeated description will be omitted.

[0151] refer to Figure 4 , Figure 5 , Figure 6 and Fig.16 , the exposure mask 800 may include a first pad opening area POA1, a second pad opening area POA2, a third pad opening area POA3, and a fourth pad opening area POA4 arranged in sequence. The exposure mask 800 may include a pad slit portion 810 formed adjacent to one side thereof. The pad slit portion 810 may be formed in each of the pad opening areas POA1, POA2, POA3, and POA4. The pad slit portion 810 may be used to Figure 5 The exposure slits for the driving pads 110 are formed on the first substrate 101 shown in FIG.

[0152] Each of the first pad opening area POA1 and the third pad opening area POA3 may include a first pad slit portion 811. The first pad slit portion 811 may be a slit for forming the first pad portion 111. For example, the first pad slit portion 811 may include pad slits PS1, PS2, and PS3 corresponding to the shape of the first pad portion 111. The pad slits PS1, PS2, and PS3 may include a plurality of slits corresponding to the shapes of the pads.

[0153] For example, the first pad slit portion 811 may include a first data pad slit PS1, a second data pad slit PS2, and a signal pad slit PS3. The first data pad slit PS1 of the first pad slit portion 811 may form a first data pad PA1 of the first pad portion 111. The second data pad slit PS2 may form a second data pad PA2 of the first pad portion 111. The signal pad slit PS3 may form a signal pad PA3 of the first pad portion 111.

[0154] Similar to the first pad portion 111, the signal pad slit PS3 of the first pad slit portion 811 may be formed on the left or right side of the first data pad slit PS1 and the second data pad slit PS2. Fig.16 As shown in FIG, the signal pad slit PS3 may be formed on the left side of the first data pad slit PS1 and the second data pad slit PS2.

[0155] Each of the second pad opening area POA2 and the fourth pad opening area POA4 may include a second pad slit portion 812. The second pad slit portion 812 may be a slit for forming the second pad portion 112. For example, the second pad slit portion 812 may include pad slits PS1, PS2, and PS3 corresponding to the shape of the second pad portion 112. The pad slits PS1, PS2, and PS3 may include a plurality of slits corresponding to the shape of the pad.

[0156] For example, the second pad slit portion 812 may include a first data pad slit PS1, a second data pad slit PS2, and a signal pad slit PS3. The first data pad slit PS1 of the second pad slit portion 812 may form a first data pad PA1 of the second pad portion 112. The second data pad slit PS2 may form a second data pad PA2 of the second pad portion 112. The signal pad slit PS3 may form a signal pad PA3 of the second pad portion 112.

[0157] Similar to the second pad portion 112, the signal pad slit PS3 of the second pad slit portion 812 may be formed on the left or right side of the first data pad slit PS1 and the second data pad slit PS2. Fig.16 As shown in FIG, the signal pad slit PS3 may be formed on the right side of the first data pad slit PS1 and the second data pad slit PS2.

[0158] One first pad slit portion 811 and one second pad slit portion 812 adjacent thereto may form one slit pair 810p. For example, the pad slit portion 810 may include a plurality of slit pairs 810p.

[0159] The signal pad slit PS3 of the outermost pad slit portion 811 or 812 of the pad slit portion 810 formed in the exposure mask 800 may include a gate signal GATE (see Figure 3 ) is provided to the gate pad slit of the pixel PX of the display device. For example, each of the signal pad slit PS3 of the first pad slit portion 811 formed in the first pad opening area POA1 and the signal pad slit PS3 of the second pad slit portion 812 formed in the fourth pad opening area POA4 may include a gate pad slit for forming a pad for transmitting the gate signal GATE.

[0160] In an exemplary embodiment of the present invention, the exposure mask 800 may further include slits connected to the first data pad slit PS1, the second data pad slit PS2, and the signal pad slit PS3 to form the signal lines PL1, PL2, and PL3 on the first substrate 101. For example, the exposure mask 800 may simultaneously form the drive pad 110 and the signal lines PL1, PL2, and PL3. However, the present invention is not limited thereto. In an exemplary embodiment of the present invention, the signal lines PL1, PL2, and PL3 may be formed in a separate process using a separate exposure mask.

[0161] A photosensitive material may be coated on the first substrate 101 . The above-mentioned exposure mask 800 may be disposed on the first substrate 101 and an exposure process may be performed. The driving pads 110 may be formed on the first substrate 101 by light passing through slits of the exposure mask 800 .

[0162] When the size of the exposure mask 800 is smaller than the size of the first substrate 101, the driving pads 110 disposed on the first substrate 101 may not be formed through a single exposure process. For example, full-sized driving pads 110 may be formed through a plurality of exposure processes.

[0163] The method for manufacturing a display device including a first substrate 101 on which a driving pad 110 is formed using an exposure mask 800 according to the present embodiment may include the following steps: exposing a first exposure area EX1 to perform a first exposure process; exposing a second exposure area EX2 to perform a second exposure process; and exposing a third exposure area EX3 to perform a third exposure process.

[0164] The first exposure area EX1 may include a first pad opening area POA1. For example, the first exposure area EX1 may include a first pad opening area POA1, which is the leftmost area among the pad opening areas POA1, POA2, POA3, and POA4 including the pad slit portion 810. In addition, the first exposure area EX1 may further include a second pad opening area POA2 and a third pad opening area POA3 adjacent to the second pad opening area POA2. The first exposure area EX1 may include an odd number of pad opening areas POA1, POA2, and POA3. However, the present invention is not limited thereto.

[0165] The first pad portion 111 , the second pad portion 112 , and the first pad portion 111 may be sequentially formed on the first substrate 101 by exposing the first exposure region EX1 and performing a first exposure process.

[0166] The second exposure area EX2 may not include the first pad opening area POA1 located at the leftmost side of the exposure mask 800 and the fourth pad opening area POA4 located at the rightmost side of the exposure mask 800. For example, the second exposure area EX2 may include the second pad opening area POA2 and the third pad opening area POA3. The second exposure area EX2 may include an even number of pad opening areas POA2 and POA3. However, the present invention is not limited thereto.

[0167] When the second exposure area EX2 is exposed and the second exposure process is performed, the positions of the exposure mask 800 and the first substrate 101 may be adjusted so that the pad portions 111 and 112 may be formed on the right side of the first pad portion 111 formed by the first exposure process. For example, the first pad portion 111 and the second pad portion 112 may be sequentially formed on the first substrate 101 by the first exposure process, and the second pad portion 112 and the first pad portion 111 may be sequentially formed on the right side of the first pad portion 111 by the second exposure process.

[0168] The second exposure process for exposing the second exposure area EX2 may be performed multiple times. For example, if the second exposure process is performed again from the right side of the pad portions 111 and 112 formed by the second exposure process, the number of pad portions 111 and 112 formed on the first substrate 101 may be increased. The number of times of the second exposure process may be adjusted according to the size of the display panel 100.

[0169] For example, the second exposure area EX2 may be included in each of the first exposure area EX1 and the third exposure area EX3. However, the present invention is not limited thereto.

[0170] The third exposure area EX3 may include a fourth pad opening area POA4. For example, the third exposure area EX3 may include a fourth pad opening area POA4, which is the rightmost area among the pad opening areas POA1, POA2, POA3, and POA4 including the pad slit portion 810. In addition, the third exposure area EX3 may further include a second pad opening area POA2 and a third pad opening area POA3 adjacent to the fourth pad opening area POA4. The third exposure area EX3 may include an odd number of pad opening areas POA2, POA3, and POA4. However, the present invention is not limited thereto.

[0171] When the third exposure area EX3 is exposed and the third exposure process is performed, the positions of the exposure mask 800 and the first substrate 101 may be adjusted so that the pad portion may be formed on the right side of the pad portions 111 and 112 formed by the second exposure process. For example, the pad portions 111 and 112 may be sequentially formed on the first substrate 101 by the first exposure process, the pad portions 111 and 112 may be formed on the right side of the first pad portion 111 formed by the first exposure process by the second exposure process, and the pad portions 111 and 112 may be formed on the right side of the pad portions 111 and 112 formed by the first exposure process and the second exposure process by the third exposure process. In an additional example, the first pad portion 111, the second pad portion 112, and another first pad portion 111 may be sequentially formed by the third exposure process.

[0172] The display device and the manufacturing method thereof according to the present invention can form a signal pad for providing a signal other than a data signal only on the left or right side of the data pad. The distance between the data pads can be fully ensured, and the reliability of the outer lead bonding (OLB) process between the pad portion of the display panel and the chip-on-film (COF) film can be increased.

[0173] In addition, according to the display device and the manufacturing method thereof of the present invention, the data lead formed on one COF film can be coupled to two rows of pad structures formed on the display panel, the number of films required for connecting the pads can be reduced, and the manufacturing cost can be reduced.

[0174] The effects according to the exemplary embodiments of the present invention are not limited to the above-exemplified contents, and more various effects may be included in the specification.

[0175] While the invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be apparent to one skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.

Claims

1. A display device, comprising: a first substrate including a plurality of pixels; as well as a driving pad disposed on the first substrate, The driving pad includes a first pad portion and a second pad portion alternately arranged along a first direction, wherein each of the first pad portion and the second pad portion includes a first data pad, a second data pad and a signal pad, and the first data pad and the second data pad are arranged along a second direction crossing the first direction, wherein the first data pad of the first pad portion and the first data pad of the second pad portion include a first side and a second side different from the first side, wherein the signal pad of the first pad portion is arranged at the first side of the first data pad of the first pad portion, and the signal pad of the second pad portion is arranged at the second side of the first data pad of the second pad portion, wherein the first data pad provides a data signal to the plurality of pixels, and the signal pad provides a driving voltage to the plurality of pixels, wherein the first pad portion and the second pad portion form a pad pair, a shape of the first pad portion and a shape of the second pad portion are symmetrical to each other with respect to a line extending between the first pad portion and the second pad portion in the second direction, and The first pad portion is provided in plurality, the second pad portion is provided in plurality, and the driving pad includes a plurality of pad pairs arranged along the first direction.

2. The display device according to claim 1, wherein: A plurality of bonding areas are provided on the first substrate, wherein the driving pads are arranged in the plurality of bonding areas, wherein each of the plurality of bonding regions comprises a data region and a signal region, wherein the signal pad is disposed in the signal region, wherein the first data pad is disposed in the data region, and The area of ​​the data region is larger than the area of ​​the signal region.

3. The display device according to claim 2, wherein: The data area includes a first row data area and a second row data area arranged along the second direction, The first data pad is disposed in the first row data region, and the second data pad is disposed in the second row data region, and The signal pad of the first pad portion or the signal pad of the second pad portion provides a gate signal to the plurality of pixels.

4. The display device according to claim 3, further comprising: a driving film electrically coupled to the driving pad, The driving film includes a flexible film and a source driving circuit arranged on the flexible film. The driving film includes a first driving film portion and a second driving film portion alternately arranged along the first direction, wherein the first driving film portion is coupled to the first pad portion and the second driving film portion is coupled to the second pad portion, wherein the first driving film portion includes a first lead portion, and the second driving film portion includes a second lead portion, wherein each of the first lead portion and the second lead portion comprises a first data lead and a signal lead, wherein the first data lead of the first lead portion and the first data lead of the second lead portion comprise a first side and a second side different from the first side, and The signal lead of the first lead part is arranged only on the first side of the first data lead of the first lead part, and the signal lead of the second lead part is arranged only on the second side of the first data lead of the second lead part.

5. The display device according to claim 4, wherein: The first data pad is electrically coupled to the first data lead to receive the data signal, and the signal pad is electrically coupled to the signal lead to receive the driving voltage, and The signal lead of the first driving film portion or the signal lead of the second driving film portion receives the gate signal from the source driving circuit.

6. The display device according to claim 3, wherein: The driving pad further includes a third pad portion disposed between the first pad portion and the second pad portion, wherein the first pad portion, the second pad portion and the third pad portion form a pad pair, wherein the third pad portion includes the first data pad and does not include the signal pad, and The third pad portion further includes the second data pad arranged in the second row data area.

7. The display device according to claim 3, wherein: The signal area includes a first row of signal areas and a second row of signal areas arranged along the second direction, The first row signal region overlaps with the first row data region in the first direction, and the second row signal region overlaps with the second row data region in the first direction, and The signal pad is arranged in the first row signal area and is not arranged in the second row signal area.

8. A method for manufacturing a display device as claimed in any one of claims 1 to 7, the method comprising: exposing a first exposure region of the exposure mask; exposing a second exposure area of ​​the exposure mask; as well as exposing the third exposure area of ​​the exposure mask, The exposure mask includes a first pad opening region, a second pad opening region, a third pad opening region and a fourth pad opening region arranged along a first direction, wherein each of the first pad opening region and the third pad opening region includes a first pad slit portion, and the first pad slit portion is used to form the first data pad, the second data pad, and the signal pad of the first pad portion, wherein each of the second pad opening region and the fourth pad opening region includes a second pad slit portion, the second pad slit portion is symmetrical to the first pad slit portion with respect to a line extending between the second pad slit portion and the first pad slit portion in a second direction intersecting the first direction, and the second pad slit portion is used to form the first data pad, the second data pad and the signal pad of the second pad portion, The first exposure area includes the first pad opening area, the second pad opening area and the third pad opening area. Wherein, the second exposure area includes the second pad opening area and the third pad opening area, and Wherein, the third exposure area includes the second pad opening area, the third pad opening area and the fourth pad opening area.

9. A display device, comprising: a first substrate; as well as a driving pad, the driving pad being arranged on the first substrate and comprising a first pad portion and a second pad portion alternately arranged along a first direction, wherein each of the first pad portion and the second pad portion includes a first pad region, a second pad region, and a third pad region, and the first pad region and the third pad region are arranged along a second direction intersecting the first direction, wherein the first pad region of the first pad portion and the first pad region of the second pad portion include a first side and a second side opposite to the first side, wherein the second pad region of the first pad portion is arranged at the first side of the first pad region of the first pad portion, and the second pad region of the second pad portion is arranged at the second side of the first pad region of the second pad portion, wherein the first pad portion and the second pad portion form a pad pair, and the shape of the first pad portion and the shape of the second pad portion are symmetrical to each other with respect to a line extending between the first pad portion and the second pad portion in the second direction, wherein the first pad portion is provided in plurality, the second pad portion is provided in plurality, and the driving pad includes a plurality of pad pairs arranged along the first direction, and Each of the first pad regions is wider than each of the second pad regions.

10. The display device according to claim 9, wherein: Each of the first pad regions includes a first pad, and each of the second pad regions includes a second pad, wherein the first pad is configured to provide a data signal to a plurality of pixels arranged on the first substrate, and the second pad is configured to provide a driving voltage to the plurality of pixels, and The second pad is not arranged at the second side of the first pad region of the first pad portion and at the first side of the first pad region of the second pad portion.

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