Flexible circuit substrate for carrying chips and manufacturing method thereof

Abstract

The present invention provides a flexible circuit substrate for carrying a chip and a manufacturing method thereof, wherein the manufacturing method comprises the following steps in sequence: (a) providing a conductive copper layer with a wiring pattern on an insulating substrate; (b) forming a first solder mask layer to partially cover the wiring pattern; (c) forming a first tin layer on the conductive copper layer using the first solder mask layer as a shield; (d) forming a second tin layer on the first tin layer using the first solder mask layer as a shield; and (e) forming a second solder mask layer to partially cover the second tin layer and at least partially cover the first solder mask layer.

Description

Technical Field

[0001] The invention relates to a flexible circuit substrate, in particular to a flexible circuit substrate capable of carrying a semiconductor chip. Background Art

[0002] The flexible circuit substrate used to carry the chip is mostly a rolled strip film. In the industry, the combination of flexible circuit substrate and chip has various names according to different assembly modes, such as TCP (Tape Carrier Package) or COF (Chip On Film). TCP and COF both use flexible circuit substrate as the carrier of the packaged chip, and the gold bump (Gold Bμmp) on the chip is connected to the inner lead (Inner Lead) of the copper wiring pattern on the flexible substrate circuit by thermal compression.

[0003] In order to connect the flexible substrate circuit to the gold bump of the chip, the presence of gold-tin eutectic is necessary, where gold is provided by the gold bump of the chip and tin is provided by the tin formed on the surface of the inner pin. Therefore, the surface of the inner pin is plated with a tin layer. In addition to the inner pin, the copper wiring pattern also has conductive terminals such as outer pins that connect to other electronic components. These terminals are usually also plated with tin. The non-pin area on the copper wiring pattern is additionally protected by covering with solder mask ink.

[0004] Existing flexible substrate circuits are prone to the following problems. One is the formation of whiskers on the surface of the tin-plated layer, which causes short circuits between adjacent circuits. The other is the formation of pits at the interface between the solder resist ink and the tin-plated layer, which causes circuit breakage. Patent document 1 (Japanese patent JP3061613) discloses a solution that first forms a thin tin-plated layer (a) on the copper wiring pattern, then applies solder resist ink to the non-pin area of ​​the wiring pattern, and then forms a thick tin-plated layer (b) on the pin area. Patent document 1 believes that the thin tin-plated layer (a) formed on the entire copper wiring pattern can prevent the formation of pits, and the thick tin-plated layer (b) can prevent the formation of whiskers. Patent document 2 (Taiwan patent TW531864) discloses another method, which is to sequentially form a first solder resist ink in the non-pin area, form a thin tin-plated layer in the pin area, then form a second solder resist ink to cover the interface between the first solder resist ink and the thin tin layer, and finally form a thick tin-plated layer on the thin tin layer. Summary of the invention

[0005] After research, the inventors of this case found that the above-mentioned prior art still has many problems in actual operation. For example, Patent Document 1 forms a thin tin-plated layer on the entire copper wiring pattern, which is not conducive to products that need to be bent because the hardness of the tin-plated layer is usually high. In addition, both Patent Document 1 and Patent Document 2 indicate that a thick tin-plated layer is formed after the final coating of solder mask ink, so the top layer of solder mask ink will still be immersed in the tin plating tank for a period of time, especially the thick tin plating time is longer, which increases the chance of pits at the interface between the top layer of solder mask ink and the thick tin plating layer. In addition, Patent Document 2 has a process in which solder mask ink is applied twice before entering the tin bath, resulting in a high cost for cleaning the tin bath contaminated by solder mask ink. In addition, Patent Document 2 teaches a process of staggered implementation of two solder mask inks and two tin platings, which is easy to confuse in actual operation, causing trouble in arranging production lines.

[0006] In view of the above, on the one hand, the present invention proposes a novel method for manufacturing a flexible circuit substrate, which does not require two solder mask inks and two tinning processes to be implemented alternately. At the same time, the present invention also applies a top layer of solder mask ink after the last tin layer is completed to prevent the top layer of solder mask ink from being soaked in the tinning tank.

[0007] According to one embodiment, the present invention provides a method for manufacturing a flexible circuit substrate for carrying a chip, which comprises the following steps in sequence:

[0008] (a) providing a conductive copper layer having a wiring pattern on an insulating substrate;

[0009] (b) forming a first solder resist layer to partially cover the wiring pattern;

[0010] (c) forming a first tin layer on the conductive copper layer using the first solder resist layer as a shield;

[0011] (d) forming a second tin layer on the first tin layer using the first solder mask as a shield; and (e) forming a second solder mask to partially cover the second tin layer and at least partially cover the first solder mask.

[0012] According to one embodiment, the present invention provides the aforementioned manufacturing method, wherein there is no step of forming a solder mask layer between the step (c) and the step (d).

[0013] According to one embodiment, the present invention provides the aforementioned manufacturing method, wherein through the step (d), the first solder mask layer at least partially covers the second tin layer.

[0014] According to one embodiment, the present invention provides the aforementioned manufacturing method, wherein through the step (d), the interface between the first tin layer and the second tin layer is conformal to the interface between the first tin layer and the conductive copper layer.

[0015] According to one embodiment, the present invention provides a manufacturing method as described above, wherein the second solder resist layer is not in contact with the tin plating solution.

[0016] On the other hand, the present invention provides a method for manufacturing a flexible circuit substrate, which is to reduce the coating area of ​​the first solder mask layer or the second solder mask layer to reduce the amount of contamination of the solder mask ink on the tin bath. For example, the first solder mask layer can be selectively coated only on the area of ​​the flexible circuit substrate that will be bent when the product is applied; or the second solder mask layer can selectively cover the outer edge of the first solder mask layer without completely covering the first solder mask layer.

[0017] According to one embodiment, the present invention provides a method for manufacturing a flexible circuit substrate for carrying a chip, which comprises the following steps in sequence:

[0018] (a) providing a conductive copper layer having a wiring pattern on an insulating substrate, wherein the wiring pattern has a test pin area, an inner pin area and an outer pin area;

[0019] (b) forming a first solder resist layer to partially cover the wiring pattern, wherein the first solder resist layer does not cover the wiring pattern between the test pin area and the inner pin area;

[0020] (c) forming a first tin layer on the conductive copper layer using the first solder resist layer as a shield;

[0021] (d) forming a second tin layer on the first tin layer using the first solder mask as a shield; and (e) forming a second solder mask to partially cover the second tin layer and at least partially cover the first solder mask.

[0022] According to one embodiment, the present invention provides the aforementioned manufacturing method, wherein in the step (e), the second solder resist layer does not completely cover the first solder resist layer.

[0023] On the other hand, the present invention provides a method for manufacturing a flexible circuit substrate, wherein the second tin layer has a roughened tin surface. The roughened tin surface can provide a larger surface area. When the flexible circuit substrate is externally connected to other electronic components, the roughened tin surface in the external pin area can increase the bonding area with the anisotropic conductive film (ACF), thereby making the flexible circuit substrate and the electronic device more closely attached.

[0024] According to one embodiment, the present invention provides a manufacturing method as described above, wherein the step (a) further includes roughening the conductive copper layer so that the conductive copper layer has a roughened copper surface, wherein the roughened copper surface can be formed, for example, by treating the conductive copper layer with a chemical solution. Since the tin layer is plated on the roughened copper surface, the first tin layer and the second tin layer will also have a roughened surface. In this embodiment, the second tin layer has a roughened tin surface, and the surface roughness Rz of the roughened tin surface ranges from 0.045 μm to 0.5 μm, preferably ranges from 0.06 μm to 0.35 μm, and more preferably ranges from 0.μm 1 to 0.3 μm.

[0025] On the other hand, the present invention also includes various structures of flexible circuit substrates formed by the above-mentioned various methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1A The figure is a top view of a semi-finished flexible circuit substrate according to an embodiment of the present invention.

[0027] Figure 1B for Figure 1A A schematic cross-sectional view of a specific area of ​​a semi-finished product.

[0028] Figure 1B and Figures 2 to 5 The cross-sectional view shows various steps of a manufacturing process of a flexible circuit substrate according to a first embodiment of the present invention.

[0029] Figure 6 FIG. 4 is a schematic structural diagram of a flexible circuit substrate according to an embodiment of the present invention.

[0030] Figure 7 FIG. 4 is a schematic structural diagram of a flexible circuit substrate according to a second embodiment of the present invention. DETAILED DESCRIPTION

[0031] The following will refer to the attached drawings to demonstrate the preferred embodiments of the present invention. In order to avoid blurring the content of the present invention, the following description also omits existing components, related materials, and related processing technologies. At the same time, in order to clearly illustrate the present invention, the components in the attached drawings may not be drawn according to the actual size or relative proportion.

[0032] Method for manufacturing flexible circuit substrate of the present invention

[0033] According to the first embodiment of the present invention, a method for manufacturing a flexible circuit substrate for carrying a chip comprises the following steps:

[0034] Step (a) providing a conductive copper layer having a wiring pattern on an insulating substrate;

[0035] Step (b) forming a first solder resist layer to partially cover the wiring pattern;

[0036] Step (c) forming a first tin layer on the conductive copper layer using the first solder mask as a shield;

[0037] Step (d) forming a second tin layer on the first tin layer using the first solder mask as a shield; and

[0038] Step (e) forms a second solder mask layer to partially cover the second tin layer and at least partially cover the first solder mask layer.

[0039] Step (a) provides a conductive copper layer with a wiring pattern on an insulating substrate.

[0040] Figure 1A FIG. 1 is a top view of a semi-finished flexible circuit substrate 10 of the present invention. Figure 1A A plurality of wiring patterns P composed of a conductive copper layer 110 are continuously formed on one surface of a film-belt-shaped insulating substrate 100 of a semi-finished soft circuit substrate 10. The insulating substrate 100 has a plurality of transmission holes 101 for transfer on the upper and lower sides. The conductive copper layer 110 (or wiring pattern P) defines a non-pin area Ps (the part framed by a dotted line), which will be covered by a solder mask later to protect the circuit. The area outside the non-pin area Ps of the wiring pattern P, namely the pin area, can be further divided into an inner pin area Ln, an outer pin area Lo, and a test pin area Lt as needed. The inner pin area Ln will be connected to the chip, the outer pin area Lo will be connected to an external circuit board or other electronic device, and the test pin area Lt is used to connect to a measuring instrument to detect the quality of the packaged chip. Figure 1B for Figure 1A The cross-sectional view of the area indicated by arrow 1B (i.e. one of the lines of the wiring pattern P). Figure 1B , it can be clearly understood that the conductive copper layer 110 is located on the insulating substrate 100. The insulating substrate 100 can use a soft material that is resistant to chemicals and heat, such as polyester, polyamide, polyimide, etc. The thickness of the insulating substrate 100 is generally 12μm to 85μm, preferably 20μm to 50μm. The conductive copper layer 110 with the wiring pattern P on the insulating substrate 100 is formed by the existing lithography method. The thickness of the conductive copper layer 110 is, for example, 2μm to 20μm, preferably 5μm to 12μm.

[0041] Step (b) forms a first solder resist layer to partially cover the wiring pattern.

[0042] refer to Figure 1A and Figure 2, forming a first solder mask 121 so that it at least partially covers the wiring pattern P, for example, covers a part or all of the non-pin area Ps. In a preferred embodiment, the first solder mask 121 only needs to be applied to certain specific areas of the non-pin area Ps, for example, only needs to be applied to the bending area generated during the back-end application of this flexible circuit substrate product. The actual position of this bending area varies depending on the characteristics of the back-end application product, wherein the area between the inner pin area Ln and the outer pin area Lo is a common bending area. Therefore, in a preferred embodiment of the present invention, the first solder mask 121 does not cover the non-pin area Ps between the test pin area Lt and the inner pin area Ln, but the present invention is not limited thereto. The present invention also has an embodiment in which the first solder mask 121 completely covers all non-pin areas Ps. This step can be completed by screen printing technology using existing epoxy resin (o-Cresol Novalac / Phenol / DGEBA) type ink or other suitable ink. The thickness of the first solder mask 121 can be in the range of 3μm to 15μm.

[0043] Step (c) forms a first tin layer on the conductive copper layer using the first solder mask as a shield.

[0044] refer to Figure 3 , a first tin layer 131 is formed on the conductive copper layer 110 with the first solder mask 121 as a shield. The first tin layer 131 is formed by the existing electroless plating (i.e. chemical plating) technology. For example, the semi-finished product formed in step (b) is immersed in a tin bath containing sulfuric acid, potassium persulfate, or tin fluoride borate tin plating solution for a predetermined period of time, then washed with water and blown dry, and then put into an oven for heat treatment. In this step, in addition to plating the first tin layer 131 on the surface of the conductive copper layer 110 not covered by the first solder mask 121, the tin plating solution can be further allowed to invade the conductive copper layer 110 under the first edge 121a of the first solder mask 121, thereby forming a structure in which the first edge 121a of the first solder mask 121 covers the first side 131a of the first tin layer 131. The thickness of the first tin layer 131 can be in the range of 0.02μm to 0.16μm, and the thickness of the first tin layer 131 in the preferred embodiment is 0.10μm.

[0045] Step (d): forming a second tin layer on the first tin layer using the first solder mask as a shield.

[0046] refer to Figure 4, using the first solder mask 121 as a shield to form a second tin layer 132 on the first tin layer 131. Preferably, there is no additional step of forming a solder mask between step (c) and step (d). The second tin layer 132 can be formed by existing electroless plating (i.e. chemical plating) technology as in step (c). For example, the semi-finished product formed in step (c) is immersed in a tin bath containing a tin plating solution of sulfuric acid, potassium persulfate, or tin borofluoride for a predetermined period of time, then washed with water and dried, and then put into an oven for heat treatment. The tin-copper alloy layer obtained by the first tin plating in step (c) will generate Cu3Sn through high temperature heat treatment, which can slow down the generation and diffusion rate of Cu6Sn5 of the tin layer generated by the second tin plating in step (d), thereby slowing down the loss rate of the pure tin layer, improving the eutectic bonding quality rate between the circuit and the chip, and avoiding the generation of tin whiskers. In this step, the tin plating liquid can be further allowed to intrude under the first edge 121a of the first solder mask 121, forming a structure in which the first edge 121a of the first solder mask 121 covers the second side 132a of the second tin layer 132. The thickness of the second tin layer 132 can be in the range of 0.12μm to 0.5μm, and the thickness of the second tin layer 132 in the preferred embodiment is 0.28μm. Because both steps (c) and (d) use electroless plating (i.e., chemical plating) technology, and both use the first solder mask 121 as a shield, in step (d), the first tin layer 131 will be pushed toward the area with high copper density by the second tin layer 132, so that the interface Iss between the first tin layer 131 and the second tin layer 132 is conformal to the interface Isc between the first tin layer 131 and the conductive copper layer 110.

[0047] Step (e) forms a second solder mask layer to partially cover the second tin layer and at least partially cover the first solder mask layer.

[0048] refer to Figure 5, forming a second solder mask 122 partially covering the second tin layer 132 and at least partially covering the first solder mask 121. Preferably, in this step, the second solder mask 122 is formed to at least cover the contact surface formed by the second tin layer 132 and the first solder mask 121 in step (d). In step (d), the first solder mask 121 is immersed in the tin bath, which may weaken the contact surface between the first solder mask 121 and the second tin layer 132. Therefore, covering this contact surface with the second solder mask 122 can prevent the solder mask from peeling off from the tin layer. This step can be completed by screen printing technology using existing epoxy resin (o-Cresol Novalac / Phenol / DGEBA type) type ink or other suitable ink. The thickness of the second solder mask 122 can be in the range of 3μm to 20μm. In this embodiment, the second solder mask 122 is printed on the entire non-pin area Ps so as to completely cover the first solder mask 121, but the present invention is not limited thereto. The present invention also includes an embodiment in which the second solder mask layer 122 only partially covers the first solder mask layer 121 (only covers the outer edge thereof) and partially covers the second tin layer 132 .

[0049] Structure of the flexible circuit substrate of the present invention

[0050] Also refer to Figure 1A and Figure 5 In the first embodiment, the flexible circuit substrate for carrying a chip of the present invention includes a conductive copper layer 110 having a wiring pattern P on an insulating substrate 100; a first tin layer 131 is located above the conductive copper layer 110; a second tin layer 132 is located above the first tin layer 131; a first solder mask layer 121 covers the conductive copper layer 110 not covered by the first tin layer 131 and the second tin layer 132, and the first solder mask layer 121 partially covers the second tin layer 132; and the second solder mask layer 122 partially covers the second tin layer 132 and at least partially covers the first solder mask layer 121.

[0051] In another embodiment, reference may be made to Figure 5 The present invention provides a flexible circuit substrate for carrying a chip, wherein the first solder mask layer 121 has a first edge 121 a contacting the second tin layer 132 .

[0052] In another embodiment, reference may be made to Figure 5 The present invention provides a flexible circuit substrate for carrying a chip, wherein the first tin layer 131 has a first longitudinal interface 131a contacting the conductive copper layer 110, the first solder mask layer 121 has a first edge 121a contacting the second tin layer 132, and the lateral distance X between the first longitudinal interface 131a and the first edge 121a is greater than the thickness of the first tin layer 131.

[0053] In another embodiment, reference may be made to Figure 5The present invention provides a flexible circuit substrate for carrying a chip, wherein the second tin layer 132 has a second longitudinal interface 132a contacting the first tin layer 131, and the first solder mask 121 covers the second longitudinal interface 132a.

[0054] In another embodiment, reference may be made to Figure 5 The present invention provides a flexible circuit substrate for carrying a chip, wherein the second tin layer 132 has a second longitudinal interface 132a contacting the first tin layer 131, the second solder mask 122 has a second edge 122a contacting the second tin layer 132, and the lateral distance Y between the second longitudinal interface 132a and the second edge 122a is greater than the thickness of the second tin layer 132.

[0055] In another embodiment, reference may be made to Figure 5 The present invention provides a flexible circuit substrate for carrying a chip, wherein the interface Iss between the first tin layer 131 and the second tin layer 132 is conformal to the interface Isc between the first tin layer 131 and the conductive copper layer 110 .

[0056] Figure 6 When the first tin layer 131 and the second tin layer 132 are considered as the tin layer 161, and the first solder mask layer 121 and the second solder mask layer 122 are considered as the solder mask layer 162, the structural characteristics of the flexible circuit substrate for carrying a chip of the present invention include a conductive copper layer 110 having a wiring pattern P disposed on an insulating substrate 100; a tin layer 161 is located above the conductive copper layer 110, wherein the conductive copper layer 110 has an exposed portion 163 not covered by the tin layer 161; and a solder mask layer 162 covers the exposed portion and partially covers the tin layer 161, wherein the tin layer 161 has a longitudinal interface 161a contacting the conductive copper layer 110, and the solder mask layer 162 has an edge 162a contacting the tin layer 161, wherein the lateral distance Z between the longitudinal interface 161a and the edge 162a is greater than the thickness of the tin layer 161. The thickness of the solder mask layer ranges from 6μm to 35μm. The thickness of the tin layer ranges from 0.14 μm to 0.66 μm. In addition, the present invention also has an embodiment in which only step (c) is performed without step (d). In this embodiment, the thickness of the tin layer ranges from 0.1 μm to 0.6 μm.

[0057] The present invention also has a second embodiment, which differs from the first embodiment in that step (a) further includes the step of "roughening the conductive copper layer before tinning" so that the conductive copper layer has a roughened copper surface, and the remaining steps are the same as the first embodiment. The roughening of the conductive copper layer can be accomplished using any suitable method. For example, after the patterned conductive copper layer 110 forms the wiring pattern P, the conductive copper layer (wiring pattern P) can be formed by treating the conductive copper layer with a chemical solution. In this embodiment, the chemical solution can be, for example, a potassium persulfate (K2S2O8) solution, with a suitable concentration of 30 to 40 g / L, a sulfuric acid or hydrochloric acid solution, with a suitable concentration of 20 to 30 g / L. The conductive copper layer (wiring pattern P) can be immersed in the chemical solution for 10 to 30 seconds at room temperature. The longer the contact time with the chemical solution, the greater the surface roughness. Figure 7 The schematic diagram of the structure of the second embodiment after the tin plating and solder mask layer are completed. Tin plating on the roughened copper surface will also cause the tin surface to produce a roughened structure similar to the roughened copper surface. As shown in the figure, the roughened conductive copper layer 110' has a roughened copper surface 701, and the first tin layer 131' and the second tin layer 132' formed subsequently have similar roughened surfaces, such as roughened tin surface 702 and roughened tin surface 703. As mentioned above, the roughened tin surface can provide a larger surface area. When the flexible circuit substrate is externally connected to other electronic components, the roughened tin surface in the external pin area can increase the bonding area with the anisotropic conductive film (ACF), thereby making the flexible circuit substrate and the electronic device more closely fit. Preferably, the surface roughness Rz range of the roughened tin surface 703 of the second tin layer 132' is: 0.045μm~0.5μm, preferably in the range of 0.06μm~0.35μm, and preferably in the range of 0.1μm~0.3μm. The surface roughness Rz is measured by cutting the tin-plated sample into a size of about 5cm×5cm and measuring it with a non-contact shape measurement laser microscope (KEYENCE Taiwan Keynes Model VK-X100). The measurement uses a laser spot diameter of about 1μm, an objective magnification setting of 10X, a field of view of 1350μm x 1012μm, and an objective magnification setting of 20X, a field of view of 675μm x 506μm, a scanning time of about 10 to 20 seconds, and a line pitch setting of 2μm.

[0058] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of the claims of the present invention; any other equivalent changes or modifications that do not depart from the spirit disclosed by the present invention should be included in the scope of the following claims.

[0059]

Explanation of symbols

[0060] 10 Semi-finished products of flexible circuit substrate

[0061] 100 Insulation substrate

[0062] 101 Transmission hole

[0063] 110 Conductive copper layer

[0064] P Wiring pattern

[0065] 1B Reference Figure

[0066] Lo outer pin area

[0067] Ps Non-pin area

[0068] Ln inner pin area

[0069] Lt test pin area

[0070] 121 First solder mask

[0071] 121a First Edge

[0072] 131 First Tin Layer

[0073] 131a First side

[0074] Iss interface

[0075] Isc interface

[0076] 132 Second Tin Layer

[0077] 122 Second solder mask

[0078] 122a The Second Edge

[0079] 132a Second side

[0080] X horizontal distance

[0081] Y horizontal distance

[0082] 161 Tin layer

[0083] 161a Vertical interface

[0084] 162 Solder mask

[0085] 162a Edge

[0086] 163 Exposed Part

[0087] Z lateral distance

[0088] 110' Conductive copper layer

[0089] 132' Second tin layer

[0090] 131' First tin layer

[0091] 701 Roughened copper surface

[0092] 702 Roughened tin surface

[0093] 703 Roughened tin surface

Claims

1. A method for manufacturing a flexible circuit substrate for carrying a chip, comprising the following steps in sequence: (a) providing a conductive copper layer having a wiring pattern on an insulating substrate; (b) forming a first solder resist layer to partially cover the wiring pattern; (c) forming a first tin layer on the conductive copper layer using the first solder resist layer as a shield; (d) forming a second tin layer on the first tin layer using the first solder resist layer as a shield; and (e) forming a second solder resist layer to partially cover the second tin layer and at least partially cover the first solder resist layer.

2. The manufacturing method according to claim 1, wherein: There is no step of forming a solder resist layer between step (c) and step (d).

3. The manufacturing method according to claim 1, wherein: Through the step (d), the first solder resist layer at least partially covers the second tin layer.

4. The manufacturing method according to claim 1, wherein: Through the step (d), the interface between the first tin layer and the second tin layer is conformal to the interface between the first tin layer and the conductive copper layer.

5. The manufacturing method according to claim 1, wherein: The wiring pattern has a test area, an inner pin area and an outer pin area. In the step (b), the first solder resist layer does not cover the wiring pattern between the test area and the inner pin area.

6. The manufacturing method according to claim 1, wherein: The step (c) or the step (b) further comprises a heat treatment step.

7. The manufacturing method according to claim 1, wherein: In the step (e), the second solder resist layer does not completely cover the first solder resist layer.

8. The manufacturing method according to claim 1, wherein: The step (a) further includes roughening the conductive copper layer so that the conductive copper layer has a roughened copper surface.

9. The manufacturing method according to claim 8, wherein: The roughened copper surface is formed by treating the conductive copper layer with a chemical solution.

10. The manufacturing method according to claim 8, wherein: The second tin layer has a roughened tin surface, and the surface roughness of the roughened tin surface ranges from 0.045 μm to 0.5 μm.

11. The manufacturing method according to claim 8, wherein: The second tin layer has a roughened tin surface, and the surface roughness of the roughened tin surface ranges from 0.06 μm to 0.35 μm.

12. The manufacturing method according to claim 8, wherein: The second tin layer has a roughened tin surface, and the surface roughness of the roughened tin surface ranges from 0.1 μm to 0.3 μm.

13. A flexible circuit substrate for carrying a chip, comprising: A conductive copper layer having a wiring pattern is on an insulating substrate; a first tin layer located above the conductive copper layer; a second tin layer located above the first tin layer; A first solder resist layer covers the conductive copper layer not covered by the first tin layer and the second tin layer, and the first solder resist layer partially covers the second tin layer; and A second solder resist layer partially covers the second tin layer and at least partially covers the first solder resist layer.

14. The flexible circuit substrate according to claim 13, wherein: The first solder resist layer has a first edge contacting the second tin layer.

15. The flexible circuit substrate according to claim 13, wherein: The first tin layer has a first longitudinal interface contacting the conductive copper layer, the first solder resist layer has a first edge contacting the second tin layer, and the lateral distance between the first longitudinal interface and the first edge is greater than the thickness of the first tin layer.

16. The flexible circuit substrate according to claim 13, wherein: The second tin layer has a second longitudinal interface that contacts the first tin layer, and the first solder resist layer covers the second longitudinal interface.

17. The flexible circuit substrate according to claim 13, wherein: The second tin layer has a second longitudinal interface contacting the first tin layer, the second solder resist layer has a second edge contacting the second tin layer, and the lateral distance between the second longitudinal interface and the second edge is greater than the thickness of the second tin layer.

18. The flexible circuit substrate according to claim 13, wherein: The interface between the first tin layer and the second tin layer conforms to the interface between the first tin layer and the conductive copper layer.

19. The flexible circuit substrate according to claim 13, wherein: The wiring pattern has a test pin area, an inner pin area and an outer pin area, and the first solder resist layer does not cover the wiring pattern between the test pin area and the inner pin area.

20. The flexible circuit substrate according to claim 13, wherein: The conductive copper layer has a roughened copper surface.

21. The flexible circuit substrate according to claim 13, wherein: The second tin layer has a roughened tin surface, and the surface roughness of the roughened tin surface ranges from 0.045 μm to 0.5 μm.

22. The flexible circuit substrate according to claim 13, wherein: The second tin layer has a roughened tin surface, and the surface roughness of the roughened tin surface ranges from 0.06 μm to 0.35 μm.

23. The flexible circuit substrate according to claim 13, wherein: The second tin layer has a roughened tin surface, and the surface roughness of the roughened tin surface ranges from 0.1 μm to 0.3 μm.

24. A flexible circuit substrate for carrying a chip, comprising: A conductive copper layer having a wiring pattern is disposed on an insulating substrate; a tin layer is located above the conductive copper layer, wherein the conductive copper layer has an exposed portion not covered by the tin layer; and A solder mask layer covers the exposed portion and partially covers the tin layer, The tin layer has a longitudinal interface contacting the conductive copper layer, and the solder mask layer has an edge contacting the tin layer, wherein the lateral distance between the longitudinal interface and the edge is greater than the thickness of the tin layer.

25. The flexible circuit substrate according to claim 24, wherein: The thickness of the solder mask ranges from 6 μm to 35 μm.

26. The flexible circuit substrate according to claim 24, wherein: The thickness of the tin layer ranges from 0.1 μm to 0.6 μm.

27. The flexible circuit substrate according to claim 24, wherein: The tin layer has a roughened tin surface, and the surface roughness of the roughened tin surface ranges from 0.045 μm to 0.5 μm.

28. The flexible circuit substrate according to claim 24, wherein: The tin layer has a roughened tin surface, and the surface roughness of the roughened tin surface ranges from 0.06 μm to 0.35 μm.

29. The flexible circuit substrate according to claim 24, wherein: The tin layer has a roughened tin surface, and the surface roughness of the roughened tin surface ranges from 0.1 μm to 0.3 μm.

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