Anti-fuse memory cell and method for forming the same

Abstract

An anti-fuse memory cell and a method for forming the same, the anti-fuse memory cell comprising: a semiconductor substrate; an active region located in the semiconductor substrate, the active region comprising an interconnection region and at least two lower electrode regions, the lower electrode regions being in contact with at least a portion of the interconnection region; a gate dielectric layer covering the surface of all lower electrode regions; and an upper electrode layer located on the gate dielectric layer. The programming voltage of the anti-fuse memory cell of the present invention is reduced.

Description

Technical Field

[0001] The present invention relates to the field of memory, and in particular to a fuse storage unit and a forming method thereof. Background Art

[0002] Antifuse is a very important programmable interconnect unit. Semiconductor devices based on antifuse have very superior performance, which is mainly reflected in the following aspects: (1) It is non-volatile. The antifuse is programmed by programming voltage. After programming, the antifuse changes from one state to another. This state change is irreversible, and the changed programming state can be permanently saved. (2) It has high reliability. Studies have shown that the reliability of antifuse devices is one order of magnitude higher than that of application-specific integrated circuits. (3) It is 100% testable. Antifuse exhibits two completely different electrical characteristics before and after programming. The use of test circuits can achieve full coverage testing of large-scale antifuse arrays. (4) It is small in size, fast in speed, and low in power consumption. The use of advanced semiconductor process processing methods can make the antifuse extremely small, thereby effectively reducing the parasitic capacitance of the antifuse itself. On the other hand, after programming, the antifuse resistance can be as small as tens of ohms. Therefore, antifuse devices are not only fast, but also low in power consumption.

[0003] The antifuse is non-conductive when not activated, but becomes a conductor after activation (breakdown, metal diffusion, amorphous silicon becoming polysilicon, etc.), forming an electrical connection. It can selectively allow two devices or chips that were originally electrically isolated to be electrically connected, and can provide different resistance values ​​for performing logic operations.

[0004] The basic structure of the existing anti-fuse unit is a sandwich structure, including upper and lower electrodes and an anti-fuse dielectric layer located between the upper and lower electrodes. The more mature anti-fuse structures currently include: ONO (silicon oxide-silicon nitride-silicon oxide) electric fuse, amorphous silicon anti-fuse and gate oxide anti-fuse. Among them, since the formation process of ONO electric fuse and amorphous silicon anti-fuse is incompatible with the existing CMOS process, the most popular anti-fuse structure is gate oxide anti-fuse, which uses the substrate, gate oxide layer and gate electrode as the sandwich structure of the anti-fuse. However, the programming voltage of the existing gate oxide anti-fuse is still relatively large. Summary of the invention

[0005] The technical problem to be solved by the present invention is how to reduce the programming voltage of the existing gate oxide layer anti-fuse.

[0006] The present invention provides an anti-fuse storage unit, comprising:

[0007] Semiconductor substrate;

[0008] An active region located in the semiconductor substrate, the active region comprising an interconnection region and at least two lower electrode regions, the lower electrode region being in contact with at least a portion of the interconnection region;

[0009] A gate dielectric layer covering all surfaces of the lower electrode region;

[0010] An upper electrode layer is located on the gate dielectric layer.

[0011] Optionally, the contact mode between the lower electrode region and the interconnection region is straight-line edge contact, curved-line contact or surrounding contact.

[0012] Optionally, a shallow trench isolation structure is provided in the semiconductor substrate around the active area and in the semiconductor substrate between adjacent lower electrode areas.

[0013] Optionally, a portion of the shallow trench isolation structure that contacts an edge of the top surface of the lower electrode region has a downward depression, and other portions of the shallow trench isolation structure are not higher than the top surface of the lower electrode region.

[0014] Optionally, the gate dielectric layer and the upper electrode layer at least cover a portion of the shallow trench isolation region, and the gate dielectric layer and the upper electrode layer fill the recess, so that the upper electrode layer has a downward convex region.

[0015] Optionally, it also includes: a connection area located between adjacent lower electrode areas and connecting the adjacent lower electrode areas, the connection area is made of the same material as the lower electrode area, and the gate dielectric layer and the upper electrode layer cover the surface of the connection area and the lower electrode area.

[0016] Optionally, the method further includes: a first contact plug connected to the interconnection region, and a second contact plug connected to the upper electrode layer, wherein the shortest distance between the first contact plug and the upper electrode layer is not less than 60 nm.

[0017] Optionally, a dielectric layer covers the upper electrode layer and the surface of the interconnection area, wherein the dielectric layer has a first through hole and a second through hole, wherein the bottom of the first through hole exposes the surface of the interconnection area, the first contact plug is located in the first through hole, the bottom of the second through hole exposes the surface of the upper electrode layer, and the second contact plug is located in the second through hole.

[0018] Optionally, when programming the anti-fuse memory cell, a programming voltage is applied to the first contact plug and the second contact plug, and the programming voltage causes a gate dielectric layer between the upper electrode layer and the lower electrode region to be broken down.

[0019] Optionally, the lower electrode region is in a strip, ring or irregular shape.

[0020] The present invention also provides a method for forming an anti-fuse memory cell, comprising:

[0021] providing a semiconductor substrate;

[0022] an active region in the semiconductor substrate, the active region comprising an interconnection region and at least two lower electrode regions, the lower electrode region being in contact with at least a portion of the interconnection region;

[0023] forming a gate dielectric layer covering all surfaces of the lower electrode region;

[0024] An upper electrode layer is formed on the gate dielectric layer.

[0025] Optionally, the contact mode between the lower electrode region and the interconnection region is straight-line edge contact, curved-line contact or surrounding contact.

[0026] Optionally, a shallow trench isolation structure is formed in the semiconductor substrate around the active area and in the semiconductor substrate between adjacent lower electrode areas.

[0027] Optionally, a portion of the shallow trench isolation structure that contacts an edge of the top surface of the lower electrode region has a downward depression, and other portions of the shallow trench isolation structure are not higher than the top surface of the lower electrode region.

[0028] Optionally, the gate dielectric layer and the upper electrode layer at least cover a portion of the shallow trench isolation region, and the gate dielectric layer and the upper electrode layer fill the recess, so that the upper electrode layer has a downward convex region.

[0029] Optionally, it also includes: a connection area located between adjacent lower electrode areas and connecting the adjacent lower electrode areas, the connection area is made of the same material as the lower electrode area, and the gate dielectric layer and the upper electrode layer cover the surface of the connection area and the lower electrode area.

[0030] Optionally, it also includes: forming a dielectric layer covering the surface of the upper electrode layer and the interconnection area; forming a first through hole and a second through hole in the dielectric layer, wherein the bottom of the first through hole exposes the surface of the interconnection area, and the bottom of the second through hole exposes the surface of the upper electrode layer; forming a first contact plug in the first through hole, and forming a second contact plug in the second through hole, wherein the shortest distance between the first contact plug and the upper electrode layer is not less than 60nm.

[0031] Optionally, when programming the anti-fuse memory cell, a programming voltage is applied to the first contact plug and the second contact plug, and the programming voltage causes a gate dielectric layer between the upper electrode layer and the lower electrode region to be broken down.

[0032] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0033] The anti-fuse memory cell of the present invention has an active area including an interconnection area and at least two lower electrode areas, wherein the lower electrode area is in contact with at least a portion of the interconnection area; a gate dielectric layer covers all surfaces of the lower electrode areas; and an upper electrode layer is located on the gate dielectric layer. That is, the anti-fuse memory cell of the present invention has a smaller lower electrode area under the same design size, so that the boundary length of the overlapping area between the upper electrode layer and the lower electrode area is increased, thereby enhancing the warping effect or kink effect (KinkEffect) of the boundary area (the area corresponding to the boundary of the overlapping area between the upper electrode layer and the lower electrode area), so that more charges are gathered in the boundary area, thereby enhancing the electric field in the boundary area. When programming is performed, the gate dielectric layer between the lower electrode area and the upper electrode layer is easily broken down, thereby effectively reducing the programming voltage of the anti-fuse memory cell.

[0034] Furthermore, a portion of the shallow trench isolation structure in contact with the edge of the top surface of the lower electrode region has a downward depression, and other portions of the shallow trench isolation structure are not higher than the top surface of the lower electrode region. The function of the depression is: when the gate dielectric layer and the upper electrode layer are formed to fill the depression, the upper electrode layer has a downward convex area, and when a programming voltage is applied to the upper electrode layer through the second contact plug, the electric field will gather toward the downward convex area, so that the electric field in the boundary area (the area corresponding to the boundary of the overlapping area of ​​the lower electrode region, the upper electrode layer and the shallow trench isolation structure) is further enhanced (warping effect or kink effect (Kink effect) The gate dielectric layer between the lower electrode region and the upper electrode layer is more easily broken down during programming, thereby further reducing the programming voltage of the anti-fuse memory cell; and the coordination of the lower convex area of ​​the upper electrode layer and the raised corners of the lower electrode region (the lower convex area of ​​the upper electrode layer and the raised corners of the lower electrode region are both easy to accumulate charges and enhance the electric field) makes the gate dielectric layer between the lower electrode region and the upper electrode layer further easy to break down, thereby further reducing the programming voltage of the anti-fuse memory cell.

[0035] Furthermore, between adjacent lower electrode regions, there is also a connection region that connects adjacent lower electrode regions. The connection region is made of the same material as the lower electrode region, and the gate dielectric layer and the upper electrode layer formed cover the surfaces of the connection region and the lower electrode region, so that the boundary length of the overlapping area between the upper electrode layer and the lower electrode region and the connection region is further increased, and thus the warping effect or kink effect (Kink Effect) of the boundary region (the region corresponding to the boundary of the overlapping area between the upper electrode layer and the lower electrode region and the connection region) is further enhanced, so that more charges are gathered in the boundary region, thereby further enhancing the electric field in the boundary region.

[0036] The method for forming the anti-fuse memory unit of the present invention has a simple forming process, and the formed anti-fuse memory unit can reduce the programming voltage of the anti-fuse memory unit while maintaining a high degree of integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1-11 It is a structural schematic diagram of the formation process of the anti-fuse memory unit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0038] As mentioned in the background art, the existing gate oxide anti-fuse still requires a relatively large programming voltage during programming.

[0039] Research has found that, in one embodiment, the gate oxide anti-fuse structure generally includes a semiconductor substrate, an active area located in the semiconductor substrate, the active area including an interconnection area and a lower electrode area connected to the interconnection area; a gate oxide layer located on the lower electrode area; an upper electrode layer located on the gate oxide layer; a dielectric layer covering the upper electrode layer and the semiconductor substrate; a first contact plug and a second contact plug located in the dielectric layer, the first contact plug being electrically connected to the interconnection area, and the second contact plug being electrically connected to the upper electrode layer. When programming the gate oxide anti-fuse structure, a programming voltage is applied to the first contact plug and the second contact plug, and the gate oxide layer is broken down under the action of the programming voltage. Since the overlapping area or boundary length of the lower electrode area and the upper electrode layer of the aforementioned gate oxide anti-fuse structure is fixed, it is difficult to reduce the programming voltage, so that the programming voltage is still large during programming, and the programming process may cause reliability problems (for example, the programming high voltage overshoots the high voltage of other parts of the circuit).

[0040] To this end, the present invention provides an anti-fuse memory cell and a method for forming the same, so as to reduce the programming voltage of the anti-fuse memory cell.

[0041] In order to make the above-mentioned objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present invention in detail, for the sake of convenience, the schematic diagrams will not be partially enlarged according to the general proportion, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0042] Figure 1-11 It is a structural schematic diagram of the formation process of the anti-fuse memory unit according to an embodiment of the present invention.

[0043] refer to Figure 1-Figure 4 , Figure 2 for Figure 1 A top view of the structure. Figure 3 for Figure 1 Schematic diagram of the cross-sectional structure along the cutting line AB. Figure 4for Figure 1 A schematic cross-sectional structure diagram along the cutting line CD direction provides a semiconductor substrate 201; an active area 205 in the semiconductor substrate 201, the active area 205 includes an interconnection area 204 and at least two lower electrode areas 203, and the lower electrode area 203 is in contact with at least a portion of the interconnection area 204.

[0044] The material of the semiconductor substrate 201 may be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it may also be silicon on insulator (SOI), germanium on insulator (GOI); or it may also be other materials, such as III-V group compounds such as gallium arsenide. In this embodiment, the material of the semiconductor substrate 201 is silicon.

[0045] The semiconductor substrate 201 has an active region 205, and part of the active region 205 is used as the lower electrode region of the anti-fuse memory cell, and part of it is used as the interconnection region. Impurity ions are doped in the active region 205, and the impurity ions are P-type impurity ions or N-type impurity ions. The P-type impurity ions are one or more of boron ions, gallium ions, or indium ions, and the N-type impurity ions are one or more of phosphorus ions, arsenic ions, or antimony ions. In this embodiment, only one active region 205 in the semiconductor substrate 201 is used as an example for description. In other embodiments, the number of the active regions 205 is greater than one.

[0046] A shallow trench isolation structure 202 is formed in the semiconductor substrate 201 around the active area 205 and in the semiconductor substrate between adjacent lower electrode areas 203. The shallow trench isolation structure 202 is used to isolate different active areas 205 and adjacent lower electrode areas 203 to prevent electrical connection between different active areas 205. The material of the shallow trench isolation structure 202 can be one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0047] In one embodiment, the formation process of the shallow trench isolation structure 202 includes: forming a mask layer on the semiconductor substrate 201, the mask layer having an opening exposing the surface of the semiconductor substrate; etching the semiconductor substrate 201 along the opening to form a trench in the semiconductor substrate 201; forming an isolation material layer on the surface of the trench and the active area, the isolation material layer filling the trench; planarizing and removing the isolation material layer on the surface of the active area to form a shallow trench isolation structure 202 in the trench, and the planarization can be carried out using a chemical mechanical polishing process.

[0048] The portion of the semiconductor substrate surrounded by the shallow trench isolation structure 202 serves as an active area 205 .

[0049] In this embodiment, the active area 205 includes an interconnection area 204 and at least two lower electrode areas 203. The at least two lower electrode areas 203 serve as lower electrodes of the anti-fuse storage unit. The interconnection area 204 is subsequently connected to an interconnection line for applying a programming voltage. Specifically, the interconnection area 204 is subsequently used to connect to the first contact plug.

[0050] The number of the lower electrode regions 203 is greater than or equal to 2, and subsequently a gate dielectric layer is formed on the plurality of (≥2) lower electrode regions 203 and an upper electrode layer is formed on the gate dielectric layer on the plurality of lower electrode regions, that is, the anti-fuse memory cell in the present application is formed with the same design size, so that the boundary length of the overlapping area between the upper electrode layer and the plurality of lower electrode regions 203 is increased (refer to Fig. 9 The position of the thick solid line frame in the middle), thereby enhancing the warping effect or kink effect (KinkEffect) of the boundary area (the area corresponding to the boundary of the overlapping area between the upper electrode layer and several lower electrode areas 203), so that more charges are gathered in the boundary area, and then the electric field in the boundary area is enhanced. Therefore, when programming is performed, the gate dielectric layer between the lower electrode area 203 and the upper electrode layer is easily broken down, thereby effectively reducing the programming voltage of the anti-fuse memory cell.

[0051] The contact mode between the lower electrode region 203 and the interconnection region 204 is straight-line edge contact, curved-line contact or surrounding contact. The straight-line edge contact means that the contact interface between the lower electrode region 203 and the interconnection region 204 is straight-line, the curved-line contact means that the contact interface between the lower electrode region 203 and the interconnection region 204 is curved, and the surrounding contact means that the lower electrode region 203 is annular, and both ends of the annular shape are in contact with the interconnection region 204.

[0052] In one embodiment, the shape of the lower electrode region 203 may be a strip, a ring, or an irregular shape. The strip may be a rectangle or a square, and the irregular shape means that the shape of the lower electrode region 203 is a non-regular polygon. When the lower electrode region 203 is an irregular shape, when a gate dielectric layer and an upper electrode layer located on the gate dielectric layer are subsequently formed on the lower electrode region 203, the boundary length of the overlapping region between the lower electrode region 203 and the upper electrode layer is further increased, so that the warping effect or kink effect (KinkEffect) of the boundary region (the region corresponding to the boundary of the overlapping region between the lower electrode region 203 and the upper electrode layer) is further enhanced, so that more charges are gathered in the boundary region, thereby further enhancing the electric field in the boundary region, and when programming is performed, the gate dielectric layer between the lower electrode region 203 and the upper electrode layer is more easily broken down, thereby further reducing the programming voltage of the anti-fuse memory cell. In addition, when the lower electrode region 203 is of irregular shape, the irregular area on the semiconductor substrate can be fully utilized for the formation process of the anti-fuse memory unit (the regular area is used to form other devices of the integrated circuit, such as transistors, etc.), which can effectively improve the integration of the integrated circuit.

[0053] In one embodiment, please refer to Figure 3 and Figure 4 When forming the shallow trench isolation structure 202, the portion of the shallow trench isolation structure 202 that contacts the edge of the top surface of the lower electrode region 203 forms a downward recess 216, and the other portions of the shallow trench isolation structure 202 are not higher than the top surface of the lower electrode region 203, and can be flush with or lower than the top surface of the lower electrode region 203. In a specific embodiment, the recess 216 can be formed when the shallow trench isolation structure 202 is formed, when the isolation material layer is planarized by a chemical mechanical polishing process, or after the isolation material layer is planarized by a chemical mechanical polishing process, it is formed by an etching process.

[0054] The function of the recess 216 is as follows: when the gate dielectric layer and the upper electrode layer are subsequently formed to fill the recess 216, the upper electrode layer has a downward convex area. When a programming voltage is applied to the upper electrode layer through the second contact plug, the electric field will gather toward the downward convex area, thereby further enhancing the electric field in the boundary area (the area corresponding to the boundary of the overlapping area of ​​the lower electrode area 203, the upper electrode layer and the shallow trench isolation structure 202) (the warping effect or the kink effect (Kink Effect) will be further enhanced). When programming is performed, the gate dielectric layer between the lower electrode area 203 and the upper electrode layer is more easily broken down, thereby further reducing the programming voltage of the anti-fuse memory cell; and the coordination of the lower convex area of ​​the upper electrode layer and the raised corners of the lower electrode area 203 (the lower convex area of ​​the upper electrode layer and the raised corners of the lower electrode area 203 are both easy to gather charges and enhance the electric field), so that the gate dielectric layer between the lower electrode area 203 and the upper electrode layer is further easily broken down, thereby further reducing the programming voltage of the anti-fuse memory cell.

[0055] In one embodiment, when the lower electrode region 203 is formed, a connection region connecting adjacent lower electrode regions 203 is also formed between adjacent lower electrode regions, and the connection region is made of the same material as the lower electrode region 203. The gate dielectric layer and the upper electrode layer formed subsequently cover the surfaces of the connection region and the lower electrode region, so that the boundary length of the overlapping area between the upper electrode layer and the lower electrode region 203 and the connection region is further increased, and thus the warping effect of the boundary region (the region corresponding to the boundary of the overlapping area between the upper electrode layer and the lower electrode region 203 and the connection region) is further enhanced, so that more charges are gathered in the boundary region, thereby further enhancing the electric field in the boundary region.

[0056] In one embodiment, the active region 205 may be formed simultaneously with other active regions used to form other devices (such as transistors, memories).

[0057] refer to Figure 5 and Figure 6 , Figure 5 exist Figure 3 Based on Figure 6 exist Figure 4 On the basis of this, a gate dielectric layer 206 covering the surface of all the lower electrode regions 203 is formed.

[0058] In this embodiment, the gate dielectric layer 206 not only covers the surface of the lower electrode region 203, but also covers at least a portion of the surface of the shallow trench isolation structure. In one embodiment, the gate dielectric layer 206 is also formed on the sidewall and bottom surface of the recess 216, and the gate dielectric layer 206 does not completely fill the recess 216.

[0059] In one embodiment, the gate dielectric layer 206 is made of silicon oxide, and the formation process includes thermal oxidation or deposition process.

[0060] refer to Figure 7 , Figure 8 and Fig. 9 , Figure 7 exist Figure 5 Based on Figure 8 exist Figure 6 Based on Fig. 9 This is a top view after the upper electrode layer is formed. An upper electrode layer 207 is formed on the gate dielectric layer 206 .

[0061] The upper electrode layer 207 serves as the upper electrode of the anti-fuse memory cell. The upper electrode layer 207 covers all the lower electrode regions 203. Therefore, in the case of the same design size, the anti-fuse memory cell in the present application has a plurality of smaller lower electrode regions 203 formed, so that the boundary length of the overlapping area between the upper electrode layer 207 and the lower electrode region 203 increases (see Fig. 9 The position of the thick solid line frame in the middle), thereby enhancing the warping effect or kink effect (Kink Effect) of the boundary area (the area corresponding to the boundary of the overlapping area of ​​the upper electrode layer 207 and the lower electrode area 203), so that more charges are gathered in the boundary area, thereby enhancing the electric field in the boundary area. When programming, the gate dielectric layer between the lower electrode area 203 and the upper electrode layer is easily broken down, thereby effectively reducing the programming voltage of the anti-fuse memory cell.

[0062] In one embodiment of the present invention, the upper electrode layer 207 is not only located above the lower electrode area 203, but also located above the shallow trench isolation structure 202 around the lower electrode area 203. The upper electrode layer 207 also fills the recess so that the upper electrode layer 207 has a downward convex area 217. The upper electrode layer 207 can be formed by deposition and etching processes.

[0063] refer to Fig.10 and Fig.11 , Fig.10 exist Figure 7 On the basis of, a dielectric layer 208 is formed to cover the upper electrode layer 207 and the surface of the interconnection area 204; a first through hole and a second through hole are formed in the dielectric layer 208, the bottom of the first through hole exposes the surface of the interconnection area 204, and the bottom of the second through hole exposes the surface of the upper electrode layer 207; a first contact plug 212 is formed in the first through hole, and a second contact plug 213 is formed in the second through hole.

[0064] The first contact plug 212 and the second contact plug 213 are used to apply a programming voltage to the first contact plug 212 and the second contact plug 213 when programming the anti-fuse memory cell. The programming voltage causes the gate dielectric layer 206 between the upper electrode layer 207 and the lower electrode region 203 to be broken down. Before and after the gate dielectric layer 206 is broken down, the resistance between the upper electrode layer 207 and the lower electrode region 203 changes greatly. Before the gate dielectric layer 206 is broken down, the upper electrode layer 207 and the lower electrode region 203 present a high resistance state. After the gate dielectric layer 206 is broken down, the upper electrode layer 207 and the lower electrode region 203 present a low resistance state. Therefore, data "1" or "0" is stored according to whether the gate dielectric layer 206 is broken down.

[0065] In one embodiment, the formation process of the first contact plug 212 includes: forming a dielectric layer 208 on the upper electrode layer 207. The dielectric layer 208 can be formed by a deposition process. The material of the dielectric layer 208 can be SiO 2 , SiN, SiON, SiCN, SiC, low-K (dielectric constant) or ultra-low-K material; etching the dielectric layer 208 to form a first through hole 209 in the dielectric layer 208, wherein the bottom of the first through hole 209 exposes the surface of the interconnection region 204, and the etching can adopt anisotropic dry etching, such as plasma etching process; forming a first contact plug 212 in the first through hole, and the specific process includes: forming a metal layer in the first through hole and on the surface of the dielectric layer 208, the metal layer fills the first through hole, planarizing and removing the metal layer above the surface of the dielectric layer 208, and forming a first metal plug 212 in the first through hole.

[0066] The material of the first metal plug 212 is metal, and the metal may be one or more of W, Al, Cu, Ti, Ta, and Co.

[0067] In one embodiment, the shortest distance between the first contact plug 212 and the upper electrode layer 207 is not less than 60 nm, so that no leakage current exists between the first contact plug 212 and the upper electrode 207 .

[0068] In one embodiment, before forming the first contact plug 212, a diffusion barrier layer is formed on the sidewall of the first through hole 209, and the diffusion barrier layer is used to prevent the metal in the first contact plug 212 from diffusing outward. The diffusion barrier layer can be a double-layer stacked structure of a TiN layer and a Ti layer or a double-layer stacked structure of a TaN layer and a Ta layer.

[0069] In one embodiment, the formation process of the second contact plug 213 includes: etching the dielectric layer 208 to form a second through hole in the dielectric layer 208, wherein the bottom of the second through hole exposes a portion of the surface of the upper electrode layer 207; forming the second contact plug 213 in the second through hole, wherein the material of the second contact plug 213 is metal.

[0070] The steps of forming the first contact plug 212 and the second contact plug 213 can be performed separately or simultaneously. When the steps of forming the first contact plug 212 and the second contact plug 213 are performed simultaneously (i.e., when forming the first through hole, the second through hole can be formed simultaneously, and then a metal layer is formed in the first through hole and the second through hole and on the surface of the dielectric layer simultaneously, and then the metal layer on the surface of the dielectric layer 208 is removed by planarization, and the first contact plug 212 is formed in the first through hole, and the second contact plug 213 is formed in the second through hole), in order to prevent the upper electrode layer 207 at the bottom of the second through hole from being further etched when etching the first through hole, an etching stop layer is formed on the surface of the upper electrode layer 207 at a position corresponding to the second through hole 210 before forming the dielectric layer 208.

[0071] The embodiment of the present invention also provides an anti-fuse storage unit, please refer to Figure 7-9 ,include

[0072] Semiconductor substrate 201;

[0073] An active region 205 located in the semiconductor substrate 201, wherein the active region 205 includes an interconnection region 204 and at least two lower electrode regions 203, wherein the lower electrode region 203 is in contact with at least a portion of the interconnection region 204;

[0074] A gate dielectric layer 206 covering all surfaces of the lower electrode region 203;

[0075] An upper electrode layer 207 is located on the gate dielectric layer 206 .

[0076] Specifically, the number of the lower electrode regions 203 is greater than or equal to 2, and the contact mode between the lower electrode regions 203 and the interconnection regions 204 is straight-line edge contact, curved-line contact, or surrounding contact.

[0077] A shallow trench isolation structure 202 is provided in the semiconductor substrate 201 around the active area 205 and in the semiconductor substrate between adjacent lower electrode areas 203 .

[0078] In one embodiment, a portion of the shallow trench isolation structure 202 that contacts the edge of the top surface of the lower electrode region 203 has a downward depression, and other portions of the shallow trench isolation structure 202 are not higher than the top surface of the lower electrode region 203. The gate dielectric layer 206 and the upper electrode layer 207 at least cover a portion of the shallow trench isolation region 202, and the gate dielectric layer 206 and the upper electrode layer 207 fill the depression, so that the upper electrode layer 207 has a downward convex area 217.

[0079] In one embodiment, it also includes: a connection area located between adjacent lower electrode areas 203 to connect adjacent lower electrode areas 203, the connection area is made of the same material as the lower electrode area, and the gate dielectric layer 206 and the upper electrode layer 207 cover the surface of the connection area and the lower electrode area.

[0080] In one embodiment, reference Fig.11 , further comprising: a first contact plug 212 connected to the interconnection region 204, and a second contact plug 213 connected to the upper electrode layer 207, wherein the shortest distance between the first contact plug and the upper electrode layer is not less than 60 nm.

[0081] It also includes: a dielectric layer 208 covering the upper electrode layer 207 and the surface of the interconnection area 204, the dielectric layer 208 having a first through hole and a second through hole, the bottom of the first through hole exposing the surface of the interconnection area 204, the first contact plug 212 is located in the first through hole, the bottom of the second through hole exposes the surface of the upper electrode layer 207, and the second contact plug 213 is located in the second through hole.

[0082] When programming the anti-fuse memory cell, a programming voltage is applied to the first contact plug 212 and the second contact plug 213 , and the programming voltage causes the gate dielectric layer 206 between the upper electrode layer 207 and the lower electrode region 203 to be broken down.

[0083] It should be noted that the limitations or descriptions of the same or similar structures in this embodiment as those in the aforementioned embodiments are not repeated in this embodiment. For details, please refer to the limitations or descriptions of the corresponding parts in the aforementioned anti-fuse memory unit formation process embodiment.

[0084] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. An anti-fuse memory cell, characterized in that: include: Semiconductor substrate; An active region located in the semiconductor substrate, the active region comprising an interconnection region and at least two lower electrode regions, the lower electrode region being in contact with at least a portion of the interconnection region; A gate dielectric layer covering all surfaces of the lower electrode region; An upper electrode layer is located on the gate dielectric layer; a shallow trench isolation structure is provided in the semiconductor substrate around the active area and in the semiconductor substrate between adjacent lower electrode areas, and the portion of the shallow trench isolation structure that contacts the edge of the top surface of the lower electrode area has a downward depression, and the gate dielectric layer and the upper electrode layer fill the depression, so that the upper electrode layer has a downward convex area.

2. The anti-fuse memory cell according to claim 1, wherein: The contact mode between the lower electrode region and the interconnection region is straight-line edge contact, curved-line contact or surrounding contact.

3. The anti-fuse memory cell according to claim 1, wherein: The shallow trench isolation structure is not higher than the top surface of the lower electrode region.

4. The anti-fuse memory cell according to claim 1, wherein: The gate dielectric layer and the upper electrode layer at least partially cover the shallow trench isolation region.

5. The anti-fuse memory cell according to claim 1, wherein: Also includes: A connection region is located between adjacent lower electrode regions and connects the adjacent lower electrode regions. The connection region is made of the same material as the lower electrode region. The gate dielectric layer and the upper electrode layer cover the surfaces of the connection region and the lower electrode region.

6. The anti-fuse memory cell according to claim 1, wherein: Also includes: A first contact plug connected to the interconnection region, and a second contact plug connected to the upper electrode layer, wherein the shortest distance between the first contact plug and the upper electrode layer is not less than 60 nm.

7. The anti-fuse memory cell according to claim 6, wherein: A dielectric layer covers the upper electrode layer and the surface of the interconnection area, wherein the dielectric layer has a first through hole and a second through hole, wherein the bottom of the first through hole exposes the surface of the interconnection area, the first contact plug is located in the first through hole, the bottom of the second through hole exposes the surface of the upper electrode layer, and the second contact plug is located in the second through hole.

8. The anti-fuse memory cell according to claim 7, wherein: When programming the anti-fuse memory cell, a programming voltage is applied to the first contact plug and the second contact plug, and the programming voltage causes the gate dielectric layer between the upper electrode layer and the lower electrode region to be broken down.

9. The anti-fuse memory cell according to claim 1, wherein: The lower electrode region is in a strip, ring or irregular shape.

10. A method for forming an anti-fuse memory cell, characterized in that: include: providing a semiconductor substrate; an active region in the semiconductor substrate, the active region comprising an interconnection region and at least two lower electrode regions, the lower electrode region being in contact with at least a portion of the interconnection region; A shallow trench isolation structure is provided in the semiconductor substrate around the active area and in the semiconductor substrate between adjacent lower electrode areas, and a portion of the shallow trench isolation structure contacting the edge of the top surface of the lower electrode area is recessed downward; forming a gate dielectric layer covering all surfaces of the lower electrode region; An upper electrode layer is formed on the gate dielectric layer, and the gate dielectric layer and the upper electrode layer fill the recess, so that the upper electrode layer has a downward convex area.

11. The method for forming an anti-fuse memory cell according to claim 10, wherein: The contact mode between the lower electrode region and the interconnection region is straight-line edge contact, curved-line contact or surrounding contact.

12. The method for forming an anti-fuse memory cell according to claim 11, wherein: The shallow trench isolation structure is not higher than the top surface of the lower electrode region.

13. The method for forming an anti-fuse memory cell according to claim 12, wherein: The gate dielectric layer and the upper electrode layer at least partially cover the shallow trench isolation region.

14. The method for forming an anti-fuse memory cell according to claim 10, wherein: Also includes: A connection region is located between adjacent lower electrode regions and connects the adjacent lower electrode regions. The connection region is made of the same material as the lower electrode region. The gate dielectric layer and the upper electrode layer cover the surfaces of the connection region and the lower electrode region.

15. The method for forming an anti-fuse memory cell according to claim 10, wherein: Also includes: forming a dielectric layer covering the upper electrode layer and the surface of the interconnection region; Forming a first through hole and a second through hole in the dielectric layer, wherein the bottom of the first through hole exposes the surface of the interconnection region, and the bottom of the second through hole exposes the surface of the upper electrode layer; A first contact plug is formed in the first through hole, and a second contact plug is formed in the second through hole, wherein the shortest distance between the first contact plug and the upper electrode layer is not less than 60 nm.

16. The method for forming an anti-fuse memory cell according to claim 15, wherein: When programming the anti-fuse memory cell, a programming voltage is applied to the first contact plug and the second contact plug, and the programming voltage causes the gate dielectric layer between the upper electrode layer and the lower electrode region to be broken down.

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