Device and system for improving branch prediction throughput

Abstract

According to one general aspect, an apparatus may include branch prediction circuitry configured to predict whether a branch instruction will be taken or not taken. The apparatus may include branch target buffer circuitry configured to store a memory segment empty flag indicating whether a memory segment following a target address includes at least one other branch instruction, wherein the memory segment empty flag is created at a commit stage before the branch instruction occurs. The branch prediction circuitry may be configured to skip a memory segment if the memory segment empty flag indicates a lack of other branch instructions.

Description

Technical Field

[0001] The present disclosure relates to processor instruction flow, and more particularly, to improving branch prediction throughput by skipping cache lines that have no branches. Background Art

[0002] In computer architecture, a branch predictor or branch prediction unit is a digital circuit that attempts to guess which way a branch (e.g., if-then-else structure, jump instruction) will go before the result is actually calculated and known. The purpose of a branch predictor is usually to improve the flow in the instruction pipeline. In many modern pipelined microprocessor architectures, branch predictors play a vital role in achieving high performance.

[0003] Conditional jump instructions are often used to implement bidirectional branches. A conditional jump can be either "not taken" and continue execution of the first code segment immediately following the conditional jump, or "taken" and jump to a different location in program memory where the second code segment is stored. Whether a conditional jump is taken or not taken is often not determined until the condition has been calculated and the conditional jump has passed through the execution stage of the instruction pipeline.

[0004] Without branch prediction, the processor would typically have to wait for a conditional jump instruction to pass through the execute stage before the next instruction could enter the fetch stage in the pipeline. Branch predictors attempt to avoid this waste of time by trying to guess whether a conditional jump is most likely to be taken or not taken. The instruction guessed most likely to be taken at the destination of the branch is then fetched and speculatively executed. If the instruction execute stage detects that the guessed branch is wrong, the speculatively executed or partially executed instruction is typically discarded and the pipeline restarts from the correct branch, causing a delay. Summary of the invention

[0005] According to one general aspect, an apparatus may include: a branch prediction circuit configured to predict whether a branch instruction is taken or not taken. The apparatus may include a branch target buffer circuit configured to store a memory segment empty flag, the memory segment empty flag indicating whether a memory segment following a target address includes at least one other branch instruction, wherein the memory segment empty flag is created during a commit phase before the branch instruction occurs. The branch prediction circuit may be configured to skip a memory segment if the memory segment empty flag indicates a lack of other branch instructions (or multiple).

[0006] According to another general aspect, an apparatus may include branch detection circuitry configured to detect the presence of at least one branch instruction stored within a portion of a memory segment during a commit phase of a current instruction. The apparatus may include branch target buffer circuitry configured to store: a branch instruction address; and a memory segment empty flag indicating whether a portion of the memory segment following the target address includes at least one other branch instruction.

[0007] According to another general aspect, a system may include branch detection circuitry configured to detect the presence of at least one branch instruction stored within a portion of a memory segment during a current commit instruction commit phase. The system may include branch target buffer circuitry configured to store: a branch instruction address; and a memory segment empty flag indicating whether a portion of the memory segment following the target address includes at least one other branch instruction. The system may include branch prediction circuitry configured to predict whether the branch instruction is taken, and wherein the branch prediction circuitry is configured to skip the memory segment if the associated memory segment empty flag indicates a lack of a branch instruction.

[0008] The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims.

[0009] A system and / or method for processor instruction flow is substantially as shown in and / or described in conjunction with at least one of the accompanying drawings, and more particularly, a system and / or method for improving branch prediction throughput by skipping cache lines without branches, as more fully set forth in the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram of an example embodiment of a system in accordance with the disclosed subject matter.

[0011] Figure 2 is a block diagram of an example embodiment of a data structure in accordance with the disclosed subject matter.

[0012] Figure 3 is a diagram of an example embodiment of a data structure in accordance with the disclosed subject matter.

[0013] Figure 4 is a block diagram of an example embodiment of a system in accordance with the disclosed subject matter.

[0014] Figure 5 is a flow diagram of an example embodiment of a technique in accordance with the disclosed subject matter.

[0015] Figure 6 is a flow diagram of an example embodiment of a technique in accordance with the disclosed subject matter.

[0016] Figure 7 is a schematic block diagram of an information processing system that may include devices formed according to the principles of the disclosed subject matter.

[0017] Like reference symbols in the various drawings indicate like elements. DETAILED DESCRIPTION

[0018] Various example embodiments will be described more fully below with reference to the accompanying drawings, some of which are shown in the accompanying drawings. However, the subject matter of the present disclosure may be embodied in many different forms and should not be construed as being limited to the example embodiments set forth herein. Instead, these example embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the subject matter of the present disclosure to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

[0019] It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it may be directly on, connected to, or coupled to another element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. Throughout, like reference numerals refer to like elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0020] It will be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another region, layer, or part. Therefore, without departing from the teachings of the subject matter of the present disclosure, the first element, component, region, layer, or part discussed below may be referred to as a second element, component, region, layer, or part.

[0021] For ease of description, spatially relative terms such as "below", "below...", "above", "above", "above", etc. may be used herein to describe the relationship of one element or feature to another element (or multiple) or feature (or multiple), as shown in the figures. It will be understood that in addition to the orientations depicted in the drawings, spatially relative terms are also intended to cover different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements described as "below" or "below" other elements or features will be oriented as "above" the other elements or features. Therefore, the exemplary term "below" can include both above and below. The device can be oriented in other ways (rotated 90 degrees or other orientations), and the spatially relative descriptors used herein are interpreted accordingly.

[0022] Likewise, for ease of description, electrical terms such as "high," "low," "pull up," "pull down," "1," "0," and the like may be used herein to facilitate description of other voltage levels or another element (or elements) or feature (or elements) relative to a voltage level or current, as shown. It will be understood that the electrical relative terms are intended to encompass different reference voltages of the device in use or operation in addition to the voltages or currents depicted in the accompanying drawings. For example, if the device or signal in the figure is reversed or uses other reference voltages, currents, or charges, an element described as "high" or "pull up" would be "low" or "pull down" compared to the new reference voltage or current. Thus, the exemplary term "high" can encompass relatively low or high voltages or currents. Otherwise, the device may be based on a different electrical reference frame, and the electrical relative descriptors used herein may be interpreted accordingly.

[0023] The terms used herein are for the purpose of describing specific example embodiments only and are not intended to limit the subject matter of the present disclosure. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "include" and / or "comprise" are used in this specification, the presence of the features, integers, steps, operations, elements, and / or components is specified, but the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof is not excluded.

[0024] Example embodiments are described herein with reference to cross-sectional views, which are schematic diagrams of ideal example embodiments (and intermediate structures). Thus, variations in the illustrated shapes, for example due to manufacturing techniques and / or tolerances, are to be expected. Therefore, the example embodiments should not be interpreted as being limited to the specific shapes of the regions shown herein, but should include shape deviations, for example, caused by manufacturing. For example, an implant region shown as a rectangle will typically have rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implant region to a non-implant region. Similarly, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implantation occurs. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device, nor are they intended to limit the scope of the subject matter of the present disclosure.

[0025] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the subject matter of the present disclosure belongs. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0026] Hereinafter, example embodiments will be explained in detail with reference to the accompanying drawings.

[0027] Figure 1 1 is a block diagram of an example embodiment of a system 100 according to the disclosed subject matter. In various embodiments, the system 100 may include a computer, a plurality of discrete integrated circuits, or a system on a chip (SoC). As described below, the system 100 may include many other components that are not shown in this figure in order not to obscure the disclosed subject matter.

[0028] In the illustrated embodiment, system 100 includes system memory 104. In various embodiments, system memory 104 may be comprised of dynamic random access memory (DRAM). However, it should be understood that the above is merely an illustrative example and the disclosed subject matter is not limited thereto. In such embodiments, system memory 104 may include on-module memory (e.g., a dual in-line memory module (DIMM)), may be an integrated chip that is soldered or otherwise fixedly integrated with system 100, or may even be incorporated as part of an integrated chip (e.g., a SoC) that includes system 100. It should be understood that the above are merely some illustrative examples and the disclosed subject matter is not limited thereto.

[0029] In the illustrated embodiment, system memory 104 may be configured to store data segments or information. These data segments may include instructions that cause processor 102 to perform various operations. Typically, system memory 104 may be part of a larger memory hierarchy that includes multiple caches. In various embodiments, the operations described herein may be performed by another layer or level of the memory hierarchy (e.g., a level 2 (L2) cache). Those skilled in the art will appreciate that although operations are described with reference to system memory 104, the disclosed subject matter is not limited to this illustrative example.

[0030] In the illustrated embodiment, the system 100 also includes a processor 102. The processor 102 may be configured to perform a number of operations as indicated by various instructions. These instructions may be executed by various execution units (most not shown), such as an arithmetic logic unit (ALU), a floating point unit (FPU), a load / store unit (LSU), an instruction fetch unit 116 (IFU), etc. It is understood that a unit is simply a collection of circuits that are combined together to perform a portion of the functionality of the processor 102. Typically, a unit performs one or more operations in a pipeline architecture of the processor 102.

[0031] In the illustrated embodiment, the processor 102 may include a branch prediction unit (BPU) 112. As described above, when the processor 102 is executing an instruction stream, one (or more) instructions may be a branch instruction. A branch instruction is an instruction that causes the instruction stream to branch or fork between two or more paths. A typical example of a branch instruction is an if-then structure, where if a certain condition is met (e.g., the user clicks an "OK" button), then a first set of instructions will be executed, and if a certain condition is not met (e.g., the user clicks a "Cancel" button), then a second set of instructions will be executed. As described above, this is a problem in pipelined processor architectures because the new instruction must enter the pipeline of the processor 102 before the result of the branch, jump, or if-then structure is known (because the pipeline stage that resolves the branch instruction is located deep in the pipeline). Therefore, new instructions must be prevented from entering the pipeline until the branch instruction is resolved (thereby negating the main advantage of the pipelined architecture), or the processor 102 must guess which way the instruction stream will branch and speculatively place those instructions into the pipeline. The BPU 112 can be configured to predict how the instruction stream will branch. In the embodiment shown, the BPU 112 can be configured to output the predicted instruction, or more accurately, the memory address where the predicted instruction is stored.

[0032] In the illustrated embodiment, processor 102 includes a branch prediction address queue (BPAQ) 114. BPAQ 114 may include a memory structure configured to store a plurality of addresses for predicted instructions that have been predicted by BPU 112. BPAQ 114 may store the addresses of these predicted instructions in a first-in, first-out (FIFO) order so that the instruction addresses are output from BPAQ 114 in the same order as the order in which BPU 112 predicted them.

[0033] In the illustrated embodiment, the processor 102 includes an instruction fetch unit (IFU) 116 configured to fetch instructions from the memory hierarchy and place them into the pipeline of the processor 102. In such an embodiment, the IFU 116 may be configured to take the memory address associated with the most recent or oldest instruction (the next instruction) from the BPAQ 114 and request the actual instruction from the memory hierarchy. Ideally, the instructions will be provided quickly from the memory hierarchy and placed into the pipeline of the processor 102.

[0034] Ideally, instructions may be fetched (via memory access(es)) from the level 1 (L1) instruction cache 118. In such an embodiment, as the top or higher level of the memory hierarchy, the L1 instruction cache 118 may be relatively fast in the pipeline and cause little or no delay. However, occasionally, the L1 instruction cache 118 may not include the desired instruction. This will result in a cache miss, and the instruction will have to be fetched or loaded from a lower, slower level of the memory hierarchy (e.g., system memory 104). Such a cache miss may cause a delay in the pipeline of the processor 102 because instructions will not be input into the pipeline at a rate of one per cycle (or the maximum rate in the processor architecture).

[0035] In the illustrated embodiment, the processor 102 includes an instruction prefetch unit (IPFU) 120. The IPFU 120 is configured to prefetch instructions into the L1 instruction cache 118 before the IFU 116 performs the actual fetch operation. Thus, the IPFU 120 reduces the occurrence of any cache misses experienced by the IFU 116. The IPFU 120 may do this by requesting predicted instructions from the L1 instruction cache 118 before the IFU 116 executes. In such an embodiment, if a cache miss then occurs, the L1 instruction cache 118 will begin the process of requesting the missing instruction from the system memory 104. In such an embodiment, instructions may be received and stored in the L1 instruction cache 118 upon request by the IFU 116.

[0036] Returning to the BPU 112, the processor 102 may include a branch target buffer (BTB) circuit 122. In various embodiments, the BTB 122 may include a memory that maps branch addresses to previously predicted target addresses (where the branch will jump to). In such embodiments, the BTB 122 may indicate which address a previous iteration of a branch instruction last jumped to or was predicted to jump to. This makes the work of the BPU 112 simpler and faster because the BPU 112 can simply request a predicted branch target address from the BTB 122 instead of performing a full address prediction calculation.

[0037] Likewise, processor 102 may include a return address stack (RAS) circuit 124. In various embodiments, RAS 124 may be a memory or data structure that stores a memory address to return to once the current branch operation or instruction (typically a return instruction) has been completed. For example, when the branch is a subroutine call, once completed, the subroutine will return to the next instruction after the calling memory address. In various embodiments, RAS calculation circuit 126 may perform this return address calculation.

[0038] The basic structure of the processor 102 is now shown. Figure 2 Operations performed by processor 102 are shown.

[0039] Figure 2 is a block diagram of an example embodiment of a data structure 200 according to the disclosed subject matter. In various embodiments, the data structure 200 may represent Figure 1 The memory stores various instructions that the processor 102 retrieves and processes.

[0040] In this context, a generic term for a block or portion of memory is a "memory segment". For purposes of example, a memory segment may include a cache line, but in certain embodiments, the cache line is larger. In this context, a cache line may be a unit of data transfer between the L1 instruction cache 118 and main memory (e.g., system memory 104). In various embodiments, the disclosed subject matter may involve memory segments of multiple cache lines, portions of cache lines, or memory sizes not measured in cache lines at all. It should be understood that the above is merely an illustrative example and the disclosed subject matter is not limited thereto.

[0041] In the illustrated embodiment, data structure 200 includes cache lines 204 and 206 that appear sequentially. In such an embodiment, processor 102 generally fetches and processes instructions from the beginning (e.g., the left side) of cache lines 204 and 206 to the end (e.g., the right side) of cache lines 204 and 206, as described above.

[0042] The cache line includes branch instructions A 211, B 212, C 213, D 214, E 215, F 216, and G 217. In various embodiments, Figure 1 The BPU 112 may be configured to process each branch instruction (for simplicity, treat it as a subroutine call) and, when the branch returns to that point, continue processing the cache line in sequence.

[0043] The BPU 112 may be configured to stop processing at a memory segment at a cache line boundary for that clock cycle(s). For example, when processing cache line 204, the BPU 112 may process A 211 in the first cycle, then process B 212 in the second cycle, then process C 213 in the third cycle, then process D 214 in the fourth cycle, then check portion 224 in the fifth cycle, and stop at the end of cache line 204 before continuing to E 215 of cache line 206 in the sixth cycle.

[0044] Since there are no branches to process in portion 224 (as opposed to portion 222), the time spent checking the cache line is a wasted cycle (or a number of cycles spent processing portion 224). In various embodiments, portion 224 may include a complete cache line. The disclosed subject matter may eliminate or reduce such branch pipeline bubbling (or lack of operation during one or more cycles).

[0045] In the disclosed subject matter, the BTB 122 and / or RAS 124 may include an indication of whether the portion 224, or more generally the portion following any given branch instruction target, is empty or devoid of branch instructions. In such an embodiment, "empty" does not mean that no instructions are stored there, only that no branch instructions are stored in the memory segment. It is expected (but not required) that many non-branch instructions will fill the portion 224.

[0046] For example, branch 202 (e.g., a return branch from call D 214) may return the program counter (PC) to the end of portion 222. After the return, BPU 112 may check RAS 124 and determine that there are no more branch instructions after D 214 (portion 224). BPU 112 may then begin processing the next cache line 206; thus, saving the wasted computation time involved in checking the branch of portion 224.

[0047] Similarly, BTB 122 may include a flag indicating whether the memory segment after the target address of the branch has no additional branch instructions. In such an embodiment, if branch 202 is not a return (from a call) but another type of branch instruction (e.g., a call, an unconditional jump, a jump, etc.), BTB 122 may include the target address (e.g., the address of the beginning of portion 224) and whether the portion from the target address to the end of the cache line (i.e., portion 224) has no additional branch instructions.

[0048] Figure 3 300 and 301 according to the disclosed subject matter. In such an embodiment, data structure 300 may be composed of a branch target buffer (e.g., Figure 1 In various embodiments, data structure 301 may be stored in a return address stack (e.g., Figure 1 It should be understood that the above are just some illustrative examples and the disclosed subject matter is not limited thereto.

[0049] In the illustrated embodiment, data structure 300 may illustrate a representative embodiment of the state of a BTB. In such an embodiment, the BTB may include at least three columns or fields (although more columns or fields may be used in various embodiments). A first field 302 includes the address (or other identifier) ​​of a branch instruction. A second field 304 may include the predicted target address of the branch (i.e., the address to which the branch may jump). In a conventional BTB, these two fields 302 and 304 may be the only columns or fields, except for a valid flag (not shown) (note whether a row, line, or entry may be used).

[0050] In such an embodiment, when the BPU encounters a branch instruction, it is looked up via its memory address (first field 302), and the BPU determines where to find the next instruction in memory (via second field 304). As described above, in such an embodiment, upon reaching that target address, the BPU may waste one or more cycles looking for a branch instruction in a non-existent memory address (i.e., the memory segment past the target address is empty or does not have a branch instruction).

[0051] However, in the embodiment shown, the BPU may be configured to check a third field or empty flag 306. In such an embodiment, the empty flag 306 may indicate whether the memory segment past the target address is empty or does not have a branch instruction. In various embodiments, the value of the empty flag 306 may be calculated when a branch instruction is first encountered. In some embodiments, this may be done at a commit stage or pipeline stage when the correctness (or lack thereof) of the branch is fully resolved.

[0052] In various embodiments, the empty flag 306 of the memory segment may include a single bit or a true / false value. In such an embodiment, the empty flag 306 may refer only to the immediate memory segment that includes the target address. In another embodiment, the empty flag 306 may indicate how many memory segments should be skipped. For example, the last row of the data structure 300 has a value of 3, indicating that there are no branch instructions for the current memory segment plus the other two memory segments.

[0053] In another embodiment, the empty flag 306 may include a valid flag. In another embodiment, the valid flag of the empty flag may be stored as a separate field (not shown). In such an embodiment, the valid flag of the empty flag may indicate whether the empty flag 306 has been calculated and whether the empty flag 306 can be relied on. For example, an entry may be placed in the BTB during the instruction fetch pipeline stage, but the empty flag 306 may not be calculated before the commit stage. Alternatively, in another example, the empty flag 306 may only be valid for branches predicted to be "taken", but not for branches predicted to be "not taken" (or vice versa). In yet another embodiment, the empty flag 306 may only be valid for certain types of branches (e.g., calls and returns). It should be understood that the above are merely a few illustrative examples, and the disclosed subject matter is not limited thereto.

[0054] In such an embodiment, the empty flag 306 may be increased by 1 bit. In such an embodiment, a valid and true (or set) empty flag may be "0x11", and a valid but false (or cleared) empty flag may be "0x10", where the first bit is a valid bit and the second bit is an empty state. It should be understood that the above is merely an illustrative example and the disclosed subject matter is not limited thereto.

[0055] In the illustrated embodiment, data structure 301 can illustrate a representative embodiment of the state of RAS. In such an embodiment, RAS can include at least two columns or two fields (although more columns or fields can be used in various embodiments). Field 312 includes the return address (or other identifier) ​​to which the call branch instruction will return. In traditional RAS, in addition to the effective flag (not shown) (note whether a row, line or entry can be used), field 312 may be a unique column or field. Traditionally, the return address is pushed into the top of data structure 301, and then popped up from the top in a last-in-first-out (LIFO) manner.

[0056] In the illustrated embodiment, the BPU may be configured to check a second field or empty flag 316. In such an embodiment, the empty flag 316 may indicate whether the memory segment past the target address (field 312) of the return instruction has no branch instruction, as described above. In various embodiments, the value of the empty flag 316 may be calculated when a call branch instruction is first encountered. In various embodiments, the empty flag 316 may be similar to the flags described above. In various embodiments, the empty flag 306 of the BTB and the empty flag 316 of the RAS may include differences in format or information.

[0057] Figure 4 400 is a block diagram of an example embodiment of a system 400 according to the disclosed subject matter. In various embodiments, the system 400 may include a computer, a plurality of discrete integrated circuits, or a system on a chip (SoC). As described below, the system 400 may include many other components that are not shown in this figure in order not to obscure the disclosed subject matter.

[0058] In the illustrated embodiment, system 400 includes system memory 104. In various embodiments, system memory 104 may be comprised of dynamic random access memory (DRAM). It should be understood, however, that the above is merely an illustrative example and the disclosed subject matter is not limited thereto. In such embodiments, system memory 104 may include memory on a module (e.g., a dual in-line memory module (DIMM)), may be an integrated chip that is soldered or otherwise fixedly integrated with system 400, or may even be incorporated as part of an integrated chip (e.g., a SoC) that includes system 400. It should be understood that the above are merely some illustrative examples and the disclosed subject matter is not limited thereto.

[0059] In the illustrated embodiment, system memory 104 may be configured to store data segments or information. These data segments may include instructions that cause processor 102 to perform various operations. Typically, system memory 104 may be part of a larger memory hierarchy that includes multiple caches. In various embodiments, the operations described herein may be performed by another layer or level of the memory hierarchy (e.g., a level 2 (L2) cache). Those skilled in the art will appreciate that although operations are described with reference to system memory 104, the disclosed subject matter is not limited to this illustrative example.

[0060] In the illustrated embodiment, the system 400 also includes a processor 102. The processor 102 may be configured to perform a number of operations as indicated by various instructions. These instructions may be executed by various execution units (most not shown), such as an arithmetic logic unit (ALU), a floating point unit (FPU), a load / store unit (LSU), an instruction fetch unit 116 (IFU), etc. It is understood that a unit is simply a collection of circuits that are combined together to perform a portion of the functionality of the processor 102. Typically, a unit performs one or more operations in the pipeline architecture of the processor 102.

[0061] In various embodiments, processor 102 may operate in various pipeline stages. In computing, a pipeline, also known as a data pipeline, is a collection of data processing elements connected in a rough series, where the output of one element is the input of the next element. The elements of the pipeline are typically executed in parallel or in a time-sliced ​​manner. A certain amount of buffer memory is typically inserted between the elements.

[0062] In a classic reduced instruction set computer (RISC) pipeline, the stages include: instruction fetch (mostly in Figure 1 ), instruction decoding, execution, memory access, and writeback. In modern out-of-order and speculative execution processors, processor 102 may execute instructions that are not needed. The pipeline stage where it is determined whether an instruction (or its result) is needed is called the commit stage. If the commit stage is placed in the Procrustean bed of a classic RISC pipeline, it may be placed in the writeback stage. In various embodiments or architectures, the commit stage can be a separate pipeline stage.

[0063] In the illustrated embodiment, processor 102 may include execution unit 402 as described above. In the illustrated embodiment, processor 102 may include a submit queue 404 in which completed instructions are placed in order of age.

[0064] In the illustrated embodiment, the processor 102 may include a register file 406. In such an embodiment, when instructions are committed (rather than discarded), the results of those instructions may be placed or committed into the register file 406. In modern computers with renamed registers, the commit action may include verifying or marking the values ​​already stored in the register file 406 as correct. In various embodiments, the processor may include a cache 418 (e.g., a data cache) where the data of the register file is eventually moved, and then to the system memory 104, as described above.

[0065] Furthermore, in the illustrated embodiment, the processor 102 may include a branch detection circuit 420. In such an embodiment, the branch detection circuit 420 may be configured to detect the presence of at least one branch instruction stored with a portion of a memory segment (e.g., a cache line) during a commit phase of a current instruction.

[0066] In such an embodiment, once branch detection circuit 420 has made a determination as to whether a memory segment portion is free of any branch instructions, it may create or update a memory segment empty tag in BTB 122, as described above. In various embodiments, this may include setting or clearing an empty tag associated with a branch instruction.

[0067] In some embodiments, the processor 102 or the branch detection circuit 420 may include a last branch memory 422 that stores the last or current branch instruction encountered from the commit queue 404. In such embodiments, the last branch memory 422 may indicate the branch instruction associated with the currently computed null label. In various embodiments, the last branch memory 422 may be valid (an active branch null label is being computed) or invalid (no active branch null label is being computed).

[0068] In various embodiments, BTB 122 may be graph-based. In such embodiments, branches may be stored as nodes, and edges may represent control flow of a program or instruction set. In various embodiments, the disclosed subject matter may be limited to a first-level BTB of a multi-level or hierarchical BTB structure. It should be understood that the above is merely an illustrative example, and the disclosed subject matter is not limited thereto.

[0069] In various embodiments, certain designs define instruction blocks and instruction sequences that end with branches. In such embodiments, the BTB 122 can find branches or index branches based on the start address of the block rather than the actual address of the branch instruction. In such embodiments, the disclosed subject matter is modified accordingly. In addition, the BTB metadata can be enhanced to store how many empty cache lines or memory segments can be skipped before encountering the next branch instruction. It should be understood that the above are merely some illustrative examples and the disclosed subject matter is not limited thereto.

[0070] In various embodiments, a branch target buffer (BTB) may be configured to store metadata associated with a branch instruction, such as an empty flag. A branch prediction pipeline (BPP) may be configured to detect branch instructions whose target cache lines are partially or completely empty and skip branch predictions for any empty target cache lines. In various embodiments, the BPP may achieve this by training with a commit instruction cache line. The BPP may mark a taken branch instruction whose target cache line is empty by setting at least one of the taken target cache line empty flags. The BPP may mark a not taken branch instruction with a not taken target cache line empty flag as true in the BTB entry of the branch instruction. The BPP may check the BTB entry or return address stack (RAS) of the branch instruction to determine whether the target cache line empty flag is set. If the target cache line empty flag is set, the BPP may skip branch predictions for one or more instruction cache lines including the target cache line of the branch instruction.

[0071] Figure 5 is a flow chart of an example embodiment of a technique according to the disclosed subject matter. In various embodiments, technique 500 may be implemented by, for example, Figure 4 or Figure 7 The system uses or generates. Although it can be understood that the above are only some illustrative examples, the disclosed subject matter is not limited thereto. It should be understood that the disclosed subject matter is not limited to the order or number of actions shown in the technology 500.

[0072] In various embodiments, as described above, technique 500 may illustrate an embodiment of a technique employed by a processor or branch detection unit for determining the correct state of a memory segment empty flag, as described above. In the illustrated embodiment, technique 500 is illustrated that may be specifically used for taken branches. In another embodiment, a technique may be employed for not-taken branches. In yet another embodiment, a technique may be employed for both taken and not-taken branches and / or various types of branch instructions (e.g., call, return, unconditional jump, conditional jump, zero-value jump or other value jump, etc.). It should be understood that the above is merely an illustrative example and the disclosed subject matter is not limited thereto.

[0073] Block 502 shows that, in one embodiment, a commit instruction may be checked to determine whether it is a branch instruction. As described above, a commit instruction may be provided by or stored in a commit queue that accommodates branch instructions or non-branch instructions in order of age. In such an embodiment, non-branch instructions may be grouped by the memory segment from which they come.

[0074] Block 504 shows that, in one embodiment, if the commit instruction is a branch instruction, the branch instruction (or its address) may be stored in the last branch memory as described above. In various embodiments, the last branch memory may be marked as valid or marked as storing an address for null flag determination.

[0075] Block 506 illustrates that, in one embodiment, if the commit instruction is not a branch instruction, a check may be made to determine if the last branch memory is valid or active.

[0076] Block 508 shows that, in one embodiment, if the commit instruction is not a branch instruction and the last branch memory value is valid, the empty flag associated with the branch stored in the last branch memory may be set to a value indicating that the remainder of the memory segment does not contain a branch instruction. As described above, the empty flag may be stored in the BTB.

[0077] Block 510 shows that, in one embodiment, if the commit instruction is not a branch instruction, the last branch memory value may be invalidated or marked as inactive. In various embodiments, if the result of block 506 indicates that the last branch memory value is already invalid, block 510 may be skipped.

[0078] Block 599 illustrates the stopping point. However, it should be understood that technique 500 may be repeated for each commit instruction.

[0079] Figure 6 is a flow chart of an example embodiment of a technique according to the disclosed subject matter. In various embodiments, technique 600 may be performed by, for example, Figure 1 or Figure 7 The system uses or generates. Although it can be understood that the above are only some illustrative examples, the disclosed subject matter is not limited to this. It should be understood that the disclosed subject matter is not limited to the order or number of actions shown in the technology 600.

[0080] In various embodiments, as described above, technique 600 may illustrate an embodiment of a technique employed by a processor or branch prediction unit to determine whether to skip or pass through a portion of a memory segment or cache line, as described above. In the illustrated embodiment, technique 600 may be specifically used for taken branches as shown. In another embodiment, the technique may be employed for not taken branches. In yet another embodiment, a technique may be employed for both taken and not taken branches and / or various types of branch instructions (e.g., call, return, unconditional jump, conditional jump, zero value jump or other value jump, etc.). It should be understood that the above is merely an illustrative example and the disclosed subject matter is not limited thereto.

[0081] Block 602 shows that, in one embodiment, a determination may be made as to whether a branch instruction is predicted to be taken. If not, the technique 600 may stop 699. However, it should be understood that the above is merely an illustrative example and the disclosed subject matter is not limited thereto.

[0082] Block 604 shows that, in one embodiment, a determination may be made as to which type of branch instruction has been encountered. In the illustrated embodiment, the determination may be whether the branch is a call, a return, or neither. It should be understood that the above is merely an illustrative example, and the disclosed subject matter is not limited thereto.

[0083] Block 606 shows that, in one embodiment, if the branch instruction is neither a call nor a return, then the memory segment empty flag (associated with the branch instruction) may be read from the BTB as described above.

[0084] Block 608 shows, in one embodiment, if branch instruction is to call branch instruction, then can determine the target of corresponding return branch instruction.Can then determine whether the target memory segment returned or the remainder of cache line do not have other branch instructions.Once made this determination and created memory segment empty mark, then can push memory segment empty mark on RAS together with return target address, as mentioned above.In such embodiment, once for the final return of calling, ready the empty mark of RAS, then BPU can be to call instruction execution block 606.

[0085] Block 610 shows that, in one embodiment, if the branch instruction is a return branch instruction, then the empty flag of the RAS for the branch may be read (prepared by block 608), as described above.

[0086] Block 612 shows that, in one embodiment, the value of the empty flag (the value of the BTB or RAS determined by the branch type) can be determined, as described above. If the empty flag is not set, is cleared, or the empty flag indicates that the rest of the memory segment is not branchless, then the technique 600 can stop 699 and branch processing can occur normally.

[0087] Block 614 shows that, in one embodiment, it may be determined whether a virtual to physical (V2P) address translation of the cache line containing the target address and the next sequential cache line after the target address is available. In various embodiments, this may be stored in a translation look-aside buffer (TLB). If a virtual to physical (V2P) address translation of the cache line containing the target address and the next sequential cache line after the target address is not available, an indication may be made to move to the next memory segment so that additional work may be performed (e.g., TLB fill). Technique 600 may stop at block 699.

[0088] Block 616 shows that, in one embodiment, it may be determined that the target cache line and the cache line after the target cache line are both available in the cache (e.g., instruction cache) and / or BTB (cache hit no miss). If not, the technique may not skip the empty memory, but move to block 699.

[0089] Block 618 shows that, in one embodiment, if the empty flag is set (or indicates that the remainder of the target memory segment can be skipped) and the target cache line and the cache lines after the target cache line are both available in the cache, the BPU can skip or pass through the remainder of the current memory segment, as described above.

[0090] Block 699 shows the stopping point. However, it is understood that the BPU can continue further processing of branch prediction as described above, and that technique 600 can be part of a larger branch prediction technique. In addition, it should be understood that technique 600 can be repeated for each branch instruction.

[0091] Figure 7 is a schematic block diagram of an information processing system 700 that may include a semiconductor device formed according to the principles of the disclosed subject matter.

[0092] Reference Figure 7 , information processing system 700 may include one or more devices constructed according to the principles of the disclosed subject matter. In another embodiment, information processing system 700 may employ or perform one or more techniques according to the principles of the disclosed subject matter.

[0093] In various embodiments, information handling system 700 may include a computing device, such as a laptop computer, a desktop computer, a workstation, a server, a blade server, a personal digital assistant, a smart phone, a tablet computer, and other suitable computers or virtual machines or their virtual computing devices. In various embodiments, information handling system 700 may be used by a user (not shown).

[0094] The information processing system 700 according to the disclosed subject matter may also include a central processing unit (CPU), logic or processor 710. In some embodiments, the processor 710 may include one or more functional unit blocks (FUBs) or combinatorial logic blocks (CLBs) 715. In such embodiments, the combinatorial logic blocks may include various Boolean logic operations (e.g., NAND, NOR, NOT, XOR), stable logic devices (e.g., flip-flops, latches), other logic devices, or combinations thereof. These combinatorial logic operations may be configured in a simple or complex manner to process input signals to obtain desired results. It should be understood that although some illustrative examples of synchronous combinatorial logic operations are described, the disclosed subject matter is not limited thereto and may include asynchronous operations or a mixture thereof. In one embodiment, the combinatorial logic operations may include a plurality of complementary metal oxide semiconductor (CMOS) transistors. In various embodiments, these CMOS transistors may be arranged in gates that perform logic operations; however, it should be understood that other techniques may be used and are within the scope of the disclosed subject matter.

[0095] The information handling system 700 according to the disclosed subject matter may also include volatile memory 720 (e.g., random access memory (RAM)). The information handling system 700 according to the disclosed subject matter may also include non-volatile memory 730 (e.g., hard drive, optical storage, NAND or flash memory). In some embodiments, the volatile memory 720, the non-volatile memory 730, or a combination or portion thereof may be referred to as a "storage medium". In various embodiments, the volatile memory 720 and / or the non-volatile memory 730 may be configured to store data in a semi-permanent or substantially permanent form.

[0096] In various embodiments, the information processing system 700 may include one or more network interfaces 740 configured to allow the information processing system 700 to become part of a communication network and communicate via the communication network. Examples of Wi-Fi protocols may include, but are not limited to, Institute of Electrical and Electronics Engineers (IEEE) 802.11g, IEEE 802.11n. Examples of cellular protocols may include, but are not limited to: IEEE 802.16m, (also known as WirelessMAN (Metropolitan Area Network) Advanced), Long Term Evolution (LTE) Advanced, Enhanced Data Rates for GSM (Global System for Mobile Communications) Evolution (EDGE), Evolved High Speed ​​Packet Access (HSPA+). Examples of wired protocols may include, but are not limited to, IEEE 802.3 (also known as Ethernet), Fiber Channel, Power Line Communications (e.g., HomePlug, IEEE 1901). It should be understood that the above are merely some illustrative examples and the disclosed subject matter is not limited thereto.

[0097] The information processing system 700 according to the disclosed subject matter may also include a user interface unit 750 (e.g., a display adapter, a tactile interface, a human-machine interface device). In various embodiments, the user interface unit 750 may be configured to receive input from a user and / or provide output to a user. Other types of devices may also be used to provide interaction with a user; for example, the feedback provided to the user may be any form of sensory feedback, such as visual feedback, auditory feedback, or tactile feedback; and input from the user may be received in any form, including sound, voice, or tactile input.

[0098] In various embodiments, information handling system 700 may include one or more other devices or hardware components 760 (e.g., display or monitor, keyboard, mouse, camera, fingerprint reader, video processor). It should be understood that the above are just some illustrative examples and the disclosed subject matter is not limited thereto.

[0099] The information processing system 700 according to the disclosed subject matter may also include one or more system buses 705. In such an embodiment, the system bus 705 may be configured to communicatively couple the processor 710, the volatile memory 720, the nonvolatile memory 730, the network interface 740, the user interface unit 750, and one or more hardware components 760. Data processed by the processor 710 or data externally input from the nonvolatile memory 730 may be stored in the nonvolatile memory 730 or the volatile memory 720.

[0100] In various embodiments, the information handling system 700 may include or execute one or more software components 770. In some embodiments, the software component 770 may include an operating system (OS) and / or an application. In some embodiments, the OS may be configured to provide one or more services to the application, and manage or act as an intermediary between the application and various hardware components (e.g., processor 710, network interface 740) of the information handling system 700. In such an embodiment, the information handling system 700 may include one or more native applications, which may be installed locally (e.g., in non-volatile memory 730) and configured to be directly executed by the processor 710 and directly interact with the OS. In such an embodiment, the native application may include precompiled machine executable code. In some embodiments, the native application may include a script interpreter (e.g., C shell (csh), AppleScript, AutoHotkey) or a virtual execution machine (VM) (e.g., Java virtual machine, Microsoft common language runtime) configured to convert source code or object code into executable code that can then be executed by the processor 710.

[0101] The semiconductor devices described above can be packaged using various packaging technologies. For example, a semiconductor device constructed according to the principles of the disclosed subject matter can be packaged using package-on-package (POP) technology, ball grid array (BGA) technology, chip size package (CSP) technology, plastic leaded chip carrier (PLCC) technology, plastic dual in-line package (PDIP) technology, die-in-stack packaging technology, die-in-wafer format technology, chip-on-board (COB) technology, ceramic dual in-line package (CERDIP) technology, plastic standard quad flat package (PMQFP) technology, plastic flat package (PQFP) technology, small outline IC (SOIC) technology, reduced small outline package (SSOP) technology, thin small outline package (TSOP) technology, thin flat package (TQFP) technology, system-level package (SIP) technology, multi-chip package (MCP) technology, wafer-level structure package (WFP) technology, wafer-level processing stack package (WSP) technology, or any of other technologies known to those skilled in the art.

[0102] The method steps may be performed by one or more programmable processors executing a computer program that performs functions by operating on input data and generating output. The method steps may also be performed by, and the apparatus may be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).

[0103] In various embodiments, the computer-readable medium may include instructions that, when executed, cause a device to perform at least a portion of the method steps. In some embodiments, the computer-readable medium may be included in magnetic media, optical media, other media, or a combination thereof (e.g., a CD-ROM, a hard drive, a read-only memory, a flash drive). In such embodiments, the computer-readable medium may be a tangible and non-transitory embodied article of manufacture.

[0104] Although the principles of the disclosed subject matter have been described with reference to example embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of these disclosed concepts. Therefore, it should be understood that the above embodiments are not restrictive, but merely illustrative. Therefore, the scope of the disclosed concepts will be determined by the broadest permissible interpretation of the appended claims and their equivalents, and should not be constrained or limited by the foregoing description. Therefore, it should be understood that the appended claims are intended to cover all such modifications and changes that fall within the scope of the embodiments.

Claims

1. A device comprising: branch prediction circuitry configured to predict that a branch instruction will be taken; as well as a return address stack circuit configured to store a memory segment empty flag indicating that the memory segment following the return address does not include at least one other branch instruction and to determine that a physical address translation for a next memory segment and subsequent sequential memory segments is available; Therein, the branch prediction circuit is configured to skip a memory segment associated with a memory segment empty flag indicating a lack of at least one other branch instruction.

2. The device according to claim 1, wherein: The branch prediction circuitry is configured as follows: determining the next memory segment to be stored in the instruction cache and return address stack circuit; and The skip memory segment empty flag indicates a memory segment that lacks a branch instruction.

3. The device according to claim 1, wherein: The branch prediction circuit is configured to, for the memory segment to include at least one other branch instruction after the return address, move to a next instruction within the memory segment.

4. The device according to claim 1, wherein: A memory segment is a cache line.

5. The device according to claim 1, wherein: The branch prediction circuitry is configured to determine whether a branch instruction is one of a call instruction or a return instruction.

6. The apparatus according to claim 5, further comprising: a branch target buffer circuit configured to store a memory segment empty flag of a target address; as well as Wherein, in response to the branch instruction being a call instruction, the device is configured to: determining that a memory segment following the associated return instruction includes at least one other branch instruction, and The determination result is stored as a memory segment empty flag within the return address stack circuit.

7. The apparatus according to claim 5, further comprising: A branch target buffer circuit is configured to store a second memory segment empty flag, wherein the second memory segment empty flag indicates that the memory segment after the target address does not include at least one other branch instruction, wherein the second memory segment empty flag is created at a commit stage before the branch instruction occurs.

8. The device according to claim 1, wherein: The branch prediction circuitry is configured as follows: The skip memory segment empty flag indicates a memory segment that lacks a branch instruction.

9. An apparatus comprising: a branch detection circuit configured to detect the presence of at least one branch instruction within the portion stored in the memory segment during a commit phase of a current instruction, wherein the commit phase includes pipeline stages at which the apparatus determines that an instruction and a result of the instruction will be needed; and The return address circuit is configured to store: the return address, and A memory segment empty flag indicating whether a portion of the memory segment after the return address includes at least one other branch instruction.

10. The device according to claim 9, wherein: A memory segment is a cache line.

11. The device according to claim 9, wherein: The apparatus includes a submission queue circuit; The submission queue circuit is configured to store the current submission instructions in order of age.

12. The device according to claim 9, wherein: The apparatus includes a last committed branch memory configured to store previously committed branch instructions.

13. The device according to claim 12, wherein: The branch detection circuit is configured as: Determining whether the current instruction is a branch instruction; and The current instruction is stored in the last committed branch memory.

14. The device according to claim 9, wherein: The branch detection circuit is configured to, in response to a current instruction not being a branch instruction, determine that a previously stored last committed branch instruction is still valid.

15. The apparatus according to claim 14, further comprising: A branch target buffer circuit configured to store: Branch instruction address; and a second memory segment empty flag indicating whether a portion of the memory segment following the target address includes at least one other branch instruction, and The branch detection circuit is configured to: in response to the current instruction not being a branch instruction and the last committed branch instruction previously stored being still valid, set a storage segment empty flag associated with the last committed branch instruction previously stored in the branch target buffer circuit.

16. The device according to claim 14, wherein: The branch detection circuit is configured to mark the last committed branch instruction previously stored as invalid if the current instruction is not a branch instruction and the last committed branch instruction previously stored is invalid.

17. The device according to claim 9, wherein: The branch target buffer circuitry includes graph-based branch target buffer circuitry.

18. The device according to claim 9, wherein: The memory segment empty flag indicates that a plurality of memory segments or portions thereof following the branch instruction address do not include at least one other branch instruction.

19. A system comprising: a branch detection circuit configured to detect the presence of at least one branch instruction stored within a portion of the memory segment during a commit phase of a currently committed instruction, wherein the commit phase includes pipeline stages at which the system determines that instructions and results of the instructions will be needed; A branch target buffer circuit configured to store: The branch instruction address, and a memory segment empty flag indicating whether a portion of the memory segment following the target address includes at least one other branch instruction; and A branch prediction circuit is configured to predict that a branch instruction will be taken, and wherein the branch prediction circuit is configured to skip a memory segment whose associated memory segment empty flag indicates that the branch instruction is absent.

20. The system of claim 19, wherein: The bank empty flag is valid only for taken branch instructions.

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