Bridgeless Power Factor Correction Converter with Zero-Current Detection Circuit

Abstract

The present disclosure relates to a bridgeless power factor correction converter having a zero current detection circuit. A critical conduction mode (CRM) bridgeless PFC system includes a PFC converter connected to an alternating current (AC) source, a zero current detection (ZCD) circuit for detecting a zero current state of the PFC converter, a zero voltage switching (ZVS) detection circuit, and a processor. A voltage divider circuit receives a first voltage and a supply voltage from the PFC converter and the AC source. The ZCD circuit receives the divided voltage generated by the voltage divider circuit and generates a ZCD signal. The ZVS detection circuit uses the ZCD signal to generate a ZVS flag, which is used by the processor to control switching of first to fourth transistors of the PFC converter.

Description

Technical Field

[0001] The present invention generally relates to electronic circuits, and more particularly, to a bridgeless power factor correction converter. Background Art

[0002] The power factor of a circuit is determined using the ratio of real power to apparent power, where the real power is associated with the load of the circuit and the apparent power is the power supplied to the circuit. The power factor indicates the efficiency of the circuit. The power factor of an efficient circuit is in the range of 0.8 - 1, where 1 is ideal.

[0003] Today's power supplies typically include a power factor correction (PFC) converter to improve power supply efficiency. An example of a PFC circuit is a critical conduction mode (CRM) totem-pole bridgeless PFC circuit. This circuit includes a zero current detection (ZCD) circuit and a bridgeless PFC converter. The bridgeless PFC converter includes transistors and inductors arranged in a totem-pole configuration. A power factor close to 1 is achieved by carefully controlling the switching of the transistors. The transistors are switched based on the zero current state on the inductor detected by the ZCD circuit.

[0004] The ZCD circuit uses an auxiliary winding to detect the zero current state based on the voltage induced in the auxiliary winding. However, the induced voltage is bipolar, so a rectifier circuit is required to detect the induced bipolar voltage. A sampling circuit is also required to sample the voltage for detecting the zero current state. The sampling circuit and the rectifier circuit increase the area required for the ZCD circuit, thus increasing the area required for the bridgeless PFC system.

[0005] Other implementations of the ZCD circuit include current transformer (CT) sensors that detect the zero current state. However, using multiple CT sensors increases the area and power consumption. In addition, other bridgeless PFC systems may include additional hardware circuitry or use software-based methods to control the bridgeless PFC converter. However, accuracy issues are common. Therefore, there is still room for improvement in CRM bridgeless PFC systems. Brief Description of the Drawings

[0006] The following detailed description of the preferred embodiments of the present invention will be better understood when read in conjunction with the accompanying drawings. The present invention is illustrated by way of example and is not limited by the drawings, in which like reference numerals indicate similar elements.

[0007] Figure 1 is a schematic block diagram of a critical conduction mode (CRM) bridgeless power factor correction (PFC) system according to an embodiment of the present invention;

[0008] Figure 2 is according to an embodiment of the present invention Figure 1Schematic circuit diagram of the bridgeless PFC converter of the CRM bridgeless PFC system;

[0009] Figure 3A is according to an embodiment of the present invention Figure 1 Schematic circuit diagram of the zero - current detection (ZCD) circuit of the CRM bridgeless PFC system;

[0010] Figure 3B Illustrates according to an embodiment of the present invention Figure 3A Timing diagram of the operation of the ZCD circuit in the positive and negative half - cycles of the power supply voltage;

[0011] Figure 4 is according to an embodiment of the present invention Figure 1 Schematic circuit diagram of the zero - voltage switching (ZVS) detection circuit of the CRM bridgeless PFC system;

[0012] Figure 5 Illustrates according to an embodiment of the present invention Figure 1 Flowchart of the operation of the processor of the CRM bridgeless PFC system; and

[0013] Figure 6 Timing diagram of the operation of the CRM bridgeless PFC system in the positive half - cycle according to an embodiment of the present invention. Detailed description of the specific implementation

[0014] The detailed description of the drawings is intended as a description of the currently preferred embodiments of the present invention and is not intended to represent the only form in which the present invention can be practiced. It should be understood that the same or equivalent functions can be achieved by different embodiments that are intended to be included within the spirit and scope of the present invention.

[0015] For the purposes of this specification, the terms "coupled", "coupled to", "is coupled", "connected", "connected to", or "is connected" refer to any manner known in the art or developed later that allows energy to transfer between two or more elements, and contemplate the insertion of one or more additional elements, although not necessarily. The terms "directly coupled", "directly connected", etc. mean that the connected elements are continuous or connected via a conductor to transmit an electrical signal.

[0016] In an embodiment, the present invention provides a critical conduction mode (CRM) bridgeless power factor correction (PFC) system, which includes a bridgeless PFC converter, a zero current detection (ZCD) circuit, a zero voltage switching (ZVS) detection circuit, and a processor. The bridgeless PFC converter receives a power supply voltage and outputs first and second voltages. The ZCD circuit is connected to the bridgeless PFC converter and includes first and second voltage divider circuits, first and second comparators, and a selection circuit. The first voltage divider circuit receives the power supply voltage and outputs a third voltage. The second voltage divider circuit is connected to the bridgeless PFC converter to receive the first voltage and outputs a fourth voltage. The first and second comparators are connected to the first and second voltage divider circuits to receive the third and fourth voltages and respectively output first and second comparison signals. The selection circuit is connected to the first and second comparators to receive the first and second comparison signals and outputs a ZCD signal. The ZCD signal indicates the zero current state of the bridgeless PFC converter. The ZVS detection circuit is connected to the bridgeless PFC converter to receive the first and second voltages and is connected to the ZCD circuit to receive the ZCD signal. The ZVS detection circuit outputs a ZVS flag signal. The processor is connected to the ZCD circuit and the ZVS detection circuit to receive the ZCD signal and the ZVS flag signal respectively, and is connected to the bridgeless PFC converter to receive the first and second voltages, and outputs a set of control signals for controlling the bridgeless PFC converter.

[0017] In another embodiment, the present invention provides a ZCD circuit for a PFC converter. The ZCD circuit includes first and second voltage divider circuits, first and second comparators, and a selection circuit. The first voltage divider circuit receives the power supply voltage and outputs a first voltage. The second voltage divider circuit is connected to the bridgeless PFC converter to receive a second voltage and outputs a third voltage. The first and second comparators are connected to the first and second voltage divider circuits to receive the first and third voltages and respectively output first and second comparison signals. The selection circuit is connected to the first and second comparators to receive the first and second comparison signals and outputs a ZCD signal. The ZCD signal indicates the zero current state of the bridgeless PFC converter.

[0018] Various embodiments of the present invention provide a CRM bridgeless PFC system. The CRM bridgeless PFC system includes a ZCD circuit for detecting the zero current state of the bridgeless PFC converter of the CRM bridgeless PFC system. The PFC converter outputs first and second voltages. The ZCD circuit is connected to the bridgeless PFC converter and an AC source to receive the first voltage and the power supply voltage respectively. The ZCD circuit outputs a ZCD signal based on the first voltage and the power supply voltage. The ZCD signal is also used by the ZVS detection circuit to generate a ZVS flag signal FS. The processor receives the power supply voltage, the first and second voltages, the ZCD signal, and the ZVS flag signal, and generates a set of control signals for controlling the PFC converter.

[0019] The CRM bridgeless PFC system eliminates the need to implement additional hardware, such as a rectifier circuit system, a sampling circuit system, and multiple CT sensors, to detect the zero-current state, thereby reducing the area required for the ZCD circuit. Compared with traditional CRM bridgeless PFC systems, the space occupied by the PFC system, the cost of the PFC system, and the power consumed by the PFC system have all been improved. In addition, the ZCD signal is used as a timing control signal for real-time generation of the ZVS flag signal. Therefore, compared with traditional bridgeless PFC systems, the accuracy and reliability of controlling the PFC system have been improved.

[0020] Now referring to Figure 1 , a block diagram of a CRM bridgeless PFC system 100 according to an embodiment of the present invention is shown. The PFC system 100 includes an AC (alternating current) source 102, a bridgeless PFC converter 104, a polarity detection circuit 106, a zero-current detection (ZCD) circuit 108, a zero-voltage switching (ZVS) detection circuit 110, and a processor 112. The AC source 102 outputs an AC voltage, i.e., a power supply voltage VS.

[0021] The PFC converter 104 is connected to the AC source 102 for receiving the power supply voltage VS. The PFC converter 104 also receives first to fourth control signals CL1-CL4 (hereinafter referred to as "a set of control signals CL1-CL4") from the processor 112. The PFC converter 104 converts the power supply voltage VS into first and second DC (direct current) output voltages V1 and V2.

[0022] The polarity detection circuit 106 is connected to the AC source 102 for receiving the power supply voltage VS. The polarity detection circuit 106 outputs a polarity signal POL indicating the positive or negative half-cycle of the power supply voltage VS. In one embodiment, during the positive and negative half-cycles, the polarity detection circuit 106 generates a polarity signal POL in a logic high and logic low state, respectively. In another embodiment, during the positive and negative half-cycles, the polarity detection circuit 106 generates a polarity signal POL in a logic low and logic high state, respectively.

[0023] The ZCD circuit 108 is connected to the AC source 102, the bridgeless PFC converter 104, and the polarity detection circuit 106 for receiving the power supply voltage VS, the first voltage V1, and the polarity signal POL, respectively. The ZCD circuit 108 outputs a ZCD signal ZCDS indicating the zero-current state of the PFC converter 104. During the positive half-cycle, when the first voltage V1 is less than the power supply voltage VS, the ZCD signal ZCDS is activated. During the negative half-cycle, when the first voltage V1 is greater than the power supply voltage VS, the ZCD signal ZCDS is activated.

[0024] The ZVS detection circuit 110 is connected to the bridgeless PFC converter 104, the polarity detection circuit 106, and the ZCD circuit 108 to receive the first and second voltages V1 and V2, the polarity signal POL, and the ZCD signal ZCDS, respectively. The ZVS detection circuit 110 also receives a delay signal DS from the processor 112. The ZVS detection circuit 110 outputs a ZVS flag signal FS. During the positive half-cycle, when the ZCD signal ZCDS is activated and the first voltage V1 is less than the first threshold voltage Vth1, the ZVS flag signal FS is activated (i.e., the ZVS flag signal FS is in the logic high state) ( Figure 6 as shown in). The processor 112 determines the value of the first threshold voltage Vth1, which is used to determine whether the ideal switching conditions for valley switching of the first and second control signals CL1 and CL2 have been achieved. During the negative half-cycle, when the ZCD signal ZCDS is activated and the first voltage V1 is greater than the second voltage V2, the ZVS flag signal FS is activated.

[0025] The processor 112 is connected to the ZVS detection circuit 110 to receive the ZVS flag signal FS. The processor 112 is also connected to the AC source 102, the PFC converter 104, the polarity detection circuit 106, and the ZCD circuit 108 to receive the power supply voltage VS, the first and second voltages V1 and V2, the polarity signal POL, and the ZCD signal ZCDS, respectively. The processor 112 generates the set of control signals CL1 - CL4 for controlling the PFC converter 104. The processor 112 also generates a delay signal DS for controlling the ZVS detection circuit 110.

[0026] Now referring to Figure 2 , a circuit diagram of the PFC converter 104 according to an embodiment of the present invention is shown. The bridgeless PFC converter 104 includes an inductor 202 and first and second bridge arms 204 and 206 connected in parallel.

[0027] The inductor 202 has a first terminal connected to the AC source 102 for receiving the power supply voltage VS and a second terminal for outputting the first voltage V1.

[0028] The first bridge arm 204 includes first and second switches 207a and 207b connected in series, where a first node N1 is between the switches 207a and 207b. The first and second switches 207a and 207b include first and second transistors 208a and 208b connected in series. A second terminal of the inductor 202 is also connected to the first node N1. The first switch 207a further includes a first body diode 210a and a first body capacitor 212a. Similarly, the second switch 207b includes a second body diode 210b and a second body capacitor 212b. The first body diode 210a and the first body capacitor 212a are coupled in parallel to the first transistor 208a. Similarly, the second body diode 210b and the second body capacitor 212b are coupled in parallel to the second transistor 208b.

[0029] The second bridge arm 206 includes third and fourth switches 213a and 213b connected in series, and a second node N2 is between the switches 213a and 213b. The third and fourth switches 213a and 213b respectively include third and fourth transistors 214a and 214b, and the third and fourth transistors 214a and 214b are connected in series. The AC source 102 is also connected to the second node N2. The third and fourth transistors 214a and 214b are respectively connected to the first and second transistors 208a and 208b at third and fourth nodes N3 and N4. The third node N3 is also connected to ground. The third and fourth switches 213a and 213b respectively include third and fourth body diodes 216a and 216b. The third and fourth body diodes 216a and 216b are respectively coupled in parallel with the third and fourth transistors 214a and 214b.

[0030] The PFC converter 104 further includes a first capacitor 218 and a load 220, and the first capacitor 218 and the load 220 are each connected between the third and fourth nodes N3 and N4 such that they are connected in parallel with the first and second bridge arms 204 and 206.

[0031] The first transistor 208a has first and second terminals respectively connected to the first and third nodes N1 and N3. During the positive half-cycle, the first and second terminals of the first transistor 208a are the drain and source terminals respectively, while during the negative half-cycle, the first and second terminals are the source and drain terminals respectively. The first transistor 208a also has a gate terminal connected to the processor 112 for receiving a first control signal CL1. The second transistor 208b has first and second terminals respectively connected to the first and fourth nodes N1 and N4. During the positive half-cycle, the first and second terminals of the second transistor 208b are the drain and source terminals respectively, and during the negative half-cycle, the first and second terminals of the second transistor 208b are the source and drain terminals respectively. The gate of the second transistor 208b is connected to the processor 112 for receiving a second control signal CL2.

[0032] The third transistor 214a has first and second terminals connected to the second and third nodes N2 and N3, respectively. During the positive half-cycle, the first and second terminals are the drain and source terminals, respectively, and during the negative half-cycle, the first and second terminals are the source and drain terminals, respectively. The gate of the third transistor 214a is connected to the processor 112 to receive a third control signal CL3. The fourth transistor 214b has first and second terminals connected to the second and fourth nodes N2 and N4, respectively. During the positive half-cycle, the first and second terminals are the drain and source terminals, respectively, and during the negative half-cycle, the first and second terminals are the source and drain terminals, respectively. The gate of the fourth transistor 214b is connected to the processor 112 to receive a fourth control signal CL4.

[0033] The first to fourth transistors 208a, 208b, 214a, and 214b are controlled by the set of control signals CL1-CL4. In one embodiment, when the set of control signals CL1-CL4 are respectively activated, the first to fourth transistors 208a, 208b, 214a, and 214b are activated. In another embodiment, when the set of control signals CL1-CL4 are respectively deactivated, the first to fourth transistors 208a, 208b, 214a, and 214b are activated.

[0034] The first transistor 208a serves as an active switch and a free-wheeling switch during the positive and negative half-cycles, respectively, and the second transistor 208b serves as a free-wheeling switch and an active switch during the positive and negative half-cycles, respectively. In one embodiment, the first and second transistors 208a and 208b are gallium nitride (GaN) high electron mobility transistors (HEMTs), and the third and fourth transistors 214a and 214b are silicon transistors. During the positive half-cycle of VS, when the inductor 202 is charging, the first and third transistors 208a and 214a are activated and the second and fourth transistors 208b and 214b are deactivated, and when the inductor 202 is discharging, the second and third transistors 208b and 214a are activated and the first and fourth transistors 208a and 214b are deactivated. Further, during the negative half-cycle, when the inductor 202 is charging, the second and fourth transistors 208b and 214b are activated and the first and third transistors 208a and 214a are deactivated, and when the inductor 202 is discharging, the first and fourth transistors 208a and 214b are activated and the second and third transistors 208b and 214a are deactivated.

[0035] Now refer to Figure 3A, showing a circuit diagram of the ZCD circuit 108 according to an embodiment of the present invention. The ZCD circuit 108 includes first and second voltage divider circuits 302a and 302b, first and second comparators 304a and 304b, and a first selection circuit 306.

[0036] The first voltage divider circuit 302a includes first to third resistors 308a - 308c connected in series. The first resistor 308a has a first terminal connected to the AC source 102 for receiving the power supply voltage VS. The second resistor 308b is connected between the first and third resistors 308a and 308c, and the third resistor 308c is connected between the second resistor 308b and ground. A first voltage tap exists between the second and third resistors 308b and 308c. The second capacitor 310 is connected in parallel to the third resistor 308c. The first voltage divider circuit 302a outputs a third voltage V3 at the first voltage tap.

[0037] The second voltage divider circuit 302b includes fourth to sixth resistors 312a - 312c, which are connected in series between a first node (where the first voltage V1 is generated) and ground. More specifically, the fourth resistor 312a has a first terminal connected to the second terminal of the inductor 202 for receiving the first voltage V1. The fifth resistor 312b is connected between the fourth and sixth resistors 312a and 312c, and the sixth resistor 312c is connected between the fifth resistor 312b and ground. A fourth voltage V4 is output from a second voltage tap located between the fifth and sixth resistors 312b and 312c. The third capacitor 314 is connected in parallel to the sixth resistor 312c.

[0038] The non - inverting and inverting (positive and negative) input terminals of the first comparator 304a receive the third and fourth voltages V3 and V4 from the first and second taps of the first and second voltage dividers 302a and 302b. The first comparator 304a outputs a first comparison signal Vc1. In one embodiment, when the fourth voltage V4 is greater than and less than the third voltage V3 respectively, the first comparator 304a outputs the first comparison signal Vc1 in the logic low and high states.

[0039] The non - inverting and inverting (positive and negative) input terminals of the second comparator 304b receive the fourth and third voltages V4 and V3 respectively. The second comparator 304b outputs a second comparison signal Vc2. In one embodiment, when the fourth voltage V4 is greater than the third voltage V3, the second comparison signal Vc2 is high, and when V4 is less than V3, Vc2 is low.

[0040] The first selection circuit 306 includes first and second switches 316a and 316b having first terminals connected to output terminals of first and second comparators 304a and 304b for receiving first and second comparison signals Vc1 and Vc2, respectively.

[0041] The ZCD circuit 108 further includes a first logic gate 318 connected to the polarity detection circuit 106 for receiving a polarity signal POL and generating / POL. In one embodiment, the first logic gate 318 is a "NOT" gate. Thus, the first logic gate 318 outputs an inverted version IPOL (hereinafter simply referred to as "IPOL") of the polarity signal. The first and second switches 316a and 316b have control terminals connected to the polarity detection circuit 106 and the first logic gate 318 for receiving POL and IPOL, respectively, for controlling switching operations of the first and second switches 316a and 316b. Thus, the first and second switches 316a and 316b are activated in the positive and negative half-cycles, respectively. The second terminals of the first and second switches 316a and 316b are connected together and provide a ZCD signal to output the ZCD signal at this connection. When the first and second switches 316a and 316b are activated during the positive and negative half-cycles, the first selection circuit 306 outputs the ZCD signal ZCDS as the first and second comparison signals Vc1 and Vc2, respectively.

[0042] Now referring to Figure 3B , a timing diagram 300 is shown illustrating the generation of the ZCD signal ZCDS in the positive and negative half-cycles according to an embodiment of the present invention.

[0043] During the positive half-cycle, the polarity detection circuit 106 outputs a polarity signal POL in a logic high state. In addition, the processor 112 activates the third control signal CL3 and deactivates the fourth control signal CL4. Thus, the third transistor 214a is activated and the fourth transistor 214b is deactivated. In addition, the first transistor 208a acts as an active switch while the second transistor 208b acts as a freewheeling switch. The inductor current IL passes through the first transistor 208a, the third transistor 214a, and the inductor 202 when the inductor 202 is charging, and passes through the second transistor 208b, the first capacitor 218, the load 220, the third transistor 214a, and the inductor 202 when the inductor 202 is discharging.

[0044] At time T 0, the inductor current IL is at the zero current value. The first control signal CL1 is activated, and the second control signal CL2 is deactivated. Thus, the first transistor 208a is activated while the second transistor 208b is deactivated. Additionally, the first voltage V1 is at the zero voltage level and the supply voltage VS is greater than the first voltage V1. Therefore, the ZCD circuit 108 asserts the ZCD signal ZCDS.

[0045] During the time period T 0 -T 1 the first and second control signals CL1 and CL2 remain unchanged. Thus, the inductor 202 is charged and the inductor current IL rises from the zero current value to the first peak value of the inductor current IL. Additionally, the first voltage V1 remains at the zero voltage level, so the ZCD signal ZCDS remains at the logic high state unchanged.

[0046] At time T 1 , the inductor current IL is at the first peak value. The first control signal CL1 transitions from the active state to the inactive state. Thus, the first transistor 208a is deactivated. Additionally, the second control signal CL2 remains unchanged. The first voltage V1 rapidly rises from the zero voltage level to the first voltage level, which is at the voltage level of the second voltage V2 and greater than the supply voltage VS. Therefore, the ZCD signal ZCDS transitions from high to low.

[0047] During the time period T 1 -T 2 the first and second control signals CL1 and CL2 remain unchanged. Thus, the first and second transistors 208a and 208b remain deactivated. As a result, the inductor 202 starts to discharge through the second body diode 210b, and the inductor current IL starts to decrease from the first peak value to the first inductor current IL value. Additionally, the first voltage V1 remains unchanged, i.e., remains greater than the supply voltage VS. Therefore, the ZCD signal ZCDS remains low.

[0048] At time T 2 , the inductor current IL is at the first inductor current IL value. The first control signal CL1 remains unchanged. The second control signal CL2 transitions from the inactive state to the active state. Thus, the second transistor 208b is activated after the first dead time (i.e., the time period T 1 -T 2 ) to avoid a short circuit between the fourth node N4 and ground caused by simultaneously activating the first and second transistors 208a and 208b. Additionally, the first voltage V1 remains unchanged, so the ZCD signal ZCDS remains low.

[0049] During the time period T 2 -T 3During this period, the inductor current IL continues to decrease until it reaches the zero current value. The first and second control signals CL1 and CL2 remain unchanged. The first voltage V1 remains unchanged, so the ZCD signal ZCDS remains low.

[0050] At time T 3 , the inductor current IL reaches the zero current value. The first control signal CL1 remains unchanged. The second control signal CL2 changes from the active state to the inactive state. As a result, the second transistor 208b is deactivated. The inductor 202 and the first and second body capacitors 212a and 212b start to resonate. The first voltage V1 remains unchanged, that is, remains greater than the power supply voltage VS, so the ZCD signal ZCDS remains low.

[0051] During the time period T 3 -T 4 During this period, since the first and second control signals CL1 and CL2 remain unchanged, the first and second transistors 208a and 208b are deactivated. As a result, a reverse current flows through the inductor 202, that is, the inductor current IL drops below the zero current value to reach the second peak value of the inductor current IL, and then starts to rise. As a result, the first voltage V1 starts to drop to the voltage level of the power supply voltage VS. The ZCD signal ZCDS remains unchanged in the logic low state.

[0052] At time T 4 , the first and second control signals CL1 and CL2 remain unchanged. Therefore, the inductor 202 and the first and second body capacitors 212a and 212b continue to resonate. The inductor current IL is greater than the second peak value, and the first voltage V1 is less than the power supply voltage VS. Therefore, the ZCD signal ZCDS changes from low to high.

[0053] During the time period T 4 -T 5 During this period, the first and second control signals CL1 and CL2 remain unchanged. Therefore, the inductor 202 and the first and second body capacitors 212a and 212b continue to resonate. The inductor current IL continues to rise from the second peak value to the zero current value. In addition, the first voltage V1 starts to drop below the power supply voltage VS to reach the second voltage level. The ZCD signal ZCDS remains high.

[0054] At time T 5 , the inductor current IL reaches the zero current value, and the first control signal CL1 changes from the inactive state to the active state. Therefore, the first transistor 208a is in the second dead time (i.e., the time period T 3 -T 5is then activated to allow the inductor current IL to reach a zero-current value. The second control signal CL2 remains unchanged. Further, the first voltage V1 reaches a zero-voltage level from a second voltage level. The ZCD signal ZCDS remains unchanged in a logic high state.

[0055] Time period T 0 -T 5 represents a first switching period. Further, the processor 112 determines the conduction time of the second transistor 208b (i.e., the duration of the time period T 2 -T 3 ), as explained below in Figure 5 and Figure 6 . It will be apparent to those skilled in the art that the positive half-cycle may have a plurality of switching periods similar to the first switching period. For example, the time period T 5 -T 10 may represent a second switching period, wherein the first and second control signals CL1 and CL2, the ZCD signal ZCDS, the inductor current IL, and the first voltage V1 transition in a manner similar to the transitions in the first switching period. Further, one switching period of the positive half-cycle and the negative half-cycle corresponds to the charging and subsequent discharging of the inductor 202.

[0056] During the negative half-cycle (i.e., the time period T 11 -T 19 ), the polarity detection circuit 106 outputs a polarity signal POL in a logic low state. Further, the processor 112 outputs third and fourth control signals CL3 and CL4 in logic low and high states, respectively. Accordingly, the third transistor 214a is deactivated and the fourth transistor 214b is activated. Further, the second transistor 208b serves as an active switch, and the first transistor 208a serves as a freewheeling switch. It will be apparent to those skilled in the art that the processor 112 controls the transitions of the first and second control signals CL1 and CL2 during the negative half-cycle in a manner similar to the transitions of the second and first control signals CL2 and CL1 during the positive half-cycle.

[0057] During the negative half-cycle, the operation of the bridgeless PFC system 100 is similar to the operation of the bridgeless PFC system 100 during the positive half-cycle. Further, the polarity of the inductor current IL is reversed, and the inductor current IL is at time T 12Reaches the third peak. In addition, the inductor current IL passes through the fourth transistor 214b, the second transistor 208b, and the inductor 202 when the inductor 202 is charging, and passes through the fourth transistor 214b, the first capacitor 218, the load 220, the first transistor 208a, and the inductor 202 when the inductor 202 is discharging. When the first voltage V1 is greater than and less than the supply voltage VS, the ZCD circuit 108 outputs the ZCD signal ZCDS in the logic high and low states. In addition, from time T 14 -T 16 The manner in which the first voltage V1 rises from the zero voltage level to the second voltage level is similar to the manner in which the first voltage V1 falls from the first voltage level to the second voltage level. Those skilled in the art will understand that when the second control signal CL2 remains active, that is, in the time period T 11 -T 12 and T 16 -T 17 During this period, the first voltage V1 remains greater than the supply voltage VS. In addition, the ZCD signal ZCDS transitions from high to low and from low to high in a manner similar to the transitions explained above for the time T 0 -T 10 at the time T 11 -T 19 .

[0058] Now referring to Figure 4 , a circuit diagram of the ZVS detection circuit 110 according to an embodiment of the present invention is shown. The ZVS detection circuit 110 includes a delay element 402, a latch 404, second and third selection circuits 406a and 406b, and third and fourth comparators 408 and 410.

[0059] The delay element 402 is connected to the first selection circuit 306 for receiving the ZCD signal ZCDS. In addition, the delay element 402 is connected to the processor 112 for receiving the delay signal DS. The delay element 402 delays the ZCD signal ZCDS and outputs a delayed version of the ZCD signal ZCDS, which is hereinafter referred to as the delayed ZCD signal DZCD. Thus, the delay element 402 delays the ZCD signal ZCDS by a first delay value, which is based on the delay signal DS. When the supply voltage VS is greater than half of the second voltage V2, the first delay value is a fixed delay value, for example, as shown in Figure 6 the duration of the time period T 4 -T 5 as a constant value. In addition, when the supply voltage VS is less than half of the second voltage V2, the first delay value is a variable delay value.

[0060] The latch 404 has first and second input terminals respectively connected to the first selection circuit 306 and the delay element 402 for receiving the ZCD signal ZCDS and the delayed ZCD signal DZCD. When the ZCD signal ZCDS and the delayed ZCD signal DZCD are in the logic high and low states respectively, the latch 404 outputs a latch output signal VL in the logic high state. When the ZCD signal ZCDS and the delayed ZCD signal DZCD are in the logic low and high states respectively, the latch 404 outputs a latch output signal VL in the logic low state. In one embodiment, the latch 404 is a set / reset (SR) latch.

[0061] The second selection circuit 406a includes third and fourth switches 412a and 412b. The first terminals of the third and fourth switches 412a and 412b are connected to the bridgeless PFC converter 104 for receiving first and second voltages V1 and V2 respectively. In one embodiment, the ZVS detection circuit 110 further includes a second logic gate 414. The second logic gate 414 is connected to the polarity detection circuit 106 for receiving the polarity signal POL and generating / POL. That is, in one embodiment, the second logic gate 414 is a "NOT" gate that receives POL and generates an inverted polarity signal IPOL. In another embodiment, the fourth switch 412b is connected to the output terminal of the first logic gate 318 for receiving the inverted polarity signal IPOL.

[0062] The third and fourth switches 412a and 412b have control terminals connected to the polarity detection circuit 106 and the second logic gate 414 for receiving POL and IPOL. The control terminals respectively control the switching operations of the third and fourth switches 412a and 412b. Therefore, the third and fourth switches 412a and 412b are respectively activated in the positive and negative half-cycles. The second terminals of the third and fourth switches 412a and 412b are connected together for outputting one of the first and second voltages V1 and V2. When the third and fourth switches 412a and 412b are activated, the second selection circuit 406a outputs the first and second voltages V1 and V2 respectively.

[0063] The third selection circuit 406b includes fifth and sixth switches 416a and 416b. The first terminals of the fifth and sixth switches 416a and 416b are respectively connected to a threshold generator (not shown) and the PFC converter 104 to receive a first threshold voltage Vth1 and a first voltage V1. The first threshold voltage Vth1 is a predetermined value. The fifth and sixth switches 416a and 416b have control terminals respectively connected to the polarity detection circuit 106 and the second logic gate 414 to receive POL and IPOL, and the control terminals respectively control the switching operations of the fifth and sixth switches 416a and 416b. Therefore, the fifth and sixth switches 416a and 416b are respectively activated in the positive and negative half-cycles. The second terminals of the fifth and sixth switches 416a and 416b are connected together to output one of the first threshold voltage Vth1 and the first voltage V1. When the fifth and sixth switches 416a and 416b are activated, the third selection circuit 406b outputs the first threshold voltage Vth1 and the first voltage V1 respectively.

[0064] The first and second terminals of the third comparator 408 are non-inverting and inverting terminals, and are respectively connected to the second and third selection circuits 406a and 406b. The third comparator 408 also has a control terminal connected to the latch 404 to receive the latch output signal VL. During the positive half-cycle, the third comparator 408 receives the first voltage V1 and the first threshold voltage Vth1 from the second and third selection circuits 406a and 406b respectively. During the negative half-cycle, the third comparator 408 receives the second and first voltages V2 and V1 from the second and third selection circuits 406a and 406b respectively.

[0065] The third comparator 408 outputs a third comparison signal Vc3. During the positive half-cycle, when the latch output signal VL is in the logic high state and the first threshold voltage Vth1 is greater than the first voltage V1, the third comparator 408 outputs a third comparison signal Vc3 in the logic high state. When the latch output signal VL is high and the first threshold voltage Vth1 is less than the first voltage V1, the third comparator 408 outputs a third comparison signal Vc3 in the logic low state.

[0066] During the negative half-cycle, when the latch output signal VL is high and the first voltage V1 is greater than the second voltage V2, the third comparator 408 outputs a third comparison signal Vc3 in the logic high state. In addition, when the latch output signal VL is high and the first voltage V1 is less than the second voltage V2, the third comparator 408 outputs a third comparison signal Vc3 in the logic low state.

[0067] The fourth comparator 410 has an inverting, a non-inverting, and a control terminal, which are connected to the threshold generator, the third comparator 408, and a driver circuit (not shown) for receiving the second threshold voltage Vth2, the third comparison signal Vc3, and the trigger voltage Vtrig, respectively. The second threshold voltage Vth2 is a predetermined value and is used as a reference signal for determining whether the third comparison signal Vc3 is high or low. During the positive half-cycle, when the first control signal CL1 transitions from an inactive state to an active state, the driver circuit outputs the trigger voltage Vtrig in a logic high state. When the first control signal CL1 transitions from an active state to an inactive state, the driver circuit outputs the trigger voltage Vtrig in a logic low state. During the negative half-cycle, when the second control signal CL2 transitions from an inactive state to an active state, the driver circuit outputs the trigger voltage Vtrig in a logic high state. When the second control signal CL2 transitions from an active state to an inactive state, the driver circuit outputs the trigger voltage Vtrig in a logic low state.

[0068] The fourth comparator 410 generates a ZVS flag signal FS. The ZVS flag signal FS indicates the voltage across the active switch of the PFC converter 104 when the active switch transitions from an inactive state to an active state. Thus, during the positive half-cycle, the ZVS flag signal FS indicates the voltage across the first transistor 208a. When the trigger voltage Vtrig is high, the first voltage V1 is less than the first threshold voltage Vth1, and the ZCD signal ZCDS is active, the ZVS flag signal FS is asserted, i.e., high. When the trigger voltage Vtrig is high and the first voltage V1 is greater than the first threshold voltage Vth1, the ZVS flag signal FS is de-asserted (i.e., low).

[0069] During the negative half-cycle, the ZVS flag signal FS indicates the voltage across the second transistor 208b. Thus, when the trigger voltage Vtrig is high, the first voltage V1 is greater than the second voltage V2, and the ZCD signal ZCDS is active, the ZVS flag signal FS is high. Additionally, when the trigger voltage Vtrig is high and the first voltage V1 is less than the second voltage V2, the ZVS flag signal FS is low.

[0070] Now referring to Figure 5 , a flow 500 is shown that illustrates the operation of the processor 112 according to an embodiment of the present invention.

[0071] In step 502, the processor 112 determines the conduction times of the active switch in the positive and negative half-cycles based on the voltage output in the control loop, i.e., the periods during which the first and second transistors 208a and 208b are respectively kept active.

[0072] In step 504, the processor 112 determines the nominal on-time Tb of the transistor implementing the freewheeling switch through the volt-second balance relationship of the inductor 202, that is, determines the nominal on-times of the first and second transistors 208a and 208b in the negative and positive half-cycles respectively. For example, the nominal on-time of the second transistor 208b used as the freewheeling switch is from time T 2 -T 3 (see Figure 6 ).

[0073] In step 506, the processor 112 checks the current state of the ZVS flag signal FS through the ZVS detection circuit 110 (i.e., the processor 112 reads the current logic state of the ZVS flag signal FS). The current state is a value indicating the current voltage level of the first voltage V1 across the transistor used as the active switch when the active switch transitions from the inactive state to the active state in the current switching cycle.

[0074] In step 508, the processor 112 determines whether the ZVS flag signal FS is in the logic high state. If not (the ZVS flag signal FS is low), step 510 is executed, and if so (the ZVS flag signal FS is high), step 512 is executed.

[0075] In step 510, the processor 112 determines the offset compensation time ΔTb_n+1 for offsetting the nominal on-time Tb of the freewheeling switch in the next switching cycle (e.g., Figure 6 the second switching cycle in). The offset compensation time ΔTb_n+1 is determined based on the current compensation time (i.e., ΔTb_n) of the freewheeling switch in the current switching cycle (e.g., Figure 6 the first switching cycle in) using equation (1):

[0076] ΔTb_n+1 = ΔTb_n + Δt1 (1)

[0077] where

[0078] Δt1 is the first offset value determined by the processor 112. For example, the difference between the time period T 2 -T 3 (as shown in Figure 6 ) and the time period T 7 -T 9 (see Figure 6 ) is the first offset value Δt1. The first offset value is used to change the offset compensation time. In this example, the time period T 8 -T 9 (see Figure 6 ) is the current compensation time ΔTb_n, and the time period T 14-T 15 (See Figure 6 ) is the offset compensation time ΔTb_n+1 determined using Equation (1).

[0079] Alternatively, in step 512, the processor 112 determines the offset compensation time for the next switching cycle based on the current compensation time using Equation (2):

[0080] ΔTb_n+1 = ΔTb_n - Δt2 (2)

[0081] where

[0082] Δt2 is the second offset value determined by the processor 112. For example, the time period T 14 -T 15 ( Figure 6 ) and the difference between the time period T 21 -T 22 ( Figure 6 ) is the second offset value Δt2. The second offset value is used to change the offset compensation time. In this example, the time period T 14 -T 15 ( Figure 6 ) is the current compensation time ΔTb_n, and the time period T 21 -T 22 ( Figure 6 ) is the offset compensation time ΔTb_n+1 determined using Equation (2).

[0083] Both steps 510 and 512 then perform step 514. In step 514, the processor 112 determines whether the supply voltage VS is greater than half of the second voltage V2. If in step 514, the processor 112 determines that the supply voltage VS is greater than half of the second voltage V2, then step 516 is performed, and if not, then step 518 is performed.

[0084] In step 516, the processor 112 sets the conduction time Tb_n+1 of the freewheeling switch for the next switching cycle using Equation (3), for example, the conduction time of the second transistor 208b in the positive half-cycle:

[0085] Tb_n+1 = Tb + ΔTb_n+1 (3)

[0086] where

[0087] Tb is the nominal conduction time of the freewheeling switch, and

[0088] ΔTb_n+1 is the offset compensation time determined by the processor 112. For example, the time period T 13 -T 15 ( Figure 6) is the current conduction time Tb_n of the freewheeling switch, i.e., the second transistor 208b, and the time period T 20 -T 22 ( Figure 6 ) is the conduction time Tb_n+1 of the second transistor 208b, which varies based on Equation (3).

[0089] If at step 514, the processor 112 determines that the supply voltage VS is less than half of the second voltage V2, then step 518 is executed. At step 518, the processor 112 sets the first delay value (designated as "Td_n+1") for the next switching cycle using Equation (4):

[0090] Td_n+1 = Td_n + ΔTb_n+1 (4)

[0091] where

[0092] Td_n is the current first delay value, and ΔTb_n+1 is the offset compensation time determined by the processor 112.

[0093] The time period T 4 -T 5 (see Figure 6 ) is the current first delay value (i.e., Td_n), and the time period T 10 -T 11 ( Figure 6 ) is the first delay value (i.e., Td_n+1) for the next switching cycle and varies based on Equation (4).

[0094] When the supply voltage VS is less than half of the second voltage V2, the processor 112 changes the first delay value of the delay element 402. Thus, when the second transistor 208b is deactivated during the positive half-cycle, the first transistor 208a is activated when the first duration has passed after the ZCD signal ZCDS is activated. Similarly, when the first transistor 208a is deactivated during the negative half-cycle, the second transistor 208b is activated when the second duration has passed after the ZCD signal ZCDS is deactivated. During the positive and negative half-cycles, the first and second durations correspond to the first delay value.

[0095] Now refer to Figure 6, a timing diagram 600 is shown which illustrates the operation of the bridgeless PFC system 100 in the positive half-cycle according to an embodiment of the present invention. In the positive half-cycle, the polarity detection circuit 106 outputs a polarity signal POL in the logic high state. The processor 112 also outputs a third control signal CL3 in the logic high state and a fourth control signal CL4 in the logic low state. Therefore, the third transistor 214a is activated while the fourth transistor 214b is deactivated. The first transistor 208a acts as an active switch, and the second transistor 208b acts as a freewheeling switch.

[0096] At time T 0 , the inductor current IL is at the zero current value. In addition, the first and second control signals CL1 and CL2 are activated and deactivated respectively. Therefore, the first and second transistors 208a and 208b are activated and deactivated respectively. The first voltage V1 is less than the first threshold voltage Vth1. In addition, the ZCD signal ZCDS is in the logic high state, and the latch output signal VL is in the logic low state. The third comparison signal Vc3 and the ZVS flag signal FS are in the logic high state.

[0097] During the time period T 0 -T 1 , the inductor current IL rises from the zero current value to the first peak, thereby charging the inductor 202. The first and second control signals CL1 and CL2 and the ZCD signal ZCDS remain unchanged. Since both the ZCD signal ZCDS and the delayed ZCD signal DZCD are high, the latch output signal VL also remains unchanged in the logic low state. Therefore, the third comparison signal Vc3 remains unchanged in the logic high state, that is, remains greater than the second threshold voltage Vth2. Therefore, the ZVS flag signal FS remains unchanged in the logic high state.

[0098] At time T 1 , the inductor current IL is at the first peak. The first control signal CL1 changes from the active state to the inactive state, thereby deactivating the first transistor 208a. Therefore, the time period T 0 -T 1corresponding to the conduction time of the first transistor 208a. The second control signal CL2 remains unchanged, and thus, the second transistor 208b remains deactivated. When the first transistor 208a is deactivated, the inductor 202 and the first and second body capacitors 212a and 212b start to resonate, and the first voltage V1 rapidly rises from the zero voltage level to the first voltage level, i.e., the voltage level of the second voltage V2. In addition, when the first voltage V1 is at the voltage level of the second voltage V2, the inductor 202 starts to discharge through the second body diode 210b. The first voltage V1 is greater than the supply voltage VS, so the ZCD signal ZCDS changes from high to low. In addition, the latch output signal VL remains unchanged in the logic low state. Therefore, the third comparison signal Vc3 and the ZVS flag signal FS remain unchanged in the logic high state.

[0099] During the time period T 1 -T 2 the first control signal CL1 and the second control signal CL2 remain unchanged, so the first and second transistors 208a and 208b remain deactivated. Thus, the inductor 202 starts to discharge through the second body diode 210b, and the inductor current IL starts to decrease from the first peak value to reach the first inductor current IL value. The first voltage V1 remains unchanged, i.e., remains greater than the supply voltage VS. Therefore, the ZCD signal ZCDS and the latch output signal VL remain unchanged in the logic low state, and the third comparison signal Vc3 and the ZVS flag signal FS remain unchanged in the logic high state.

[0100] At time T 2 the second control signal CL2 changes from the inactive state to the active state. Thus, the second transistor 208b is activated after the first dead time. The first control signal CL1 remains unchanged. The inductor current IL is at the first inductor current IL value. The first voltage V1 remains unchanged, i.e., remains greater than the supply voltage VS. Therefore, the ZCD signal ZCDS and the latch output signal VL remain unchanged in the logic low state, and the third comparison signal Vc3 and the ZVS flag signal FS remain unchanged in the logic high state.

[0101] During the time period T 2 -T 3 the inductor current IL continues to decrease until it reaches the zero current value, causing the inductor 202 to discharge. The first and second control signals CL1 and CL2 and the first voltage V1 remain unchanged. As a result, the ZCD signal ZCDS and the latch output signal VL remain unchanged in the logic low state, and the third comparison signal Vc3 and the ZVS flag signal FS remain unchanged in the logic high state.

[0102] At time T 3, the first control signal CL1 remains unchanged, and the second control signal CL2 transitions from an active state to an inactive state. Consequently, the second transistor 208b is deactivated. Thus, the time period T 2 -T 3 corresponds to the conduction time of the second transistor 208b. Additionally, the inductor 202 and the first and second body capacitors 212a and 212b start to resonate. The inductor current IL reaches a zero-current value, and the first voltage V1 remains greater than the supply voltage VS. As a result, the ZCD signal ZCDS and the latch output signal VL remain unchanged in the logic low state, and the third comparison signal Vc3 and the ZVS flag signal FS remain unchanged in the logic high state.

[0103] During the time period T 3 -T 4 , since the first and second control signals CL1 and CL2 remain unchanged, the first and second transistors 208a and 208b are deactivated. Thus, a reverse current flows through the inductor 202, i.e., the inductor current IL drops below the zero-current value to reach a second peak value and then starts to rise. Additionally, the first voltage V1 starts to drop to the voltage level of the supply voltage VS. The ZCD signal ZCDS and the latch output signal VL remain unchanged in the logic low state. The third comparison signal Vc3 and the ZVS flag signal FS remain unchanged in the logic high state.

[0104] At time T 4 , the first and second control signals CL1 and CL2 remain unchanged. Thus, the inductor 202 and the first and second body capacitors 212a and 212b continue to resonate. The inductor current IL is greater than the second peak value, and the first voltage V1 is less than the supply voltage VS. The ZCD signal ZCDS transitions from low to high. Consequently, the latch output signal VL transitions from low to high. Additionally, the third comparison signal Vc3 transitions from high to low (i.e., the voltage level of the third comparison signal Vc3 drops below the second threshold voltage Vth2). When the trigger voltage Vtrig is in the logic low state, the ZVS flag signal FS remains unchanged in the logic high state.

[0105] During the time period T 4 -T 5 , the first and second control signals CL1 and CL2 remain unchanged. Thus, the inductor 202 and the first and second body capacitors 212a and 212b continue to resonate. Therefore, the inductor current IL continues to rise to the zero-current value, and the first voltage V1 continues to drop and is less than the supply voltage VS. The ZCD signal ZCDS and the latch output signal VL remain unchanged in the logic high state. The third comparison signal Vc3 remains unchanged in the logic low state, and the ZVS flag signal FS remains unchanged in the logic high state.

[0106] At time T 5 , the inductor current IL reaches the zero-current value. In addition, the first control signal CL1 changes from the inactive state to the active state, thereby activating the first transistor 208a after the second dead time. The second control signal CL2 remains unchanged. The first voltage V1 drops to the zero voltage level. The ZCD signal ZCDS remains unchanged in the logic high state. The latch output signal VL changes from the logic high state to the logic low state (because the delayed ZCD signal DZCD changes from the logic low state to the logic high state due to the delay value equal to the time period T 4 -T 5 ). The third comparison signal Vc3 remains unchanged in the logic low state. Since the voltage level of the third comparison signal Vc3 is less than the second threshold voltage Vth2, the ZVS flag signal FS changes from high to low.

[0107] The time period T 0 -T 5 is the first switching period. Based on the ZVS flag signal FS at time T 5 and the first to third equations (1)-(3), the processor 112 sets the conduction time of the second transistor 208b for the next switching period T 5 -T 11 .

[0108] The inductor current IL, the first control signal CL1, the ZCD signal ZCDS, and the latch output signal VL change periodically in the time periods T 5 -T 11 , T 11 -T 18 and T 18 -T 25 in the same manner as explained in the first switching period T 0 -T 5 . The conduction time of the second control signal CL2 changes based on the ZVS flag signal FS. Therefore, as explained above with reference to Figure 5 , based on the ZVS flag signal FS, at time T 9 , T 15 and T 22 , the second transistor 208b is deactivated.

[0109] The ZVS flag signal FS goes low at time T 0 -T 5 in the first switching period T 5 . Therefore, the processor 112 increases the conduction time of the second transistor 208b in the second switching period T 5 -T 11 based on equations (1) and (3), as explained above with reference to Figure 5 . At time T8 The inductor current IL drops to the zero-current value. However, the second control signal CL2 remains active. Accordingly, the second transistor 208b remains active. During the time period T 8 -T 9 the inductor current IL drops below the zero-current value, and the first and second control signals CL1 and CL2, the ZCD signal ZCDS, and the third comparison signal Vc3 remain unchanged.

[0110] At time T 9 the second control signal CL2 transitions from the active state to the inactive state, deactivating the second transistor 208b. The inductor 202 and the first and second body capacitors 212a and 212b begin to resonate. Accordingly, a reverse current flows through the inductor 202, i.e., the inductor current IL drops below the zero-current value. Accordingly, the first voltage V1 drops to a voltage level closer to the first threshold voltage Vth1.

[0111] In the second switching period T 5 -T 11 the ZVS flag signal FS remains unchanged in the logic low state. Accordingly, as described above, the processor 112 increases the on-time of the second transistor 208b based on equations (1) and (3) in the third switching period T 11 -T 18 At time T 14 the inductor current IL drops to the zero-current value. However, the second control signal CL2 remains active. Accordingly, the second transistor 208b remains active. During the time period T 14 -T 15 the inductor current IL drops below the zero-current value, and the first and second control signals CL1 and CL2, the ZCD signal ZCDS, and the third comparison signal Vc3 remain unchanged.

[0112] At time T 15 the second control signal CL2 transitions from the active state to the inactive state, deactivating the second transistor 208b. The offset compensation time T 11 -T 18 in the third switching period T 14 -T 15 is greater than the offset compensation time T 5 -T 11 in the second switching period T 8 -T 9 . Accordingly, at the moment T 17 the first voltage V1 is less than the first threshold voltage Vth1. Further, the latch output signal VL is in the logic high state. Accordingly, the third comparison signal Vc3 transitions from the logic low state to the logic high state.

[0113] At time T 18 , the first control signal CL1 transitions from an inactive state to an active state, thereby activating the first transistor 208a. Additionally, the third comparison signal Vc3 is greater than the second threshold voltage Vth2, so the ZVS flag signal FS transitions from a logic low state to a logic high state.

[0114] The ZVS flag signal FS transitions to a logic high state at time T in the third switching period T 11 -T 18 . Thus, as previously explained, the processor 112 decreases the conduction time of the second transistor 208b based on equations (2) and (3) in the fourth switching period T 18 -T 18 . At time T 25 , the inductor current IL drops to a zero current value. However, the second control signal CL2 remains active. Thus, the second transistor 208b remains active. During the time period T 21 -T 21 , the inductor current IL drops below the zero current value, and the first and second control signals CL1 and CL2, the ZCD signal ZCDS, and the third comparison signal Vc3 remain unchanged. 22 During the time period T

[0115] At time T 22 , the second control signal CL2 transitions from an active state to an inactive state, thereby deactivating the second transistor 208b. The offset compensation time T 18 -T 25 in the fourth switching period T 21 -T 22 is less than the offset compensation time T 11 -T 18 in the third switching period T 14 -T 15 . This causes the first voltage V1 to drop to a zero voltage level at a time closer to time T 25 when the first transistor 208a is activated.

[0116] The ZCD circuit 108 uses configurable comparators (i.e., the first and second comparators 304a and 304b) and a sampling circuitry (not shown) of the ZVS detection circuit 110. Thus, the need for a separate sampling circuitry to sample the first and supply voltages V1 and VS is eliminated. In addition, the sampling of the first voltage V1 and the supply voltage VS by the ZVS detection circuit 110 ensures that the first voltage V1 and the supply voltage VS are maintained at a positive voltage level during both the positive and negative half-cycles. Thus, the need for a rectifier circuit in the bridgeless PFC system 100 is eliminated. Therefore, the absence of a separate sampling circuitry and a rectifier circuit reduces the area occupied by the ZCD circuit 108. Additionally, the area and cost of the bridgeless PFC system 100 are less than those of a conventional bridgeless PFC system because the ZCD circuit requires less area.

[0117] The processor 112 outputs the first and second control signals CL1 and CL2 in real time based on the detection of the zero-current state by the ZCD circuit 108 without additional circuitry (such as a current transducer sensor for detecting the zero-current state). Thus, the power consumed by the bridgeless PFC system 100 is less than that of a conventional bridgeless PFC system that requires additional circuitry for detecting the zero-current state. Additionally, the ZCD signal ZCDS serves as a timing control signal for generating the ZVS flag signal FS in real time, resulting in better accuracy and reliability.

[0118] Those skilled in the art will understand that the same function can be performed by different arrangements of transistors that can operate using high-active or low-active signals. Therefore, variations in the arrangements of some of the above transistors should not be considered to depart from the scope of the present invention. When describing transistors, the terms gate, drain, and source may be used interchangeably with the corresponding terms "gate terminal", "drain terminal", and "source terminal".

[0119] Although various embodiments of the present invention have been illustrated and described, it is obvious that the present invention is not limited to these embodiments. Many modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art without departing from the spirit and scope of the present invention as set forth in the claims.

Claims

1. A critical conduction mode (CRM) bridgeless power factor correction (PFC) system, comprising: A bridgeless PFC converter that receives a power supply voltage and outputs a first voltage and a second voltage; A zero current detection (ZCD) circuit connected to the bridgeless PFC converter for receiving the first voltage, the ZCD circuit comprising: A first voltage divider circuit that receives the power supply voltage and outputs a third voltage; A second voltage divider circuit that receives the first voltage and outputs a fourth voltage; A first comparator and a second comparator connected to the first voltage divider circuit and the second voltage divider circuit for receiving the third voltage and the fourth voltage and outputting corresponding first and second comparison signals; and A first selection circuit connected to the first comparator and the second comparator for receiving the first and second comparison signals respectively and outputting a ZCD signal, wherein the ZCD signal indicates the zero current state of the bridgeless PFC converter; A zero voltage switching (ZVS) detection circuit connected to the bridgeless PFC converter for receiving the first voltage and the second voltage, and connected to the ZCD circuit for receiving the ZCD signal, wherein the ZVS detection circuit outputs a ZVS flag signal; and A processor connected to the ZCD circuit and the ZVS detection circuit for receiving the ZCD signal and the ZVS flag signal respectively, and connected to the bridgeless PFC converter for receiving the first voltage and the second voltage, wherein the processor outputs a set of control signals for controlling the bridgeless PFC converter.

2. The critical conduction mode (CRM) bridgeless power factor correction (PFC) system according to claim 1, further comprising: A polarity detection circuit that receives the power supply voltage and generates a polarity signal indicating the positive and negative half-cycles of the power supply voltage, and wherein the set of control signals is output based on the polarity signal.

3. The critical conduction mode (CRM) bridgeless power factor correction (PFC) system according to claim 2, wherein, The first selection circuit comprises: A first switch connected to the first comparator for receiving the first comparison signal; and A second switch connected to the second comparator for receiving the second comparison signal, wherein the output terminals of the first switch and the second switch are connected together and provide the ZCD signal, and wherein the first switch and the second switch are controlled by the polarity signal.

4. The critical conduction mode (CRM) bridgeless power factor correction (PFC) system according to claim 3, wherein: The first switch and the second switch are respectively activated in the positive and negative half-cycles of the power supply voltage, When the first switch is activated, the first selection circuit outputs the first comparison signal as the ZCD signal, and When the second switch is activated, the first selection circuit outputs the second comparison signal as the ZCD signal.

5. The critical conduction mode (CRM) bridgeless power factor correction (PFC) system according to claim 2, wherein, The ZVS detection circuit comprises: A delay element that receives the ZCD signal and outputs a delayed version of the ZCD signal; A latch that receives the ZCD signal and the delayed version of the ZCD signal respectively, and outputs a latch output signal; A second selection circuit that receives the first voltage and the first threshold voltage, and outputs one of the first voltage and the first threshold voltage based on the polarity signal; A third selection circuit that receives the first voltage and the second voltage, and outputs one of the first voltage and the second voltage based on the polarity signal; A third comparator connected to the second selection circuit for receiving one of the first voltage and the first threshold voltage, connected to the third selection circuit for receiving one of the first voltage and the second voltage, and connected to the latch for receiving the latch output signal, wherein the third comparator outputs a third comparison signal; and A fourth comparator that compares the third comparison signal with a second threshold voltage to generate the ZVS flag signal.

6. The critical conduction mode CRM bridgeless power factor correction PFC system according to claim 1, wherein, the bridgeless PFC converter includes: A first bridge arm including a first transistor and a second transistor connected in series, with a first node between the first transistor and the second transistor; A second bridge arm including a third transistor and a fourth transistor connected in series, with a second node between the third transistor and the fourth transistor, wherein the second bridge arm is connected in parallel to the first bridge arm such that the third transistor is connected to the first transistor at a third node, and the fourth transistor is connected to the second transistor at a fourth node, wherein the second voltage is output at the fourth node, and wherein the first to fourth transistors are controlled by the set of control signals; and An inductor having a first terminal for receiving the power supply voltage and a second terminal connected to the first node for outputting the first voltage.

7. The critical conduction mode CRM bridgeless power factor correction PFC system according to claim 6, wherein during the positive half-cycle of the power supply voltage: When the inductor is charging, the first transistor and the third transistor are activated, and the second transistor and the fourth transistor are deactivated, and When the inductor is discharging, the second transistor and the third transistor are activated, and the first transistor and the fourth transistor are deactivated.

8. The critical conduction mode CRM bridgeless power factor correction PFC system according to claim 7, wherein during the negative half-cycle of the power supply voltage: When the inductor is charging, the second transistor and the fourth transistor are activated, and the first transistor and the third transistor are deactivated, and When the inductor is discharging, the first transistor and the fourth transistor are activated, and the second transistor and the third transistor are deactivated.

9. The critical conduction mode CRM bridgeless power factor correction PFC system according to claim 8, wherein: During the positive half-cycle, when the ZCD signal is activated, the first voltage is less than the first threshold voltage, and the first transistor is activated, the ZVS flag signal is activated, and during the negative half-cycle, when the ZCD signal is activated, the first voltage is greater than the second voltage, and the second transistor is activated, the ZVS flag signal is activated.

10. The critical conduction mode CRM bridgeless power factor correction PFC system according to claim 8, wherein the processor determines the conduction time of the second transistor during each switching cycle of the positive half-cycle and the conduction time of the first transistor during each switching cycle of the negative half-cycle based on the volt-second balance of the inductor, and wherein the switching cycles of the positive half-cycle and the negative half-cycle correspond to the charging and subsequent discharging of the inductor.

11. The critical conduction mode CRM bridgeless power factor correction PFC system of claim 10, wherein when the supply voltage is greater than half of the second voltage, the conduction time of the second transistor and the conduction time of the first transistor are further determined based on the ZVS flag signal.

12. The critical conduction mode CRM bridgeless power factor correction PFC system according to claim 11, wherein: during the positive half-cycle, the first transistor is activated after a first duration when the second transistor is deactivated, during the negative half-cycle, the second transistor is activated after a second duration when the first transistor is deactivated, when the supply voltage is less than half of the second voltage, the first duration and the second duration vary for each switching cycle of the positive half-cycle and the negative half-cycle, respectively, and when the supply voltage is greater than half of the second voltage, the first duration and the second duration are constant for each switching cycle of the positive half-cycle and the negative half-cycle, respectively.

13. The critical conduction mode CRM bridgeless power factor correction PFC system according to claim 1, wherein: during the positive half-cycle of the supply voltage, the ZCD signal is activated when the first voltage is less than the supply voltage, and during the negative half-cycle of the supply voltage, the ZCD signal is activated when the first voltage is greater than the supply voltage.

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