Fingerprint sensor and display device including the same

Abstract

A fingerprint sensor and a display device including the same are disclosed. The fingerprint sensor includes a substrate, a circuit element layer on a first surface of the substrate and including a plurality of conductive layers, a light emitting element layer on the circuit element layer and including a light emitting element and a light blocking layer, and a light sensor layer on a second surface of the substrate and including a light sensor, wherein the light blocking layer includes a contact hole exposing a first electrode of the light emitting element and a first opening portion exposing a portion of the circuit element layer, and the circuit element layer includes a second opening portion formed in the plurality of conductive layers and includes a light transmission hole of which at least a portion overlaps the first opening portion.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2019-0062644, filed on May 28, 2019, the entire contents of which are incorporated herein by reference. Background Technology

[0002] Aspects of some exemplary embodiments of this disclosure relate to a fingerprint sensor and a display device including the fingerprint sensor. Technical Field

[0003] In recent years, with the widespread use of display devices such as smartphones and tablet PCs, biometric authentication methods utilizing users' fingerprints have become available. To provide fingerprint sensing functionality, fingerprint sensors can be embedded in or attached to the display device.

[0004] For example, a fingerprint sensor can be constructed using a photosensitive method. A photosensitive fingerprint sensor can include a light source, a lens, and a photosensitive array. When such a fingerprint sensor is attached to a display panel, the thickness of the display device increases, and the manufacturing cost also increases.

[0005] The information disclosed in this background section is only for enhancing the understanding of the background, and therefore the information discussed in this background section does not necessarily constitute prior art. Summary of the Invention

[0006] Aspects of some exemplary embodiments of this disclosure may include a fingerprint sensor using a photosensitive method that can reduce the manufacturing cost of a display device, and a display device including the fingerprint sensor.

[0007] Additionally, some example embodiments may include a fingerprint sensor and a display device including the fingerprint sensor, wherein the fingerprint sensor includes a light-transmitting area capable of selectively receiving reflected light from a user's finger without including a separate light-shielding layer.

[0008] Additionally, some example embodiments may include a fingerprint sensor capable of selectively receiving reflected light by forming an opening in a pixel-defining layer with high reflectivity, and a display device including the fingerprint sensor.

[0009] Additionally, some example embodiments may include a fingerprint sensor with a light-transmitting area arranged to maximize the effective area extracted from reflected light, and a display device including the fingerprint sensor.

[0010] According to some disclosed example embodiments, a fingerprint sensor includes: a substrate; a circuit element layer located on a first surface of the substrate and including a plurality of conductive layers; a light-emitting element layer located on the circuit element layer and including a light-emitting element and a light-shielding layer; and a light sensor layer located on a second surface of the substrate and including a light sensor. The light-shielding layer may include a contact hole exposing a first electrode of the light-emitting element and a first opening exposing a portion of the circuit element layer, and the circuit element layer may include a second opening formed in the plurality of conductive layers, and includes a light-transmitting hole at least a portion thereof superimposed on the first opening.

[0011] According to some example embodiments, the light-emitting element layer may include: a first electrode located on the circuit element layer and exposed by a contact hole to form a light-emitting region; a plurality of light-emitting layers located on the exposed first electrode; and a plurality of second electrodes located on a light-shielding layer to cover the plurality of light-emitting layers. Each of the first openings may be formed to be adjacent to at least a portion of the light-emitting region.

[0012] According to some example embodiments, the first opening may be arranged along a first direction relative to the light-emitting area or diagonally relative to a second direction perpendicular to the first direction.

[0013] According to some example embodiments, the distance between two adjacent first openings is substantially equal to that between each other.

[0014] According to some example embodiments, the light-emitting region may include: a first light-emitting region that emits light of a first color; a second light-emitting region that emits light of a second color; and a third light-emitting region that emits light of a third color.

[0015] According to some example embodiments, the first color may be red, the second color may be green, and the third color may be blue. The first opening may be arranged adjacent to at least one of the first and third light-emitting regions.

[0016] According to some example embodiments, the light-emitting region can be constructed as a unit pixel including a first light-emitting region, a second light-emitting region and a third light-emitting region, and the first opening can be arranged to be adjacent to at least a portion of the unit pixel.

[0017] According to some example embodiments, the first opening may be spaced at eight unit pixels in a first direction and at seven unit pixels in a second direction.

[0018] According to some example embodiments, a unit pixel may include a first light-emitting region, a second light-emitting region, and a third light-emitting region arranged in sequence, and a first opening may be arranged adjacent to at least a portion of the first light-emitting region of the unit pixel.

[0019] According to some example embodiments, a unit pixel may include: a first unit pixel, in which a first light-emitting region and a second light-emitting region are sequentially arranged; and a second unit pixel, in which a third light-emitting region and a second light-emitting region are sequentially arranged. The first unit pixel and the second unit pixel may be arranged alternately.

[0020] According to some example embodiments, the first opening may be arranged adjacent to a first light-emitting region of at least a portion of the first unit pixel and a third light-emitting region of at least a portion of the second unit pixel.

[0021] According to some example embodiments, one of two adjacent first openings in the diagonal direction can be arranged to be adjacent to one of the first unit pixels, and the other can be arranged to be adjacent to one of the second unit pixels.

[0022] According to some example embodiments, the circuit element layer may include: a semiconductor layer located on a substrate and including at least one active pattern; a first conductive layer located on at least one active pattern and including at least one gate electrode; a second conductive layer located on the first conductive layer and including at least one capacitor electrode; and a third conductive layer located on the second conductive layer and including at least one wiring, and at least one insulating layer may be inserted between the semiconductor layer and the first conductive layer, at least one insulating layer may be inserted between the first conductive layer and the second conductive layer, and at least one insulating layer may be inserted between the second conductive layer and the third conductive layer.

[0023] According to some example embodiments, the light transmission aperture may include a second opening formed in at least two of the semiconductor layer, the first conductive layer, the second conductive layer, and the third conductive layer, stacked on top of each other.

[0024] According to some example embodiments, the first opening and the light transmission aperture can guide light incident from the outside to the light sensor.

[0025] According to some example embodiments, a display device according to some disclosed example embodiments may include a display panel and a light sensor layer located on a second surface of the display panel and including a light sensor. The display panel includes: a substrate; a circuit element layer located on a first surface of the substrate and including a plurality of conductive layers; and a light-emitting element layer located on the circuit element layer and including a light-emitting element and a light-shielding layer. The light-shielding layer may include a contact hole exposing a first electrode of the light-emitting element and a first opening exposing a portion of the circuit element layer. The circuit element layer may include a second opening formed in the plurality of conductive layers and includes a light-transmitting hole, at least a portion of which overlaps with the first opening.

[0026] According to some example embodiments, the light-emitting element layer may include: a first electrode located on the circuit element layer and exposed by a contact hole to form a light-emitting region; a plurality of light-emitting layers located on the exposed first electrode; and a plurality of second electrodes located on a light-shielding layer to cover the plurality of light-emitting layers. Each of the first openings may be formed to be adjacent to at least a portion of the light-emitting region.

[0027] According to some example embodiments, the first opening may be arranged along a first direction relative to the light-emitting area or diagonally relative to a second direction perpendicular to the first direction.

[0028] According to some example embodiments, the distance between two adjacent first openings is substantially equal to that between each other.

[0029] According to some example embodiments, the circuit element layer may include: a semiconductor layer located on a substrate and including at least one active pattern; a first conductive layer located on at least one active pattern and including at least one gate electrode; a second conductive layer located on the first conductive layer and including at least one capacitor electrode; and a third conductive layer located on the second conductive layer and including at least one wiring, and at least one insulating layer may be inserted between the semiconductor layer and the first conductive layer, at least one insulating layer may be inserted between the first conductive layer and the second conductive layer, and at least one insulating layer may be inserted between the second conductive layer and the third conductive layer, and a light transmission aperture may be formed as a second opening stacked on top of each other in at least two of the semiconductor layer, the first conductive layer, the second conductive layer and the third conductive layer.

[0030] According to some example embodiments, the fingerprint sensor and the display device including the fingerprint sensor can reduce the module thickness of the display device by integrally forming the light-transmitting region with the circuit element layer and the light-emitting layer in the photosensitive fingerprint sensor.

[0031] According to some example embodiments, the disclosed fingerprint sensor and display device including the fingerprint sensor can improve the efficiency and reliability of fingerprint sensing by maximizing the effective area. Attached Figure Description

[0032] The above and other features of the invention will become clearer by referring to the accompanying drawings, which describe in further detail aspects of some exemplary embodiments of the invention, in which:

[0033] Figure 1 and Figure 2 This is a schematic diagram illustrating a display device according to some exemplary embodiments disclosed;

[0034] Figures 3A to 3E It is a plan view illustrating the structural relationship between pixels and light sensors according to some exemplary embodiments disclosed;

[0035] Figure 4 This is an exploded perspective view of a display device according to some of the disclosed example embodiments;

[0036] Figure 5 This is a cross-sectional view of a display device according to some of the disclosed example embodiments;

[0037] Figure 6 This is a circuit diagram illustrating pixels according to some exemplary embodiments disclosed;

[0038] Figure 7 This is a circuit diagram illustrating pixels according to some exemplary embodiments disclosed;

[0039] Figure 8 This illustrates some example embodiments based on the disclosure. Figure 7 A plan view of the pixel layout shown;

[0040] Figure 9 It is along Figure 8 A sectional view taken by line I-I';

[0041] Figure 10 It is along Figure 8 A sectional view taken from line II-II';

[0042] Figure 11 It is a plan view illustrating the layout of pixels according to some exemplary embodiments disclosed;

[0043] Figure 12 It is along Figure 11 A sectional view taken from line III-III';

[0044] Figure 13 It is along Figure 11 A sectional view taken by line IV-IV';

[0045] Figures 14A to 14C It is a plan view showing the structural arrangement of the opening and the reflected light arrival area (or arrival area) corresponding to the opening according to some exemplary embodiments disclosed;

[0046] Figure 15 A schematic plan view of a display device according to some exemplary embodiments disclosed is shown;

[0047] Figure 16 A schematic plan view of a display device according to some exemplary embodiments disclosed is shown; and

[0048] Figure 17 A schematic plan view of a display device according to some of the disclosed example embodiments is shown. Detailed Implementation

[0049] In the following description, aspects of some exemplary embodiments will be described in more detail with reference to the accompanying drawings. The same or similar reference numerals are used for the same components in the drawings.

[0050] Figure 1 and Figure 2 This is a schematic diagram illustrating a display device according to some exemplary embodiments disclosed. More specifically, Figure 1 and Figure 2 This is a schematic diagram illustrating a display panel and a driving circuit for driving the display panel, included in a display device according to some exemplary embodiments disclosed. For convenience, in Figure 1 and Figure 2 In this design, the display panel and the driving circuitry are separate from each other, but the disclosure is not limited to this. For example, all or part of the driving circuitry can be integrated into the display panel.

[0051] Reference Figure 1 and Figure 2 The display device 10 includes a display panel 110 and a driving circuit 200 for driving the display panel 110.

[0052] Display panel 110 includes a display area AA and a non-display area NA. The display area AA is an area provided with a plurality of pixels PXL (which may be referred to as sub-pixels) and may be referred to as the effective area. In various embodiments, each of the pixels PXL may include at least one light-emitting element. Display device 10 displays an image in display area AA by driving the pixels PXL corresponding to image data input from the outside.

[0053] According to some disclosed example embodiments, the display area AA may include a sensing area SA. The sensing area SA may include at least some of the pixels PXL disposed in the display area AA.

[0054] According to some example embodiments, such as Figure 1 As shown, at least a portion of the display area AA can be set as the sensing area SA. According to some example embodiments, the entire display area AA can be as follows: Figure 2 The setting shown is the sensing area SA.

[0055] At the same time, despite Figure 1 An example is shown in which only one sensing area SA is formed in the display area AA, but the spirit of the disclosed technology is not limited thereto. That is, according to some example embodiments, multiple sensing areas SA arranged regularly or irregularly can be formed in the display area AA. According to some example embodiments, the multiple sensing areas SA can have the same or different areas and shapes.

[0056] In addition, although Figure 1An example is shown in which the sensing region SA is formed in at least a portion of the display region AA, but the spirit of the disclosed technology is not limited thereto. That is, according to some example embodiments, the display region AA and the sensing region SA may be configured to overlap only at least a portion of the display region AA and the sensing region SA.

[0057] The non-display area NA is the area surrounding the display area AA and may be referred to as an inactive area. According to some example embodiments, the non-display area NA can refer comprehensively to the area in the display panel 110 other than the display area AA. According to some example embodiments, the non-display area NA may include wiring areas, pad areas (or "solder pad areas"), various dummy areas, etc.

[0058] According to some example embodiments disclosed, the display device 10 may further include a plurality of light sensors PHS disposed in the sensing area SA. According to some example embodiments, the light sensors PHS can sense light emitted from a light source reflected by a user's finger and analyze the reflected light to sense the user's fingerprint. Hereinafter, the disclosure will be described using examples in which the light sensors PHS are used for fingerprint sensing purposes; however, in various embodiments, the light sensors PHS can be used for purposes such as performing various functions of a touch sensor or scanner.

[0059] According to some disclosed example embodiments, the light sensor PHS can be located within the sensing region SA. In this case, the light sensor PHS can be superimposed on at least some or all of the pixels PXL disposed in the sensing region SA, or it can be arranged around the pixels PXL. For example, at least some or all of the light sensor PHS can be disposed between the pixels PXL. (Refer to...) Figures 3A to 3E Various embodiments of the structural relationship between the optical sensor PHS and the pixel PXL are described in more detail.

[0060] According to some example embodiments where the optical sensor PHS is positioned adjacent to the pixel PXL, the optical sensor PHS can use a light-emitting element disposed in at least one pixel PXL located at or around the sensing region SA as a light source. In such embodiments, the optical sensor PHS can be constructed together with the pixel PXL of the sensing region SA (specifically, the light-emitting element disposed in the pixel PXL) to form a photosensitive fingerprint sensor. As described above, when a fingerprint sensor-integrated display device is constructed by using the pixel PXL as a light source without a separate external light source, the module thickness of the photosensitive fingerprint sensor and the display device including the fingerprint sensor can be reduced, and manufacturing costs can be lowered.

[0061] According to some example embodiments, the light sensor PHS may be located on the rear surface (e.g., the back surface) of the two surfaces of the display panel 110, opposite the surface on which the image is displayed (e.g., the front surface). However, the disclosure is not limited thereto.

[0062] The driving circuit 200 can drive the display panel 110. For example, the driving circuit 200 can output a data signal corresponding to image data to the display panel 110, or it can output a driving signal for the light sensor PHS and receive a sensing signal received from the light sensor PHS. The driving circuit 200 that receives the sensing signal can use the sensing signal to detect the user's fingerprint.

[0063] According to some disclosed example embodiments, the driving circuit 200 may include a panel driver 210 and a fingerprint detector 220. For convenience, in Figure 1 and Figure 2 In this design, the panel driver 210 and the fingerprint detector 220 are separate from each other, but the spirit of the disclosed technology is not limited thereto. For example, at least a portion of the fingerprint detector 220 may be integrated with or operated in conjunction with the panel driver 210.

[0064] The panel driver 210 can sequentially supply data signals corresponding to image data to pixels PXL, while sequentially scanning pixels PXL in the display area AA. Then, the display panel 110 can display an image corresponding to the image data.

[0065] According to some example embodiments, the panel driver 210 can supply a driving signal for fingerprint sensing to the pixel PXL. The driving signal can be provided to cause the pixel PXL to emit light and operate as a light source for the light sensor PHS. In such embodiments, the driving signal for fingerprint sensing can be provided to the pixel PXL located in a specific area within the display panel 110, for example, the pixel PXL located in the sensing area SA. According to some example embodiments, the driving signal for fingerprint sensing can be provided by the fingerprint detector 220.

[0066] The fingerprint detector 220 can transmit a drive signal for driving the optical sensor PHS to the optical sensor PHS, and can detect the user's fingerprint based on the sensing signal received from the optical sensor PHS.

[0067] Figures 3A to 3E This is a plan view illustrating various embodiments of the structural arrangement of pixels and light sensors. Figures 3A to 3E Different embodiments are shown in relation to the relative size, resolution, and relative structural arrangement of at least one pixel PXL disposed in the sensing area SA and the light sensor PHS.

[0068] Reference Figure 3A In the sensing area SA, the light sensors PHS can be arranged at the same resolution (density) as the pixels PXL. In other words, the same number of light sensors PHS as the pixels PXL can be located in the sensing area SA. In such an embodiment, the pixels PXL and the light sensors PHS can be arranged to form a 1:1 pair. According to... Figure 3A In one embodiment, the pixel PXL and the light sensor PHS can be arranged to overlap each other, but in other embodiments, the pixel PXL and the light sensor PHS can be arranged not to overlap each other or only a portion of the pixel PXL and the light sensor PHS can overlap each other.

[0069] At the same time, according to Figure 3A In some embodiments, the light sensor PHS may have a size smaller than the pixel PXL, but the spirit of the disclosed technology is not limited thereto. That is, in other embodiments, the light sensor PHS may have the same size as the pixel PXL or may have a size larger than the pixel PXL. Such embodiments are... Figure 3C and Figure 3D As shown in the image.

[0070] Reference Figures 3B to 3E The light sensor PHS can be arranged in the sensing area SA at a lower resolution than the pixel PXL. In other words, a smaller number of light sensors PHS than the number of pixels PXL can be located in the sensing area SA. Figures 3B to 3E The image shows an example in which a light sensor PHS is arranged for every four pixels of PXL, but the disclosure is not limited to this.

[0071] In such an embodiment, the optical sensor PHS can be as follows: Figure 3B and Figure 3E The size shown is smaller than the size of the pixel PXL, or it can be as follows: Figure 3C and Figure 3D The one shown has a size larger than the size of the pixel PXL.

[0072] When the light sensor PHS is arranged at a resolution lower than that of the pixel PXL, part or all of the light sensor PHS can be arranged to overlap with the pixel PXL. That is, as Figure 3B and Figure 3C As shown, the light sensor PHS can be partially superimposed on a portion of the pixel PXL.

[0073] Optionally, such as Figure 3D As shown, the light sensor PHS can be located between and partially superimposed on the pixels PXL. In such an embodiment, the light sensor PHS can be as follows: Figure 3DThe dimensions shown are larger than the size of pixel PXL. For example, a light sensor PHS can have a size that covers at least one pixel PXL.

[0074] Optionally, such as Figure 3E As shown, the light sensor PHS may not be stacked with the pixel PXL.

[0075] According to some disclosed example embodiments, the relative structural arrangement between the pixel PXL and the light sensor PHS is not limited to the aforementioned relative structural arrangement. That is, within the scope of the disclosed technical spirit, various modifications can be made to the shape, arrangement, relative size, number, resolution, etc., of the pixel PXL and the light sensor PHS in the sensing area SA. Furthermore, in various embodiments, the pixel PXL and the light sensor PHS can be combined in various ways. Figures 3A to 3E One or more of the forms or structural arrangements in the embodiments.

[0076] in addition, Figures 3A to 3E An example is shown in which the optical sensor PHS is regularly arranged in the sensing area SA, but the spirit of the disclosed technology is not limited thereto. In other embodiments, the optical sensor PHS may be irregularly arranged in the sensing area SA.

[0077] Figure 4 This is an exploded perspective view of a display device based on some of the disclosed example embodiments. Figure 5 This is a cross-sectional view of a display device according to some of the disclosed example embodiments. Figure 4 and Figure 5 Specifically shown Figure 1 and Figure 2 A cross-sectional view of the sensing area SA shown in the figure.

[0078] Reference Figure 4 and Figure 5 The display device 10 according to some of the disclosed example embodiments may include a display module 100 including a display panel 110 and a light sensor layer 300 located on one surface of the display panel 110.

[0079] The display module 100 may include a display panel 110, one or more functional layers 120 located on the image display surface (e.g., the front surface) of the display panel 110, and a window 130. However, at least one of the functional layers 120 and the window 130 may be omitted or may be combined with the display panel 110.

[0080] The display panel 110 includes a plurality of light-emitting areas LA located in the display area AA. Each of the light-emitting areas LA can constitute each of the pixels PXL.

[0081] The light-emitting region LA includes a first light-emitting region LA1 that emits light of a first color (e.g., red), a second light-emitting region LA2 that emits light of a second color (e.g., green), and a third light-emitting region LA3 that emits light of a third color (e.g., blue). However, the spirit of the disclosed technology is not limited thereto, and in other embodiments, the light-emitting region LA may emit light of one of the colors cyan, magenta, yellow, and white.

[0082] The luminous area LA can be distributed in the display area AA according to rules (e.g., predetermined rules). For example, the luminous area LA can be distributed in the display area AA in a pentile pattern, but it can also be distributed in the display area AA in a stripe pattern. In addition, the luminous area LA can be shown in a diamond shape, but it can have various shapes such as circles, ovals, squares, and rectangles.

[0083] The display panel 110 may include a substrate 111. The substrate 111 may include a transparent insulating material to transmit light. Alternatively, the substrate 111 may be a rigid substrate or a flexible substrate.

[0084] Rigid substrates may include glass substrates, quartz substrates, glass-ceramic substrates, and crystalline glass substrates. Flexible substrates may include film substrates comprising polymeric organic materials and plastic substrates. For example, flexible substrates may include at least one of polyethersulfone (“PES”), polyacrylate, polyetherimide (“PEI”), polyethylene naphthalate (“PEN”), polyethylene terephthalate (“PET”), polyphenylene sulfide (“PPS”), polyarylate (“PAR”), polyimide (“PI”), polycarbonate (“PC”), cellulose triacetate (“TAC”), and cellulose acetate propionate (“CAP”). Additionally, flexible substrates may include glass fiber reinforced plastic (“FRP”).

[0085] The material to be applied to the substrate 111 may preferably have resistance to high process temperatures (or heat resistance) in the manufacturing process of the display device 10. According to some disclosed example embodiments, the entire substrate 111 or at least some portions thereof may be flexible.

[0086] A light-emitting element LD, which forms a plurality of pixels PXL, and at least one transistor M connected to the light-emitting element LD are located on a substrate 111. The at least one transistor M may be located in a circuit element layer PDL on the substrate 111.

[0087] The circuit element layer (PDL) may include at least one conductive layer. For example, the circuit element layer (PDL) may include a plurality of circuit elements comprising a pixel circuit for each pixel PXL, including a transistor M, and wiring for applying power and signals to drive the pixel PXL.

[0088] For example, a buffer layer 112 may be formed on the substrate 111. The buffer layer 112 can prevent or reduce the diffusion of impurities into the upper component, which will be described later. The buffer layer 112 may be a single layer or multiple layers. When the buffer layer 112 is multiple layers, each layer may be formed of the same or different materials. The buffer layer 112 may be omitted depending on the material and process conditions of the substrate 111.

[0089] The active pattern ACT for constructing transistor M can be formed on buffer layer 112. The channel CH, source electrode SE (or source region), and drain electrode DE (or drain region) can be formed in the active pattern ACT.

[0090] The gate electrode GE can be arranged to overlap with the channel CH of the active pattern ACT. In this case, the gate insulating layer 113 can be inserted between the active pattern ACT and the gate electrode GE.

[0091] The gate insulating layer 113 may be an inorganic insulating film comprising inorganic materials. For example, the gate insulating layer 113 may comprise at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0092] The gate electrode GE may be covered with a first insulating intermediate layer 114. The first insulating intermediate layer 114 may be formed as a single layer as shown in the figure, or it may be formed as multiple layers. When the first insulating intermediate layer 114 is formed as multiple layers, the first insulating intermediate layer 114 may have a structure in which multiple inorganic insulating films or multiple organic insulating films are alternately stacked. For example, the first insulating intermediate layer 114 may have a structure in which a first organic insulating layer, an inorganic insulating layer, and a second organic insulating layer are sequentially stacked, but is not limited thereto.

[0093] A second insulating intermediate layer 115 may be disposed on the first insulating intermediate layer 114. The second insulating intermediate layer 115 may cover the conductive pattern disposed on the first insulating intermediate layer 114. The second insulating intermediate layer 115 may be formed of a single layer or multiple layers, similar to the first insulating intermediate layer 114. According to some example embodiments, the first insulating intermediate layer 114 and the second insulating intermediate layer 115 may be formed of the same or different materials and structures.

[0094] Conductive patterns, such as connection wiring CNL, can be disposed on the second insulating intermediate layer 115. According to some example embodiments, the connection wiring CNL can be connected to underlying components via contact holes passing through the gate insulating layer 113, the first insulating intermediate layer 114, and the second insulating intermediate layer 115. Figure 5 The image shows an example where the connecting wire CNL is connected to the drain electrode DE.

[0095] The bridging pattern BRP can also be disposed on the second insulating intermediate layer 115. The bridging pattern BRP can be connected to the underlying components via contact holes passing through the gate insulating layer 113, the first insulating intermediate layer 114, and the second insulating intermediate layer 115. Figure 5 The image shows an example where the bridging pattern BRP is connected to the source electrode SE.

[0096] The protective layer 116 can be disposed on the second insulating intermediate layer 115. The light-emitting element LD can be located on the protective layer 116. The light-emitting element LD can be located in the light-emitting element layer LDL on the circuit element layer PDL.

[0097] The light-emitting element LD can be electrically connected to the transistor M through contact holes formed through the protective layer 116. For example, the light-emitting element LD can be connected to the bridging pattern BRP through contact holes formed through the protective layer 116, and can be connected to the transistor M through the bridging pattern BRP. However, the spirit of the disclosed technology is not limited thereto.

[0098] The light-emitting element (LD) includes a first electrode AD and a second electrode CD stacked on top of each other in at least one region, and a light-emitting layer EML inserted between the first electrode AD and the second electrode CD. According to some example embodiments, the first electrode AD and the second electrode CD can be an anode electrode and a cathode electrode, respectively. However, the disclosed technical spirit is not limited thereto. For example, the first electrode AD, electrically connected to a transistor M, can be a cathode electrode according to a pixel structure.

[0099] The light-emitting layer (EML) can be disposed on the exposed surface of the first electrode (AD). The EML can have a multilayer thin film structure including a light-generating layer. For example, the EML may include a hole injection layer for injecting holes, a hole transport layer for increasing the chance of hole recombination by suppressing the movement of unbound electrons in the light-generating layer and having excellent hole transport capability, a light-generating layer for emitting light by recombination of injected electrons and holes, a hole blocking layer for suppressing the movement of unbound holes in the light-generating layer, an electron transport layer for smoothly transporting electrons to the light-generating layer, and an electron injection layer for injecting electrons.

[0100] In various embodiments, the area where the first electrode AD of the light-emitting element LD is exposed can form a light-emitting region LA. In various embodiments, the light-emitting region LA may be referred to as a pixel, pixel region, light-emitting portion, etc. The light-emitting region LA is shown as a rhombus shape, but it can have various shapes such as circle, ellipse, square, rectangle, etc.

[0101] The light emitted from the emitting region LA can be any one of red, blue, and green light. Optionally, the light emitted from the emitting region LA can include white light. Optionally, the light emitted from the emitting region LA can be any one of cyan, magenta, and yellow light.

[0102] A pixel defining layer 117 (or pixel defining film) may be formed between the light-emitting regions LA. In the various disclosed embodiments, the pixel defining layer 117 may include an organic insulating material. For example, the pixel defining layer 117 may include at least one selected from polystyrene, polymethyl methacrylate (“PMMA”), polyacrylonitrile (“PAN”), polyamide (“PA”), polyimide (“PI”), polyaryl ether (“PAE”), heterocyclic polymers, parylene, epoxy resins, benzocyclobutene (“BCB”), siloxane resins, and silane resins.

[0103] In the various disclosed embodiments, the pixel defining layer 117 may include a light-blocking material. For example, the pixel defining layer 117 may include chromium (Cr) or chromium oxide (CrO). x Light-blocking materials, or light-blocking layers including carbon or black pigments.

[0104] In such a disclosed embodiment, an opening OPA may be provided in the pixel defining layer 117. The opening OPA may be configured to selectively transmit at least some of the light generated in the display panel 110 or at least some of the incident light incident on the display panel 110. The opening OPA may be an "optical opening region" formed by removing a portion of the pixel defining layer 117 or formed of a transparent material, such that light can be transmitted differently from the peripheral region formed as non-transmissive.

[0105] In the various disclosed embodiments, the openings OPA can be arranged regularly or irregularly in the pixel defining layer 117. For example, the openings OPA can be arranged at certain intervals (e.g., predetermined intervals) between the light-emitting regions LA. The openings OPA can be arranged in, for example... Figure 4 The light-emitting region LA shown has a low density. However, the spirit of the disclosed technology is not limited to this.

[0106] In the various disclosed embodiments, the openings (OPA) can have suitable sizes and spacing to sense clearer fingerprint patterns while preventing or reducing diffraction of incident light. For example, to prevent or reduce light diffraction, the width of the openings (OPA) can be set to be about 10 times or more the wavelength of the incident light. In the various disclosed embodiments, the size of the openings (OPA) can be smaller than the size of the light-emitting region (LA). However, the spirit of the disclosed technology is not limited thereto.

[0107] According to some example embodiments, the display panel 110 may be configured such that at least a portion of the display panel 110 is transparent or translucent to transmit light. For example, the display panel 110 may include a light-transmitting region LTP disposed around the light-emitting region LA.

[0108] The light-transmitting region LTP can be formed inside the pixel PXL. For example, the light-transmitting region LTP can exist in the gaps between circuit elements (e.g., transistors M) that are not positioned to construct the pixel PXL and / or light-shielding elements (such as wiring) connected to the circuit elements.

[0109] The light-transmitting region LTP can be formed such that at least a portion of the light-transmitting region LTP is superimposed on the opening OPA formed in the pixel defining layer 117. That is, the light-transmitting region LTP can be formed in the region between the light-emitting regions LA. Then, reflected light passing through the opening OPA can reach the light sensor layer 300 through the light-transmitting region LTP.

[0110] The encapsulation layer 118 may be further formed on the pixel defining layer 117. The encapsulation layer 118 may include multiple insulating films covering the light-emitting element LD. For example, the encapsulation layer 118 may include multiple inorganic films and organic films. For example, the encapsulation layer 118 may have a structure in which inorganic films and organic films are alternately stacked. In addition, depending on the situation, the encapsulation layer 118 may be an encapsulation substrate disposed on the light-emitting element LD and adhered to the substrate 111 by a sealant or the like.

[0111] The functional layer 120 may include a polarization layer, a touch sensor layer, an adhesive layer, and / or a protective layer, etc., and there are no particular limitations on the construction of the functional layer 120. In addition, the functional layer 120 may be omitted or integrated with the display panel 110. For example, the functional layer 120 may be directly formed or disposed on the encapsulation layer 118.

[0112] The window 130 can be positioned at the top of the display module 100. The window 130 can transmit images from the display panel 110 and mitigate external impacts to prevent or reduce the possibility of the display device 10 breaking or malfunctioning due to external impacts.

[0113] The light sensor layer 300 can be constructed as a sensor (IC) attached to the lower surface of the display panel 110. According to the embodiment described above in which the light sensor layer 300 is disposed on the lower surface (or back surface) of the display panel 110, the degradation of the image quality of the display device 10 caused by the light sensor layer 300 can be prevented or reduced.

[0114] The light sensor layer 300 may include a light sensor array constructed from multiple light sensor PHSes. The light sensor PHS may be a photodiode, a CMOS image sensor, or a CCD camera, but is not limited to these. (See reference...) Figures 3A to 3EAs described, the light sensor PHS can have various sizes, numbers, resolutions, and arrangements relative to the pixels PXL in the display panel 110.

[0115] At least a portion of the optical sensor PHS may include a light receiver stacked with an opening OPA between the light-emitting regions LA of at least two adjacent pixels PXL and a light-transmitting region LTP. At least a portion of the optical sensor PHS may output a signal corresponding to light incident on the light receiver through the opening OPA and the light-transmitting region LTP. The output signal generated by the optical sensor PHS may be input to... Figure 1 and Figure 2 The driving circuit 200 shown is used to generate the user's fingerprint information. That is, the display device 10 according to some of the disclosed example embodiments can use the output signal from the light sensor PHS to sense the fingerprint pattern of a finger located on the display panel 110.

[0116] In the various disclosed embodiments, the display device 10 may be a fingerprint sensor-integrated display device that uses the internal light of the display panel 110 to sense fingerprints. Specifically, during the fingerprint sensing period in which the light sensor PHS is activated, the display device 10 may cause at least a portion of the pixels PXL in the sensing area SA to emit light. The display device 10 may cause all or some of the pixels PXL in the sensing area SA (e.g., pixels PXL arranged at specific intervals or pixels PXL emitting a specific light) to emit light simultaneously or sequentially.

[0117] According to some example embodiments, when a user's finger (specifically, the fingerprint area) contacts or is positioned close to the sensing area SA, light emitted from the emitting pixel PXL is reflected at the user's finger and enters the light sensor PHS through the light transmission area LTP. At this time, the amount and / or waveform of the reflected light reflected from the ridges and valleys of each fingerprint can be different from each other. Therefore, the display device 10 can use the characteristics of the reflected light to detect the shape (fingerprint pattern) of the user's fingerprint.

[0118] In various embodiments, a filter (e.g., an IR filter) for transmitting or shielding light of a specific wavelength may be further located on a surface of the light sensor layer 300, specifically on the upper surface of the light receiving portion of the light sensor PHS positioned thereon.

[0119] Figure 6 This is a circuit diagram illustrating pixels according to some exemplary embodiments disclosed. Figure 6 For ease of description, an active pixel PXL, comprising two transistors, is shown, connected to the i-th (i is a natural number) scan line Si in the i-th horizontal pixel row and the j-th (j is a natural number) data line Dj in the j-th vertical pixel column. However, the structure of the pixel PXL disclosed is not limited to... Figure 6 The structure shown.

[0120] Reference Figure 6 According to some of the disclosed example embodiments, the pixel PXL may include a first transistor M1, a second transistor M2, a storage capacitor Cst, and a light-emitting element LD.

[0121] A first transistor M1 (driving transistor) is connected between the j-th data line Dj and the first node N1, and the gate electrode of the first transistor M1 is connected to the i-th scan line Si. When a scan signal with a gate turn-on voltage (e.g., a low voltage) is supplied from the i-th scan line Si, the first transistor M1 is turned on. When the first transistor M1 is turned on, the j-th data line Dj and the first node N1 can be electrically connected to each other.

[0122] A second transistor M2 (switching transistor) is connected between the signal line supplying the first power ELVDD and the light-emitting element LD. The gate electrode of the second transistor M2 is connected to the first node N1. The voltage of the second transistor M2 and the first node N1 correspond to control the amount of current supplied from the signal line supplying the first power ELVDD through the light-emitting element LD to the signal line supplying the second power ELVSS. In various embodiments, the first power ELVDD can be high-potential pixel power, and the second power ELVSS can be low-potential pixel power.

[0123] A storage capacitor Cst is connected between the signal line supplying the first power ELVDD and the first node N1. The storage capacitor Cst can store the voltage corresponding to the data signal supplied to the first node N1.

[0124] The light-emitting element LD is connected between the second transistor M2 and the signal line supplying the second power ELVSS. The light-emitting element LD emits light with a brightness corresponding to the current controlled by the second transistor M2. In various embodiments, the light-emitting element LD may be an organic light-emitting diode (“OLED”).

[0125] Figure 7 This is a circuit diagram illustrating pixels according to some exemplary embodiments disclosed. Figure 7 For ease of description, an active pixel PXL, comprising seven transistors, is shown, connected to the i-th (i is a natural number) scan line Si in the i-th horizontal pixel row and the j-th (j is a natural number) data line Dj in the j-th vertical pixel column. However, the structure of the pixel PXL disclosed is not limited to... Figure 7 The structure shown.

[0126] Reference Figure 7 According to some of the disclosed example embodiments, the pixel PXL may include a first transistor M1 to a seventh transistor M7, a storage capacitor Cst, and a light-emitting element LD.

[0127] The first electrode of the first transistor M1 can be connected to the signal line supplying the first power ELVDD via the fifth transistor M5, and the second electrode of the first transistor M1 can be connected to the anode electrode of the light-emitting element LD via the sixth transistor M6. Additionally, the gate electrode of the first transistor M1 can be connected to the first node N1. The first transistor M1 can control the amount of current flowing from the signal line supplying the first power ELVDD through the light-emitting element LD to the signal line supplying the second power ELVSS, corresponding to the voltage of the first node N1.

[0128] The second transistor M2 (switching transistor) can be connected between the j-th data line Dj and the first electrode of the first transistor M1. Additionally, the gate electrode of the second transistor M2 can be connected to the i-th scan line Si. When a scan signal is supplied to the i-th scan line Si, the second transistor M2 can be turned on to electrically connect the j-th data line Dj to the first electrode of the first transistor M1.

[0129] The third transistor M3 can be connected between the second electrode of the first transistor M1 and the first node N1. Additionally, the gate electrode of the third transistor M3 can be connected to the i-th scan line Si. When a scan signal with a gate-on voltage is supplied to the i-th scan line Si, the third transistor M3 can be turned on, electrically connecting the second electrode of the first transistor M1 and the first node N1. Therefore, when the third transistor M3 is turned on, the first transistor M1 can be connected in a diode configuration.

[0130] The fourth transistor M4 (initialization transistor) can be connected between the first node N1 and the signal line supplying the initialization power Vint. Additionally, the gate electrode of the fourth transistor M4 can be connected to the (i-1)th scan line Si-1. When the scan signal is supplied to the (i-1)th scan line Si-1, the fourth transistor M4 can be turned on to supply the voltage of the initialization power Vint to the first node N1.

[0131] Figure 7 An embodiment is shown in which the (i-1)th scan line Si-1 is used as an initialization control line for initializing the gate node (i.e., the first node N1) of the first transistor M1. However, the spirit of the disclosed technology is not limited thereto. For example, according to some exemplary embodiments disclosed, another control line, such as the (i-2)th scan line, can be used as an initialization control line for initializing the gate node of the first transistor M1.

[0132] The fifth transistor M5 can be connected between the signal line supplying the first power ELVDD and the first transistor M1. Additionally, the gate electrode of the fifth transistor M5 can be connected to the i-th light-emitting control line Ei. When the light-emitting control signal with a gate cutoff voltage is supplied to the i-th light-emitting control line Ei, the fifth transistor M5 can be turned off, and can be turned on under other conditions.

[0133] The sixth transistor M6 can be connected between the first transistor M1 and the light-emitting element LD. Additionally, the gate electrode of the sixth transistor M6 can be connected to the i-th light-emitting control line Ei. When a light-emitting control signal with a gate cutoff voltage is supplied to the i-th light-emitting control line Ei, the sixth transistor M6 can be turned off, and can be turned on under other conditions.

[0134] The seventh transistor M7 can be connected between the signal line supplying the initialization power Vint and the first electrode (e.g., the anode electrode) of the light-emitting element LD. Additionally, the gate electrode of the seventh transistor M7 can be connected to the (i+1)th scan line Si+1. When a scan signal with a gate on-state voltage (e.g., a low-level voltage) is supplied to the (i+1)th scan line Si+1, the seventh transistor M7 can be turned on to supply the initialization power Vint voltage to the anode electrode of the light-emitting element LD. Here, the initialization power Vint voltage can be set to a voltage lower than the data signal voltage. That is, the initialization power Vint voltage can be set to be equal to or less than the minimum voltage of the data signal.

[0135] Figure 7 The illustration shows a case where the gate electrode of the seventh transistor M7 is connected to its anode initialization control line, which is the (i+1)th scan line Si+1. However, the spirit of the disclosed technology is not limited thereto. For example, according to some exemplary embodiments disclosed, the gate electrode of the seventh transistor M7 can be connected to the i-th scan line Si. In this case, when a scan signal for the gate on-state voltage is supplied to the i-th scan line Si, the voltage of the initialization power Vint can be supplied to the anode electrode of the light-emitting element LD through the seventh transistor M7.

[0136] The storage capacitor Cst can be connected between the signal line supplying the first power ELVDD and the first node N1. The storage capacitor Cst can store a voltage corresponding to the data signal and the threshold voltage of the first transistor M1.

[0137] The anode of the light-emitting element (LD) can be connected to the first transistor M1 via a sixth transistor M6, and the cathode can be connected to the signal line supplying the second power ELVSS. The LD produces light with a brightness (e.g., a predetermined brightness) corresponding to the amount of current supplied from the first transistor M1. The voltage value of the first power ELVDD can be set to be higher than the voltage value of the second power ELVSS, allowing current to flow to the LD.

[0138] On the other hand, the structure of the pixel PXL is not limited to Figure 7 The embodiment shown is illustrated. For example, pixel circuits of various currently known structures can be applied to the pixel PXL.

[0139] Figure 8 This illustrates some example embodiments. Figure 7 A planar diagram showing the layout of the pixels. For example, Figure 8 It shows the location Figure 1 and Figure 2 An example layout for any pixel PXL within the display area AA. For example, Figure 8 It is shown Figure 7 The diagram shows the layout of the pixel PXL. Figure 9 It is along Figure 8 A sectional view taken from line I-I'. Figure 10 It is along Figure 8 The sectional view taken from line II-II'.

[0140] In the description Figures 8 to 10 In the example embodiments, for convenience, the scan line of the (i+1)th row is referred to as "scan line i+1" (i+1), the light emission control line of the i-th row is referred to as "light emission control line Ei" (i), the data line of the j-th column is referred to as "data line Dj" (dj), and the power line of the j-th column (e.g., the power line of the j-th column to which the first power ELVDD is applied) is referred to as "power line PL" (pj).

[0141] Reference Figures 8 to 10 as well as Figures 1 to 7 The display device 10 may include a pixel PXL located in the display area AA and a wiring section for supplying drive signals and / or power to the pixel PXL. The wiring section may include scan lines Si-1, Si and Si+1, data line Dj, light emission control line Ei, power line PL and initialization power line IPL.

[0142] Scan lines Si-1, Si, and Si+1 may extend along a first direction DR1 within the display area AA. Scan lines Si-1, Si, and Si+1 may include an (i-1)th scan line Si-1, an ith scan line Si, and an (i+1)th scan line Si+1 arranged sequentially along a second direction DR2 intersecting the first direction DR1. Scan lines Si-1, Si, and Si+1 may receive scan signals. For example, the (i-1)th scan line Si-1 may receive the (i-1)th scan signal, the ith scan line Si may receive the ith scan signal, and the (i+1)th scan line Si+1 may receive the (i+1)th scan signal.

[0143] The light emission control line Ei can extend in the first direction DR1 to be parallel to the scan lines Si-1, Si, and Si+1 in the display area AA. The light emission control line Ei can receive the light emission control signal.

[0144] Data line Dj can extend along the second direction DR2 within the display area AA. That is, data line Dj can extend in a direction intersecting with control lines Si-1, Si, Si+1, and Ei, which include scan lines Si-1, Si, and Si+1, and light emission control line Ei. Data line Dj can receive data signals.

[0145] The power line PL can extend along the second direction DR2 within the display area AA, but is not limited thereto. The power line PL can be arranged separately from the data line Dj and can receive the first power line ELVDD.

[0146] The initialization power line IPL can extend along the first direction DR1 in the display area AA, but is not limited to this. The initialization power line IPL can receive the initialization power Vint.

[0147] According to some published example embodiments, the pixel PXL may include a first transistor M1 to a seventh transistor M7, a storage capacitor Cst, and a light-emitting element LD.

[0148] The first transistor M1 may include a first gate electrode GE1, a first channel CH1, a first source electrode SE1, and a first drain electrode DE1.

[0149] According to some example embodiments, the first gate electrode GE1 may be arranged to overlap with the first channel CH1 of the active pattern ACT, and at least one insulating layer (e.g., gate insulating layer 113) is inserted between the first gate electrode GE1 and the first channel CH1 of the active pattern ACT. The first gate electrode GE1 may be connected to the third drain electrode DE3 (including DE3a and DE3b) of the third transistor M3 and the fourth source electrode SE4 (including SE4a and SE4b) of the fourth transistor M4.

[0150] The first gate electrode GE1 can be connected to the third drain electrode DE3 and the fourth source electrode SE4 via the connecting wire CNL. One end of the connecting wire CNL can be connected to the first gate electrode GE1 via the first contact hole CT1, and the other end can be connected to the third drain electrode DE3 and the fourth source electrode SE4 via the second contact hole CT2.

[0151] According to some disclosed example embodiments, the first channel CH1, the first source electrode SE1, and the first drain electrode DE1 can be formed from semiconductor patterns that are either undoped or doped with impurities. For example, the first source electrode SE1 and the first drain electrode DE1 can be formed from semiconductor patterns that are doped with impurities, and the first channel CH1 can be formed from semiconductor patterns that are undoped with impurities.

[0152] The first channel CH1 has a shape that extends in any direction and can be bent several times along the longitudinal direction of extension. When viewed in a plan view, the first channel CH1 can be stacked with the first gate electrode GE1. By forming the first channel CH1 as long, the channel region of the first transistor M1 can also be formed as long. Therefore, the driving range of the gate voltage applied to the first transistor M1 is widened. Thus, the grayscale of the light emitted from the light-emitting element LD can be precisely controlled.

[0153] The first source electrode SE1 can be connected to one end of the first channel CH1. The first source electrode SE1 can be connected to the second drain electrode DE2 of the second transistor M2 and the fifth drain electrode DE5 of the fifth transistor M5. According to some example embodiments, the first drain electrode DE1 can be connected to the other end of the first channel CH1. The first drain electrode DE1 can be connected to the third source electrode SE3 of the third transistor M3 and the sixth source electrode SE6 of the sixth transistor M6.

[0154] The second transistor M2 may include a second gate electrode GE2, a second channel CH2, a second source electrode SE2, and a second drain electrode DE2.

[0155] The second gate electrode GE2 may be arranged to overlap with the second channel CH2, and at least one insulating layer (e.g., gate insulating layer 113) may be inserted between the second gate electrode GE2 and the second channel CH2. The second gate electrode GE2 may be connected to the i-th scan line Si.

[0156] The second channel CH2, the second source electrode SE2, and the second drain electrode DE2 can be formed from semiconductor patterns that are either undoped or doped. For example, the second source electrode SE2 and the second drain electrode DE2 can be formed from semiconductor patterns that are doped, and the second channel CH2 can be formed from a semiconductor pattern that is undoped. The second channel CH2 can correspond to the portion superimposed on the second gate electrode GE2.

[0157] One end of the second source electrode SE2 can be connected to the second channel CH2, and the other end of the second source electrode SE2 can be connected to the data line Dj through the sixth contact hole CT6. According to some example embodiments, one end of the second drain electrode DE2 can be connected to the second channel CH2, and the other end of the second drain electrode DE2 can be connected to the first source electrode SE1 of the first transistor M1 and the fifth drain electrode DE5 of the fifth transistor M5.

[0158] The third transistor M3 may have a dual-gate structure to prevent or reduce leakage current. That is, the third transistor M3 may include a 3a transistor M3a and a 3b transistor M3b. The 3a transistor M3a may include a 3a gate electrode GE3a, a 3a channel CH3a of the active pattern ACT, a 3a source electrode SE3a, and a 3a drain electrode DE3a. The 3b transistor M3b may include a 3b gate electrode GE3b, a 3b channel CH3b of the active pattern ACT, a 3b source electrode SE3b, and a 3b drain electrode DE3b. In the following text, the 3a gate electrode GE3a and the 3b gate electrode GE3b are referred to as the third gate electrode GE3, the 3a channel CH3a and the 3b channel CH3b of the active pattern ACT are referred to as the third channel CH3, the 3a source electrode SE3a and the 3b source electrode SE3b are referred to as the third source electrode SE3, and the 3a drain electrode DE3a and the 3b drain electrode DE3b are referred to as the third drain electrode DE3.

[0159] The third gate electrode GE3 may be arranged to be stacked with the third channel CH3, and at least one insulating layer (e.g., gate insulating layer 113) may be inserted between the third gate electrode GE3 and the third channel CH3. The third gate electrode GE3 may be connected to the i-th scan line Si.

[0160] The third channel CH3, the third source electrode SE3, and the third drain electrode DE3 can be formed from semiconductor patterns that are either undoped or doped. For example, the third source electrode SE3 and the third drain electrode DE3 can be formed from semiconductor patterns that are doped, and the third channel CH3 can be formed from a semiconductor pattern that is undoped. The portion of the third channel CH3 that is superimposed on the third gate electrode GE3 is also present.

[0161] One end of the third source electrode SE3 can be connected to the third channel CH3, and the other end of the third source electrode SE3 can be connected to the first drain electrode DE1 of the first transistor M1 and the sixth source electrode SE6 of the sixth transistor M6. According to some example embodiments, one end of the third drain electrode DE3 can be connected to the third channel CH3, and the other end of the third drain electrode DE3 can be connected to the fourth source electrode SE4 of the fourth transistor M4. Additionally, the third drain electrode DE3 can be connected to the first gate electrode GE1 of the first transistor M1 via connecting wiring CNL, the second contact hole CT2, and the first contact hole CT1.

[0162] The fourth transistor M4 may have a dual-gate structure to prevent or reduce leakage current. That is, the fourth transistor M4 may include a fourth transistor M4a and a fourth transistor M4b. The fourth transistor M4a may include a fourth gate electrode GE4a, a fourth channel CH4a of the active pattern ACT, a fourth source electrode SE4a, and a fourth drain electrode DE4a. The fourth transistor M4b may include a fourth gate electrode GE4b, a fourth channel CH4b of the active pattern ACT, a fourth source electrode SE4b, and a fourth drain electrode DE4b. In the following text, the fourth gate electrode GE4a and the fourth gate electrode GE4b are referred to as the fourth gate electrode GE4, the fourth channel CH4a and the fourth channel CH4b of the active pattern ACT are referred to as the fourth channel CH4, the fourth source electrode SE4a and the fourth source electrode SE4b are referred to as the fourth source electrode SE4, and the fourth drain electrode DE4a and the fourth drain electrode DE4b are referred to as the fourth drain electrode DE4.

[0163] The fourth gate electrode GE4 may be arranged to be stacked with the fourth channel CH4, and at least one insulating layer (e.g., gate insulating layer 113) is inserted between the fourth gate electrode GE4 and the fourth channel CH4. The fourth gate electrode GE4 may be connected to the (i-1)th scan line Si-1.

[0164] The fourth channel CH4, the fourth source electrode SE4, and the fourth drain electrode DE4 can be formed from semiconductor patterns that are either undoped or doped. For example, the fourth source electrode SE4 and the fourth drain electrode DE4 can be formed from semiconductor patterns that are doped, and the fourth channel CH4 can be formed from a semiconductor pattern that is undoped. The portion of the fourth channel CH4 stacked with the fourth gate electrode GE4 corresponds to this portion.

[0165] One end of the fourth source electrode SE4 can be connected to the fourth channel CH4, and the other end of the fourth source electrode SE4 can be connected to the third drain electrode DE3 of the third transistor M3. Additionally, the fourth source electrode SE4 can be connected to the first gate electrode GE1 of the first transistor M1 via the connecting wiring CNL, the second contact hole CT2, and the first contact hole CT1. One end of the fourth drain electrode DE4 can be connected to the fourth channel CH4, and the other end of the fourth drain electrode DE4 can be connected to the seventh drain electrode DE7 of the seventh transistor M7 of the pixel PXL in the (i-1)th row. The fourth drain electrode DE4 can be connected to the initialization power line IPL via the auxiliary connecting wiring AUX, the ninth contact hole CT9, and the eighth contact hole CT8.

[0166] The fifth transistor M5 may include a fifth gate electrode GE5, a fifth channel CH5, a fifth source electrode SE5, and a fifth drain electrode DE5.

[0167] The fifth gate electrode GE5 may be arranged to be stacked with the fifth channel CH5, and at least one insulating layer (e.g., gate insulating layer 113) may be inserted between the fifth gate electrode GE5 and the fifth channel CH5. The fifth gate electrode GE5 may be connected to the light-emitting control line Ei.

[0168] The fifth channel CH5, the fifth source electrode SE5, and the fifth drain electrode DE5 can be formed from semiconductor patterns that are either undoped or doped. For example, the fifth source electrode SE5 and the fifth drain electrode DE5 can be formed from semiconductor patterns that are doped, and the fifth channel CH5 can be formed from a semiconductor pattern that is undoped. The portion of the fifth channel CH5 stacked with the fifth gate electrode GE5 corresponds to this portion.

[0169] One end of the fifth source electrode SE5 can be connected to the fifth channel CH5, and the other end of the fifth source electrode SE5 can be connected to the power line PL through the fifth contact hole CT5. According to some example embodiments, one end of the fifth drain electrode DE5 can be connected to the fifth channel CH5, and the other end of the fifth drain electrode DE5 can be connected to the first source electrode SE1 of the first transistor M1 and the second drain electrode DE2 of the second transistor M2.

[0170] The sixth transistor M6 may include a sixth gate electrode GE6, a sixth channel CH6, a sixth source electrode SE6, and a sixth drain electrode DE6.

[0171] The sixth gate electrode GE6 may be arranged to be stacked with the sixth channel CH6, and at least one insulating layer (e.g., gate insulating layer 113) may be inserted between the sixth gate electrode GE6 and the sixth channel CH6. The sixth gate electrode GE6 may be connected to the light emission control line Ei.

[0172] The sixth channel CH6, the sixth source electrode SE6, and the sixth drain electrode DE6 are formed from semiconductor patterns that are either undoped or doped. For example, the sixth source electrode SE6 and the sixth drain electrode DE6 can be formed from semiconductor patterns that are doped, while the sixth channel CH6 can be formed from an undoped semiconductor pattern. The portion of the sixth channel CH6 stacked with the sixth gate electrode GE6 corresponds to this portion.

[0173] One end of the sixth source electrode SE6 can be connected to the sixth channel CH6, and the other end of the sixth source electrode SE6 can be connected to the first drain electrode DE1 of the first transistor M1 and the third source electrode SE3 of the third transistor M3. According to some example embodiments, one end of the sixth drain electrode DE6 can be connected to the sixth channel CH6, and the other end of the sixth drain electrode DE6 can be connected to the seventh source electrode SE7 of the seventh transistor M7.

[0174] The seventh transistor M7 may include a seventh gate electrode GE7, a seventh channel CH7, a seventh source electrode SE7, and a seventh drain electrode DE7.

[0175] The seventh gate electrode GE7 can be arranged to be stacked with the seventh channel CH7, and at least one insulating layer (e.g., gate insulating layer 113) is inserted between the seventh gate electrode GE7 and the seventh channel CH7. The seventh gate electrode GE7 can be connected to the (i+1)th scan line Si+1.

[0176] The seventh channel CH7, the seventh source electrode SE7, and the seventh drain electrode DE7 can be formed from semiconductor patterns that are either undoped or doped. For example, the seventh source electrode SE7 and the seventh drain electrode DE7 can be formed from semiconductor patterns that are doped, and the seventh channel CH7 can be formed from a semiconductor pattern that is undoped. The portion of the seventh channel CH7 stacked with the seventh gate electrode GE7 corresponds to this portion.

[0177] One end of the seventh source electrode SE7 can be connected to the seventh channel CH7, and the other end of the seventh source electrode SE7 can be connected to the sixth drain electrode DE6 of the sixth transistor M6. According to some example embodiments, one end of the seventh drain electrode DE7 can be connected to the seventh channel CH7, and the other end of the seventh drain electrode DE7 can be connected to the initialization power line IPL through auxiliary connection wiring AUX, the ninth contact hole CT9, and the eighth contact hole CT8.

[0178] The storage capacitor Cst may include a first capacitor electrode LE and a second capacitor electrode UE. According to some example embodiments, the first capacitor electrode LE may be the lower electrode of the storage capacitor Cst and may be integrally formed with the first gate electrode GE1 of the first transistor M1. According to some example embodiments, the second capacitor electrode UE may be the upper electrode of the storage capacitor Cst and may be stacked with the first gate electrode GE1. Additionally, as seen in a plan view, the second capacitor electrode UE may cover at least one area of ​​the first capacitor electrode LE. The capacitance of the storage capacitor Cst can be increased by expanding the stacked area of ​​the first capacitor electrode LE and the second capacitor electrode UE.

[0179] The second capacitor electrode UE may extend in the first direction DR1. According to some disclosed example embodiments, a voltage at the same level as the first power ELVDD may be applied to the second capacitor electrode UE. The second capacitor electrode UE may have another opening OPN in the region where the first gate electrode GE1 and the connection wiring CNL are in contact.

[0180] A light-emitting element (LD) may include a first electrode (e.g., an anode electrode) AD, a second electrode (e.g., a cathode electrode) CD, and a light-emitting layer EML disposed between the first electrode AD and the second electrode CD. According to some example embodiments, the first electrode AD and the second electrode CD are arranged to overlap each other in the light-emitting region LA of the light-emitting element layer LDL, and the light-emitting layer EML may be formed in the light-emitting region LA. That is, the light-emitting region LA of each pixel PXL may be the region where the first electrode AD, the light-emitting layer EML, and the second electrode CD of the light-emitting element LD overlap each other.

[0181] The first electrode AD can be disposed in the light-emitting region (e.g., a predetermined light-emitting region) LA. The first electrode AD can be connected to the seventh source electrode SE7 of the seventh transistor M7 and the sixth drain electrode DE6 of the sixth transistor M6 through the fourth contact hole CT4 and the seventh contact hole CT7. The bridging pattern BRP can be disposed between the fourth contact hole CT4 and the seventh contact hole CT7. The bridging pattern BRP can connect the sixth drain electrode DE6, the seventh source electrode SE7, and the first electrode AD.

[0182] In the following, a stacked structure (cross-sectional structure) of a pixel PXL and a display area AA including the pixel PXL will be described according to some of the disclosed example embodiments.

[0183] First, the buffer layer 112 can be disposed on the first surface of the substrate 111.

[0184] Active patterns (as in the following text, such as) Figure 5The "ACT" in the text can be disposed on the buffer layer 112. According to some example embodiments, the active pattern ACT can include a first channel CH1 to a seventh channel CH7. The first channel CH1 to the seventh channel CH7 can be formed of a semiconductor material.

[0185] The gate insulating layer 113 may be disposed on a buffer layer 112 on which the first channel CH1 to the seventh channel CH7 are disposed. According to some example embodiments, the gate insulating layer 113 may be a gate insulating film inserted between the active pattern ACT of transistors M1 to M7 included in pixel PXL and the gate electrodes GE1 to GE7.

[0186] The gate insulating layer 113 may include at least one inorganic film and / or an organic film. For example, the gate insulating layer 113 may be composed of SiO2. x SiN x Inorganic films such as, but not limited to, can be formed. For example, the gate insulating layer 113 may include, for example, SiO2. x SiN x SiON, SiOF or AlO x It can be an inorganic or organic insulating material, and can be a single or multiple membrane including at least one of these materials.

[0187] According to some disclosed example embodiments, the gate insulating layer 113 may have a finite thickness within a certain range (e.g., a predetermined range) to easily drive transistors M1 to M7. For example, the gate insulating layer 113 may have approximately to (e.g., about The thickness of the gate insulating layer 113 is not limited to this.

[0188] The first conductive layer may be located on the gate insulating layer 113. According to some example embodiments, the first conductive layer may be a first gate layer. The first conductive layer may be provided with control lines Si-1, Si, Si+1, and Ei, and gate electrodes GE1 to GE7. Additionally, one electrode of the storage capacitor Cst (e.g., the first capacitor electrode LE) may be disposed in the first conductive layer. Specifically, the (i-1)th scan line Si-1, the ith scan line Si, the (i+1)th scan line Si+1, the light emission control line Ei, and the first gate electrodes GE1 to the seventh gate electrodes GE7 may be disposed. According to some example embodiments, the first gate electrode GE1 may also be the first capacitor electrode LE of the storage capacitor Cst. That is, the first gate electrode GE1 and the first capacitor electrode LE may be integrally formed.

[0189] The control lines Si-1, Si, Si+1, and Ei, the gate electrodes GE1 to GE7, and / or the first capacitor electrode LE, which serves as the lower electrode of the storage capacitor Cst, located in the first conductive layer, can be constructed from the same material. For example, the control lines Si-1, Si, Si+1, and Ei, the gate electrodes GE1 to GE7, and / or the first capacitor electrode LE of the storage capacitor Cst can be formed from the first gate metal (e.g., a predetermined first gate metal).

[0190] Examples of materials capable of constructing the first gate metal include Ti, Cu, Mo, Al, Au, Cr, TiN, Ag, Pt, Pd, Ni, Sn, Co, Rh, Ir, Fe, Ru, Os, Mn, W, Nb, Ta, Bi, Sb, Pb, etc., and various other metals can be used as materials capable of constructing the first gate metal. Examples of alloys capable of constructing the first gate metal include MoTi, AlNiLa, etc., and various other alloys can be used as alloys capable of constructing the first gate metal. Examples of multilayer films capable of constructing the first gate metal include Ti / Cu, Ti / Au, Mo / Al / Mo, ITO / Ag / ITO, TiN / Ti / Al / Ti, TiN / Ti / Cu / Ti, etc., and various other conductive materials for multilayer film structures can be used as multilayer films capable of constructing the first gate metal.

[0191] On the other hand, the materials used to construct the control lines Si-1, Si, Si+1 and Ei, the gate electrodes GE1 to GE7 and / or the first capacitor electrode LE are not limited to metals. That is, any material capable of providing sufficient conductivity to smoothly drive the pixel PXL can be used as the material for constructing the control lines Si-1, Si, Si+1 and Ei, the gate electrodes GE1 to GE7 and / or the first capacitor electrode LE.

[0192] For example, the control lines Si-1, Si, Si+1, and Ei, the gate electrodes GE1 to GE7, and / or the first capacitor electrode LE can be constructed from conductive polymers or conductive metal oxides. Examples of conductive polymers capable of constructing the control lines Si-1, Si, Si+1, and Ei, the gate electrodes GE1 to GE7, and / or the first capacitor electrode LE include polythiophene compounds, polypyrrole compounds, polyaniline compounds, polyacetylene compounds, polyphenylene compounds, mixtures thereof, etc. Specifically, in polythiophene compounds, PEDOT / PSS compounds can be used. Examples of conductive metal oxides capable of constructing the control lines Si-1, Si, Si+1, and Ei, the gate electrodes GE1 to GE7, and / or the first capacitor electrode LE include ITO, IZO, AZO, ITZO, ZnO, SnO2, etc.

[0193] A first insulating intermediate layer 114 may be disposed on the first conductive layer. According to some example embodiments, the first insulating intermediate layer 114 may be a first interlayer insulating film inserted between the first capacitor electrode LE and the second capacitor electrode UE. According to some example embodiments, the first insulating intermediate layer 114 may have a thickness limited to a certain range (e.g., a predetermined range) to sufficiently ensure the capacity of the storage capacitor Cst within a limited area. According to some example embodiments, the first insulating intermediate layer 114 may have a thickness similar to that of the gate insulating layer 113. For example, the first insulating intermediate layer 114 may have approximately... to (e.g., about The thickness of the first insulating intermediate layer 114 is not limited to this.

[0194] The first insulating intermediate layer 114 may include one or more inorganic and / or organic films. For example, the first insulating intermediate layer 114 may be composed of SiO2. x SiN x Inorganic film structures, such as, but not limited to, are also possible. For example, the first insulating intermediate layer 114 may include, for instance, SiO2. x SiN x SiON, SiOF or AlO x It is an inorganic or organic insulating material, and may be a single-film or multilayer film including at least one of these materials.

[0195] The second conductive layer may be disposed on the first insulating intermediate layer 114. According to some example embodiments, the second conductive layer may be a second gate layer.

[0196] The second conductive layer may be provided with a second capacitor electrode UE and an initialization power line IPL. According to some example embodiments, the second capacitor electrode UE may cover the first capacitor electrode LE. The second capacitor electrode UE is stacked with the first capacitor electrode LE, and a first insulating interlayer 114 is inserted between the second capacitor electrode UE and the first capacitor electrode LE to form a storage capacitor Cst together with the first capacitor electrode LE.

[0197] The second capacitor electrode UE and the initialization power line IPL disposed in the second conductive layer can be constructed from the same material. For example, the second capacitor electrode UE and the initialization power line IPL can be formed from a second gate metal (e.g., a predetermined second gate metal). According to some example embodiments, the second gate metal can be one of the metallic materials previously presented as examples of the first gate metal, but is not limited thereto. Furthermore, the construction material of the second capacitor electrode UE and the initialization power line IPL disposed in the second conductive layer is not necessarily limited to metal. That is, any material capable of providing sufficient conductivity to smoothly drive the pixel PXL can be used as the material for constructing the second capacitor electrode UE and the initialization power line IPL. For example, the second capacitor electrode UE and the initialization power line IPL disposed in the second conductive layer can be constructed from a conductive polymer or a conductive metal oxide.

[0198] The second insulating intermediate layer 115 may be disposed on the second conductive layer. According to some example embodiments, the second insulating intermediate layer 115 may be a second interlayer insulating film. The second insulating intermediate layer 115 may have a thickness greater than the thickness of the gate insulating layer 113 and the first insulating intermediate layer 114. For example, the thickness of the second insulating intermediate layer 115 may be equal to or greater than the sum of the thickness of the gate insulating layer 113 and the thickness of the first insulating intermediate layer 114. For example, the second insulating intermediate layer 115 may have approximately... The thickness of the second insulating intermediate layer 115 is not limited to this. When the second insulating intermediate layer 115 is formed to have a sufficient thickness greater than the sum of the thickness of the gate insulating layer 113 and the thickness of the first insulating intermediate layer 114 as described above, electrical stability between components located above and below the second insulating intermediate layer 115 can be ensured. Therefore, short-circuit defects can be effectively prevented or reduced.

[0199] The second insulating interlayer 115 may include one or more inorganic and / or organic films. For example, the second insulating interlayer 115 may be composed of SiO2. x SiN x Inorganic film structures, such as, but not limited to, are also possible. For example, the second insulating intermediate layer 115 may include, for instance, SiO2. x SiN x SiON, SiOF or AlO x It can be an inorganic or organic insulating material, and can be a single or multiple membrane including at least one of these materials.

[0200] The third conductive layer may be disposed on the second insulating intermediate layer 115. According to some example embodiments, the third conductive layer may be a source-drain layer.

[0201] The third conductive layer can be configured with data lines (Dj), power lines (PL), connection wiring (CNL), bridging patterns (BRP), and auxiliary connection wiring (AUX).

[0202] The data line Dj can be electrically connected to the second source electrode SE2 through the sixth contact hole CT6 passing through the gate insulating layer 113, the first insulating intermediate layer 114, and the second insulating intermediate layer 115.

[0203] The power line PL can be connected to the second capacitor electrode UE, which serves as the upper electrode of the storage capacitor Cst, via the third contact hole CT3 passing through the second insulating intermediate layer 115. Additionally, the power line PL can be connected to the fifth source electrode SE5 via the fifth contact hole CT5 passing through the gate insulating layer 113, the first insulating intermediate layer 114, and the second insulating intermediate layer 115.

[0204] The connection wiring CNL can be connected to the first gate electrode GE1 through the first contact hole CT1 passing through the first insulating intermediate layer 114 and the second insulating intermediate layer 115. In addition, the connection wiring CNL can be electrically connected to the third drain electrode DE3 and the fourth source electrode SE4 through the second contact hole CT2 passing through the gate insulating layer 113, the first insulating intermediate layer 114 and the second insulating intermediate layer 115.

[0205] The bridging pattern BRP can be a pattern configured to connect the sixth drain electrode DE6 and the first electrode AD. This bridging pattern BRP can be electrically connected to the sixth drain electrode DE6 and the seventh source electrode SE7 through a fourth contact hole CT4 passing through the gate insulating layer 113, the first insulating intermediate layer 114, and the second insulating intermediate layer 115.

[0206] The auxiliary connection wiring AUX can be connected to the initialization power line IPL via the eighth contact hole CT8 passing through the second insulating intermediate layer 115. Additionally, the auxiliary connection wiring AUX can be connected to the seventh drain electrode DE7 via the ninth contact hole CT9 passing through the gate insulating layer 113, the first insulating intermediate layer 114, and the second insulating intermediate layer 115.

[0207] The data lines Dj, power lines PL, connection wiring CNL, bridging pattern BRP, and / or auxiliary connection wiring AUX arranged in the third conductive layer can be constructed from the same material. For example, the data lines Dj, power lines PL, connection wiring CNL, bridging pattern BRP, and / or auxiliary connection wiring AUX can be formed from source and drain metals (e.g., predetermined source and drain metals).

[0208] The source and drain metals can be, but are not limited to, one of the metallic materials previously presented as examples of the first gate metal and / or the second gate metal. Furthermore, the construction materials for the data lines Dj, power lines PL, connection wiring CNL, bridging pattern BRP, and / or auxiliary connection wiring AUX disposed in the third conductive layer are not necessarily limited to metals. That is, any material capable of providing sufficient conductivity to smoothly drive the pixel PXL can be used as the material for constructing the data lines Dj, power lines PL, connection wiring CNL, bridging pattern BRP, and / or auxiliary connection wiring AUX. For example, the data lines Dj, power lines PL, connection wiring CNL, bridging pattern BRP, and / or auxiliary connection wiring AUX can be constructed from conductive polymers or conductive metal oxides.

[0209] At least two of the first gate metal, the second gate metal, and the source and drain metals can be formed of the same material. For example, even if the first gate metal and the second gate metal are disposed on different layers, the first gate metal and the second gate metal can still be formed of the same material. However, the disclosure is not limited thereto. For example, according to some exemplary embodiments, all of the first gate metal, the second gate metal, and the source and drain metals can be formed of different materials.

[0210] The protective layer 116 may be disposed on the third conductive layer. According to some example embodiments, the protective layer 116 may include a passivation film and / or a planarization film. The protective layer 116 may include a seventh contact hole CT7 that exposes a portion of the bridging pattern BRP.

[0211] The light-emitting element LD can be disposed on the protective layer 116. The light-emitting element LD may include a first electrode AD, a second electrode CD, and a light-emitting layer EML disposed between the first electrode AD and the second electrode CD.

[0212] At least one of the first electrode AD and the second electrode CD can be a transmission electrode. For example, when the light-emitting element LD is a back-surface emitting organic light-emitting display element, the first electrode AD can be a transmission electrode, and the second electrode CD can be a reflection electrode. On the other hand, when the light-emitting element LD is a front-surface emitting organic light-emitting display element, the first electrode AD can be a reflection electrode, and the second electrode CD can be a transmission electrode. Furthermore, when the light-emitting element LD is a dual-surface emitting organic light-emitting display element, both the first electrode AD and the second electrode CD can be transmission electrodes. In the following description, the case where the light-emitting element LD is a front-surface emitting organic light-emitting display element and the first electrode AD is an anode electrode will be used as an example. In this embodiment, the light-emitting element LD is used as a light source, but the disclosure is not limited thereto. For example, another type of light-emitting element can be used instead of the light-emitting element LD.

[0213] The first electrode AD can be disposed on the protective layer 116. The first electrode AD can be connected to the bridging pattern BRP through the seventh contact hole CT7 passing through the protective layer 116. Because the bridging pattern BRP is connected to the sixth drain electrode DE6 and the seventh source electrode SE7 through the fourth contact hole CT4, the first electrode AD can ultimately be connected to the sixth drain electrode DE6 and the seventh source electrode SE7 through the bridging pattern BRP.

[0214] The first electrode AD may include a reflective film capable of reflecting light and a transparent conductive film disposed above or below the reflective film. At least one of the transparent conductive film and the reflective film may be connected to the sixth drain electrode DE6 and the seventh source electrode SE7.

[0215] The reflective film may include materials capable of reflecting light. For example, the reflective film may include at least one of aluminum (Al), silver (Ag), chromium (Cr), molybdenum (Mo), platinum (Pt), nickel (Ni), and alloys thereof.

[0216] Transparent conductive films may include transparent conductive oxides. For example, a transparent conductive film may include at least one transparent conductive oxide selected from indium tin oxide (“ITO”), indium zinc oxide (“IZO”), zinc aluminum oxide (“AZO”), gallium-doped zinc oxide (“GZO”), zinc tin oxide (“ZTO”), gallium tin oxide (“GTO”), and fluorine-doped tin oxide (“FTO”).

[0217] The light-emitting layer (EML) can be disposed on the exposed surface of the first electrode (AD). The EML can have a multilayer thin film structure including a light-generating layer (“LGL”). For example, the EML may include a hole injection layer (“HIL”) for injecting holes, a hole transport layer (“HTL”) for increasing the chance of hole recombination by suppressing the movement of unbound electrons in the light-generating layer and having excellent hole transport capability, a light-generating layer for emitting light by recombination of injected electrons and holes, a hole blocking layer (“HBL”) for suppressing the movement of unbound holes in the light-generating layer, an electron transport layer (“ETL”) for smoothly transporting electrons to the light-generating layer, and / or an electron injection layer (“EIL”) for injecting electrons.

[0218] The color of the light generated in the light-generating layer can be one of red, green, blue, and white, but the disclosure is not limited to this. For example, the color of the light generated in the light-generating layer of the emissive layer (EML) can be one of magenta, cyan, and yellow.

[0219] The hole injection layer, hole transport layer, hole blocking layer, electron transport layer, and electron injection layer can be common films that are connected to each other in adjacent light-emitting regions (LA).

[0220] The second electrode CD can be a transmissive and reflective film. For example, the second electrode CD can be a thin-film metal layer with a thickness sufficient to transmit light emitted from the light-emitting layer EML. For example, the second electrode CD can transmit some of the light emitted from the light-emitting layer EML and reflect the remaining light emitted from the light-emitting layer EML.

[0221] According to some example embodiments, the second electrode CD may comprise a material having a work function lower than that of the transparent conductive film. For example, the second electrode CD may comprise at least one of molybdenum (Mo), tungsten (W), silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), and alloys thereof.

[0222] Some light emitted from the emissive layer (EML) can bypass the second electrode (CD), and the light reflected from the second electrode (CD) can be reflected again in the reflective film. That is, the light emitted from the emissive layer (EML) can resonate between the reflective film and the second electrode (CD). The light extraction efficiency of the light-emitting element (LD) can be improved through light resonance.

[0223] A pixel defining layer (or dam layer) 117 for dividing the light-emitting region LA of each pixel PXL can be disposed on a substrate 111 on which a first electrode AD is positioned. The pixel defining layer 117 can expose the upper surface of the first electrode AD and can protrude from the substrate 111 along the outer periphery of each light-emitting region LA.

[0224] The light-emitting layer EML can be disposed in the light-emitting region LA surrounded by the pixel-defining layer 117 of each pixel PXL, and the second electrode CD can be disposed on the light-emitting layer EML. One of the first electrode AD and the second electrode CD can be an anode electrode, and the other can be a cathode electrode. For example, the first electrode AD can be an anode electrode, and the second electrode CD can be a cathode electrode.

[0225] The pixel defining layer 117 may include an organic insulating material. For example, the pixel defining layer 117 may include at least one of polystyrene, polymethyl methacrylate (“PMMA”), polyacrylonitrile (“PAN”), polyamide (“PA”), polyimide (“PI”), polyaryl ether (“PAE”), heterocyclic polymer, parylene, epoxy resin, benzocyclobutene (“BCB”), siloxane resin, and silane resin.

[0226] In the various disclosed embodiments, the pixel defining layer 117 may include a light-blocking material. For example, the pixel defining layer 117 may include carbon or black pigment. Thus, the pixel defining layer 117 can reflect light incident from above to the outside without passing through the underlying layer.

[0227] An encapsulation layer 118 covering the second electrode CD can be disposed on the second electrode CD. According to some example embodiments, the encapsulation layer 118 can be replaced by another type of encapsulation film, encapsulation substrate, at least one protective film, etc.

[0228] The encapsulation layer 118 can prevent or reduce the penetration of oxygen and moisture into the light-emitting element (LD). For this purpose, the encapsulation layer 118 may include an inorganic film. The inorganic film may include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, zirconium oxide, and tin oxide.

[0229] Each of the circuit elements and wirings arranged on the first surface of the substrate 111, from the buffer layer 112 to the protective layer 116, can constitute the circuit element layer PDL of the display device 10 and / or the fingerprint sensor. Additionally, the light-emitting elements LD arranged in each pixel PXL from the first electrode AD to the second electrode CD, and the pixel defining layer 117 arranged between the light-emitting elements LD, can constitute the light-emitting element layer LDL of the display device 10 and / or the fingerprint sensor. Furthermore, an encapsulation layer 118, etc., can be formed to at least cover the light-emitting element layer LDL.

[0230] Figure 11 It is a plan view showing the layout of pixels according to some of the disclosed example embodiments. Figure 12 It is along Figure 11 The sectional view taken from line III-III'. Figure 13 It is along Figure 11 A sectional view taken along line IV-IV'. Based on... Figures 11 to 13 In the embodiments, with respect to Figures 8 to 10 Components that are identical or similar to those in the embodiments are indicated by the same reference numerals, and their detailed descriptions will be omitted.

[0231] Specifically, Figures 11 to 13 The first pixel PXL1 shown is in Figure 1 and Figure 2 The pixel PXL of the sensing region SA shown includes at least one light transmission aperture LTH and any pixel that includes at least one opening OPA in a portion of the pixel defining layer 117. That is, according to some disclosed example embodiments, at least a portion of the pixel PXL of the sensing region SA can be as follows: Figure 11 and Figure 12 The first pixel PXL1 shown includes an opening OPA formed in the pixel defining layer 117 and a light transmission aperture LTH, at least a portion of which is superimposed on the opening OPA.

[0232] Reference Figures 11 to 13According to some of the disclosed example embodiments, a first pixel PXL1 may include a light-transmitting aperture LTH formed in at least one conductive layer of a circuit element layer PDL. A sensing region SA may include a plurality of first pixels PXL1 including light-transmitting apertures LTH.

[0233] The light transmission aperture (LTH) may include a multilayer opening formed to be stacked with multiple conductive layers that constitute a circuit element layer (PDL). For example, the light transmission aperture (LTH) may include a multilayer opening formed to be stacked with at least two of the following layers: a semiconductor layer in which an active pattern ACT is disposed, a first conductive layer in which gate electrodes GE1 to GE7 are disposed, a second conductive layer in which second capacitor electrodes UE are disposed, and a third conductive layer in which power lines PL and bridging patterns BRP are disposed.

[0234] According to some disclosed example embodiments, a light transmission aperture LTH can be arranged in a first pixel PXL1 such that at least a portion of the light transmission aperture LTH is superimposed on an opening OPA formed in the pixel defining layer 117. That is, the light transmission aperture LTH can be arranged in a region other than the light-emitting region LA of the first pixel PXL1, so as not to be superimposed on the first electrode AD that constitutes the light-emitting element LD.

[0235] According to the above embodiments, an array of light-transmitting apertures can be formed to receive reflected light integrally with the light-emitting element layer (LDL) and the circuit element layer (PDL), without forming an additional layer in the circuit element layer (PDL). Therefore, the module thickness of the display device 10 can be reduced.

[0236] On the other hand, in the various disclosed embodiments, the structure and form of the light transmission aperture LTH are not limited to... Figures 11 to 13 The structure and form of the light transmission aperture LTH are shown. That is, according to some example embodiments, the light transmission aperture LTH can be formed in another region (e.g., including the region of another opening OPN formed in the second capacitor electrode UE). According to some example embodiments, various modifications can be made to the layout structure so that the conductive layer is not arranged in the light transmission aperture LTH.

[0237] Figures 14A to 14C This is a plan view showing various embodiments of the relative structural arrangement of the opening and the area where the reflected light reaches corresponding to the opening.

[0238] According to some example embodiments, such as Figure 14A and Figure 14BAs shown, the opening OPA and the light-transmitting region LTP can be regularly arranged along a first direction DR1 and a second direction DR2 perpendicular to the first direction DR1. In such an embodiment, eight adjacent opening OPAs and light-transmitting regions LTP can be arranged for any opening OPA and light-transmitting region LTP, and the adjacent opening OPAs and light-transmitting regions LTP can be arranged to form a quadrilateral. That is, adjacent opening OPAs and light-transmitting regions LTP can be arranged at each vertex and each side of the quadrilateral.

[0239] Optionally, according to some example embodiments, such as Figure 14C As shown, the opening OPA and the light-transmitting region LTP can be arranged regularly along the diagonal directions of the first direction DR1 and the second direction DR2. According to some example embodiments, six adjacent opening OPAs and light-transmitting regions LTP can be arranged for any given opening OPA and light-transmitting region LTP, and these adjacent opening OPAs and light-transmitting regions LTP can be arranged to form a hexagon. That is, adjacent opening OPAs and light-transmitting regions LTP can be located at each vertex of the hexagon.

[0240] and Figures 1 to 5 Refer to together Figures 14A to 14C Reflected light can be incident on the display surface of the display device 10 by contact with or from the finger of a user adjacent to the display device 10. Some of the reflected light is reflected by the pixel defining layer 117, but the remaining reflected light can pass through the opening OPA and the light transmission region LTP formed in the pixel defining layer 117 to reach the arrival region RA.

[0241] The size and shape of the reachable region RA can be determined differently by the size and shape of the opening OPA and the light transmission region LTP, the distance between the opening OPA and the light transmission region LTP, and the distance from the opening OPA to the light sensor PHS. In this case, at least a portion of the reachable region RA corresponding to each opening OPA and light transmission region LTP can be superimposed according to the distance between the opening OPA and the light transmission region LTP.

[0242] In the region where the arrival area RA is superimposed, because the characteristics of the reflected light may change due to mutual interference, the fingerprint detector 220 can use light collected only relative to the effective region TA in the arrival area RA that is not superimposed with another arrival area RA to detect fingerprints.

[0243] According to some example embodiments, when the distance between the opening OPA and the light transmission region LTP is close, such as Figure 14AAs shown, this may increase the area of ​​the overlapping region between the reaching regions RA and may decrease the area of ​​the effective region TA. Furthermore, as the area of ​​the effective region TA decreases, it becomes difficult to detect the precise shape of the fingerprint.

[0244] Conversely, when the distance between the opening OPA and the light transmission region LTP is widened to reduce the area of ​​the overlapping region between the arrival regions RA, the area of ​​the region where reflected light does not reach between the arrival regions RA increases, thus allowing for sufficient detection of the precise shape of the fingerprint.

[0245] Therefore, in the various disclosed embodiments, the opening OPA and the light transmission region LTP can be arranged in a suitable shape and distance such that the reach region RA overlaps minimally between the opening OPA and the light transmission region LTP, and ensures a sufficiently large effective region TA.

[0246] Reference Figure 14C In the various disclosed embodiments, the opening OPA and the light-transmitting region LTP can be regularly arranged along the diagonal directions of the first direction DR1 and the second direction DR2. In such embodiments, six adjacent opening OPAs and light-transmitting regions LTP can be arranged for any given opening OPA and light-transmitting region LTP, and the adjacent opening OPAs and light-transmitting regions LTP can be arranged to form a hexagon. That is, adjacent opening OPAs and light-transmitting regions LTP can be located at each vertex of the hexagon.

[0247] According to some example embodiments, the opening OPA and the light-transmitting region LTP are arranged not to be separated from the reflected light arrival region RA of each opening OPA and light-transmitting region LTP. Then, the effective region TA of the reflected light to the opening OPA and the light-transmitting region LTP can have a substantially hexagonal shape.

[0248] Through such Figure 14C The arrangement of the opening OPA and light transmission region LTP shown minimizes the area not reached by reflected light and maximizes the area of ​​the effective region TA within the reached region RA. Therefore, this disclosure improves the efficiency and reliability of fingerprint sensing.

[0249] Figure 15 A schematic plan view of a display device according to some exemplary embodiments disclosed is shown. Specifically, Figure 15 An example is shown in which a pixel-defining layer 117 is formed between the light-emitting areas LA of the display panel 110 according to the disclosed opening OPA.

[0250] According to some disclosed example embodiments, multiple light-emitting regions LA1, LA2, and LA3 can be arranged in the display panel 110. In the illustrated embodiment, the light-emitting regions LA1, LA2, and LA3 can have a rectangular shape. However, the spirit of the disclosed technology is not limited thereto, and the light-emitting regions LA1, LA2, and LA3 can have various shapes such as circular, elliptical, hexagonal, and octagonal. The light-emitting regions LA1, LA2, and LA3 can be arranged in a stripe pattern.

[0251] Specifically, the light-emitting regions LA1, LA2, and LA3 may include a first light-emitting region LA1 emitting light of a first color (e.g., red), a second light-emitting region LA2 emitting light of a second color (e.g., green), and a third light-emitting region LA3 emitting light of a third color (e.g., blue). The first light-emitting region LA1, the second light-emitting region LA2, and the third light-emitting region LA3 are arranged repeatedly. For example, the first light-emitting region LA1, the second light-emitting region LA2, and the third light-emitting region LA3 may be arranged sequentially.

[0252] At this point, a first light-emitting region LA1, a second light-emitting region LA2, and a third light-emitting region LA3 can construct a unit pixel UPXL. In the illustrated embodiment, the unit pixel UPXL is shown as slightly enlarged to clearly distinguish each of the light-emitting regions LA1, LA2, and LA3. An example in which the unit pixel UPXL has a rectangle is shown. However, in the various disclosed embodiments, the unit pixel UPXL can have a substantially square shape. However, the spirit of the disclosed technique is not limited thereto.

[0253] According to some example embodiments, the order of the light-emitting regions LA1, LA2, and LA3 can be maintained the same in all rows. For example, the second light-emitting region LA2 can be adjacent to the first light-emitting region LA1 in the horizontal direction H, the third light-emitting region LA3 can be adjacent to the second light-emitting region LA2 in the horizontal direction H, and the first light-emitting region LA1 can be adjacent to the third light-emitting region LA3 in the horizontal direction H. The light-emitting regions LA1, LA2, and LA3 can be surrounded by the non-light-emitting region of each of the light-emitting regions LA1, LA2, and LA3 (i.e., the pixel defining layer 117 (e.g.)). Figures 8 to 13 As shown in the diagram, they are separated.

[0254] At least one of the openings OPA1, OPA2, and OPA3 may be formed in the pixel defining layer 117. In various disclosed embodiments, at least one of the openings OPA1, OPA2, and OPA3 may be formed at a lower density than the light-emitting regions LA1, LA2, and LA3. For example, one of the openings OPA1, OPA2, and OPA3 may be arranged adjacent to some of the light-emitting regions LA1, LA2, and LA3, while the openings OPA1, OPA2, and OPA3 may not be arranged adjacent to the remaining light-emitting regions LA1, LA2, and LA3. In other words, one of the openings OPA1, OPA2, and OPA3 may be arranged adjacent to some of the unit pixels UPXL, while the openings OPA1, OPA2, and OPA3 may not be arranged adjacent to the remaining unit pixels UPXL. In this case, the openings OPA1, OPA2, and OPA3 may be arranged adjacent to a first light-emitting region LA1 that emits red light in a unit pixel UPXL. However, the disclosure is not limited to this.

[0255] According to some exemplary embodiments, at least one of the openings OPA1, OPA2, and OPA3 can be as described in reference. Figure 14C The arrangement is described along the diagonal direction D1 of the horizontal direction H and the vertical direction V. That is, when the first opening OPA1 and the second opening OPA2 constitute the first row of openings OPA1, OPA2 and OPA3, the first opening OPA1 constitutes the first column of openings OPA1, OPA2 and OPA3, and the second opening OPA2 constitutes the third column of openings OPA1, OPA2 and OPA3, the third opening OPA3 can constitute the second row of openings OPA1, OPA2 and OPA3 and the second column of openings OPA1, OPA2 and OPA3.

[0256] When this arrangement is repeated, six adjacent openings OPA1, OPA2, and OPA3 can be arranged relative to any of the openings OPA1, OPA2, and OPA3, and the adjacent openings OPA1, OPA2, and OPA3 can be arranged to form a hexagon. That is, the adjacent openings OPA1, OPA2, and OPA3 can be located at each vertex of the hexagon.

[0257] In the above embodiment, openings OPA1, OPA2, and OPA3 can be located between unit pixels UPXL, such that three adjacent openings OPA1, OPA2, and OPA3 form a substantially equilateral triangle. For example, openings OPA1, OPA2, and OPA3 can be arranged sequentially in the horizontal direction H for every eight unit pixels UPXL, as shown in the figure, and can be arranged sequentially in the vertical direction V for every seven unit pixels UPXL. Then, as referred to Figure 14CAs described, there is no separation between the arrival areas RA of the reflected light to each of the openings OPA1, OPA2 and OPA3, and the effective area TA can be maximized in each arrival area RA.

[0258] According to some example embodiments, an opening OPA1, OPA2, and OPA3, along with an adjacent light-emitting region LA1, LA2, and LA3, can form a pixel PXL. For example, in Figure 15 In this embodiment, the first opening OPA1 and the first light-emitting region LA1 can constitute a pixel PXL. In such an embodiment, adjacent openings OPA1, OPA2, and OPA3, as well as light-emitting regions LA1, LA2, and LA3, can be connected with... Figures 11 to 13 The first pixel PXL1 shown corresponds to this. Conversely, the light-emitting areas LA1, LA2, and LA3, which are not adjacent to the openings OPA1, OPA2, and OPA3, can be arranged with... Figures 8 to 10 The pixel PXL shown corresponds to this.

[0259] Figure 16 A schematic plan view of a display device according to some of the disclosed example embodiments is shown. Figure 16 An example is shown in which a pixel-defining layer 117 is formed between the light-emitting areas LA of the display panel 110 according to the disclosed opening OPA.

[0260] According to some disclosed example embodiments, multiple light-emitting regions LA1, LA2, and LA3 can be arranged in the display panel 110. In the illustrated embodiment, the light-emitting regions LA1, LA2, and LA3 can have a rectangular shape. However, the spirit of the disclosed technology is not limited thereto, and the light-emitting regions LA1, LA2, and LA3 can have various shapes such as circular, elliptical, hexagonal, and octagonal. According to some example embodiments, the light-emitting regions LA1, LA2, and LA3 can be formed such that at least some of the light-emitting regions LA1, LA2, and LA3 have different areas. For example, as shown in the figure, the second light-emitting region LA2 can have a smaller area than the first light-emitting region LA1 and the third light-emitting region LA3. However, the disclosure is not limited thereto.

[0261] The emitting regions LA1, LA2, and LA3 can be arranged in a pentile configuration. Each emitting region LA1, LA2, and LA3 may include a first emitting region LA1 emitting light of a first color (e.g., red), a second emitting region LA2 emitting light of a second color (e.g., green), and a third emitting region LA3 emitting light of a third color (e.g., blue). The first emitting region LA1, the second emitting region LA2, and the third emitting region LA3 are arranged repeatedly. For example, the first emitting region LA1, the second emitting region LA2, and the third emitting region LA3 can be arranged sequentially.

[0262] At this point, a region of the first light-emitting region LA1 adjacent to the second light-emitting region LA2, a region of the second light-emitting region LA2, and a region of the third light-emitting region LA3 adjacent to the second light-emitting region LA2 can construct a unit pixel UPXL. According to some example embodiments, the unit pixel UPXL can have a substantially square shape. However, the spirit of the disclosed technology is not limited thereto.

[0263] According to some example embodiments, the order of the light-emitting regions LA1, LA2, and LA3 can be changed according to the row. For example, the second light-emitting region LA2 can be adjacent to the first light-emitting region LA1 in the horizontal direction H, and the third light-emitting region LA3 can be adjacent to the first light-emitting region LA1 in the vertical direction V. Specifically, as Figure 16 As shown, a first luminescent region LA1 can be arranged adjacent to two second luminescent regions LA2. The luminescent regions LA1, LA2, and LA3 can be arranged around the non-luminescent region of each of the luminescent regions LA1, LA2, and LA3 (i.e., the pixel-defining layer 117). Figures 8 to 13 As shown in the diagram, they are separated.

[0264] At least one of the openings OPA1, OPA2, and OPA3 may be formed in the pixel defining layer 117. In various disclosed embodiments, at least one of the openings OPA1, OPA2, and OPA3 may be formed at a lower density than the light-emitting regions LA1, LA2, and LA3. For example, one of the openings OPA1, OPA2, and OPA3 may be arranged adjacent to some of the light-emitting regions LA1, LA2, and LA3, while the openings OPA1, OPA2, and OPA3 may not be arranged adjacent to the remaining light-emitting regions LA1, LA2, and LA3. In other words, one of the openings OPA1, OPA2, and OPA3 may be arranged adjacent to some of the unit pixels UPXL, while the openings OPA1, OPA2, and OPA3 may not be arranged adjacent to the remaining unit pixels UPXL. In this case, the openings OPA1, OPA2, and OPA3 may be arranged adjacent to a first light-emitting region LA1 or a third light-emitting region LA3 that emits red or blue light in a unit pixel UPXL. However, the disclosure is not limited to this.

[0265] According to some exemplary embodiments, at least one of the openings OPA1, OPA2, and OPA3 can be as described in reference. Figure 14CThe arrangement is described along the diagonal direction D1 of the horizontal direction H and the vertical direction V. That is, when the first opening OPA1 and the second opening OPA2 constitute the first row of openings OPA1, OPA2 and OPA3, the first opening OPA1 constitutes the first column of openings OPA1, OPA2 and OPA3, and the second opening OPA2 constitutes the third column of openings OPA1, OPA2 and OPA3, the third opening OPA3 can constitute the second row of openings OPA1, OPA2 and OPA3 and the second column of openings OPA1, OPA2 and OPA3.

[0266] When this arrangement is repeated, six adjacent openings OPA1, OPA2, and OPA3 can be arranged relative to any of the openings OPA1, OPA2, and OPA3, and the adjacent openings OPA1, OPA2, and OPA3 can be arranged to form a hexagon. That is, the adjacent openings OPA1, OPA2, and OPA3 can be arranged at each vertex of the hexagon.

[0267] In the above embodiment, openings OPA1, OPA2, and OPA3 can be arranged between unit pixels UPXL such that three adjacent openings OPA1, OPA2, and OPA3 form a substantially equilateral triangle. For example, openings OPA1, OPA2, and OPA3 can be arranged sequentially in the horizontal direction H for every eight unit pixels UPXL, as shown in the figure, and sequentially in the vertical direction V for every seven unit pixels UPXL. Then, as referred to... Figure 14C As described, there is no separation between the arrival areas RA of the reflected light to each of the openings OPA1, OPA2 and OPA3, and the effective area TA can be maximized in each arrival area RA.

[0268] According to some example embodiments, an opening OPA1, OPA2, and OPA3 and an adjacent light-emitting region LA1, LA2, and LA3 can form a pixel PXL. For example, in Figure 16 In this embodiment, the first opening OPA1 and the first light-emitting region LA1 can constitute a pixel PXL. In such an embodiment, adjacent openings OPA1, OPA2, and OPA3, as well as light-emitting regions LA1, LA2, and LA3, can be connected with... Figures 11 to 13 The first pixel PXL1 shown corresponds to this. Conversely, the light-emitting areas LA1, LA2, and LA3, which are not adjacent to the openings OPA1, OPA2, and OPA3, can be arranged with... Figures 8 to 10 The pixel PXL shown corresponds to this.

[0269] Figure 17 A schematic plan view of a display device according to some of the disclosed example embodiments is shown. Figure 17An example is shown in which a pixel-defining layer 117 is formed between the light-emitting areas LA of the display panel 110 according to the disclosed opening OPA.

[0270] According to some disclosed example embodiments, multiple light-emitting regions LA1, LA2, and LA3 can be arranged in the display panel 110. In the illustrated embodiment, the light-emitting regions LA1, LA2, and LA3 can have a rhomboid shape. According to some example embodiments, the light-emitting regions LA1, LA2, and LA3 can be formed such that at least some of the light-emitting regions LA1, LA2, and LA3 have different areas. For example, as shown in the figure, the second light-emitting region LA2 can have a smaller area than the first light-emitting region LA1 and the third light-emitting region LA3. However, the disclosure is not limited thereto.

[0271] The emitting regions LA1, LA2, and LA3 can be arranged in a pentile configuration. Each emitting region LA1, LA2, and LA3 may include a first emitting region LA1 emitting light of a first color (e.g., red), a second emitting region LA2 emitting light of a second color (e.g., green), and a third emitting region LA3 emitting light of a third color (e.g., blue). The first emitting region LA1, the second emitting region LA2, and the third emitting region LA3 are arranged repeatedly. For example, the first emitting region LA1, the second emitting region LA2, and the third emitting region LA3 can be arranged sequentially.

[0272] For example, the second luminescent region LA2 can be adjacent to the first luminescent region LA1 in a diagonal direction D1 inclined to the horizontal direction H, and the third luminescent region LA3 can be adjacent to the first luminescent region LA1 in the horizontal direction H. Specifically, as Figure 17 As shown, a second light-emitting region LA2 can be surrounded by two first light-emitting regions LA1 and two third light-emitting regions LA3. In this case, the two first light-emitting regions LA1 can be arranged diagonally opposite each other, and the two third light-emitting regions LA3 can be arranged diagonally opposite each other. In such an embodiment, the area of ​​the second light-emitting region LA2 can be smaller than the areas of the first light-emitting regions LA1 and the third light-emitting regions LA3, but the disclosure is not limited thereto.

[0273] A unit pixel UPXL can be constructed from a region adjacent to the second light-emitting region LA2 in the first light-emitting region LA1, a region adjacent to the second light-emitting region LA2 in the second light-emitting region LA2, and a region adjacent to the second light-emitting region LA2 in the third light-emitting region LA3. According to some example embodiments, the unit pixel UPXL can have a substantially square shape. However, the spirit of the disclosed technology is not limited thereto.

[0274] The luminescent regions LA1, LA2, and LA3 can be surrounded by a non-luminescent region (i.e., pixel-defining layer 117) surrounding each of the luminescent regions LA1, LA2, and LA3. Figures 8 to 13 As shown in the diagram, the openings OPA1, OPA2, and OPA3 may be formed in the pixel defining layer 117.

[0275] In the various disclosed embodiments, at least one of the openings OPA1, OPA2, and OPA3 can be formed at a lower density than the light-emitting regions LA1, LA2, and LA3. For example, one of the openings OPA1, OPA2, and OPA3 can be arranged adjacent to some of the light-emitting regions LA1, LA2, and LA3, while the openings OPA1, OPA2, and OPA3 may not be arranged adjacent to the remaining light-emitting regions LA1, LA2, and LA3. However, the disclosure is not limited to this. In other words, one of the openings OPA1, OPA2, and OPA3 can be arranged adjacent to some of the unit pixels UPXL, while the openings OPA1, OPA2, and OPA3 may not be arranged adjacent to the remaining unit pixels UPXL. In this case, the openings OPA1, OPA2, and OPA3 can be arranged adjacent to a first light-emitting region LA1 or a third light-emitting region LA3 that emits red or blue light in a unit pixel UPXL. However, the disclosure is not limited to this.

[0276] According to some exemplary embodiments, at least one of the openings OPA1, OPA2, and OPA3 can be as described in reference. Figure 14C The arrangement is described along the diagonal direction D1 of the horizontal direction H and the vertical direction V. That is, when the first opening OPA1 and the second opening OPA2 constitute the first row of openings OPA1, OPA2 and OPA3, the first opening OPA1 constitutes the first column of openings OPA1, OPA2 and OPA3, and the second opening OPA2 constitutes the third column of openings OPA1, OPA2 and OPA3, the third opening OPA3 can constitute the second row of openings OPA1, OPA2 and OPA3 and the second column of openings OPA1, OPA2 and OPA3.

[0277] When this arrangement is repeated, the six adjacent openings OPA1, OPA2, and OPA3 can be positioned relative to any of the openings OPA1, OPA2, and OPA3, and the adjacent openings OPA1, OPA2, and OPA3 can be arranged to form a hexagon. That is, the adjacent openings OPA1, OPA2, and OPA3 can be positioned at each vertex of the hexagon.

[0278] In the above embodiment, the openings OPA1, OPA2, and OPA3 can be located between unit pixels UPXL, such that the three adjacent openings OPA1, OPA2, and OPA3 form a substantially equilateral triangle. In other words, the openings OPA1, OPA2, and OPA3 can be arranged such that the distances between two adjacent openings OPA1, OPA2, and OPA3 have substantially similar values.

[0279] For example, openings OPA1, OPA2, and OPA3 can be arranged sequentially in the horizontal direction H for every eight unit pixels UPXL, as shown in the figure, and sequentially in the vertical direction V for every seven unit pixels UPXL. In this case, the horizontal distance between adjacent openings OPA1 and OPA3 in the horizontal direction H can be 356 μm, and the diagonal distance between adjacent openings OPA1 and OPA2 or OPA3 and OPA2 in the diagonal direction D1 can be 358.8 μm. Because the horizontal and diagonal distances are substantially similar, it can be seen that adjacent openings OPA1, OPA2, and OPA3 are arranged in a substantially equilateral triangle.

[0280] Then, as referenced Figure 14C As described, there is no separation between the arrival areas RA of the reflected light to each of the openings OPA1, OPA2 and OPA3, and the effective area TA can be maximized in each arrival area RA.

[0281] According to some example embodiments, an opening OPA1, OPA2, and OPA3, along with an adjacent light-emitting region LA1, LA2, and LA3, can form a pixel PXL. For example, in Figure 17 In this embodiment, the first opening OPA1 and the first light-emitting region LA1 can constitute a pixel PXL. In such an embodiment, adjacent openings OPA1, OPA2, and OPA3, as well as light-emitting regions LA1, LA2, and LA3, can be connected with... Figures 11 to 13 The first pixel PXL1 shown corresponds to this. Conversely, the light-emitting areas LA1, LA2, and LA3, which are not adjacent to the openings OPA1, OPA2, and OPA3, can be arranged with... Figures 8 to 10 The pixel PXL shown corresponds to this.

[0282] Those skilled in the art will understand that the disclosure may be implemented in other specific forms without altering the technical spirit or essential characteristics of the disclosure. Therefore, it should be understood that the above embodiments are illustrative in all respects and not restrictive. The scope of the disclosure is defined by the claims rather than the detailed description above, and it is intended that all changes and modifications derived from the meaning and scope of the claims and their equivalents be included within the scope of the disclosure.

Claims

1. A fingerprint sensor, the fingerprint sensor comprising: Base; A circuit element layer is located on a first surface of the substrate and includes multiple conductive layers; A light-emitting element layer is located on the circuit element layer and includes a light-emitting element and a light-shielding layer; as well as A light sensor layer, located on the second surface of the substrate, includes a light sensor. The light-shielding layer includes a contact hole that exposes the first electrode of the light-emitting element and a first opening that exposes a portion of the circuit element layer. The circuit element layer includes a second opening formed in a closed shape by at least two of the plurality of conductive layers on a plane parallel to the first surface, and includes a light transmission hole in which at least a portion of the second opening is superimposed with the first opening.

2. The fingerprint sensor according to claim 1, wherein, The light-emitting element layer includes: The first electrode is located on the circuit element layer, wherein the first electrode is exposed by the contact hole to form a light-emitting area; Multiple light-emitting layers are located on the exposed first electrode; and Multiple second electrodes are located on the light-shielding layer to cover the multiple light-emitting layers, and Each of the first openings is formed to be adjacent to at least a portion of the light-emitting region.

3. The fingerprint sensor according to claim 2, wherein, The first opening is arranged along a first direction relative to the light-emitting area or along a diagonal direction relative to a second direction perpendicular to the first direction.

4. The fingerprint sensor according to claim 3, wherein, The distance between two adjacent first openings is equal to that between each other.

5. The fingerprint sensor according to claim 3, wherein, The luminescent region includes: The first luminescent region is configured to emit light of the first color; The second luminescent region is configured to emit light of a second color; and The third luminescent region is configured to emit light of the third color.

6. The fingerprint sensor according to claim 5, wherein, The first color is red, the second color is green, and the third color is blue. The first opening is arranged to be adjacent to at least one of the first light-emitting region and the third light-emitting region.

7. The fingerprint sensor according to claim 5, wherein, The light-emitting area includes unit pixels, and the unit pixel includes the first light-emitting area, the second light-emitting area, and the third light-emitting area. The first opening is arranged to be adjacent to at least a portion of the unit pixel.

8. The fingerprint sensor according to claim 7, wherein, The first opening is spaced at eight unit pixels in the first direction and at seven unit pixels in the second direction.

9. The fingerprint sensor according to claim 7, wherein, The unit pixel includes a first light-emitting region, a second light-emitting region, and a third light-emitting region arranged sequentially, and The first opening is arranged adjacent to the first light-emitting region of at least a portion of the unit pixel.

10. The fingerprint sensor according to claim 7, wherein, The unit pixel includes: A first unit pixel, wherein the first light-emitting region and the second light-emitting region are sequentially arranged in the first unit pixel; and The second unit pixel, wherein the third light-emitting region and the second light-emitting region are sequentially arranged in the second unit pixel, and The first unit pixel and the second unit pixel are arranged alternately.

11. The fingerprint sensor according to claim 10, wherein, The first opening is adjacent to at least a portion of the first light-emitting region of the first unit pixel and at least a portion of the third light-emitting region of the second unit pixel.

12. The fingerprint sensor according to claim 11, wherein, In the two adjacent first openings along the diagonal direction, the first first opening is adjacent to one of the first unit pixels in the first unit pixel, and the second first opening is adjacent to one of the second unit pixels in the second unit pixel.

13. The fingerprint sensor according to claim 2, wherein, The circuit element layer includes: A semiconductor layer, located on the substrate, includes at least one active pattern; A first conductive layer is located on the at least one active pattern and includes at least one gate electrode; A second conductive layer, located on the first conductive layer and including at least one capacitor electrode; and A third conductive layer, located on the second conductive layer and including at least one wiring, and At least one insulating layer is located between the semiconductor layer and the first conductive layer, at least one insulating layer is located between the first conductive layer and the second conductive layer, and at least one insulating layer is located between the second conductive layer and the third conductive layer.

14. The fingerprint sensor according to claim 13, wherein, The light transmission aperture includes a second opening formed in at least two of the semiconductor layer, the first conductive layer, the second conductive layer, and the third conductive layer, which are stacked on top of each other.

15. The fingerprint sensor according to claim 1, wherein, The first opening and the light transmission hole guide externally incident light to the light sensor.

16. A display device, the display device comprising: A display panel includes: a substrate; a circuit element layer located on a first surface of the substrate and including a plurality of conductive layers; and a light-emitting element layer located on the circuit element layer and including a light-emitting element and a light-shielding layer; and... A light sensor layer, located on the second surface of the display panel, includes multiple light sensors. The light-shielding layer includes a contact hole that exposes the first electrode of the light-emitting element and a first opening that exposes a portion of the circuit element layer. The circuit element layer includes a second opening formed in a closed shape by at least two of the plurality of conductive layers on a plane parallel to the first surface, and includes a light transmission hole in which at least a portion of the second opening is superimposed with the first opening.

17. The display device according to claim 16, wherein, The light-emitting element layer includes: The first electrode is located on the circuit element layer and exposed by the contact hole to form a light-emitting area; Multiple light-emitting layers are located on the exposed first electrode; and Multiple second electrodes are located on the light-shielding layer to cover the multiple light-emitting layers, and Each of the first openings is adjacent to at least a portion of the light-emitting region.

18. The display device according to claim 17, wherein, The first opening is arranged along a first direction relative to the light-emitting area or along a diagonal direction relative to a second direction perpendicular to the first direction.

19. The display device according to claim 18, wherein, The distance between two adjacent first openings is equal to that between each other.

20. The display device according to claim 17, wherein, The circuit element layer includes: A semiconductor layer, located on the substrate, includes at least one active pattern; A first conductive layer is located on the at least one active pattern and includes at least one gate electrode; A second conductive layer, located on the first conductive layer and including at least one capacitor electrode; and A third conductive layer, located on the second conductive layer, includes at least one wiring. At least one insulating layer is located between the semiconductor layer and the first conductive layer, at least one insulating layer is located between the first conductive layer and the second conductive layer, and at least one insulating layer is located between the second conductive layer and the third conductive layer. The light transmission aperture includes a second opening formed in at least two of the semiconductor layer, the first conductive layer, the second conductive layer, and the third conductive layer, which are stacked on top of each other.

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