Interpolation Methods, Graphics Pipeline, and GPU

Abstract

An interpolation method, a graphics pipeline, and a graphics processor are provided. The graphics pipeline can reduce the number of inverse, multiplication, or addition calculations used for interpolation calculations when GPU hardware has been programmed or set to perform linear perspective interpolation by determining whether the homogeneous coordinates of each vertex of a primitive are within a predetermined threshold of 1 when a linear perspective interpolation technique has been specified in a shader program, and determining one or more attributes of the element using a linear interpolation technique based on the homogeneous coordinates of each vertex of the primitive being within the predetermined threshold of 1.

Description

Technical Field

[0001] The subject matter disclosed herein relates to graphics processing units (GPUs). More specifically, the subject matter disclosed herein relates to systems and methods that can reduce the number of inverse, multiplication, and / or addition calculations used for interpolation calculations when GPU hardware has been programmed to perform linear perspective interpolation. Background Art

[0002] Pixel / fragment shader programs typically process multiple input data elements called "attributes". Typically, each shader program thread executing for a single sample can process sixteen or more different attributes, although fewer attributes can be processed. Attributes can be processed by interpolation calculations. Typically, each element can be independent of the other elements.

[0003] For most application programming interfaces (APIs), interpolation of pixel / fragment shader data can use one of three interpolation modes (planar interpolation mode, linear interpolation mode, or linear perspective interpolation mode). For the planar interpolation mode to be used, all values ​​of all samples of a given primitive are the same. For the linear interpolation mode to be used, all values ​​of all samples of a given primitive are calculated as if the values ​​were on a plane. For the linear perspective interpolation mode to be used, all values ​​of all samples of a given primitive are calculated in a planar manner and with perspective correction applied (called "perspective warp"). The most computationally expensive interpolation mode is linear perspective interpolation, and the calculation of the perspective correction is not linear.

[0004] In a graphics pipeline, position information within an image can be represented using four coordinates: X (horizontal position in the image), Y (vertical position in the image), Z (depth or distance from the eye in the image), and W (homogeneous coordinates). Homogeneous coordinates can be used to perform perspective-corrected interpolation. Each vertex of a primitive in an image has zero or more values ​​for the position (X, Y, Z, W) and other attributes associated with the vertex.

[0005] A commonly used API does not provide the application programmer with a linear interpolation mode option. To provide linear interpolation, the programmer selects linear perspective mode and sets the value of the W coordinate of all vertices of the primitive equal to 1.0. Doing so provides linear interpolation, but also uses the full computational cost associated with linear perspective interpolation. The maximum single cost of full linear perspective interpolation can be the interpolation of 1 / W, from the subsequent operation of W using the reciprocal process of 1 / W, followed by the multiplication of W and the result of the linear interpolation.

[0006] A typical GPU may have limited area provided for interpolation and, in particular, for reciprocal calculations. As a result, the reciprocal, multiplication, or division calculations used for interpolation may present a performance bottleneck. Summary of the invention

[0007] Example embodiments provide a method for interpolating one or more attributes of an element of a primitive rendered in a graphics pipeline, the method may include: determining whether the homogeneous coordinates of the element are within a predetermined threshold range centered on 1 based on a linear perspective interpolation technique that has been specified for rendering the primitive; interpolating the attributes of the element using a linear interpolation technique based on the homogeneous coordinates of the element being within the predetermined threshold range centered on 1; and interpolating the attributes of the element using a linear perspective interpolation technique based on the homogeneous coordinates of the element being outside the predetermined threshold range centered on 1. In one embodiment, the step of determining whether the homogeneous coordinates of the primitive are within the predetermined threshold range centered on 1 may also include: determining whether the homogeneous coordinates of each vertex of the primitive are equal to 1. In another embodiment, the attributes of the element may also be associated with the vertices of the primitive. In yet another embodiment, the primitive may be a triangle or a line.

[0008] Example embodiments provide a graphics pipeline, which may include: an input unit, a comparator, and an interpolator. The input unit may receive one or more attributes of a primitive. The comparator may compare the value of the homogeneous coordinate of the attribute of the primitive with 1 to determine whether the value of the homogeneous coordinate is within a predetermined threshold range centered on 1 based on a linear perspective interpolation technique that has been specified for rendering the primitive. The interpolator may interpolate the attribute of the primitive using a linear interpolation technique based on the value of the homogeneous coordinate being determined to be within a predetermined threshold range centered on 1, and may interpolate the attribute of the primitive using a linear perspective interpolation technique based on the value of the homogeneous coordinate being determined to be outside the predetermined threshold range centered on 1. In one embodiment, the comparator may also determine whether the value of the homogeneous coordinate of the primitive is a constant that is not equal to 1 based on the linear perspective interpolation technique that has been specified for rendering the primitive, the interpolator may also interpolate the attribute of the primitive using a linear perspective interpolation technique based on the value of the homogeneous coordinate being determined to be a constant that is not equal to 1, and interpolate the attribute of the primitive using a linear interpolation technique based on the value of the homogeneous coordinate being determined to be a constant that is equal to 1. In another embodiment, the comparator may also determine whether the coefficients of the plane equation of the attributes of the primitive are constants, and the interpolator may also interpolate the attributes of the primitive based on the coefficients of the plane equation being determined to be not constants, and may omit interpolating the attributes of the primitive based on the coefficients of the plane equation being determined to be constants.

[0009] Example embodiments provide a graphics processor, which may include a graphics pipeline and a shader unit. The graphics pipeline may include: an input unit, a comparator, and an interpolator. The input unit may receive one or more attributes of a primitive. The comparator may determine whether the value of the homogeneous coordinate of the primitive is a constant not equal to 1 based on a linear perspective interpolation technique that has been specified for rendering the primitive. The interpolator may interpolate the attribute of the primitive using a linear perspective interpolation technique based on the value of the homogeneous coordinate being determined to be a constant not equal to 1, and may interpolate the attribute of the primitive using a linear interpolation technique based on the value of the homogeneous coordinate being determined to be a constant equal to 1. The shader may receive the output of the interpolator and may render the primitive. In one embodiment, the comparator may also compare the value of the homogeneous coordinate of the attribute of the primitive with 1 to determine whether the value of the homogeneous coordinate is within a predetermined threshold range centered on 1 based on the linear perspective interpolation technique that has been specified for rendering the primitive. The interpolator may also interpolate the attribute of the primitive using the linear interpolation technique based on the value of the homogeneous coordinate being determined to be within the predetermined threshold range centered on 1, and may interpolate the attribute of the primitive using the linear perspective interpolation technique based on the value of the homogeneous coordinate being determined to be outside the predetermined threshold range centered on 1. In another embodiment, the comparator may also determine whether the coefficient of the plane equation of the attribute of the primitive is a constant. The interpolator may also interpolate the attribute of the primitive based on the coefficient of the plane equation being determined to be not a constant, and may omit interpolating the attribute of the primitive based on the coefficient of the plane equation being determined to be a constant. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the following section, aspects of the subject matter disclosed herein will be described with reference to exemplary embodiments shown in the accompanying drawings, in which:

[0011] Figure 1A Describing example objects in 3D space viewable from a human eye;

[0012] Figure 1B Describes the projection onto a 2D screen Figure 1A An example object of

[0013] Figure 2A depicting a perspective view of an example planar object tilted away from a viewer within the viewer's viewing frustum (not shown);

[0014] Figure 2B Describes the projection onto a 2D screen (not shown) Figure 2A Example:

[0015] Figure 3 depicts a block diagram of a portion of an example GPU that may include a planar W optimized interpolation pipeline according to the subject matter disclosed herein;

[0016] Figure 4depicts a block diagram of an example embodiment of an interpolation unit that may be configured to include a plane W optimization according to the subject matter disclosed herein;

[0017] Figure 5 depicts a block diagram showing an example position at the input of a crop-cull-viewport unit in which it may be effective to detect whether a homogeneous coefficient W is equal to or nearly equal to 1.0 in accordance with the subject matter disclosed herein;

[0018] Figure 6 depicts a block diagram illustrating an example location within a setup unit in which detecting whether a homogeneous coefficient is equal to or nearly equal to 1.0 may be effective in accordance with the subject matter disclosed herein;

[0019] Figure 7 A flowchart depicting a method of interpolating one or more attributes of an element associated with a primitive rendered in a graphics pipeline where a linear perspective interpolation technique has been specified, for example, in a shader program, in accordance with the subject matter disclosed herein;

[0020] Figure 8 A flow chart depicting an example embodiment of an optimization following a determination process of whether a homogeneous coefficient W is equal to or nearly equal to 1.0 that may be used in accordance with the subject matter disclosed herein;

[0021] Fig. 9 Depicts an electronic device including a graphics pipeline that can reduce the number of inversion, multiplication, or division calculations used for interpolation calculations when GPU hardware has been programmed, for example, to perform linear perspective interpolation. DETAILED DESCRIPTION

[0022] In the following detailed description, numerous specific details are set forth to provide a comprehensive understanding of the disclosure. However, those skilled in the art will appreciate that the disclosed aspects may be practiced without these specific details. In other instances, well-known methods, processes, components, and circuits are not described in detail to avoid obscuring the subject matter disclosed herein.

[0023] References throughout this specification to "one embodiment" or "an embodiment" indicate that a particular feature, structure, or characteristic described in conjunction with the embodiment may be included in at least one embodiment disclosed herein. Therefore, the phrases "in one embodiment" or "in an embodiment" or "according to an embodiment" (or other phrases with similar meanings) appearing in various locations throughout this specification may not necessarily all represent the same embodiment. In addition, in one or more embodiments, the particular features, structures, or characteristics may be combined in any suitable manner. In this regard, as used herein, the word "exemplary" means "used as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not to be construed as necessarily preferred or superior to other embodiments. In addition, in one or more embodiments, the particular features, structures, or characteristics may be combined in any suitable manner. In addition, depending on the context discussed herein, a singular term may include a corresponding plural form, and a plural term may include a corresponding singular form. Similarly, hyphenated words (e.g., "two-dimensional", "pre-determined", "pixel-specific", etc.) may occasionally be used interchangeably with corresponding non-hyphenated versions (e.g., "two dimensional", "predetermined", "pixel specific", etc.), and capitalized items (e.g., "Counter Clock", "Row Select", "PIXOUT", etc.) may be used interchangeably with corresponding non-capitalized versions (e.g., "counter clock", "row select", "pixout", etc.). Such occasional interchangeable usage should not be considered inconsistent with each other.

[0024] It should also be noted that the various drawings (including component diagrams) shown and discussed herein are for illustrative purposes only and are not drawn to scale. Similarly, various waveforms and timing diagrams are shown for illustrative purposes only. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. In addition, reference numerals are repeated in the drawings to indicate corresponding and / or similar elements, if deemed appropriate.

[0025] The terms used herein are only for the purpose of describing some example embodiments and are not intended to limit the claimed subject matter. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. It will also be understood that when the term "comprising" and its variations are used in this specification, the presence of the described features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof is not excluded.

[0026] As used herein, the terms "first", "second", etc. are used as labels for the nouns that follow them, and unless clearly defined as such, do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). In addition, the same reference numerals may be used in two or more figures to represent parts, components, blocks, circuits, units, or modules having the same or similar functions. However, such use is only for simplicity of illustration and ease of discussion; it does not imply that the structure or construction details of such components or units are the same in all embodiments, or that such commonly referenced components / modules are the only way to implement some of the multiple example embodiments disclosed herein.

[0027] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the subject matter belongs. It will also be understood that, unless expressly so defined herein, terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense.

[0028] As used herein, the term "module" means any combination of software, firmware, and / or hardware configured to provide the functionality described herein in conjunction with the module. Software may be implemented as a software package, code, and / or instruction set or instructions, and the term "hardware" as used in any embodiment described herein may include, for example, a single or in any combination of hard-wired circuits, programmable circuits, state machine circuits, and / or firmware storing instructions executed by programmable circuits. Modules may be implemented collectively or individually as circuits that form part of a larger system (such as, but not limited to, an integrated circuit (IC), a system on a chip (SoC), etc.). The various components and / or functional blocks disclosed herein may be implemented as modules, which may include software, firmware, and / or hardware that provide the functionality described herein in conjunction with the various components and / or functional blocks.

[0029] The subject matter disclosed herein provides a plane W optimization that can reduce the number of inverse, multiplication and / or addition calculations used for interpolation calculations when the GPU hardware may have been programmed to perform linear perspective interpolation. When linear perspective interpolation has been specified through an API and the calculation can be modified to use linear calculations, the conditions under which linear interpolation can be used can be detected. One method for determining whether the optimization disclosed herein can be used is to determine whether the W values ​​of the vertices of the primitives are all equal to 1.0. Another method for determining whether the optimization disclosed herein can be used is to determine whether the W plane equation coefficients or barycentric factors calculated from the vertices of the primitives are equal to 1.0. The application of the optimization disclosed herein can save area within the GPU and / or can improve the performance of the graphics pipeline. Energy can also be saved, and PPA (power, performance and area) can be further optimized.

[0030] The subject matter disclosed herein can be implemented in one of a number of locations in a graphics pipeline. In one example embodiment, the optimization can be implemented in the final interpolation stage where the majority of the interpolation calculations are actually performed.

[0031] Two algorithms, plane equation interpolation and barycentric interpolation, are used to interpolate data. The two algorithms generally involve similar calculations and produce the same results. The following discussion focuses on plane equation interpolation, however, the same principles apply to barycentric interpolation. Consider Figure 1A An example object 100 in a three-dimensional (3D) space as viewed from a human eye. Figure 1A , such a view is called a viewing frustum 101. For example, if the object 100 is tilted away from the viewer (or towards the viewer) in 3D space, the shape of the object 100 from the eye's viewpoint changes as does the image data at the object's location. Figure 1B ), the data representing the object 100 must be calculated in a way that takes into account the 3D tilt (known as perspective distortion). The data should be calculated in a perspective-corrected way.

[0032] Figure 2A 1 depicts a perspective view of a planar object 200 tilted away from a viewer within the viewer's viewing frustum (not shown). Figure 2B As depicted in , data at, for example, surface 201 of a planar object 200 may be linearly (planarly) interpolated across its surface if the object 200 is perpendicular to the viewer's viewpoint.

[0033] According to the subject matter disclosed herein, linear interpolation can be used for interpolation calculations for both linear interpolation and linear perspective interpolation. Linear interpolation will be described first, followed by a description of how linear interpolation can be modified to perform linear perspective interpolation.

[0034] Equation (1) describes the plane equation that can be used for linear interpolation. j The value of can be calculated from the three plane equation coefficients in equation (1).

[0035] Attribute j [x, y] = A j ×x+B j ×y+C j , (1)

[0036] Among them, the coefficient A j is the gradient of attribute j in the x dimension. Coefficient B j is the gradient of attribute j in the y dimension, coefficient C j is the value of attribute j at (x,y)=(0,0).

[0037] Equation (1) may be modified to ensure that if the value of coefficient C at (0,0) is not a well-formed number (such as infinity or IEEE floating point "not a number (NaN)"), or is outside the dynamic range of the interpolation hardware, then a correct result is provided. The seed position is typically chosen to be inside a primitive (such as one of a plurality of vertices). Equation (1) may be modified as shown in equation (2). For the modified equation (2), coefficient C is the value of the attribute at the seed position.

[0038] Attribute j [x, y] = A j ×(x-seed·x)+B j ×(y-seed·y)+C j (2)

[0039] Where seed.x is the x-coordinate of the seed position and seed.y is the y-coordinate of the seed position.

[0040] The coefficients are calculated from the primitive vertex positions and interpolated attribute values. For example, for a triangle (the most basic primitive rendered on most GPUs), three vertices are used. The plane equation coefficients (A j ,B j ,C j The calculation of ) (and the center of gravity equivalent) is known and will not be described in detail here.

[0041] The linear perspective interpolation algorithm can be modified to calculate the plane equation coefficients (A j ,B j ,C j) and applying corrections after the plane equations have been evaluated to modify the linear interpolation of equations (1) and (2). For example, the following process or steps may be used to modify the linear interpolation equations (1) and (2).

[0042] First, the vertex attribute values ​​may be modified by dividing them by the W coordinate at each vertex before calculating the plane equation coefficients, which is called a pre-interpolation correction calculation. As a second step, 1 / W[X,Y] (1 / W[X,Y] is planar) may be linearly interpolated, and a reciprocal calculation may be performed at each interpolation position [X,Y]. As a third step, the interpolation result at each sample point may be modified by a post-interpolation correction calculation that multiplies W at the sample point.

[0043] The inverse of W (ie, 1 / W) can be calculated at each vertex during the second step. The attribute value at the vertex interpolated with perspective correction is multiplied by 1 / W, resulting in Attribute j / W values, and from these values ​​rather than the primitive vertex attributes j Therefore, linear interpolation can actually be used to calculate the plane equation. j / W is interpolated. W may not be planar, and W is actually calculated by linearly interpolating 1 / W of a plane as described above. W can usually be calculated from the depth value (Z value) at the vertex.

[0044] Rasterization generates sample locations in an image being rendered (i.e., generated). The sample locations are inside the bounds of the primitive based on the locations of the primitive's vertices. During rasterization of a primitive, many more sample locations may be generated than the number of vertices of the primitive. In addition, the attributes corresponding to each sample location are interpolated. For example, a primitive that may be defined as a triangle with three vertices may cover 10, 50, 1000, or more sample locations (commonly referred to as pixels) generated from the primitive. For example, a primitive may include one of a triangle and a line.

[0045] The first step of modifying the linear interpolation to perform linear perspective interpolation (i.e., modifying equations (1) and (2)) described above may be optionally optimized, although the benefit may be only about 5% of the benefit provided by optimizing at the second step of modifying the linear interpolation. The difference in benefit may be based on the spread caused by the rasterization that occurs in conjunction with the second step. Therefore, the cost / benefit of optimizing the first step of modifying the linear interpolation may be limited, and the application of optimization during the first step may not affect the application of optimization during the second step. Another reason why optimization of the first step may be considered optional is that if the first step premultiplies the attributes by 1 / W before calculating the plane equation coefficients, and if W=1.0, then 1 / W=1.0. Premultiplying the attributes by 1.0 does not change the plane equation coefficients. However, the first step may be optimized, in which case the optimization may be performed once for each vertex of each primitive. Optimization of the modified second step may provide the greatest benefit. The optimization at the modified second step may be performed repeatedly for each primitive.

[0046] Detection of conditions that allow optimization and implementation of optimization according to the subject matter disclosed herein can be performed at different locations in the graphics pipeline and can be implemented in hardware, software, or a combination of hardware and software. For example, detection and implementation can be performed at a relatively early stage in the graphics pipeline (such as at the clipping, culling, and viewport (CCV) stage or unit, or at the primitive setup (SU) stage or unit). Condition detection and implementation can also be performed at the interpolation pipeline stage or unit that performs the final interpolation and corrected post-calculation. Most of any potential benefits of utilizing the optimization disclosed herein may be in the interpolation pipeline stage.

[0047] If the optimized condition is detected before the setup calculation for calculating the plane equation coefficients (or barycentric factors) (i.e., at a relatively early stage in the graphics pipeline), the W values ​​of the vertices can be tested to determine whether the W values ​​of the vertices of the primitive are exactly 1.0. Alternatively, the W values ​​of the vertices of the primitive can be determined to be within a predetermined threshold of 1.0 (such as, 1.0±0.001). If the W values ​​of all vertices of the primitive are equal to 1.0 (or within a predetermined threshold range centered on 1.0), then no linear perspective interpolation calculation is required and the optimization disclosed herein can be applied.

[0048] If an optimized condition is detected after the plane equation coefficients have been calculated (i.e., at a relatively late stage in the graphics pipeline), the plane equation coefficients (or barycentric factors) may be tested to determine whether the W value for the attribute is exactly 1.0. That is, the coefficients A and B of the plane equation are determined to be 0.0 (or within a predetermined threshold), and the coefficient C may be tested to determine whether it is exactly 1.0 (or within a predetermined threshold). In one embodiment, the predetermined thresholds for the coefficients A and B may be ±0.001, and the predetermined threshold for the coefficient C may be ±0.001.

[0049] Multiple stages in the graphics pipeline architecture can benefit from the optimizations disclosed herein. For example, the CCV unit can benefit from reduced linear perspective interpolation computational work with a corresponding reduction in power. The SU unit can benefit from reduced computational work and corresponding power reduction. The IPA unit can reduce computational work (power reduction, performance improvement).

[0050] Figure 3 Depicted is a block diagram of a portion of an example graphics processor (GPU) 300 that may include a planar W-optimized interpolation pipeline in accordance with the subject matter disclosed herein. Figure 3 The portion of the example embodiment of the GPU 300 depicted in FIG. 3 may include a processing element (PE) Quad 301 and a hardware interpolator (HWInterp) unit 310. The PE Quad 301 may include one or more PEs 302a, 302b, 302c, and 302d, one or more load store units (LSUs) 303a and 303b, and one or more WARP sequencers (WSQ) 304. The hardware interpolator (HWInterp) unit 310 may include a shader processing controller (SPC) 311, one or more raster and Z units (RASTZ) 312, one or more interpolation units (IPA) 313a to 313b, and one or more interpolation setup (ISetup) units 314. The shader processing controller 311 may include one or more pixel shader constructors (PSC) 315 and one or more WARP schedulers (WS) 316. It should be understood that the formation Figure 3 The various components of the portions of the interpolation pipeline depicted in may be modules, which may be any combination of software, firmware, and / or hardware configured to, in conjunction with the components or modules, provide the functionality described herein.

[0051] In general, the control flow of the interpolation operation may be as follows. In one embodiment, RASTZ 312 sends a pixel quad with information such as, X coordinate, Y coordinate, pixel or sample mask, primitive ID, primitive, and drawing end information to PSC 315 of SPC 311. In one example, PSC 315 constructs a pixel shader (PS) warp that may, for example, contain eight quads, and makes a request to WS 316. WS 316 may allocate a warp ID, and supply other control information for the PS warp, and pass the allocation back to PSC 315. WS 316 may also notify WSQ 304 in PE quad 301 to prepare to perform the warp. PSC 315 may pass the warp ID, X coordinate, Y coordinate, mask, and primitive information of the pixel quad to, for example, IPA 313a or IPA 313b. IPA 313a (or IPA 313b) may determine the pixel quad based on, for example, status register 403 ( Figure 4) and the interpolation mode in the attribute mask. IPA 313a (or IPA 313b) performs the interpolation.

[0052] In one embodiment, IPA 313a may send the interpolation result to a vector register file (RF) in a processing element (PE, 302 (302a, 302b, 302c, or 302d)) of PE quad 301 via a load store unit (LSU, 303 (303a or 303b)). LSU 303 notifies WSQ 304 after writing the last attribute data for the warp to the vector RF so that WSQ 304 may update the state of the warp and prepare the warp for shader execution. In one embodiment, when IPA 313a (or IPA 313b) completes interpolation of a primitive, IPA 313a (or IPA 313b) passes a primitive completion signal to PSC 315. When PSC 315 receives a primitive completion signal for a primitive from either or both of IPA 313a and 313b, PSC 315 returns the final primitive completion signal to ISetup unit 314. The ISetup unit 314 may also include a plane equation table (PET) 317 that supplies attribute plane equations and triangle seed positions to a shared block interpolator and reciprocal unit (SBR) within the IPA. The plane equations may be generated by the ISetup unit 314 and stored in the PET 317. The plane equations may be released after all interpolations associated with the primitives are completed.

[0053] Figure 4 A block diagram depicting an example embodiment of an IPA 313 that may be configured to include a planar W optimization in accordance with the subject matter disclosed herein. In one embodiment, the IPA 313 may include interfaces for a PSC 315, an ISetup unit 314, Bus 1, and Bus 2, which are interconnecting buses for control data and requests for interpolation by, for example, a shader program, respectively. In one embodiment, the IPA 313 may include one or more block interpolators 401a-401b, one or more quad pixel interpolators 402a-402b, a status register 403, a request buffer 404, a scheduler 405, a position attribute manager 406, a W buffer 407, a perspective correction multiplier (PCM) 408, a shared block and reciprocal unit (RCP front end) 409, and an output buffer 410. Other numbers of modules forming the IPA 313 are possible. It should be understood that the modules forming the IPA 313 are not limited to the modules of FIG. 1 . Figure 4 The various components of the example embodiment of the IPA 313 depicted in may be modules, which may be any combination of software, firmware, and / or hardware configured to combine the components or modules to provide the functionality described herein.

[0054] In one embodiment, request buffer 404 may store requests from Figure 3 302 in , which may include information about interpolation precision, perspective division enable flag, interpolation position, starting attribute slot number and component mask, valid channel mask, programmable pixel offset and sample index, and request the synchronization flag of each pixel of the shader distortion. Interpolation can be divided into two steps (8×8 block interpolation and pixel interpolation). For pixels within the same 8×8 block, the block result can be reused, allowing the block interpolator 401 (including block interpolators 401a and 401b) to be used for reciprocal calculations. Block interpolator 401 can receive attribute plane equations, triangle seed positions, and X coordinates and Y coordinates of the 8×8 block in which the input pixel quadrilateral is located, and can perform block interpolation. The result of block interpolation can be forwarded to four-pixel interpolator 402 (including four-pixel interpolators 402a and 402b) and used as the basis for four-pixel interpolation. Block interpolator 401 can also perform reciprocal calculations of W values ​​used in perspective correction.

[0055] In one embodiment, IPA 313 may process varying attribute interpolation at each pixel or subsample, as well as merging of pixel screen coordinates for pixel shader input. Varying attribute interpolation may be performed in two stages, the first stage may be a block-level basis interpolation at the center of an 8×8 pixel block using one or more block interpolators in block interpolator 401, and the second stage may be a pixel-level interpolation within the 8×8 pixel block using one or more quad-pixel interpolators in one or more quad-pixel interpolators 402. Once IPA 313 receives the XY screen coordinates of, for example, a 2×2 pixel quad, and there is available space in output buffer 410, IPA 313 may begin processing the pixel block.

[0056] If a primitive covers more than one 2×2 quad in an 8×8 pixel block, the IPA 313 may perform optimizations to reuse existing 8×8 interpolation results without recalculating the results, and avoid any unnecessary plane equation reads, which may reduce resource (e.g., processing power, physical hardware area, etc.) consumption. The PAM 406 may receive the pixel quad information from the PSC 315, and may package the quad positions, pixel and sample masks, and the primitive ID into a warp data structure. The PAM 406 may also request attribute plane equations and triangle seed positions from the PET 317 in the ISetup unit 314, and pass this information to the block interpolator unit 401 to perform interpolation.

[0057] The four-pixel interpolator 402 may perform four-pixel interpolation based on the attribute plane equation, the 8×8 block interpolation result, and the X, Y offsets of the pixels within the 8×8 block. In one example, the W buffer 407 may store the interpolated W value from the four-pixel interpolator 402 and the inverse of W from the block interpolator 401, and may send the interpolated W value to the RCP front end 409 for inverse calculation, and send the inverse of W to the PCM 408 for final multiplication.

[0058] The scheduler 405 can schedule interpolation requests on a per-warp basis and can also order requests from the block interpolator 401 and the quad pixel interpolator 402 for block, pixel interpolation, and inverse calculations of W. The PCM 408 can perform multiplication of the inverse of W with each interpolated attribute value at the selected interpolation location. The output buffer 410 can collect the final output of the interpolation results after perspective correction. The output buffer 410 can compensate for the latency of the interpolation pipeline and can help smooth the output traffic to the interconnect bus.

[0059] Figures 4 to 6 Depicting an example location in an example graphics pipeline disclosed herein in accordance with the subject matter disclosed herein, in which it may be effective to detect whether a homogeneous coefficient W is equal to or nearly equal to 1.0. Determining whether W is equal to or nearly equal to 1.0 may be conceptually considered to be testing individual vertices or testing vertices of individual primitives. Determining whether W is equal to or nearly equal to 1.0 may be performed, for example, by one or more comparators in hardware, in software, in firmware, or in a combination of hardware, software, and / or firmware. Furthermore, the result of determining whether W is equal to or nearly equal to 1.0 may be passed down the graphics pipeline for use at a later stage.

[0060] When testing each vertex of W equal to or nearly equal to 1.0, the valid position in the graphics pipeline may be at the input of the clipping-culling-viewport (CCV) unit and / or at the input of the ISetup unit 314. When testing each vertex of primitives, the valid position in the graphics pipeline may be at the input of the position attribute manager module 406 in the IPA unit 313 in the graphics pipeline. Optionally, the detection of conditions for applying the optimizations disclosed herein may be implemented using both testing each vertex and testing each primitive's vertices. The computational savings provided by the optimizations disclosed herein may be increased from the CCV unit to the ISetup unit 314 and again at the IPA 313.

[0061] Determining whether W is equal to or nearly equal to 1.0 on a primitive-by-primitive basis can be done in Figure 44. In addition, it may be determined whether the X gradient and the Y gradient are equal to or nearly equal to 0, while the offset C is equal to or nearly equal to 1. Determining within the IPA unit 313 whether W is equal to or nearly equal to 1.0 may allow the linear interpolation of 1 / W(x,y) at each pixel or sample location and calculating W as In addition, output attribute correction (ie, Interpolated.Attribute[x, y]×W(x, y)) can be skipped. The determination and skipping of the operation can be applied to all tile rendering passes.

[0062] Figure 5 A block diagram is depicted showing an example location at the input of a CCV unit 500 in which it may be effective to detect whether the homogeneous coefficient W is equal to or nearly equal to 1.0 in accordance with the subject matter disclosed herein. The CCV unit 500 may include a vertex pipeline module 501, a command processor module 502, a primitive processor module 503, a clipper module 504, and an output control module 505. The various module components forming the CCV unit 500 may be implemented as any combination of software, firmware, and / or hardware configured to provide the functionality described herein in conjunction with the CCV unit 500. It should be understood that the CCV unit 500 may include a plurality of vertex pipeline modules, command processor modules, primitive processor modules, primitive processor modules, clipper modules, and output control modules. Figure 5 Additional components, modules and / or functional blocks not shown.

[0063] The vertex pipeline module 501 may receive input data from a stream-out (SO) unit 506, and the command processor module 502 may receive commands from the SO unit 506. The output of the vertex pipeline module 501 may be input to the primitive processor module 503. The command processor module 502 may control the vertex pipeline module 501 and the primitive processor module 503 based on the commands received from the SO unit 506. The primitive processor module 503 may also be controlled by the clipper module 504. The output of the primitive processor module 503 may be input to the output control module 505. The output control module 505 may output the processed primitives to the ISetup unit 314 and the merging (BIN) unit 507.

[0064] The determination of whether W is equal to or nearly equal to 1.0 for each vertex may be at the input of CCV unit 500. More specifically, the determination of whether W is equal to or nearly equal to 1.0 may be at the input of vertex pipeline module 501 (as indicated at 508). The determination of whether W is equal to or nearly equal to 1.0 may be performed, for example, by one or more comparators in hardware, in software, in firmware, or in a combination of hardware, software, and / or firmware.

[0065] Determining whether W is equal to or nearly equal to 1.0 at the input of CCV unit 500 may allow skipping of operations for calculating attributes of each vertex where W is equal to or nearly equal to 1.0. In addition, operations involving normalized device coordinate (NDC) position calculations (such as Xclip×1 / W, Yclip×1 / W, and Zclip×1 / W) may be skipped. The determination and skipping of operations may apply to all processing (including merging) passes and all tile rendering passes.

[0066] Figure 6 A block diagram is depicted showing an example position within the ISetup unit 314 in which it may be effective to detect whether the homogeneous coefficient W is equal to or nearly equal to 1.0 in accordance with the subject matter disclosed herein. The ISetup unit 314 may include a CCV position input interface module 601, a CCV attribute input interface module 602, a position input and buffer module 603, a rasterization setup module 604, an attribute input and queue module 605, a plane equation (Peqn) setup module 606, a raster (rast) output interface module 607, and a plane equation table 317 ( Figure 3 ). The various module components that form the ISetup unit 314 may be implemented as any combination of software, firmware, and / or hardware that is configured to provide the functionality described herein in conjunction with the ISetup unit 314. It should be understood that the ISetup unit 314 may include Figure 6 Additional components, modules and / or functional blocks not shown.

[0067] The determination of whether W is equal to or nearly equal to 1.0 for each vertex may be located at the input of the position input and buffer module 603 (indicated at 608) and / or at the input of the attribute input and queue module 605 (indicated at 609). The determination of whether W is equal to or nearly equal to 1.0 may be performed in hardware, in software, in firmware, or in a combination of hardware, software, and / or firmware, for example, by one or more comparators. Determining whether W is equal to or nearly equal to 1.0 within the ISetup unit 314 may allow operations for calculating attributes for each vertex where W is equal to or nearly equal to 1.0 to be skipped. Specifically, the operations that may be allowed to be skipped may include pre-multiplying the vertex attribute perspective by 1 / W (i.e., yertex.Attribute[Vertex.N]×1 / w) at the attribute input and queue 605 for unclipped primitives or primitives clipped at the Peqn setup 606. A plane equation does not have to be created and stored in the plane equation table 317 for 1 / W. The determination and skipping of operations may apply to all tile rendering passes.

[0068] Figure 7Flowchart depicting a method 700 of interpolating one or more attributes of an element associated with a primitive rendered in a graphics pipeline where a linear perspective interpolation technique has been specified, for example, in a shader program, in accordance with the subject matter disclosed herein. It should be understood that a linear perspective interpolation technique may be specified for interpolating attributes of an element associated with a primitive rendered in a manner other than a shader program. The process begins at 701 and may begin with Figure 8 810 is reached in 702. At 702, it is determined whether a linear perspective interpolation technique has been specified for interpolating the attributes of the elements of the primitive. If so, the process continues to 703, otherwise the process continues to 704, in which the interpolation is performed in the manner specified for the attribute. The process continues to 707, in which the method 700 ends.

[0069] At 703, it is determined whether the primitive state W=1 is set. If so, the flow continues to 705, where one or more attributes of the element associated with the primitive may be determined using a linear interpolation technique. The flow continues to 707, where, for example, the shader program continues to execute. If at 703, the primitive state W=1 is not set, the flow continues to 706, where one or more attributes of the element associated with the primitive may be determined using a linear perspective interpolation technique. The flow continues to 707, where the shader program continues to execute.

[0070] Figure 8 Flowchart 800 depicts an example embodiment of an optimization that can be used according to the subject matter disclosed herein after a determination process of whether the homogeneous coefficient W is equal to or nearly equal to 1.0. The process starts at 801. At 802, a plane equation is received from the ISetup unit 314. A plane equation for 1 / W or for an attribute of a primitive may be received. The computational data path through the IPA 313 is shared by 1 / W interpolation and conventional attribute interpolation. At 803, it is determined whether the plane equation is for 1 / W. If so, the process continues to 804, where it is determined whether the primitive state is 1 / W == 1 (or nearly equal to 1)? If so, the process continues to 805, where the primitive state of W=1 is set. The process continues to 809, where the interpolation of 1 / W is completed.

[0071] If it is determined at 804 that the primitive state 1 / W is not equal to 1 (or not nearly equal to 1), flow continues to 806 where the primitive state 1 / W is cleared. Flow continues to 807 where 1 / W is submitted to the IPA pipeline. At 808, a reciprocal operation is performed to calculate the W value. Flow continues to 809 where the interpolation of 1 / W is completed.

[0072] If at 803, it is determined that the plane equation is not for 1 / W, then the flow continues to 810 ( Figure 7 ), in 810, one or more elements associated with the primitive being rendered are interpolated. The flow continues to 809, in 809, the interpolation operation is completed.

[0073] If W is planar and not equal to 1.0, then no premultiplication by W or postmultiplication by W is required because there is no perspective distortion. However, if premultiplication by planar 1 / W is applied in ISetup unit 314, postmultiplication is still required during interpolation. If W is planar, both premultiplication and postmultiplication can be eliminated, but both multiplications must be eliminated together, or neither multiplication can be eliminated. Only when W == 1.0 can one of the multiplications be eliminated. That is, only when W == 1.0 can either premultiplication or postmultiplication be eliminated.

[0074] In an optional embodiment, additional conditions that may be detected so that the plane optimization disclosed herein may be used include detecting whether the coefficients of the plane equation of the attribute are constants (i.e., A j =0,B j =0,C j = constant). No interpolation is required for attributes that are determined to be constant, and no plane equations need to be generated for constant attributes. j ×(x-seed.x)+B j ×(y-seed.y)+C j Convert to C j That is, C j The values ​​may be propagated as attribute values ​​through the interpolation pipeline from the plane equation table 317. In yet another alternative embodiment, if all vertices of a primitive are the same but not equal to 1.0, the plane W optimization disclosed herein may be used.

[0075] Fig. 9An electronic system 900 is depicted that includes a GPU 960, which includes a graphics pipeline that can reduce the number of inverse, multiplication, or addition calculations used for interpolation calculations when the GPU 960 has been programmed, for example, to perform linear perspective interpolation. The electronic system 900 can be used for, but is not limited to, a computing device, a personal digital assistant (PDA), a laptop computer, a mobile computer, a web tablet, a wireless phone, a cellular phone, a smart phone, a digital music player, or a wired or wireless electronic device. The electronic system 900 may include a controller 910, an input / output device 920 (such as, but not limited to, a keypad, a keyboard, a display, a touch screen display, a camera, and / or an image sensor), a memory device 930, and an interface 940 that are coupled to each other via a bus 950. The controller 910 may include, for example, at least one microprocessor, at least one digital signal processing, at least one microcontroller, etc. The memory device 930 may be configured to store command codes or user data to be used by the controller 910. The various system components of the electronic system 900 and the GPU 960 may include a graphics pipeline, which can reduce the number of inverse, multiplication, or division calculations used for interpolation calculations when the GPU 960 has been programmed to perform linear perspective interpolation. The interface 940 may be configured to include a wireless interface configured to send data to or receive data from a wireless communication network using RF signals. The wireless interface 940 may include, for example, an antenna, a wireless transceiver, etc. The electronic system 900 can also be used in communication interface protocols of communication systems, such as, but not limited to: Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), North American Digital Communications (NADC), Extended Time Division Multiple Access (E-TDMA), Wideband CDMA (WCDMA), CDMA2000, Wi-Fi, Municipal Wi-Fi (Muni Wi-Fi), Bluetooth, Digital Enhanced Cordless Telephone System (DECT), Wireless Universal Serial Bus (Wireless USB), Fast Low Latency Access using Seamless Switching Orthogonal Frequency Division Multiplexing (Flash-OFDM), IEEE 802.20, General Packet Radio Service (GPRS), iBurst, Wireless Broadband (WiBro), WiMAX, Advanced WiMAX, Universal Mobile Telecommunications Service Time Division Duplex (UMTS-TDD), High Speed ​​Packet Access (HSPA), Evolution Data Optimized (EVDO), Long Term Evolution Advanced (LTE-Advanced), Multi-channel Multipoint Distribution Service (MMDS), etc.

[0076] The operations and embodiments of the subject matter described in this specification may be implemented in digital electronic circuits, or in computer software, firmware or hardware, or in a combination of one or more of them, including the structures disclosed in this specification and their structural equivalents. The embodiments of the subject matter described in this specification may be implemented as one or more computer programs (i.e., one or more modules of computer program instructions) encoded on a computer storage medium for execution by a data processing device or for controlling the operation of the data processing device. Alternatively or in addition, the program instructions may be encoded on an artificially generated propagation signal (e.g., a machine-generated electrical, optical or electromagnetic signal), which is generated to encode information for transmission to a suitable receiver device for execution by a data processing device. The computer storage medium may be a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination thereof, or may be included in a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination thereof. In addition, although a computer storage medium is not a propagation signal, a computer storage medium may be a source or destination of computer program instructions encoded in an artificially generated propagation signal. The computer storage media may also be, or be included in, one or more separate physical components or media (eg, multiple CDs, disks, or other storage devices).

[0077] The operations described in this specification may be implemented as operations performed by a data processing apparatus on data stored on one or more computer-readable storage devices or received from other sources.

[0078] The term "data processing device" includes all kinds of devices, apparatuses and machines for processing data (including, for example, programmable processors, computers, systems on chip, or multiple or combinations of the foregoing). The device may include a dedicated logic circuit (e.g., an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit)). In addition to hardware, the device may also include code that creates an execution environment for a computer program (e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, a cross-platform runtime environment, a virtual machine, or a combination thereof). The device and the execution environment can implement a variety of different computing model infrastructures (such as web services, distributed computing, and grid computing infrastructures).

[0079] A computer program (also referred to as a program, software, software application, script, or code) may be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, object, or other unit suitable for use in a computing environment. A computer program may, but need not, correspond to a file in a file system. A program may be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, subroutines, or portions of code). A computer program may be deployed to execute on one computer or on multiple computers located at one site or distributed across multiple sites and interconnected by a communications network.

[0080] The processes and logic flows described in this specification may be performed by one or more programmable processors executing one or more computer programs to perform actions by operating on input data and generating output. The processes and logic flows may also be performed by special purpose logic circuits (e.g., FPGAs (field programmable gate arrays) or ASICs (application specific integrated circuits)), and data processing devices may also be implemented as special purpose logic circuits.

[0081] Processors suitable for executing computer programs include, for example, general-purpose microprocessors and special-purpose microprocessors, and any one or more processors of any kind of digital computer. Typically, the processor can receive instructions and data from a read-only memory or a random access memory or both. The basic elements of a computer are a processor for performing actions according to instructions and one or more memory devices for storing instructions and data. Typically, a computer will also include one or more large-capacity storage devices (e.g., disks, magneto-optical disks, or optical disks) for storing data, or operatively combined to receive data from one or more large-capacity storage devices (e.g., disks, magneto-optical disks, or optical disks) for storing data or to transmit data or both to one or more large-capacity storage devices (e.g., disks, magneto-optical disks, or optical disks) for storing data. However, a computer need not have such a device. In addition, a computer may be embedded in another device (e.g., a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver, or a portable storage device (e.g., a universal serial bus (USB) flash drive), to name a few). Devices suitable for storing computer program instructions and data include all forms of non-volatile memory, media and storage devices, including, for example, semiconductor memory devices (e.g., EPROM, EEPROM and flash memory devices), magnetic disks (e.g., internal hard disks or removable disks), magneto-optical disks, and CDROM and DVD-ROM disks. The processor and memory may be supplemented by, or incorporated in, special purpose logic circuitry.

[0082] To provide interaction with a user, embodiments of the subject matter described in this specification may be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user, and a keyboard and pointing device (e.g., a mouse or trackball) with which the user can provide input to the computer. Other kinds of devices may also be used to provide interaction with the user, for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback), and the input from the user may be received in any form (including acoustic, voice, or tactile input).

[0083] Embodiments of the subject matter described in this specification may be implemented in a computing system that includes a back-end component (e.g., such as a data server), or includes a middleware component (e.g., an application server), or includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the subject matter described in this specification), or any combination of one or more such back-end, middleware, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include local area networks ("LANs") and wide area networks ("WANs"), internetworks (e.g., the Internet), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks).

[0084] A computing system may include users and servers. Users and servers are generally remote from each other and generally interact through a communication network. The relationship of user and server arises by virtue of computer programs running on the respective computers and having a user-server relationship to each other.

[0085] Although this specification contains many specific implementation details, these details should not be interpreted as limitations on any invention or the scope of protection that can be claimed, but should be interpreted as descriptions of features specific to specific embodiments of specific inventions. Specific features described in the context of separate embodiments in this specification may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. In addition, although features may be described above as working in a specific combination and even initially claimed as such, one or more features from the claimed combination may be removed from the combination in some cases, and the claimed combination may be directed to a sub-combination or a variation of the sub-combination.

[0086] Similarly, although the operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring that the operations be performed in the particular order shown or in a continuous order, or that all of the operations shown be performed to achieve the desired result. In certain cases, multitasking and parallel processing can be advantageous. In addition, the separation of various system components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0087] Thus, particular embodiments of the subject matter have been described. Other embodiments are within the scope of the appended claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve the desired results. Furthermore, the processes depicted in the accompanying drawings do not necessarily require the particular order or sequential order shown to achieve the desired results. In particular embodiments, multitasking and parallel processing may be advantageous.

[0088] As those skilled in the art will recognize, the innovative concepts described herein are susceptible to modification and variation over a wide range of applications. Therefore, the scope of the claimed subject matter should not be limited to any specific exemplary teachings discussed above, but rather is defined by the appended claims.

Claims

1. A method for interpolating one or more attributes of an element of a primitive rendered in a graphics pipeline, the method comprising: Determining whether a homogeneous coordinate of the element is within a predetermined threshold range centered on 1 based on a linear perspective interpolation technique that has been specified for rendering the primitive; interpolating the attributes of the element using a linear interpolation technique based on the homogeneous coordinates of the element being within a predetermined threshold range centered at 1; and Based on the homogeneous coordinates of the element being outside a predetermined threshold range centered at 1, the attributes of the element are interpolated using a linear perspective interpolation technique.

2. The method according to claim 1, wherein: The attributes of an element are associated with the vertices of the primitive.

3. The method according to claim 1, wherein: The step of determining whether the homogeneous coordinates of the element are within a predetermined threshold range centered at 1 includes determining whether the homogeneous coordinates of each vertex of the primitive are equal to 1.

4. The method according to claim 1, wherein: The primitives include one of a triangle and a line.

5. The method according to claim 1, wherein: The step of determining whether the homogeneous coordinates of the element are within a predetermined threshold range centered on 1 includes determining whether the homogeneous coordinates of the element are within a predetermined threshold range centered on 1 at one of an input and an output of the graphics pipeline.

6. The method according to claim 5, wherein: The graphics pipeline includes: one of a clipping-culling-viewport unit, a setup unit, and an interpolation unit.

7. The method according to claim 1, further comprising: Determining whether a value of a homogeneous coordinate of the primitive is a constant not equal to 1 based on a linear perspective interpolation technique that has been specified for rendering the primitive; Based on the value of the homogeneous coordinate being determined to be a constant that is not equal to 1, the attribute of the primitive is interpolated using a linear perspective interpolation technique; and Based on the values ​​of the homogeneous coordinates being determined to be a constant equal to 1, the attributes of the primitive are interpolated using a linear interpolation technique.

8. The method according to claim 1, further comprising: Determine whether the coefficients of the plane equations of the primitive's attributes are constants; The properties of the primitives are interpolated based on the coefficients of the plane equation being determined to be non-constant; as well as The coefficients based on the plane equation are determined to be constants, omitting the interpolation of the primitive's attributes.

9. A graphics pipeline comprising: An input unit, receiving one or more attributes of a primitive; a comparator that compares the value of the homogeneous coordinate of the attribute of the primitive with 1 to determine whether the value of the homogeneous coordinate is within a predetermined threshold range centered on 1 based on a linear perspective interpolation technique that has been specified for rendering the primitive; as well as An interpolator that interpolates the attributes of a primitive using a linear interpolation technique based on a value of a homogeneous coordinate being determined to be within a predetermined threshold range centered on 1, and that interpolates the attributes of a primitive using a linear perspective interpolation technique based on a value of a homogeneous coordinate being determined to be outside a predetermined threshold range centered on 1.

10. The graphics pipeline of claim 9, wherein: The attributes of a primitive are associated with the primitive's vertices.

11. The graphics pipeline of claim 9, wherein: Attributes are associated with the vertices of a primitive, and The primitive includes one of a triangle and a line.

12. The graphics pipeline of claim 9, wherein: The comparator also determines whether the value of the homogeneous coordinate of the primitive is a constant not equal to 1 based on the linear perspective interpolation technique that has been specified for rendering the primitive, and Among them, the interpolator also interpolates the attributes of the primitive using linear perspective interpolation technology based on the value of the homogeneous coordinate being determined to be a constant not equal to 1, and interpolates the attributes of the primitive using linear interpolation technology based on the value of the homogeneous coordinate being determined to be a constant equal to 1.

13. The graphics pipeline of claim 9, wherein: The comparator also determines whether the coefficients of the plane equation of the primitive's attributes are constants, and The interpolator further interpolates the attributes of the primitive based on the coefficients of the plane equation being determined to be not constants, and omits interpolating the attributes of the primitive based on the coefficients of the plane equation being determined to be constants.

14. The graphics pipeline of claim 9, wherein: The graphics pipeline includes one of a clipping-culling-viewport unit, a setup unit, and an interpolation unit.

15. A graphics processor, comprising: Graphics pipeline, including: An input unit, receiving one or more attributes of a primitive; a comparator that determines whether a value of a homogeneous coordinate of the primitive is a constant that is not equal to 1 based on a linear perspective interpolation technique that has been specified for rendering the primitive; and an interpolator that interpolates the attributes of the primitive using a linear perspective interpolation technique based on the value of the homogeneous coordinate being determined to be a constant that is not equal to 1, and interpolates the attributes of the primitive using a linear interpolation technique based on the value of the homogeneous coordinate being determined to be a constant that is equal to 1; and Shaders, which receive the output of the interpolator and render the primitives.

16. The graphics processor according to claim 15, wherein: The comparator also compares the value of the homogeneous coordinate of the attribute of the primitive with 1 based on the linear perspective interpolation technique that has been specified for rendering the primitive to determine whether the value of the homogeneous coordinate is within a predetermined threshold range centered on 1, and Among them, the interpolator also uses linear interpolation technology to interpolate the attributes of the primitive based on the value of the homogeneous coordinate being determined to be within a predetermined threshold range centered on 1, and uses linear perspective interpolation technology to interpolate the attributes of the primitive based on the value of the homogeneous coordinate being determined to be outside a predetermined threshold range centered on 1.

17. The graphics processor according to claim 15, wherein: The primitives include one of a triangle and a line.

18. The graphics processor according to claim 15, wherein: The attributes of an element are associated with the vertices of the primitive.

19. The graphics processor according to claim 15, wherein: The comparator also determines whether the coefficients of the plane equation of the primitive's attributes are constants, and The interpolator further interpolates the attributes of the primitive based on the coefficients of the plane equation being determined to be not constants, and omits interpolating the attributes of the primitive based on the coefficients of the plane equation being determined to be constants.

20. The graphics processor of claim 15, wherein: The graphics pipeline includes: one of a clipping-culling-viewport unit, a setup unit, and an interpolation unit.

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