Semiconductor package

Abstract

A semiconductor package is disclosed that includes a logic die mounted on an interposer substrate and a memory stack structure disposed side-by-side with the logic die. The memory stack structure includes a buffer die mounted on the interposer substrate and a plurality of memory dies stacked on the buffer die. The buffer die has a first surface facing the interposer substrate and a second surface facing the plurality of memory dies. The number of data terminals on the second surface is greater than the number of connection terminals on the first surface.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2019-0063579, filed on May 30, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. TECHNICAL FIELD

[0002] The disclosure relates to a semiconductor package, and more particularly, to a semiconductor package in which a logic die and a memory stack structure are disposed side by side. BACKGROUND

[0003] In the semiconductor industry, there has been a demand for high capacity, thin, and small size semiconductor devices and electronic products using the semiconductor devices, and thus various packaging technologies have been proposed. A semiconductor package is provided so that an integrated circuit chip is implemented to conform to use in electronic products. The semiconductor package is generally constructed so that a semiconductor chip is mounted on a printed circuit board (PCB), and a wire or bump is used to electrically connect the semiconductor chip to the printed circuit board. As the electronic industry develops, there is an increasing demand for high performance, high speed, and compact size in electronic products. SUMMARY

[0004] Certain example embodiments disclosed provide a semiconductor package having improved electrical characteristics and increased operating speed.

[0005] According to an aspect of the disclosure, a semiconductor package is provided, the semiconductor package including a logic die disposed on an intermediate substrate, a memory stack structure disposed adjacent to the logic die, wherein the memory stack structure includes a buffer die disposed on the intermediate substrate and a plurality of memory dies stacked on the buffer die, wherein the buffer die has a first surface facing the intermediate substrate and a second surface facing the plurality of memory dies, and wherein a number of data terminals on the second surface is greater than a number of connection terminals on the first surface.

[0006] According to another aspect of the disclosure, a semiconductor package is provided, the semiconductor package including a logic die disposed on an intermediate substrate, a memory stack structure disposed adjacent to the logic die, wherein the memory stack structure includes a buffer die disposed on the intermediate substrate and a plurality of memory dies stacked on the buffer die, wherein the buffer die includes an active layer including a first active pattern disposed on a first substrate, a first device isolation layer disposed on the first substrate and configured to define the first active pattern, and a first gate electrode disposed on a channel of the first active pattern, and wherein the channel of the first active pattern is located at a position higher than an upper surface of the first device isolation layer.

[0007] According to another aspect of the disclosure, a semiconductor package is provided, the semiconductor package comprising: a logic die disposed on an intermediate substrate; a memory stack structure disposed adjacent to the logic die, wherein the memory stack structure comprises a buffer die disposed on the intermediate substrate and a memory die disposed on the buffer die, wherein a number of bumps between the buffer die and the memory die is greater than a number of bumps between the buffer die and the intermediate substrate. BRIEF DESCRIPTION OF DRAWINGS

[0008] The above and / or other aspects of the present disclosure will become apparent and more readily appreciated from the following description, taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 A plan view showing a semiconductor package according to embodiments of the disclosure is shown.

[0010] Figure 2 A cross-sectional view taken along line I-I' of Figure 1 is shown.

[0011] Figure 3 An enlarged cross-sectional view showing portions M and N of Figure 2 is shown.

[0012] Figure 4 An enlarged cross-sectional view showing portions M and N in Figure 2 is shown, showing a semiconductor package according to embodiments of the disclosure.

[0013] Figure 5 A cross-sectional view taken along line I-I' of Figure 1 is shown, showing a semiconductor package according to embodiments of the disclosure. DETAILED DESCRIPTION

[0014] Figure 1 A plan view showing a semiconductor package according to embodiments of the disclosure is shown. Figure 2 A cross-sectional view taken along line I-I' of Figure 1 is shown. Figure 3 An enlarged cross-sectional view showing portions M and N of Figure 2 is shown.

[0015] Reference is made to Figures 1 to 3A package substrate PSUB can be provided. An interposer IPS can be disposed on the package substrate PSUB. For example, the package substrate PSUB can be a printed circuit board (PCB). The interposer IPS can be a redistribution substrate. Bumps BP can be disposed on a bottom surface of the interposer IPS. The bumps BP can be interposed between the interposer IPS and the package substrate PSUB. Solder balls SB can be disposed on a bottom surface of the package substrate PSUB. According to an embodiment, wires and at least one via can be disposed on the package substrate PSUB.

[0016] A logic die SOC and a plurality of memory stack structures SS can be disposed on the interposer IPS. For example, four memory stack structures SS can be disposed around the logic die SOC. However, the disclosure is not limited thereto, but the number of memory stack structures SS can vary. The logic die SOC and each of the memory stack structures SS can be mounted side by side on the interposer IPS.

[0017] The logic die SOC can include a central processing unit CPU, a physical layer interface PHY, and a memory controller MCT. For example, the logic die SOC can be a system on chip. The logic die SOC can have a first surface SOCa facing the interposer IPS and a second surface SOCb facing away from the first surface SOCa. The logic die SOC can include a first substrate SUB1 and a first active layer ACL1 on the first substrate SUB1. The first active layer ACL1 can be adjacent to the first surface SOCa. The first substrate SUB1 can be adjacent to the second surface SOCb.

[0018] The first active layer ACL1 can include a first transistor TRT1 formed on the first substrate SUB1. Further, the first active layer ACL1 can include interconnection line layers ILL1 and ILL2 on the first transistor TRT1. This will be described below with reference to FIGS. 4A and 4B. Figure 3 The first active layer ACL1 is discussed in further detail. The interposer IPS can have the logic die SOC mounted thereon in a downward-facing state with the first active layer ACL1 facing the interposer IPS.

[0019] The first connection terminals IMa1 to IMa4 can be interposed between the logic die SOC and the interposer IPS. For example, the first connection terminals IMa1 to IMa4 can include a first terminal IMa1, a second terminal IMa2, a third terminal IMa3, and a fourth terminal IMa4. Each of the first connection terminals IMa1 to IMa4 can be a micro bump.

[0020] The logic die SOC can be flip-chip bonded to the interposer IPS through the first connection terminals IMa1 to IMa4. According to an embodiment, an underfill resin layer can be filled between the logic die SOC and the interposer IPS.

[0021] The plurality of memory stack structures SS can have substantially the same structure. The following description will exemplarily describe one of the plurality of memory stack structures SS in detail. The memory stack structure SS can include a buffer chip BC and first to fourth memory chips MC1 to MC4 sequentially stacked on the buffer chip BC.

[0022] The buffer chip BC can have a first surface BCa facing the intermediate substrate IPS and a second surface BCb facing away from the first surface BCa. For example, the second surface BCb faces a direction opposite to a direction in which the first surface BCa faces. The buffer chip BC can include a second substrate SUB2 and a second active layer ACL2 on the second substrate SUB2. The second active layer ACL2 can be adjacent to the first surface BCa. The second substrate SUB2 can be adjacent to the second surface BCb.

[0023] The second active layer ACL2 can include an integrated circuit. For example, the second active layer ACL2 can include a memory circuit, a logic circuit, or a combination thereof. The logic circuit of the second active layer ACL2 can include a latch circuit that processes a data signal input to the first to fourth memory chips MC1 to MC4 and a data signal output from the first to fourth memory chips MC1 to MC4.

[0024] The second active layer ACL2 can include a second transistor TRT2 formed on the second substrate SUB2, and can further include interconnection layers ILL1 and ILL2 on the second transistor TRT2. This will be described in detail below with reference to FIGS. 6A and 6B. Figure 3 The second active layer ACL2 is discussed in further detail. The intermediate substrate IPS can have the buffer chip BC mounted thereon in a downward-facing state in which the second active layer ACL2 faces the intermediate substrate IPS.

[0025] According to an embodiment, second connection terminals IMb1 to IMb4 can be interposed between the buffer chip BC and the intermediate substrate IPS. For example, the second connection terminals IMb1 to IMb4 can include a first terminal IMb1, a second terminal IMb2, a third terminal IMb3, and a fourth terminal IMb4. For example, each of the second connection terminals IMb1 to IMb4 can be a micro bump.

[0026] The buffer chip BC can be flip-chip bonded to the intermediate substrate IPS through the second connection terminals IMb1 to IMb4. According to an embodiment, an underfill resin layer can be filled between the buffer chip BC and the intermediate substrate IPS.

[0027] The first to fourth memory dies MC1 to MC4 can be dynamic random access memory (DRAM) chips. In certain embodiments, the first to fourth memory dies MC1 to MC4 can have substantially the same chip size. For example, the first to fourth memory dies MC1 to MC4 can have substantially the same planar shape and size.

[0028] Each of the first to fourth memory dies MC1 to MC4 can include a third substrate SUB3 and a third active layer ACL3 on the third substrate SUB3. The third active layer ACL3 can include memory transistors and a layer of connection lines on the memory transistors. A memory circuit can be constituted by the memory transistors and the layer of connection lines in the third active layer ACL3. The intermediate substrate IPS can have each of the first to fourth memory dies MC1 to MC4 mounted thereon in a state in which the third active layer ACL3 faces downward toward the intermediate substrate IPS.

[0029] The third memory die MC3 can include a first via TV1 that penetrates the third memory die MC3. The second memory die MC2 can include the first via TV1 and a second via TV2 that penetrate the second memory die MC2. The first memory die MC1 can include the first via TV1, the second via TV2, and a third via TV3 that penetrate the first memory die MC1. The fourth memory die MC4 can not include a via, but the present disclosure is not particularly limited thereto.

[0030] According to an embodiment, a first data terminal IM1 can be disposed between the fourth memory die MC4 and the first via TV1 of the third memory die MC3. The first data terminal IM1 between the third memory die MC3 and the fourth memory die MC4 can be disposed on and electrically connected to the third active layer ACL3 of the fourth memory die MC4. The first data terminal IM1 can also be disposed between the first via TV1 of the third memory die MC3 and the first via TV1 of the second memory die MC2. The first data terminal IM1 can also be disposed between the first via TV1 of the second memory die MC2 and the first via TV1 of the first memory die MC1. The first data terminal IM1 can also be disposed between the buffer die BC and the first via TV1 of the first memory die MC1.

[0031] The first data input / output path DP1 of the memory stack structure SS can include first data terminals IM1 disposed between the dies and first vias TV1 that penetrate the dies. The first data terminals IM1 and the first vias TV1 can be alternately stacked to constitute a vertical data path. The first data terminals IM1 and the first vias TV1 of the first data input / output path DP1 can be vertically stacked with each other. The third active layer ACL3 of the fourth memory die MC4 can be electrically connected to the buffer die BC through the first data input / output path DP1. Data can be exchanged between the fourth memory die MC4 and the buffer die BC through the first data input / output path DP1.

[0032] According to an embodiment, second data terminals IM2 can be disposed between the third memory die MC3 and the second vias TV2 of the second memory die MC2. The second data terminals IM2 between the second memory die MC2 and the third memory die MC3 can be disposed on and electrically connected to the third active layer ACL3 of the third memory die MC3. The second data terminals IM2 can also be disposed between the second vias TV2 of the second memory die MC2 and the second vias TV2 of the first memory die MC1. The second data terminals IM2 can also be disposed between the buffer die BC and the second vias TV2 of the first memory die MC1.

[0033] The second data input / output path DP2 of the memory stack structure SS can include second data terminals IM2 disposed between the dies and second vias TV2 that penetrate the dies. The second data terminals IM2 and the second vias TV2 can be alternately stacked to constitute a vertical data path. The second data terminals IM2 and the second vias TV2 of the second data input / output path DP2 can be vertically stacked with each other. The third active layer ACL3 of the third memory die MC3 can be electrically connected to the buffer die BC through the second data input / output path DP2. Data can be exchanged between the third memory die MC3 and the buffer die BC through the second data input / output path DP2.

[0034] According to an embodiment, third data terminals IM3 can be disposed between the second memory die MC2 and the third vias TV3 of the first memory die MC1. The third data terminals IM3 between the first memory die MC1 and the second memory die MC2 can be disposed on and electrically connected to the third active layer ACL3 of the second memory die MC2. The third data terminals IM3 can also be disposed between the buffer die BC and the third vias TV3 of the first memory die MC1.

[0035] The third data input / output path DP3 of the memory stack structure SS can include third data terminals IM3 disposed between the dies and third vias TV3 that penetrate the dies. The third data terminals IM3 and the third vias TV3 can be alternately stacked to constitute a vertical data path. The third data terminals IM3 and the third vias TV3 of the third data input / output path DP3 can be vertically stacked with each other. The third active layer ACL3 of the second memory die MC2 can be electrically connected to the buffer die BC through the third data input / output path DP3. Data can be exchanged between the second memory die MC2 and the buffer die BC through the third data input / output path DP3.

[0036] According to an embodiment, a fourth data terminal IM4 can be disposed between the first memory die MC1 and the buffer die BC. The fourth data terminal IM4 can be disposed on and electrically connected to the third active layer ACL3 of the first memory die MC1.

[0037] The fourth data input / output path DP4 of the memory stack structure SS can include fourth data terminals IM4 disposed between the dies. The third active layer ACL3 of the first memory die MC1 can be electrically connected to the buffer die BC through the fourth data input / output path DP4. Data can be exchanged between the first memory die MC1 and the buffer die BC through the fourth data input / output path DP4.

[0038] Each of the first data terminal IM1 to the fourth data terminal IM4 can be a micro bump. The first data terminal IM1 to the fourth data terminal IM4 can be disposed between the first memory die MC1 and the buffer die BC. For example, sixteen data terminals can be disposed between the buffer die BC and the first memory die MC1. The first data terminal IM1 to the third data terminal IM3 can be disposed between the first memory die MC1 and the second memory die MC2. For example, twelve data terminals can be disposed between the first memory die MC1 and the second memory die MC2. The first data terminal IM1 and the second data terminal IM2 can be disposed between the second memory die MC2 and the third memory die MC3. For example, eight data terminals can be disposed between the second memory die MC2 and the third memory die MC3. The first data terminal IM1 can be disposed between the third memory die MC3 and the fourth memory die MC4. For example, four data terminals can be disposed between the third memory die MC3 and the fourth memory die MC4. According to an embodiment, the number of data terminals of the memory stack structure SS can decrease as the distance from the buffer die BC in the vertical direction (e.g., the third direction D3) increases.

[0039] The first active layer ACL1 of the logic die SOC can include a first physical layer interface region PHY1. The second active layer ACL2 of the buffer die BC of each memory stack structure SS can include a second physical layer interface region PHY2.

[0040] A data line IOd can be disposed between the first physical layer interface region PHY1 and the second physical layer interface region PHY2. Data can be exchanged between the logic die SOC and the buffer die BC through the data line IOd.

[0041] The intermediate substrate IPS can include a plurality of conductive lines CL. The first terminal IMa1 of the first connection terminals IMa1 to IMa4 can be electrically connected to the fourth terminal IMb4 of the second connection terminals IMb1 to IMb4 through the conductive lines CL. The second terminal IMa2 of the first connection terminals IMa1 to IMa4 can be electrically connected to the third terminal IMb3 of the second connection terminals IMb1 to IMb4 through the conductive lines CL. The third terminal IMa3 of the first connection terminals IMa1 to IMa4 can be electrically connected to the second terminal IMb2 of the second connection terminals IMb1 to IMb4 through the conductive lines CL. The fourth terminal IMa4 of the first connection terminals IMa1 to IMa4 can be electrically connected to the first terminal IMb1 of the second connection terminals IMb1 to IMb4 through the conductive lines CL.

[0042] The data line IOd can be composed of the conductive lines CL connecting the first connection terminals IMa1 to IMa4 of the logic die SOC to the second connection terminals IMb1 to IMb4 of the buffer die BC.

[0043] As described above, Figure 3 An enlarged portion M of the first physical layer interface region PHY1 and an enlarged portion N of the second physical layer interface region PHY2 are shown. In Figure 3 In this regard, Figure 2 The portions M and N are shown in a reversed manner.

[0044] Referring back to Figure 3 Each of the first substrate SUB1 and the second substrate SUB2 can include a first active region PR and a second active region NR. The first active region PR can be a PMOSFET region, and the second active region NR can be an NMOSFET region. The first active region PR and the second active region NR can be defined by a second trench TR2 formed on an upper portion of each of the first substrate SUB1 and the second substrate SUB2.

[0045] A plurality of first active patterns AP1 can be disposed on the first active region PR. A plurality of second active patterns AP2 can be disposed on the second active region NR. The first active patterns AP1 and the second active patterns AP2 can vertically protrude from the first substrate SUB1 and the second substrate SUB2, respectively. The first trench TR1 can be defined between a pair of adjacent active patterns AP1 and AP2.

[0046] A device isolation layer ST can be disposed on the first substrate SUB1 and the second substrate SUB2. The device isolation layer ST can fill the first trench TR1 and the second trench TR2. For example, the device isolation layer ST can include a silicon oxide layer.

[0047] An upper portion of each first active pattern AP1 can include a first channel CH1, and an upper portion of each second active pattern AP2 can include a second channel CH2.

[0048] The first channel CH1 and the second channel CH2 can be located at a higher position than a top surface STt of the device isolation layer ST. The first channel CH1 and the second channel CH2 can vertically protrude above the device isolation layer ST. The first channel CH1 and the second channel CH2 can have a fin shape protruding from the device isolation layer ST.

[0049] A gate electrode GE can be disposed to extend across the first active patterns AP1 and the second active patterns AP2. The gate electrode GE can vertically overlap the first channel CH1 and the second channel CH2. Each gate electrode GE can be disposed on a top surface and opposite sidewalls of each of the first channel CH1 and the second channel CH2.

[0050] A gate dielectric layer GI can be disposed between the gate electrode GE and the first channel CH1 and the second channel CH2. The gate dielectric layer GI can extend along a bottom surface of the gate electrode GE. The gate dielectric layer GI can cover a top surface and opposite sidewalls of each of the first channel CH1 and the second channel CH2. A gate cap layer GP can be disposed on the gate electrode GE.

[0051] A first interlayer dielectric layer ILD1, a second interlayer dielectric layer ILD2, and a third interlayer dielectric layer ILD3 can be sequentially stacked on the gate cap layer GP. A gate contact GC can be disposed to penetrate the first interlayer dielectric layer ILD1 and the gate cap layer GP and electrically connect with the gate electrode GE. A first connection line layer ILL1 can be disposed in the second interlayer dielectric layer ILD2. A second connection line layer ILL2 can be disposed in the third interlayer dielectric layer ILD3. Each of the first connection line layer ILL1 and the second connection line layer ILL2 can include a plurality of connection lines IL and a plurality of vias VI. Although not shown, an additional connection line layer can also be disposed on the second connection line layer ILL2.

[0052] The respective channels CH1 and CH2 of the first transistor TRT1 and the second transistor TRT2 according to the disclosed embodiments can be located at a position higher than a top surface STt of the device isolation layer ST, and thus can have a three-dimensional shape. For example, each of the first transistor TRT1 and the second transistor TRT2 can be a three-dimensional transistor. For example, each of the first transistor TRT1 and the second transistor TRT2 according to the disclosed embodiments can be a fin field effect transistor (FinFET) having a fin-shaped channel.

[0053] The first transistor TRT1 of the first physical layer interface region PHY1 can have substantially the same structure as that of the second transistor TRT2 of the second physical layer interface region PHY2. For example, the first pitch PI1 can be provided between the active patterns API and AP2 of the first transistor TRT1. The second pitch PI2 can be provided between the active patterns API and AP2 of the second transistor TRT2. The first pitch PI1 and the second pitch PI2 can be substantially the same. According to an embodiment, the first pitch PI1 and the second pitch PI2 can be the same.

[0054] A logic process can be used to form the first transistor TRT1 of the first physical layer interface region PHY1. The same logic process can be used to form the second transistor TRT2 of the second physical layer interface region PHY2.

[0055] The second physical layer interface region PHY2 of the buffer die BC can operate at substantially the same speed and performance as those of the first physical layer interface region PHY1 of the logic die SOC. According to an embodiment, the second physical layer interface region PHY2 of the buffer die BC can operate at the same speed and performance as those of the first physical layer interface region PHY1 of the logic die SOC.

[0056] Referring back to Figures 1 to 3 , the logic circuit of the second active layer ACL2 of the buffer die BC can handle data signals between the second connection terminals IMb1 to IMb4 on the first surface BCa and the first data terminals IM1 to the fourth data terminals IM4 on the second surface BCb. For example, the second physical layer interface region PHY2 can handle data signals between the second connection terminals IMb1 to IMb4 on the first surface BCa and the first data terminals IM1 to the fourth data terminals IM4 on the second surface BCb.

[0057] The second transistor TRT2 of the logic circuit constituting the second physical layer interface area PHY2 can have substantially the same structure as that of the first transistor TRT1 of the logic circuit constituting the first physical layer interface area PHY1 of the logic die SOC. For example, the second transistor TRT2 can employ a transistor (e.g., a three-dimensional transistor such as a FinFET or a GAAFET) for the logic die SOC, and thus can operate at a high speed. The buffer die BC can reduce the number of data lines connected to the first memory die MC1 through the fourth memory die MC4. According to an embodiment, the buffer die BC can increase a data rate compared to a data rate of the first memory die MC1 through the fourth memory die MC4.

[0058] The number of data lines between the buffer die BC and the intermediate substrate IPS can be less than the number of data lines between the first memory die MC1 and the buffer die BC. The number (e.g., 4) of second connection terminals IMb1 through IMb4 between the buffer die BC and the intermediate substrate IPS can be less than the number (e.g., 16) of first data terminals IM1 through IM4 between the first memory die MC1 and the buffer die BC. The number of first data terminals IM1 through IM4 between the first memory die MC1 and the buffer die BC can be greater than or equal to twice the number of second connection terminals IMb1 through IMb4 between the buffer die BC and the intermediate substrate IPS. For example, the number of first data terminals IM1 through IM4 on the second surface BCb can be 2 to 4 times the number of second connection terminals IMb1 through IMb4 on the first surface BCa.

[0059] For example, the buffer die BC can be inputted with data through four first data terminals IM1 of the first data input / output path DP1. For example, four first data lines are provided in the first data input / output path DP1. The data inputted to the buffer die BC can be processed in the logic circuit of the second physical layer interface area PHY2 and then outputted to a single first terminal IMb1. For example, a single second data line is provided between the buffer die BC and the intermediate substrate IPS. The buffer die BC can reduce the number of second data lines to one fourth of the number of first data lines, but can increase a data rate of the second data line to four times compared to a data rate of the first data line.

[0060] In certain embodiments, the first to fourth data terminals IM1 to IM4 and the second connection terminals IMb1 to IMb4 can be terminals for transmitting data signals. However, the disclosure is not limited thereto. The first to fourth data terminals IM1 to IM4 and the second connection terminals IMb1 to IMb4 can include terminals for transmitting power, command signals, and access signals in addition to data signals. For example, the total number of terminals (e.g., micro bumps) between the first memory die MC1 and the buffer die BC can be 2 to 4 times the total number of terminals (e.g., micro bumps) between the buffer die BC and the intermediate substrate IPS.

[0061] Figure 4 An enlarged sectional view of portions M and N in FIG. 1 is shown, illustrating a semiconductor package according to an embodiment of the disclosure. The detailed description of the technical features repeated from the technical features discussed above with reference to FIG. 1 will be omitted, and the differences will be explained in detail. Figure 2 Figures 1 to 3 The detailed description of the technical features repeated from the technical features discussed above with reference to FIG. 1 will be omitted, and the differences will be explained in detail.

[0062] Referring to FIG. 2, the first to fourth data terminals IM1 to IM4 and the second connection terminals IMb1 to IMb4 can be disposed on the first to fourth active patterns AP1 to AP4, respectively. Figure 4 The first channels CH1 can be disposed on the first active patterns AP1. The first channels CH1 on the first active patterns AP1 can be vertically spaced apart from each other. The second channels CH2 can be disposed on the second active patterns AP2. The second channels CH2 on the second active patterns AP2 can be vertically spaced apart from each other.

[0063] The first channels CH1 and the second channels CH2 can be located at positions higher than a top surface STt of the device isolation layer ST. For example, a lowermost one of the stacked first channels CH1 can have a bottom surface higher than the top surface STt of the device isolation layer ST.

[0064] A gate electrode GE can surround each of the first channels CH1 and the second channels CH2. The gate electrode GE can be disposed on a top surface, a bottom surface, and opposite side walls of each of the first channels CH1 and the second channels CH2. A gate dielectric layer GI can be interposed between the gate electrode GE and each of the first channels CH1 and the second channels CH2. The gate dielectric layer GI can cover the top surface, the bottom surface, and the opposite side walls of each of the first channels CH1 and the second channels CH2.

[0065] ​The respective channels CH1 and CH2 of the first transistor TRT1 and the second transistor TRT2 according to the disclosed embodiments can be located at a position higher than a top surface STt of the device isolation layer ST, and thus can have a three-dimensional shape. For example, each of the first transistor TRT1 and the second transistor TRT2 can be a three-dimensional transistor. For example, each of the first transistor TRT1 and the second transistor TRT2 according to the disclosed embodiments can be a gate-all-around field effect transistor (GAAFET) in which a gate surrounds a channel.

[0066] Figure 5 A cross-sectional view taken along a line I-I' of Figure 1 a semiconductor package according to the disclosed embodiments is shown. Technical features that are repeated from the technical features discussed above with reference to Figures 1 to 3 will be omitted, and differences will be explained in detail.

[0067] Referring to Figure 1 and Figure 5 , the first memory die MC1 to the fourth memory die MC4 can be dynamic random access memory (DRAM) chips. In certain embodiments, the first memory die MC1 to the fourth memory die MC4 can have different chip sizes.

[0068] Among the first memory die MC1 to the fourth memory die MC4, the first memory die MC1 can have a largest planar area. Among the first memory die MC1 to the fourth memory die MC4, the fourth memory die MC4 can have a smallest planar area. The third memory die MC3 can have a planar area greater than the planar area of the fourth memory die MC4. The second memory die MC2 can have a planar area greater than the planar area of the third memory die MC3. The planar area of the first memory die MC1 can be greater than the planar area of the second memory die MC2.

[0069] The fourth memory die MC4 can include only the first data input / output path DP1, and thus can have a relatively small chip size. In contrast, the first memory die MC1 can include the first data input / output path DP1 to the fourth data input / output path DP4, and thus can have a relatively large chip size.

[0070] Each of the first memory die MC1 to the fourth memory die MC4 can have a first sidewall SW1 and a second sidewall SW2 opposite to each other. The first sidewalls SW1 of the first memory die MC1 to the fourth memory die MC4 can be aligned in the third direction D3.

[0071] The second sidewall SW2 of the third memory die MC3 can protrude much more in the second direction D2 than the second sidewall SW2 of the fourth memory die MC4. The second sidewall SW2 of the second memory die MC2 can protrude much more in the second direction D2 than the second sidewall SW2 of the third memory die MC3. The second sidewall SW2 of the first memory die MC1 can protrude much more in the second direction D2 than the second sidewall SW2 of the second memory die MC2. In such a case, the first memory die MC1 to the fourth memory die MC4 can be stacked in a stepped structure.

[0072] The semiconductor package according to one or more embodiments of the disclosure can use a buffer die including a transistor formed through a logic process, and thus can process data signals in time between a logic die and a memory stack structure. An increase in data rate between the logic die and the buffer die of the memory stack structure can improve electrical characteristics and operating speed of the semiconductor package.

[0073] Although some example embodiments of the disclosure have been discussed with reference to the accompanying drawings, it will be understood that various changes in form and details can be made thereto without departing from the spirit and scope of the disclosure. Accordingly, it will be understood that some example embodiments described above are merely illustrative in all aspects and are not restrictive.

Claims

1. A semiconductor package comprising: a logic die disposed on an intermediate substrate; and a memory stack structure disposed adjacent to the logic die, wherein the memory stack structure comprises: a buffer die disposed on the intermediate substrate; a plurality of memory dies stacked on the buffer die; a plurality of first data lines disposed between the buffer die and the plurality of memory dies; and a plurality of second data lines disposed between the buffer die and the intermediate substrate, wherein the buffer die has a first surface facing the intermediate substrate and a second surface facing the plurality of memory dies, wherein a number of data terminals on the second surface is greater than a number of connection terminals on the first surface, and wherein the buffer die comprises an active layer configured to cause the plurality of second data lines to have a first data rate greater than a second data rate of the plurality of first data lines. 2.The semiconductor package of claim 1, a number of the plurality of first data lines is greater than a number of the plurality of second data lines. wherein the active layer of the buffer die comprises a three-dimensional transistor having a three-dimensional structure channel.

3. The semiconductor package of claim 1, wherein, the memory stack structure further comprises a data input / output path connecting the buffer die vertically to a first memory die of the plurality of memory dies, 4. The semiconductor package of claim 1, wherein, wherein the data input / output path comprises a plurality of vias. 5.The semiconductor package of claim 1, wherein the logic die comprises a first physical layer interface region, the buffer die comprises a second physical layer interface region, the first physical layer interface region and the second physical layer interface region are connected to each other by a data line, and a transistor of the first physical layer interface region has substantially the same structure as a transistor of the second physical layer interface region. the plurality of memory dies comprises a first memory die disposed on the buffer die and a second memory die disposed on the first memory die, 6. The semiconductor package of claim 1, wherein, wherein a planar area of the first memory die is greater than a planar area of the second memory die. a number of data terminals on the second surface is 2 to 4 times a number of connection terminals on the first surface.

7. The semiconductor package of claim 1, wherein, 8.A semiconductor package comprising: a logic die disposed on an intermediate substrate; and a memory stack structure disposed adjacent to the logic die, wherein the memory stack structure comprises: a buffer die disposed on the intermediate substrate; a plurality of memory dies stacked on the buffer die; a plurality of first data lines disposed between the buffer die and the plurality of memory dies; and a plurality of second data lines disposed between the buffer die and the intermediate substrate, wherein the buffer die comprises an active layer comprising: a first active pattern disposed on a first substrate; a first device isolation layer disposed on the first substrate and configured to define the first active pattern; and a first gate electrode disposed on a channel of the first active pattern, ​ ​ wherein the trench of the first active pattern is located at a position higher than an upper surface of the first device isolation layer, and wherein the active layer of the buffer die is configured such that the plurality of second data lines have a first data rate greater than a second data rate of the plurality of first data lines.

9. The semiconductor package of claim 8, wherein, The logic die includes an active layer, the active layer of the logic die including: a second active pattern disposed on a second base; a second device isolation layer disposed on the second base and configured to define the second active pattern; and a second gate electrode disposed on a trench of the second active pattern, wherein the trench of the second active pattern is located at a position higher than an upper surface of the second device isolation layer.

10. The semiconductor package of claim 9, wherein the first active pattern includes a plurality of first active patterns arranged at a first pitch, the second active pattern includes a plurality of second active patterns arranged at a second pitch, and the first pitch and the second pitch are substantially the same.

11. The semiconductor package of claim 8, wherein, the active layer of the buffer die includes a three-dimensional transistor having a trench of a three-dimensional structure type.

12. The semiconductor package of claim 8, wherein the logic die includes a first physical layer interface region, the buffer die includes a second physical layer interface region, the first physical layer interface region and the second physical layer interface region are connected to each other by a data line, and a transistor of the first physical layer interface region has a structure substantially the same as a structure of a transistor of the second physical layer interface region.

13. The semiconductor package of claim 8, wherein a number of the plurality of first data lines is greater than a number of the plurality of second data lines.

14. A semiconductor package, the semiconductor package including: a logic die disposed on an intermediate base; and a memory stack structure disposed adjacent to the logic die, wherein the memory stack structure includes: a buffer die disposed on the intermediate base; and a memory die disposed on the buffer die, wherein a number of bumps between the buffer die and the memory die is greater than a number of bumps between the buffer die and the intermediate base, and wherein the buffer die includes an active layer, wherein the active layer of the buffer die is configured such that a second data line between the buffer die and the intermediate base has a first data rate greater than a second data rate of a first data line between the buffer die and the memory die.

15. The semiconductor package of claim 14, wherein, the memory stack structure is configured such that a number of the first data lines is greater than a number of the second data lines.

16. The semiconductor package of claim 14, wherein, the active layer of the buffer die includes a three-dimensional transistor having a trench of a three-dimensional structure type.

17. The semiconductor package of claim 14, wherein the logic die includes a first physical layer interface region, the buffer die includes a second physical layer interface region, the first physical layer interface region and the second physical layer interface region are connected to each other by a data line, and a transistor of the first physical layer interface region has a structure substantially the same as a structure of a transistor of the second physical layer interface region. The first transistor of the first physical layer interface region has substantially the same structure as a structure of a second transistor of the second physical layer interface region.

18. The semiconductor package of claim 17, wherein, Each of the first and second transistors is a fin field effect transistor or a gate-all-around field effect transistor.

19. The semiconductor package of claim 14, wherein, A number of bumps between the buffer die and the memory die is 2 to 4 times a number of bumps between the buffer die and the intermediate substrate.

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