Display device and display device manufacturing method

Abstract

A display device and a method for manufacturing the display device are provided, the display device comprising: a substrate layer; a pixel circuit disposed on the substrate layer; a pixel electrode electrically connected to the pixel circuit; an intermediate layer disposed on the pixel electrode and comprising a polymer resin layer and a conductive layer; a plurality of light-emitting diodes disposed on the conductive layer and electrically connected to the pixel electrode; and a common electrode configured to cover the plurality of light-emitting diodes and electrically connected to the plurality of light-emitting diodes. Each of the plurality of light-emitting diodes comprises a first electrode, a light-generating layer, and a second electrode sequentially stacked in a thickness direction of the substrate layer.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0062300, filed on May 28, 2019, which is hereby incorporated by reference in its entirety. Technical Field

[0002] The present disclosure relates to a display device with a simplified manufacturing process and a method for manufacturing the display device. Background Art

[0003] In the technical field of displays, a display device may include a light emitting diode. The light emitting diode may be electrically connected to an electrode, and may emit light according to a voltage applied to the electrode. The light emitting diode may be directly formed on the electrode, or a light emitting diode formed separately from the electrode may be connected to the electrode. When the light emitting diode is formed separately and connected to the electrode, a process of aligning the light emitting diode on the electrode is required. If the light emitting diode is not properly aligned on the electrode, the light emitting diode will not emit light. Summary of the invention

[0004] The present disclosure is to provide a display device with a simplified manufacturing process and a method for manufacturing the display device.

[0005] An embodiment of the inventive concept provides a display device, comprising: a base layer; a pixel circuit disposed on the base layer; a pixel electrode electrically connected to the pixel circuit; an intermediate layer disposed on the pixel electrode and comprising a polymer resin layer and a conductive layer; a plurality of light-emitting diodes disposed on the conductive layer and electrically connected to the pixel electrode; and a common electrode configured to cover the plurality of light-emitting diodes and electrically connected to the plurality of light-emitting diodes, wherein each of the plurality of light-emitting diodes comprises a first electrode, a light-generating layer, and a second electrode sequentially stacked in a thickness direction of the base layer.

[0006] In an embodiment, the pixel electrode may include copper, silver, gold, or an alloy thereof.

[0007] In an embodiment, the conductive layer may be provided as conductive particles condensed between the pixel electrode and the plurality of light emitting diodes.

[0008] In an embodiment, the conductive particles may include a tin-bismuth alloy.

[0009] In an embodiment, the conductive layer may be provided as conductive particles dispersed and provided in the intermediate layer and condensed onto the pixel electrode by heating.

[0010] In an embodiment, a conductive layer may be disposed between the pixel electrode and the first electrode, and a portion of each of the plurality of light emitting diodes may be surrounded by the polymer resin layer.

[0011] In an embodiment, the display device may further include: a cover layer covering a side wall of each of the plurality of light emitting diodes.

[0012] In an embodiment, the display device may further include: an insulating layer disposed on the intermediate layer and exposing the second electrode of each of the plurality of light emitting diodes, wherein the common electrode may be disposed on the insulating layer.

[0013] In an embodiment, the display device may further include: a reflective layer surrounding a portion of each of the plurality of light emitting diodes and disposed under the first electrode of each of the plurality of light emitting diodes.

[0014] In an embodiment, the plurality of light emitting diodes may be configured to output blue light.

[0015] In an embodiment, the display device may further include: an optical layer, arranged on a plurality of light emitting diodes and including a first wavelength conversion layer, a second wavelength conversion layer and a light transmitting layer, wherein the first wavelength conversion layer may be configured to absorb blue light and output red light, wherein the second wavelength conversion layer may be configured to absorb blue light and output green light, wherein the light transmitting layer may be configured to transmit blue light.

[0016] In an embodiment, the common electrode may be in direct contact with the second electrode, and the pixel electrode may be electrically connected to the first electrode through a conductive layer.

[0017] In an embodiment of the inventive concept, a method for manufacturing a display device includes the following steps: forming a base layer; forming a pixel circuit on the base layer; forming a pixel electrode electrically connected to the pixel circuit on the pixel circuit; forming an intermediate layer in which a polymer resin and conductive particles are mixed on the pixel electrode; a plurality of light-emitting diodes attached to a donor substrate are in contact with the intermediate layer; heating the intermediate layer to condense the conductive particles on the pixel electrode; separating the donor substrate from the intermediate layer; and forming a common electrode on effective light-emitting diodes transferred to the pixel electrode among the plurality of light-emitting diodes.

[0018] In an embodiment, the method may further include the steps of: forming an insulating layer on the effective light emitting diode; and removing a portion of the insulating layer to expose at least a portion of the effective light emitting diode, wherein the common electrode may be formed on the insulating layer.

[0019] In an embodiment, the step of heating the intermediate layer may include heating the intermediate layer at a temperature between 140 degrees and 180 degrees.

[0020] In an embodiment, the pixel electrode may be formed of copper, silver, gold, or an alloy thereof.

[0021] In an embodiment, the method may further include forming a reflective layer on each of the plurality of light emitting diodes formed on the donor substrate.

[0022] In an embodiment, the step of forming the intermediate layer may include screen-printing a material in which a polymer resin and conductive particles are mixed.

[0023] In an embodiment, the step of forming the intermediate layer may include slit coating a material in which a polymer resin and conductive particles are mixed.

[0024] In an embodiment, the base layer may include an active region and a peripheral region surrounding the active region, wherein the intermediate layer may be formed only in the region overlapping the active region on a plane.

[0025] In an embodiment, the step of heating the intermediate layer may be performed after the plurality of light emitting diodes are in contact with the intermediate layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate exemplary embodiments of the inventive concept and together with the description serve to explain the principles of the inventive concept. In the drawings:

[0027] Figure 1A is an assembled perspective view of a display device according to an embodiment of the inventive concept;

[0028] Figure 1B is an exploded perspective view of a display device according to an embodiment of the inventive concept;

[0029] Figure 2 is a plan view showing a display panel according to an embodiment of the inventive concept;

[0030] Figure 3 is an equivalent circuit diagram of a pixel according to an embodiment of the inventive concept;

[0031] Figure 4 is a cross-sectional view of a display panel according to an embodiment of the inventive concept;

[0032] Figure 5A is a cross-sectional view of a display panel according to an embodiment of the inventive concept;

[0033] Figure 5B is a cross-sectional view of a second substrate according to an embodiment of the inventive concept;

[0034] Figure 6 is a cross-sectional view of a light emitting diode according to an embodiment of the inventive concept;

[0035] Figure 7 is a cross-sectional view of a second substrate according to an embodiment of the inventive concept;

[0036] Figure 8is a cross-sectional view of a second substrate according to an embodiment of the inventive concept;

[0037] Fig. 9 is a cross-sectional view of a display panel according to another embodiment of the inventive concept;

[0038] Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D , Fig.10E , Fig.10F and Figure 10G is a view showing a portion of a manufacturing process of a display panel according to an embodiment of the inventive concept;

[0039] Fig.11 is a cross-sectional view of a portion of a structure of a display panel according to an embodiment of the inventive concept;

[0040] Fig. 12A , Fig. 12B , Fig. 12C and Fig.12D is a view showing a portion of a manufacturing process of a display panel according to an embodiment of the inventive concept;

[0041] Fig.13 is a view showing a portion of a manufacturing process of a display panel according to an embodiment of the inventive concept;

[0042] Fig.14 is a perspective view of a display device according to an embodiment of the inventive concept; and

[0043] Fig.15 is a perspective view of a display device according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0044] In this specification, when a component (or region, layer, part, etc.) is referred to as being "on", "connected to" or "coupled to" another component, this means that the component may be directly on, connected to or coupled to the other component, or there may be a third component located between the component and the other component.

[0045] The same reference numerals refer to the same elements. In addition, in the drawings, the thickness, proportion and size of components are exaggerated for effective description.

[0046] “And / or” includes all of one combination or more combinations defined by the relevant components.

[0047] It will be understood that the terms "first" and "second" are used herein to describe various components, but these components should not be limited by these terms. The above terms are only used to distinguish one component from another component. For example, without departing from the scope of the inventive concept, a first component may be referred to as a second component, and vice versa. Unless the context clearly indicates otherwise, a singular expression includes a plural expression.

[0048] In addition, terms such as "below", "lower side", "on", and "upper side" are used to describe the relationship of the configurations shown in the drawings. The terms are described as relative concepts based on the directions shown in the drawings.

[0049] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art to which the present invention belongs. Generally, terms defined in dictionaries should be considered to have the same meaning as the contextual meaning of the relevant art, and should not be understood abnormally or as having an overly formal meaning unless clearly defined herein.

[0050] In various embodiments of the inventive concept, the terms "comprises" and their variations or "includes" and their variations indicate the existence of properties, regions, fixed numbers, steps, processes, elements and / or components, but do not exclude the existence of other properties, regions, fixed numbers, steps, processes, elements and / or components.

[0051] Hereinafter, embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0052] Figure 1A is an assembled perspective view of a display device according to an embodiment of the inventive concept. Figure 1B is an exploded perspective view of a display device according to an embodiment of the inventive concept.

[0053] Reference Figure 1A and Figure 1B , the display device DD can be a device activated according to an electrical signal. The display device DD may include various embodiments. For example, in addition to large electronic devices (such as televisions, monitors, or external billboards), the display device DD can also be used for medium-sized electronic devices (such as personal computers, notebook computers, personal digital terminals, vehicle navigation units, game consoles, portable electronic devices, and cameras). In addition, these are only suggested as embodiments, and the display device DD described in this way can be used in other electronic devices without departing from the scope of the inventive concept. In the present embodiment, for the purpose of illustration and convenience, the display device DD is described as a smart phone.

[0054] The display device DD may display an image IM toward a third direction DR3 on a display surface FS that is parallel to the first direction DR1 and the second direction DR2. The image IM may include a static image and a dynamic image. Figure 1A , a viewing window and an icon are shown as examples of an image IM. The display surface FS on which the image IM is displayed may correspond to the front surface of the display device DD and may correspond to the front surface of the window WP.

[0055] In the present embodiment, the front surface (or upper surface) and the rear surface (or lower surface) of each component are defined with reference to the direction in which the image IM is displayed. The front surface and the rear surface are opposite to each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface may be parallel to the third direction DR3. In addition, the directions indicated by the first direction DR1, the second direction DR2, and the third direction RE3 may be converted into other directions as relative concepts. In the specification, "when viewed in a plane" may refer to viewing in the third direction DR3 and / or from the third direction DR3.

[0056] The display device DD may include a window WP, a display module DM, and a housing HU. In this embodiment, the window WP and the housing HU are combined to constitute the appearance of the display device DD.

[0057] The window WP may include an optically transparent insulating material. For example, the window WP may include glass or plastic. The window WP may have a multilayer structure or a single-layer structure. For example, the window WP may include a plurality of plastic films bonded together with an adhesive, or may include a glass substrate and a plastic film bonded together with an adhesive.

[0058] As described above, the front surface of the window WP defines the front surface of the display device DD. The transmission area TA may be an optically transparent area. For example, the transmission area TA may be an area having a visible light transmittance of about 90% or more.

[0059] The bezel area BZA may be an area having a lower light transmittance than the transmission area TA. The bezel area BZA defines the shape of the transmission area TA. The bezel area BZA is adjacent to the transmission area TA and may surround the transmission area TA.

[0060] The border area BZA may have a predetermined color. The border area BZA covers the peripheral area NAA of the display module DM to prevent the peripheral area NAA from being visually recognized from the outside (e.g., outside the display device DD). On the other hand, in an alternative example, the border area BZA of the window WP according to an embodiment of the inventive concept may be omitted.

[0061] The display module DM may display an image IM and sense an external input. The display module DM includes a front surface IS including an active area AA and a peripheral area NAA. The active area AA may be an area activated according to an electrical signal.

[0062] In the present embodiment, the active area AA may be an area in which the image IM is displayed and at the same time may be an area in which the external input is detected. The transmissive area TA may overlap at least the active area AA. For example, the transmissive area TA overlaps the front surface of the active area AA or at least a portion of the active area AA. Therefore, the user may view the image IM or provide an external input through the transmissive area TA. However, this is only an example, and the area in which the image IM is displayed in the active area AA and the area in which the external input is detected may be separated from each other so as not to overlap even partially, and are not limited to any single embodiment.

[0063] The peripheral area NAA may be an area covered by the frame area BZA. The peripheral area NAA is adjacent to the active area AA. The peripheral area NAA may surround the active area AA. A driving circuit, a driving wiring, etc. for driving the active area AA may be provided in the peripheral area NAA.

[0064] The display module DM includes a display panel DP, an input sensing panel ISL, and a driving circuit DC.

[0065] The display panel DP may have a configuration for basically generating an image IM. The image IM generated by the display panel DP is visually recognized from the outside through the transmissive area TA.

[0066] The input sensing panel ISL senses an external input applied from the outside. As described above, the input sensing panel ISL may sense an external input provided to the window WP.

[0067] The driving circuit DC is electrically connected to the display panel DP and the input sensing panel ISL. The driving circuit DC includes a main circuit board MB, a first circuit board CCF1, and a second circuit board CCF2.

[0068] The first circuit board CCF1 is electrically connected to the display panel DP. The first circuit board CCF1 may connect the display panel DP and the main circuit board MB. In the present embodiment, the first circuit board CCF1 is shown as a flexible circuit film. However, this is only an example. The first circuit board CCF1 may not be connected to the main circuit board MB. The first circuit board CCF1 may be a rigid substrate.

[0069] The first circuit board CCF1 may be connected to a pad (e.g., a display pad) of the display panel DP disposed in the peripheral area NAA. The first circuit board CCF1 provides the display panel DP with an electrical signal for driving the display panel DP. The electrical signal may be generated in the first circuit board CCF1 or in the main circuit board MB.

[0070] The second circuit board CCF2 is electrically connected to the input sensing panel ISL. The second circuit board CCF2 can connect the input sensing panel ISL and the main circuit board MB. In the present embodiment, the second circuit board CCF2 is shown as a flexible circuit film. However, this is only an example. The second circuit board CCF2 may not be connected to the main circuit board MB. The second circuit board CCF2 may be a rigid substrate.

[0071] The second circuit board CCF2 may be connected to a pad (sensing pad) of the input sensing panel ISL disposed in the peripheral area NAA. The second circuit board CCF2 provides the input sensing panel ISL with an electrical signal for driving the input sensing panel ISL. The electrical signal may be generated in the second circuit board CCF2 or in the main circuit board MB.

[0072] The main circuit board MB may include various driving circuits for driving the display module DM, a connector for power supply, etc. Each of the first circuit board CCF1 and the second circuit board CCF2 may be connected to the main circuit board MB. According to the inventive concept, the display module DM can be easily controlled by one main circuit board MB. However, this is only an example. In the display module DM according to an embodiment of the inventive concept, the display panel DP and the input sensing panel ISL may be connected to different main circuit boards, and the first circuit board CCF1 or the second circuit board CCF2 may not be connected to the main circuit board MB. However, the inventive concept is not limited to any specific embodiment.

[0073] The housing HU is combined with the window WP. The housing HU is combined with the window WP to provide a predetermined inner space. The display module DM may be accommodated in the inner space.

[0074] The housing HU may include a material having relatively high rigidity. For example, the housing HU may include a plurality of frames and / or plates including glass, plastic, or metal, or a combination thereof. The housing HU may stably protect the structure of the display device DD accommodated in the internal space from external impact.

[0075] Figure 2 is a plan view illustrating a display panel according to an embodiment of the inventive concept. Figure 3 is an equivalent circuit diagram of a pixel according to an embodiment of the inventive concept.

[0076] Reference Figure 2 and Figure 3 , the display panel DP includes a plurality of pixels PX, a plurality of signal wirings SL, DL, PWL1, PWL2, and ECL, and a plurality of display pads PDD.

[0077] The active area AA of the display panel DP is an area in which the image IM is displayed and the peripheral area NAA may be an area in which a driving circuit and a driving wiring are disposed. Figure 2 , an active area AA and a peripheral area NAA of the display panel DP are indicated. A plurality of pixels PX may be disposed in the active area AA.

[0078] A plurality of signal wirings SL, DL, PWL1, PWL2, and ECL are connected to the pixel PX to transmit an electrical signal to the pixel PX. Among the signal wirings included in the display panel DP, a scan wiring SL, a data wiring DL, power wirings PWL1 and PWL2, and a light emission control wiring ECL are schematically shown. However, this is only an example, and the signal wirings SL, DL, PWL1, PWL2, and ECL may also include an initialization voltage wiring, and are not limited to any specific embodiment.

[0079] exist Figure 3 , as an example, an equivalent circuit of one pixel PX among a plurality of pixels PX (hereinafter, referred to as a pixel) is schematically shown.

[0080] Reference Figure 3 , the pixel PX may be electrically connected to a plurality of signal wirings SL, DL, PWL1, PWL2, and ECL. Figure 3 , among the signal wirings SL, DL, PWL1, PWL2, and ECL, scan wirings SLi and SLi-1, data wiring DL, first power wiring PWL1, second power wiring PWL2, initialization power wiring VIL, and i-th light emission control wiring ECLi are shown by way of example. However, the pixel PX according to an embodiment of the inventive concept may also be connected to various signal wirings, and some of the shown signal wirings may be omitted.

[0081] The pixel PX may include a light emitting diode LD and a pixel circuit CC. The pixel circuit CC may include a plurality of transistors T1 to T7 and a capacitor CP. The pixel circuit CC may control the amount of current flowing in the light emitting diode LD in correspondence with a data signal.

[0082] The light emitting diode LD may emit light of predetermined brightness corresponding to the amount of current supplied from the pixel circuit CC. To this end, the level of the first power source ELVDD may be set higher than the level of the second power source ELVSS.

[0083] The light emitting diode LD may be a light emitting diode having a size between several nanometers and several hundred micrometers. However, the size of the light emitting diode LD is only an example, and the size of the light emitting diode LD is not limited to the above numerical range. Figure 3 In FIG. 1 , one light emitting diode LD connected between the pixel circuit CC and the second power wiring PWL2 is shown by way of example. However, a plurality of light emitting diodes LD may be provided. The plurality of light emitting diodes LD may be connected in parallel to each other.

[0084] Each of the plurality of transistors T1 to T7 may include an input electrode (or source electrode), an output electrode (or drain electrode), and a control electrode (or gate electrode). In the specification, for convenience, an input electrode or an output electrode may be referred to as a first electrode and the other may be referred to as a second electrode.

[0085] The first electrode of the first transistor T1 may be connected to the first power wiring PWL1 through the fifth transistor T5. The first power wiring PWL1 may be a wiring supplied with the first power ELVDD. The second electrode of the first transistor T1 is connected to the anode electrode of the light emitting diode LD through the sixth transistor T6. In the specification, the first transistor T1 may be referred to as a driving transistor.

[0086] The first transistor T1 may control the amount of current flowing in the light emitting diode LD corresponding to a voltage applied to a control electrode of the first transistor T1 .

[0087] The second transistor T2 is connected between the data wiring DL and the first electrode of the first transistor T1. Then, the control electrode of the second transistor T2 is connected to the i-th scan wiring SLi. When the i-th scan signal is supplied to the i-th scan wiring SLi, the second transistor T2 is turned on to electrically connect the data wiring DL and the first electrode of the first transistor T1.

[0088] The third transistor T3 is connected between the second electrode of the first transistor T1 and the control electrode of the first transistor T1. The control electrode of the third transistor T3 is connected to the i-th scan wiring SLi. When the i-th scan signal is supplied to the i-th scan wiring SLi, the third transistor T3 is turned on to electrically connect the second electrode of the first transistor T1 and the control electrode of the first transistor T1. Therefore, when the third transistor T3 is turned on, the first transistor T1 is connected in a diode form.

[0089] The fourth transistor T4 is connected between the node ND and the initialization power wiring VIL. The control electrode of the fourth transistor T4 is connected to the i-1th scan wiring SLi-1. The node ND may be a node to which the control electrode of the first transistor T1 and the fourth transistor T4 are connected. When the i-1th scan signal is supplied to the i-1th scan wiring SLi-1, the fourth transistor T4 is turned on to provide the initialization voltage Vint to the node ND.

[0090] The fifth transistor T5 is connected between the first power wiring PWL1 and the first electrode of the first transistor T1. The sixth transistor T6 is connected between the second electrode of the first transistor T1 and the anode electrode of the light emitting diode LD. The control electrode of the fifth transistor T5 and the control electrode of the sixth transistor T6 are connected to the i-th light emission control wiring ECLi.

[0091] The seventh transistor T7 is connected between the initialization power wiring VIL and the anode electrode of the light emitting diode LD. Then, the control electrode of the seventh transistor T7 is connected to the i-th scanning wiring SLi. When the i-th scanning signal is supplied to the i-th scanning wiring SLi, the seventh transistor T7 is turned on to provide the initialization voltage Vint to the anode electrode of the light emitting diode LD.

[0092] The seventh transistor T7 can improve the black display capability of the pixel PX. Specifically, when the seventh transistor T7 is turned on, the parasitic capacitor (not shown) of the light emitting diode LD is discharged. Then, when black brightness is achieved, the light emitting diode LD does not emit light due to the leakage current from the first transistor T1, and thus, the black display capability can be improved.

[0093] In addition, despite the Figure 3 The control electrode of the seventh transistor T7 is shown as being connected to the i-th scan wiring SLi, but the inventive concept is not limited thereto. In another embodiment of the inventive concept, the control electrode of the seventh transistor T7 may be connected to the i-1th scan wiring SLi-1 or the i+1th scan wiring (not shown).

[0094] exist Figure 3 In the embodiment, PMOS is shown as a reference, but the inventive concept is not limited thereto. In another embodiment of the inventive concept, the pixel circuit CC may be composed of NMOS. In another embodiment of the inventive concept, the pixel circuit CC may be constructed by a combination of NMOS and PMOS.

[0095] The capacitor CP is provided between the first power wiring PWL1 and the node ND. The capacitor CP stores a voltage corresponding to the data signal. When the fifth transistor T5 and the sixth transistor T6 are turned on according to the voltage stored in the capacitor CP, the amount of current flowing through the first transistor T1 may be determined.

[0096] The light emitting diode LD may be electrically connected to the sixth transistor T6 and the second power wiring PWL2. The light emitting diode LD may receive the second power ELVSS via the second power wiring PWL2. The light emitting diode LD may include a light emitting layer.

[0097] The light emitting diode LD may emit light at a voltage corresponding to a difference between a signal transmitted through the sixth transistor T6 and a second power source ELVSS received through the second power source wiring PWL2 .

[0098] The equivalent circuit of the pixel PX in the inventive concept is not limited to Figure 3 In another embodiment of the inventive concept, the pixel PX may be implemented in various forms that cause the light emitting diode LD to emit light.

[0099] Refer again Figure 2 , the power pattern VDD is disposed in the peripheral area NAA. In the present embodiment, the power pattern VDD is connected to the first power wiring PWL1. The display panel DP includes the power pattern VDD so as to supply the same first power signal to the plurality of pixels PX.

[0100] The display pad PDD may include a first pad D1 and a second pad D2. A plurality of first pads D1 may be connected to a data wiring DL. The second pad D2 may be connected to a power pattern VDD and electrically connected to a first power wiring PWL1. The display panel DP may provide an externally provided electrical signal to the pixel PX through the display pad PDD. Meanwhile, the display pad PDD may further include a pad for receiving an electrical signal in addition to the first pad D1 and the second pad D2, and is not limited to any embodiment.

[0101] Figure 4 is a cross-sectional view of a display panel according to an embodiment of the inventive concept.

[0102] Reference Figure 4 , the display panel DP may include a first substrate 100, a second substrate 200, a panel intermediate layer FM, and a sealant SLM. The first substrate 100 may be a wavelength conversion substrate, and the second substrate 200 may be a display substrate. For example, the first substrate 100 may include a wavelength conversion material or a material that blocks a specific wavelength band. The second substrate 200 may be a substrate that provides light. The details of the first substrate 100 and the second substrate 200 will be described later.

[0103] The first substrate 100 and the second substrate 200 may be combined by a sealant SLM. The sealant SLM may be disposed to overlap the peripheral area NAA. The sealant SLM may include an organic bonding member, an inorganic bonding member, or glass frit. In an embodiment of the inventive concept, the sealant SLM may be omitted.

[0104] The panel intermediate layer FM may be disposed between the first substrate 100 and the second substrate 200. The panel intermediate layer FM may be a filler. The panel intermediate layer FM may include a resin and may include, for example, a silicone polymer, an epoxy resin, or an acrylic resin. In an embodiment of the invention, the panel intermediate layer FM may be omitted.

[0105] Figure 5A is a cross-sectional view of a display panel according to an embodiment of the inventive concept. Figure 5B is a cross-sectional view of a second substrate according to an embodiment of the inventive concept.

[0106] Reference Figure 5A , a first pixel area PXA1, a second pixel area PXA2, a third pixel area PXA3, and a light blocking area NFXA may be defined on the display panel DP.

[0107] The first pixel area PXA1 provides a first color light, the second pixel area PXA2 provides a second color light, and the third pixel area PXA3 provides a third color light. The first color light, the second color light, and the third color light may be lights of different colors. For example, one color light of the first to third color lights may be red light, another color light may be green light, and another color light may be blue light.

[0108] The light shielding area NFXA may be an area defined as being adjacent to the first pixel area PXA1, the second pixel area PXA2, and the third pixel area PXA3. The light shielding area NFXA may set a boundary of the first pixel area PXA1, the second pixel area PXA2, and the third pixel area PXA3. The light shielding area NFXA may prevent color mixing between the first pixel area PXA1, the second pixel area PXA2, and the third pixel area PXA3. In addition, the light shielding area NFXA may block light so that the light is not provided to the user.

[0109] The first substrate 100 may include a base layer BS1 , first, second, and third color filter layers CF1 , CF2 , and CF3 , a light blocking layer BM, optical layers WCL1 , WCL2 , and TL, and first and second protection layers PL1 and PL2 .

[0110] The base layer BS1 may be a silicon substrate, a plastic substrate, a glass substrate, an insulating film, or a stacked structure including a plurality of insulating layers.

[0111] The light shielding layer BM may be disposed on one surface of the base layer BS1. The light shielding layer BM may overlap the light shielding region NFXA on a plane. The light shielding layer BM may not overlap the first pixel region PXA1, the second pixel region PXA2, and the third pixel region PXA3. That is, a plurality of opening portions may be defined in the light shielding layer BM, and the plurality of opening portions may overlap the first pixel region PXA1, the second pixel region PXA2, and the third pixel region PXA3 on a plane.

[0112] The first color filter layer CF1 may be disposed on one surface of the base layer BS1. For example, the first color filter layer CF1 may be disposed under the base layer BS1. The first color filter layer CF1 may overlap the first pixel area PXA1 on a plane.

[0113] The second color filter layer CF2 may be disposed on one surface of the base layer BS1. For example, the second color filter layer CF2 may be disposed under the base layer BS1. The second color filter layer CF2 may overlap the second pixel area PXA2 on a plane.

[0114] The third color filter layer CF3 may be disposed on one surface of the base layer BS1. For example, the third color filter layer CF3 may be disposed under the base layer BS1. The third color filter layer CF3 may overlap the third pixel area PXA3 on a plane.

[0115] The first color filter layer CF1 may be a red color filter layer, the second color filter layer CF2 may be a green color filter layer, and the third color filter layer CF3 may be a blue color filter layer.

[0116] The arrangement relationship of the first color filter layer CF1, the second color filter layer CF2, the third color filter layer CF3 and the light shielding layer BM is not limited to Figure 5A . For example, in an embodiment of the inventive concept, at least one of the first color filter layer CF1, the second color filter layer CF2, the third color filter layer CF3, and the light shielding layer BM may be omitted. In addition, in an embodiment of the inventive concept, the third color filter layer CF3 may be disposed between the light shielding layer BM and one surface of the base layer BS1. In this case, the third color filter layer CF3 may overlap the light shielding area NFXA and the third pixel area PXA3, and may not overlap the first pixel area PXA1 and the second pixel area PXA2.

[0117] The first protection layer PL1 may cover the first, second and third color filter layers CF1, CF2 and CF3 and the light shielding layer BM. The first protection layer PL1 may include one of silicon oxide, silicon nitride and silicon oxynitride. In another embodiment of the inventive concept, the first protection layer PL1 may be omitted.

[0118] The optical layers WCL1, WCL2, and TL may be disposed under the first protective layer PL1. The optical layers WCL1, WCL2, and TL may include a first wavelength conversion layer WCL1, a second wavelength conversion layer WCL2, and a light-transmitting layer TL.

[0119] The first wavelength conversion layer WCL1 is disposed in the first pixel area PXA1, the second wavelength conversion layer WCL2 is disposed in the second pixel area PXA2, and the light-transmitting layer TL is disposed in the third pixel area PXA3. The first wavelength conversion layer WCL1 may be disposed under the first color filter layer CF1, the second wavelength conversion layer WCL2 may be disposed under the second color filter layer CF2, and the light-transmitting layer TL may be disposed under the third color filter layer CF3.

[0120] The first wavelength conversion layer WCL1 may include a first matrix resin BR1, first scattering particles SC1, and a first light emitting body EP1, the second wavelength conversion layer WCL2 may include a second matrix resin BR2, second scattering particles SC2, and a second light emitting body EP2, and the light transmitting layer TL may include a third matrix resin BR3 and third scattering particles SC3.

[0121] The first matrix resin BR1, the second matrix resin BR2, and the third matrix resin BR3 are media in which the light-emitting body or scattering particles are dispersed, and may be composed of various resin compositions generally referred to as adhesives. However, the inventive concept is not limited thereto, and in this specification, the medium capable of dispersing the light-emitting body or scattering particles may be referred to as a matrix resin regardless of its name, other functions attached, constituent materials, etc. The matrix resin may be a polymer resin. For example, the matrix resin may be an acrylic resin, a polyurethane resin, a silicone resin, an epoxy resin, etc. The matrix resin may be a transparent resin.

[0122] The first scattering particles SC1, the second scattering particles SC2 and the third scattering particles SC3 may be TiO 2 Or silicon-based nanoparticles. The first scattering particles SC1, the second scattering particles SC2, and the third scattering particles SC3 may scatter light. Since the light-transmitting layer TL does not include a light-emitting body, the number of the third scattering particles SC3 included in the light-transmitting layer TL may be equal to or greater than the number of each of the first scattering particles SC1 included in the first wavelength conversion layer WCL1 and the second scattering particles SC2 included in the second wavelength conversion layer WCL2. In another embodiment of the inventive concept, the first scattering particles SC1 and the second scattering particles SC2 may be omitted.

[0123] Each of the first light emitting body EP1 and the second light emitting body EP2 may be a particle that converts the wavelength of light. For example, each of the first light emitting body EP1 and the second light emitting body EP2 may be a quantum dot, a quantum rod, or a phosphor.

[0124] Quantum dots are materials with a crystal structure of several nanometers in size and are composed of hundreds to thousands of atoms, and show a quantum confinement effect in which the energy band gap is increased due to the small size. When light of a wavelength having higher energy than the band gap is incident on the quantum dot, the quantum dot absorbs the light and becomes an excited state and drops to the ground state while emitting light of a specific wavelength. The emitted wavelength of light has a value corresponding to the band gap. When the size and composition of the quantum dot are adjusted, the quantum dot can adjust the light emission characteristics of the quantum confinement effect.

[0125] The quantum dots may have a full width at half maximum (FWHM) of an emission wavelength spectrum of about 45 nm or less (preferably about 40 nm or less, more preferably about 30 nm or less), and within this range, color purity and color reproducibility may be improved. In addition, since the light emitted by the quantum dots is emitted in all directions, a wide viewing angle may be improved.

[0126] In addition, the shape of the quantum dots is not particularly limited as long as it is a form commonly used in the art, and more specifically, it can be in the form of spherical, pyramidal, multi-arm or cubic nanoparticles, nanotubes, nanowires, nanofibers, nanoplate-like particles, etc.

[0127] Quantum dots can control the color of emitted light according to the particle size, so quantum dots can have various luminescent colors such as blue, red, and green. According to an embodiment of the inventive concept, when the first light-emitting body EP1 and the second light-emitting body EP2 are quantum dots, the particle size of the first light-emitting body EP1 and the particle size of the second light-emitting body EP2 can be different from each other. For example, the particle size of the first light-emitting body EP1 can be larger than the particle size of the second light-emitting body EP2. In this case, the first light-emitting body EP1 can emit light with a longer wavelength than the second light-emitting body EP2.

[0128] The first wavelength conversion layer WCL1 may convert blue light into red light and provide it to the first color filter layer CF1, the second wavelength conversion layer WCL2 may convert blue light into green light and provide it to the second color filter layer CF2, and the light transmitting layer TL may scatter blue light and provide it to the third color filter layer CF3.

[0129] The first color filter layer CF1 may transmit light in a wavelength range of red light and absorb other light. The second color filter layer CF2 may transmit light in a wavelength range of green light and absorb other light. The third color filter layer CF3 may transmit light in a wavelength range of blue light and absorb other light.

[0130] The second protection layer PL2 may cover the first wavelength conversion layer WCL1, the second wavelength conversion layer WCL2, and the light-transmitting layer TL. The second protection layer PL2 may include one of silicon oxide, silicon nitride, and silicon oxynitride.

[0131] Will refer to Figure 5A and Figure 5B The second substrate 200 is described.

[0132] The base layer BS2 of the second substrate 200 may be a silicon substrate, a plastic substrate, a glass substrate, an insulating film, or a stacked structure including a plurality of insulating layers.

[0133] The buffer layer BFL may be disposed on the base layer BS2. The buffer layer BFL may include an inorganic material. The buffer layer BFL may provide a lower surface energy than the base layer BS2 so that the pixel PX is stably formed on the base layer BS2.

[0134] The transistors TR1, TR2, and TR3 may be disposed on the buffer layer BFL. Figure 5A Each of the transistors TR1, TR2 and TR3 shown in FIG. Figure 3 The sixth transistor T6 (see Figure 3 ) corresponds. Figure 5B The transistor TR shown in FIG. Figure 5A Each of the transistors TR1, TR2, and TR3 shown in corresponds to . Hereinafter, as an example, the transistor TR will be described.

[0135] The transistor TR may include a semiconductor layer SP, a control electrode CNE, a first electrode IE, and a second electrode OE.

[0136] The semiconductor layer SP may be disposed on the buffer layer BFL. The semiconductor layer SP may include polycrystalline silicon or amorphous silicon. In addition, the semiconductor layer SP may include a metal oxide semiconductor. The semiconductor layer SP may include a channel region serving as a channel through which electrons or holes may travel, and a first ion doping region and a second ion doping region disposed between the channel regions.

[0137] The first insulating layer L1 is disposed on the buffer layer BFL and may cover the semiconductor layer SP. The first insulating layer L1 may include an inorganic material. The inorganic material may include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide.

[0138] The control electrode CNE may be disposed on the first insulating layer L1. The control electrode CNE may be used as a reference Figure 3 The second insulating layer L2 is disposed on the first insulating layer L1 and may cover the control electrode CNE. The second insulating layer L2 may include an inorganic material.

[0139] The upper electrode UE may be disposed on the second insulating layer L2. The upper electrode UE may be a reference Figure 3 The other electrode of capacitor CP is described.

[0140] The third insulating layer L3 covers the upper electrode UE and may be disposed on the second insulating layer L2. The first electrode IE and the second electrode OE of the transistor TR may be disposed on the third insulating layer L3. The first electrode IE and the second electrode OE of the transistor TR may be electrically connected to the semiconductor layer SP through a through hole penetrating the first insulating layer L1, the second insulating layer L2, and the third insulating layer L3.

[0141] The fourth insulating layer L4 is disposed on the third insulating layer L3 and may cover the first electrode IE and the second electrode OE of the transistor TR. The fourth insulating layer L4 may be composed of a single layer or a plurality of layers. For example, a single layer may include an organic layer. A plurality of layers may be provided by stacking an organic layer and an inorganic layer. The fourth insulating layer L4 may be a planarization layer providing a flat surface on its upper portion.

[0142] The pixel electrode PE may be disposed on the fourth insulating layer L4. Figure 5A , a first pixel electrode PE1 electrically connected to the first transistor TR1, a second pixel electrode PE2 electrically connected to the second transistor TR2, and a third pixel electrode PE3 electrically connected to the third transistor TR3 are shown. Figure 5B The transistor TR shown in FIG. Figure 5A Each of the transistors TR1, TR2, and TR3 shown in corresponds to . Hereinafter, as an example, the pixel electrode PE will be described.

[0143] The pixel electrode PE may be electrically connected to the second electrode OE of the transistor TR. In an embodiment of the inventive concept, the pixel electrode PE may include copper, silver, gold, or an alloy thereof. In this case, the conductive particles may be condensed on the pixel electrode PE. The conductive particles may be particles mixed in the intermediate layer PL.

[0144] The intermediate layer PL may be disposed on the pixel electrode PE. The intermediate layer PL may include a polymer resin layer EP and conductive particles. The conductive particles may be condensed on the pixel electrode PE to form a conductive layer EC.

[0145] A plurality of light emitting diodes LD may be disposed on the conductive layer EC. The plurality of light emitting diodes LD may be electrically connected to the pixel electrode PE. Figure 5Bexemplarily shows that three light emitting diodes LD are arranged on one pixel electrode PE, but the inventive concept is not limited thereto. For example, in another embodiment of the inventive concept, two or more light emitting diodes LD may be arranged on one pixel electrode PE. According to an embodiment of the inventive concept, a plurality of light emitting diodes LD are arranged on one pixel electrode PE. Therefore, even if one of the plurality of light emitting diodes LD does not emit light, another light emitting diode LD may emit light. As a result, the possibility of occurrence of defective pixels that do not provide light can be reduced.

[0146] In addition, Figure 5A and Figure 5B In the embodiment of the present invention, a plurality of light emitting diodes LD are shown to be arranged on the conductive layer EC. However, the inventive concept is not limited thereto. In an embodiment of the inventive concept, a portion of each of the plurality of light emitting diodes LD may be surrounded by the conductive layer EC. For example, at least a portion of each of the plurality of light emitting diodes LD in the thickness direction may be recessed in the conductive layer EC.

[0147] In addition, in an embodiment of the inventive concept, the conductive layer EC and the polymer resin layer EP may be distinguished by the concentration of the conductive particles. For example, the concentration of the conductive particles included in the conductive layer EC may be higher than the concentration of the conductive particles included in the polymer resin layer EP. Therefore, in an embodiment of the inventive concept, as shown in the drawings, the boundary between the conductive layer EC and the polymer resin layer EP may not be clearly distinguished.

[0148] Refer again Figure 5A , the first light emitting diode LD1 may be disposed on the first pixel electrode PE1, the second light emitting diode LD2 may be disposed on the second pixel electrode PE2, and the third light emitting diode LD3 may be disposed on the third pixel electrode PE3. The first light emitting diode LD1, the second light emitting diode LD2, and the third light emitting diode LD3 may output blue light. In an embodiment of the inventive concept, when the first light emitting diode LD1, the second light emitting diode LD2, and the third light emitting diode LD3 output blue light, the third color filter layer CF3 may be omitted.

[0149] exist Figure 5B The light emitting diode LD shown in FIG. Figure 5A The first light emitting diode LD1, the second light emitting diode LD2, and the third light emitting diode LD3 shown in FIG.

[0150] Each of the plurality of light emitting diodes LD may include a first electrode E1, a light generating layer LEL, and a second electrode E2. In an embodiment of the inventive concept, the first electrode E1, the light generating layer LEL, and the second electrode E2 may be stacked in a thickness direction of the base layer BS2. The thickness direction of the base layer BS2 may be a third direction DR3. That is, each of the plurality of light emitting diodes LD may be a vertical light emitting diode.

[0151] In the case of a vertical light emitting diode, the process of removing a portion of the stacked structure can be omitted. Therefore, the damage caused by the additional etching process can be minimized. In addition, the current of the vertical light emitting diode can be vertically injected. Therefore, the current concentration phenomenon, electrostatic discharge phenomenon, etc. that cause current leakage can be prevented. In addition, the first electrode E1 of the light emitting diode LD can be set as a reflective electrode, and among the generated light, the light directed to the first electrode E1 of the light emitting diode LD can be reflected and then emitted upward again. Therefore, the luminous efficiency of the vertical light emitting diode can be improved.

[0152] The cap layer ILS may be disposed on the sidewall of each of the light emitting diodes LD. The cap layer ILS may include an insulating material. For example, the cap layer ILS may include any one of silicon oxide, silicon nitride, and silicon oxynitride. The cap layer ILS protects each of the light emitting diodes LD and may prevent current from leaking from the sidewall of the light emitting diode LD.

[0153] The first electrode E1 of the light emitting diode LD may be electrically connected to the pixel electrode PE through the conductive layer EC. A portion of each of the light emitting diodes LD may be surrounded by the polymer resin layer EP.

[0154] The insulating layer ILL may be disposed on the intermediate layer PL. The insulating layer ILL may expose the second electrode E2 of each of the light emitting diodes LD. The insulating layer ILL may be a photoresist layer.

[0155] The common electrode CE may be disposed on the insulating layer ILL. The common electrode CE may be electrically connected to the light emitting diode LD. For example, the common electrode CE may directly contact the second electrode E2 of each of the light emitting diodes LD. The common electrode CE may be a transparent electrode. For example, the common electrode CE may include IZO or ITO.

[0156] In addition, as an example, refer to Figure 5B The structure in which the first insulating layer L1, the second insulating layer L2, the third insulating layer L3, and the fourth insulating layer L4 are arranged and the structure in which the pixel electrode PE is directly connected to the second electrode OE of the transistor TR is described, but they are not limited thereto. The number of insulating layers may be four or more, and a connecting electrode may be further provided between the pixel electrode PE and the second electrode OE of the transistor TR.

[0157] Figure 6 is a cross-sectional view of a light emitting diode according to an embodiment of the inventive concept.

[0158] Reference Figure 6 , shows a cross-sectional view of a light emitting diode LD. The light emitting diode LD may include a first electrode E1, a light generating layer LEL, and a second electrode E2. The light generating layer LEL may include a p-type semiconductor layer SCP, an active layer AL, and an n-type semiconductor layer SCN. The p-type semiconductor layer SCP, the active layer AL, and the n-type semiconductor layer SCN may be sequentially stacked on the first electrode E1 of the light emitting diode LD. The p-type semiconductor layer SCP may be connected to the first electrode E1 of the light emitting diode LD and the n-type semiconductor layer SCN may be connected to the second electrode E2 of the light emitting diode LD. The active layer AL may be disposed between the n-type semiconductor layer SCN and the p-type semiconductor layer SCP.

[0159] The n-type semiconductor layer SCN can be provided by doping the semiconductor layer with an n-type dopant, and the p-type semiconductor layer SCP can be provided by doping the semiconductor layer with a p-type dopant. The semiconductor layer may include a semiconductor material, and the semiconductor material may be, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN or AlInN, but is not limited thereto. The n-type dopant may be silicon (Si), germanium (Ge), tin (Sn), selenium (Se), tellurium (Te) or a combination thereof, but is not limited thereto. The p-type dopant may be magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba) or a combination thereof, but is not limited thereto.

[0160] The active layer AL may be formed of at least one of a single quantum well structure, a multi-quantum well structure, a quantum wire structure, and a quantum dot structure. The active layer AL may be a region where electrons injected through the n-type semiconductor layer SCN and holes injected through the p-type semiconductor layer SCP are recombined. The active layer AL may be a layer that emits light having energy determined by a material-specific energy band. The position of the active layer AL may vary based on the type of diode.

[0161] Figure 7 is a cross-sectional view of a second substrate according to an embodiment of the inventive concept.

[0162] Reference Figure 7 , when compared with the above Figure 5B Compared with the second substrate 200 described above, the second substrate 200-1 may not include the insulating layer ILL (see Figure 5B ).

[0163] The intermediate layer PL-1 may be disposed on the pixel electrode PE. The intermediate layer PL-1 may include a polymer resin layer EP-1 and conductive particles. The conductive particles may condense on the pixel electrode PE to form a conductive layer EC. That is, the intermediate layer PL-1 may include a conductive layer EC and a polymer resin layer EP-1.

[0164] The conductive layer EC may electrically connect the plurality of light emitting diodes LD and the pixel electrode PE. The polymer resin layer EP-1 may cover the conductive layer EC.

[0165] The common electrode CE may be disposed on the polymer resin layer EP-1. The common electrode CE is spaced apart from the conductive layer EC by the polymer resin layer EP-1 and may be electrically connected to the light emitting diode LD.

[0166] Figure 8 is a cross-sectional view of a second substrate according to an embodiment of the inventive concept.

[0167] Reference Figure 8 , and refer to the above Figure 5B Compared with the second substrate 200 described above, the second substrate 200 - 2 may further include a reflective layer RC.

[0168] The reflective layers RC may surround at least a portion of the light emitting diodes LD, respectively.

[0169] The reflective layer RC may improve light emitting efficiency by reflecting light provided by the light emitting diode LD. The reflective layer RC may include metal or metal alloy.

[0170] The reflective layer RC may have a cup shape, and at least a portion of the light emitting diode LD may be surrounded by the cup-shaped reflective layer RC. For example, a portion of the reflective layer RC may be disposed between the light emitting diode LD and the conductive layer EC. In addition, another portion of the reflective layer RC may surround a portion of the side wall of the light emitting diode LD. The cover layer ILS may be disposed between the other portion of the reflective layer RC and the side wall of the light emitting diode LD.

[0171] Fig. 9 is a cross-sectional view of a display panel according to another embodiment of the inventive concept.

[0172] Reference Fig. 9 , a first pixel area PXA1, a second pixel area PXA2, a third pixel area PXA3, and a light shielding area NFXA are defined in the display panel DP-1.

[0173] The first pixel area PXA1 provides a first color light, the second pixel area PXA2 provides a second color light, and the third pixel area PXA3 provides a third color light. The first color light, the second color light, and the third color light may be lights of different colors. For example, one color light of the first to third color lights may be red light, another color light may be green light, and another color light may be blue light.

[0174] The light emitting diode LDR disposed in the first pixel region PXA1 may provide a first color light. The light emitting diode LDG disposed in the second pixel region PXA2 may provide a second color light. The light emitting diode LDB disposed in the third pixel region PXA3 may provide a third color light.

[0175] and Figure 5A The embodiments are different. Fig. 9 The light emitting diodes LDR, LDG and LDB shown in FIG. 1 can provide light of different colors. Therefore, the first substrate 100 (see FIG. 10 ) can be omitted. Figure 5A ).

[0176] The display panel DP-1 may include a thin film sealing layer TFE disposed on the common electrode CE. The thin film sealing layer TFE may include inorganic layers and organic layers alternately stacked.

[0177] FIG. 10A to FIG. 10G is a view illustrating a portion of a manufacturing process of a display panel according to an embodiment of the inventive concept.

[0178] Reference Fig. 10A , forming a base layer BS2. A pixel circuit CC is formed on the base layer BS2. A pixel electrode PE is formed on the pixel circuit CC. The pixel electrode PE may be electrically connected to the pixel circuit CC. For example, the pixel electrode PE may be electrically connected to the second electrode OE of the transistor TR.

[0179] The pixel electrode PE may be formed using gold, silver, or copper. However, the material constituting the pixel electrode PE is not limited to the above examples. For example, the pixel electrode PE may include a material on which conductive particles included in the intermediate layer PL-P to be described later may condense.

[0180] Reference Fig. 10B , forming an intermediate layer PL-P on the pixel electrode PE. The intermediate layer PL-P may include a polymer resin EPa and conductive particles ECP. The step of forming the intermediate layer PL-P may include screen printing or slit coating a mixed material of the polymer resin EPa and the conductive particles ECP. The material mixed with the polymer resin EPa and the conductive particles ECP may be a solder paste that melts at a low temperature.

[0181] Reference Fig. 10C , the base layer BS2 may include an active area AA-B and a peripheral area NAA-B. The peripheral area NAA-B may surround the active area AA-B. The active area AA-B is adjacent to the active area AA (see Figure 1B ) corresponds to, and the peripheral area NAA-B corresponds to the peripheral area NAA (see Figure 1B )correspond.

[0182] The intermediate layer PL-P may be formed only in the region overlapping with the active area AA-B on a plane. For example, the intermediate layer PL-P may not be formed in the region overlapping with the peripheral area NAA-B.

[0183] Reference Fig. 10D , a donor substrate DNP to which a plurality of light emitting diodes LDS are attached is prepared. Thereafter, the plurality of light emitting diodes LDS contact the intermediate layer PL-P.

[0184] Reference Fig.10E , heating the intermediate layer PL-P. The conductive particles ECP of the heated intermediate layer PL-P can condense on the pixel electrode PE to form a conductive layer EC, and the polymer resin EPa in which the concentration of the conductive particles ECP is reduced can form a polymer resin layer EP-1. The heating temperature can be between 140 degrees and 180 degrees. As the heating temperature is higher, the heating time can be shortened. For example, if the heating temperature is 140 degrees, the intermediate layer PL-P can be heated for 3 minutes, and if the heating temperature is 180 degrees, the intermediate layer PL-P can be heated for 30 seconds. However, the heating temperature and the heating time are only numerical values, and the inventive concept is not limited thereto. The heating temperature and the heating time can be changed according to the properties of the conductive particles ECP.

[0185] When the intermediate layer PL-P is heated, the conductive particles ECP may melt. The conductive particles ECP may include a tin-bismuth alloy. The melting point of the tin-bismuth alloy may be about 139 degrees. In an embodiment of the inventive concept, the melted conductive particles ECP may condense onto the pixel electrode PE.

[0186] According to an embodiment of the inventive concept, when the intermediate layer PL-P is heated after the donor substrate DNP on which the light emitting diode LDS is disposed contacts the intermediate layer PL-P, the conductive particles ECP condense and melt between the pixel electrode PE and the light emitting diode LDS so that the conductive layer EC can be formed. That is, the alignment process for transferring a portion of the light emitting diode LDS to the pixel electrode PE can be omitted. Therefore, the process for manufacturing the display panel can be simplified and the process speed can be improved.

[0187] In another embodiment of the inventive concept, Fig.10EUnlike the embodiment shown in , the conductive layer EC may surround a portion of each of the light emitting diodes LDS in the thickness direction (eg, the third direction DR3 ).

[0188] Reference Fig.10F After hardening the polymer resin layer EP-1, the donor substrate DNP is separated. Fig.10E ) among the effective light emitting diodes LD-E disposed on the pixel electrode PE may be transferred to the pixel electrode PE. The remaining light emitting diodes LD-NE (hereinafter, referred to as ineffective light emitting diodes) may be separated from the polymer resin layer EP-1 together with the donor substrate DNP.

[0189] The polymer resin layer EP-1 and the conductive layer EC may be distinguished by the difference in the concentration of the conductive particles ECP. For example, the concentration of the conductive particles ECP included in the conductive layer EC may be higher than the concentration of the conductive particles ECP included in the polymer resin layer EP-1. The conductive particles ECP may not be included in the polymer resin layer EP-1, but some non-condensed conductive particles ECP may be dispersed.

[0190] Reference Figure 10G , a common electrode CE is formed on the intermediate layer PL-1. An effective light emitting diode LD-E may be electrically connected to the common electrode CE and the pixel electrode PE to provide light.

[0191] Fig.11 is a cross-sectional view of a portion of a structure of a display panel according to an embodiment of the inventive concept.

[0192] Reference Fig.11 , at least some of the invalid light emitting diodes LD-NE may not be separated from the polymer resin layer EP-1. The invalid light emitting diodes LD-NE are not electrically connected to the pixel electrode PE. Therefore, the invalid light emitting diodes LD-NE may not provide light.

[0193] FIG. 12A to FIG. 12D is a view illustrating a portion of a manufacturing process of a display panel according to an embodiment of the inventive concept.

[0194] Reference Fig. 12A , the thickness of the polymer resin layer EP can be greater than Fig.10F The thickness of the polymer resin layer EP-1 is thin.

[0195] Reference Fig. 12B , an initial insulating layer ILL-P is formed on the intermediate layer PL. The initial insulating layer ILL-P may be a photoresist.

[0196] Reference Fig. 12C, a portion of the initial insulating layer ILL-P in the thickness direction is etched to form an insulating layer ILL. The insulating layer ILL forms a second electrode E2 (see Figure 5B ) exposes and may cover the intermediate layer PL.

[0197] Reference Fig.12D , a common electrode CE is formed on the insulating layer ILL.

[0198] Fig.13 is a view illustrating a portion of a manufacturing process of a display panel according to an embodiment of the inventive concept.

[0199] Reference Fig.13 , shows an operation of forming a reflective layer RC on a plurality of light emitting diodes LDS formed on one side of a donor substrate DNP. The reflective layer RC may be formed after forming a cap layer ILS that covers the side walls of the light emitting diodes LDS, respectively.

[0200] Fig.14 is a perspective view of a display device according to an embodiment of the inventive concept. Fig.15 is a perspective view of a display device according to an embodiment of the inventive concept.

[0201] Reference Fig.14 and Fig.15 , the display device DD1 may be an extendable display device. In this case, the shape of the display device DD1 may be variously modified. For example, the display device DD1 may be extended in various directions.

[0202] like Fig.14 As shown in , the display device DD1 may extend in various directions on a plane defined by the first direction DR1 and the second direction DR2. The display device DD1 may be shape-modified by an externally applied force.

[0203] like Fig.15 As shown in , the display device DD1 may extend in a direction protruding from the display surface FS.

[0204] Since the shape of the display device DD1 can be easily modified, the display device DD1 can be installed on a mounting surface having various shapes. For example, the display device DD1 can be installed on a curved mounting surface inside a car.

[0205] Refer to above Figures 2 to 13 The description can also be applied to Fig.14 and Fig.15 The display device DD1 shown in FIG.

[0206] According to an embodiment of the inventive concept, when the intermediate layer is heated after the intermediate layer contacts the donor substrate on which the light-emitting diode is arranged, the conductive particles can condense and melt between the pixel electrode and the light-emitting diode to form a conductive layer. That is, the alignment process for transferring the light-emitting diode to the pixel electrode can be omitted. Therefore, the process for manufacturing the display panel can be simplified, and the process speed can be improved. In addition, a plurality of light-emitting diodes can be arranged on one pixel electrode. Therefore, even if one of the plurality of light-emitting diodes does not emit light, another light-emitting diode can also emit light. As a result, the possibility of the occurrence of defective pixels that do not provide light can be reduced.

[0207] Although exemplary embodiments of the inventive concept have been described, it is understood that the inventive concept should not be limited to the exemplary embodiments but various changes and modifications may be made by one of ordinary skill in the art within the spirit and scope of the inventive concept as claimed.

Claims

1. A display device, comprising: Base layer; A pixel circuit is arranged on the substrate layer; a pixel electrode electrically connected to the pixel circuit; an intermediate layer, comprising a conductive layer disposed on the one pixel electrode and completely overlapping the one pixel electrode, and a polymer resin layer covering the conductive layer; a plurality of light emitting diodes disposed on the conductive layer and electrically connected to the one pixel electrode; as well as a common electrode configured to cover the plurality of light emitting diodes and be electrically connected to the plurality of light emitting diodes, Each of the plurality of light emitting diodes includes a first electrode, a light generating layer, and a second electrode sequentially stacked in a thickness direction of the base layer.

2. The display device according to claim 1, wherein: The one pixel electrode includes copper, silver, gold or an alloy thereof.

3. The display device according to claim 1, wherein: The conductive layer is provided with conductive particles condensed between the one pixel electrode and the plurality of light emitting diodes.

4. The display device according to claim 3, wherein: The conductive particles include a tin-bismuth alloy.

5. The display device according to claim 3, wherein: The conductive layer is provided with the conductive particles dispersed and provided in the intermediate layer and coagulated onto the one pixel electrode by heating.

6. The display device according to claim 1, wherein: The conductive layer is disposed between the one pixel electrode and the first electrode, and a portion of each of the plurality of light emitting diodes is surrounded by the polymer resin layer.

7. The display device according to claim 1, further comprising: A capping layer covers a side wall of each of the plurality of light emitting diodes.

8. The display device according to claim 1, further comprising: An insulating layer is disposed on the intermediate layer and exposes the second electrode of each of the plurality of light emitting diodes, wherein the common electrode is disposed on the insulating layer.

9. The display device according to claim 1, further comprising: A reflective layer surrounds a portion of each of the plurality of light emitting diodes and is disposed under the first electrode of each of the plurality of light emitting diodes.

10. A method for manufacturing a display device, the method comprising the following steps: forming a matrix layer; forming a pixel circuit on the substrate layer; forming a pixel electrode electrically connected to the pixel circuit on the pixel circuit; forming an intermediate layer in which a polymer resin and conductive particles are mixed on the one pixel electrode; contacting a plurality of light emitting diodes attached to a donor substrate with the intermediate layer; heating the intermediate layer to condense the conductive particles on the one pixel electrode; separating the donor substrate from the intermediate layer; as well as A common electrode is formed on the effective light emitting diodes transferred to the one pixel electrode among the plurality of light emitting diodes.

11. The method according to claim 10, further comprising the steps of: forming an insulating layer on the effective light emitting diode; as well as removing a portion of the insulating layer to expose at least a portion of the effective light emitting diode, Wherein, the common electrode is formed on the insulating layer.

12. The method according to claim 10, wherein: The step of heating the intermediate layer includes heating the intermediate layer at a temperature between 140 degrees and 180 degrees.

13. The method according to claim 10, wherein: The step of forming the intermediate layer includes screen-printing a material in which the polymer resin and the conductive particles are mixed.

14. The method according to claim 10, wherein: The step of forming the intermediate layer includes slit coating a material in which the polymer resin and the conductive particles are mixed.

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