Display devices

Abstract

The display device includes: a substrate; a display area disposed on the substrate and including a plurality of pixels; a non-display area disposed outside the display area; a first power supply voltage line including a first conductive layer disposed in the non-display area and a second conductive layer disposed on the first conductive layer; a second power supply voltage line disposed in the non-display area and including a third conductive layer spaced apart from the first conductive layer and a fourth conductive layer disposed on the third conductive layer; a first baffle portion surrounding the display area and overlapping the second power supply voltage line; a second baffle portion disposed adjacent to the first baffle portion; and a covering layer covering a first end portion of the fourth conductive layer, the first end portion of the fourth conductive layer being formed in a direction intersecting the extending directions of the first baffle portion and the second baffle portion.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2019-0062586, filed on May 28, 2019, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of this disclosure relate to display devices, and specifically to display devices that can reduce the area of ​​narrow dead spaces in the display device and prevent cracks from occurring due to poor step coverage of wiring units. Background Technology

[0004] Display devices are devices used to visually represent or display data. Display devices are currently used for a variety of purposes and applications. Furthermore, the application range of display devices has expanded due to reductions in their thickness and weight.

[0005] Display devices may include a substrate, which may be divided into a display area and a non-display area outside the display area. Non-display components, such as pad units, wiring, and drive circuit units, may be placed or disposed in the non-display area, which may be dead space where no image is displayed. Recently, there has been an increasing demand for further reduction of the dead space in display devices.

[0006] It should be understood that this background section is intended to provide useful background for understanding the technology. However, this background section may also include ideas, concepts, or knowledge that were not known or understood by one of skill in the art prior to the relevant valid submission date of the subject matter disclosed herein. Summary of the Invention

[0007] Embodiments of this disclosure can prevent undercutting in the upper conductive layer of the second power voltage line by applying a double-layer structure to the second power voltage line, rather than reducing the width of the second power voltage line due to the reduction of dead space. However, the above problem is merely an example and therefore does not limit the scope of this disclosure.

[0008] Other aspects will be set forth in part in the description which follows, and in part will be obvious from the description or may be learned by practice of the embodiments of this disclosure presented.

[0009] According to one or more embodiments, a display device may include a substrate; a display area disposed on the substrate and including a plurality of pixels; a non-display area disposed outside the display area; a first power supply voltage line including a first conductive layer disposed in the non-display area and a second conductive layer disposed on the first conductive layer; a second power supply voltage line disposed in the non-display area and including a third conductive layer spaced apart from the first conductive layer and a fourth conductive layer disposed on the third conductive layer; a first baffle portion surrounding the display area and overlapping the second power supply voltage line; a second baffle portion disposed adjacent to the first baffle portion; and a covering layer covering a first end portion of the fourth conductive layer, the first end portion of the fourth conductive layer being formed in a direction intersecting the extending directions of the first baffle portion and the second baffle portion.

[0010] The display device may further include a first planarization film disposed in a display area and a non-display area; a second planarization film disposed on the first planarization film; and a pixel defining film disposed on the second planarization film. A first baffle portion may include a first layer comprising a portion of the second planarization film; and a second layer comprising a portion of the pixel defining film. The second baffle portion may also include a first layer comprising a portion of the second planarization film; and a second layer comprising a portion of the pixel defining film.

[0011] The coating layer may include the same material as the second planarization film.

[0012] A first planarization film may be disposed between a first conductive layer and a second conductive layer, wherein the first conductive layer and the second conductive layer are electrically connected to each other through a first contact hole formed in the first planarization film.

[0013] A first planarization film may be disposed between a third conductive layer and a fourth conductive layer, wherein the third conductive layer and the fourth conductive layer are electrically connected to each other through a second contact hole formed in the first planarization film.

[0014] The display device may further include a third baffle portion disposed between the display area and the first baffle portion, and the third baffle portion includes a first layer including a portion of a second planarization film; and a second layer including a portion of a pixel defining film.

[0015] Each of the plurality of pixels may include a first electrode; an emission layer disposed on the first electrode; and a second electrode disposed on the emission layer, wherein the second electrodes are disposed together on the plurality of pixels, wherein the second electrodes extend into a non-display area and cover a portion of a third baffle portion.

[0016] A pixel defining film may be disposed on a second planarization film and cover the end portion of the first electrode, wherein the display device further includes a spacer disposed on the pixel defining film, wherein the second baffle portion further includes a third layer comprising the same material as the spacer and formed on the second layer comprising a portion of the pixel defining film.

[0017] The height of the second baffle section can be greater than the height of each of the first and third baffle sections.

[0018] The third baffle section, the first baffle section, and the second baffle section may overlap with the second power supply voltage line.

[0019] The third baffle portion may overlap with the first power supply voltage line, and the first baffle portion and the second baffle portion may overlap with the second power supply voltage line.

[0020] The third baffle portion may include a first portion, which is disposed adjacent to the display area; and a second portion, which is disposed adjacent to the first baffle portion.

[0021] The width of the first power supply voltage line can be greater than the width of the second power supply voltage line.

[0022] The second planarization film may cover the third end portion of the fourth conductive layer, which is formed in a direction parallel to the direction in which the first baffle portion and the second baffle portion extend.

[0023] The first conductive layer may include the same material as the third conductive layer, and the second conductive layer may include the same material as the fourth conductive layer.

[0024] The fourth conductive layer may further include a second end portion facing the first end portion outside the second baffle portion, and the covering layer may cover the top surface of the fourth conductive layer outside the second baffle portion as well as the first end portion and the second end portion.

[0025] Between the first baffle portion and the second baffle portion, the covering layer may cover the first end portion but not at least a portion of the top surface of the fourth conductive layer.

[0026] The fourth conductive layer may further include a second end portion facing the first end portion outside the second baffle portion, and the covering layer may cover the first end portion and the second end portion outside the second baffle portion without covering at least a portion of the top surface of the fourth conductive layer.

[0027] The display device may further include a plurality of star-shaped wirings between the substrate and the first conductive layer and the third conductive layer, the plurality of star-shaped wirings being spaced apart from each other in a direction intersecting the directions in which the first conductive layer and the third conductive layer extend.

[0028] Between the multiple star-shaped wirings and the first and third conductive layers, at least two insulating layers may extend to the display area.

[0029] The display device may further include a thin-film encapsulation layer, the thin-film encapsulation layer including a first inorganic encapsulation layer covering the display area; an organic encapsulation layer disposed on the first inorganic encapsulation layer; and a second inorganic encapsulation layer disposed on the organic encapsulation layer; wherein the thin-film encapsulation layer covers the third baffle portion and the first baffle portion.

[0030] The first inorganic encapsulation layer and the second inorganic encapsulation layer can contact each other on the outside of the second baffle portion.

[0031] The first inorganic encapsulation layer and the second inorganic encapsulation layer can be in direct contact with each other on the outer side of the second baffle portion.

[0032] According to one or more embodiments, a display device includes: a display area including a plurality of pixels; a non-display area disposed outside the display area; a first power supply voltage line disposed outside the non-display area; a second power supply voltage line spaced apart from the first power supply voltage line; a first baffle portion surrounding the display area and overlapping the second power supply voltage line; a second baffle portion disposed adjacent to the first baffle portion; a third baffle portion disposed between the display area and the first baffle portion; and an insulating layer forming a portion of the first baffle portion and the second baffle portion; wherein the insulating layer covers a first end portion of the second power supply voltage line and a third end portion of the second power supply voltage line, the first end portion of the second power supply voltage line being formed in a direction intersecting the direction extending from the first baffle portion to the third baffle portion, and the third end portion of the second power supply voltage line being formed in a direction parallel to the direction extending from the first baffle portion to the third baffle portion.

[0033] Between the first end portion and the third end portion, the insulating layer may further cover the top surface of the second power supply voltage line. Attached Figure Description

[0034] The above and other aspects, features, and advantages of the embodiments of this disclosure will become more apparent from the following description, taken in conjunction with the accompanying drawings, wherein:

[0035] Figure 1 This is a plan view of a display device according to an embodiment;

[0036] Figure 2A and Figure 2B To illustrate the equivalent circuit diagram of the pixels included in the display device according to the embodiment;

[0037] Figure 3 To explain Figure 1 Plan view of Part III;

[0038] Figure 4 For along Figure 3 Explanation of the IVA-IVB line segment Figure 1 A schematic cross-sectional view of the pixels included in the display device;

[0039] Figure 5 For along Figure 3 The lines IVA-IVB and Figure 1 A schematic cross-sectional view of the display device according to the embodiment, taken from lines VA-VB;

[0040] Figure 6 To explain Figure 1 A magnified plan view of part of AR1;

[0041] Figure 7A For along Figure 6 A schematic cross-sectional view of lines VIIA-VIIB;

[0042] Figure 7B It is along Figure 6 A schematic cross-sectional view of the section intercepted by lines VIIA'-VIIB';

[0043] Figure 8 To illustrate the enlarged plan view of AR2 based on the comparative example;

[0044] Figure 9 For along Figure 8 A schematic cross-sectional view of line IXA-IXB;

[0045] Figure 10 This is a schematic cross-sectional view of a display device according to an embodiment;

[0046] Figure 11 To illustrate a portion of the enlarged planar view of AR3;

[0047] Figure 12A For along Figure 11A schematic cross-sectional view of the line XIIA-XIIB;

[0048] Figure 12B For along Figure 11 A schematic cross-sectional view of the line XIIA'-XIIB';

[0049] Figure 13 This is a schematic cross-sectional view of a display device according to an embodiment;

[0050] Figure 14 This is a plan view of a display device according to an embodiment;

[0051] Figure 15 For along Figure 3 The lines IVA-IVB and Figure 14 A schematic cross-sectional view of the display device according to the embodiment, taken from lines XVA-XVB; and

[0052] Figure 16 This is a schematic cross-sectional view of a display device according to an embodiment. Detailed Implementation

[0053] Detailed embodiments will now be referenced to, examples of which are illustrated in the accompanying drawings, wherein the same reference numerals refer to the same elements throughout the text. In this regard, embodiments may take different forms and should not be construed as limited to the descriptions set forth herein. Therefore, embodiments are described below with reference to the drawings only to explain the aspects described.

[0054] The present disclosure will now be described in detail with reference to the accompanying drawings, in which the same reference numerals denote the same elements and therefore will not be repeated.

[0055] In order to describe embodiments of this disclosure, some parts that are not related to the description may be omitted, and throughout the specification, the same reference numerals refer to the same elements.

[0056] It will be understood that although the terms “first,” “second,” and “third” may be used, for example, to describe various elements in this document, these elements should not be limited by these terms, and these elements are used only to distinguish one element from another.

[0057] As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0058] It will be further understood that the terms “comprises” and / or “comprising” as used herein indicate the presence of a feature or component of the description, but do not exclude the presence or addition of one or more other features or components.

[0059] It will be understood that when a layer, region, or component is referred to as "formed on" another layer, region, or component, it may be formed directly on the other layer, region, or component, or indirectly on the other layer, region, or component, with an intermediate layer, region, or component between the layer, region, or component and the other layer, region, or component.

[0060] For ease of explanation, the dimensions of the components in the figure may be enlarged. In other words, because the dimensions and thicknesses of the components in the figure are arbitrarily interpreted for ease of explanation, the following implementation is not limited to this.

[0061] Furthermore, in the specification, the phrase "in a plan view" means when viewing a portion of the object from above, and the phrase "in a schematic cross-sectional view" means when viewing a schematic cross-section taken by vertically cutting a portion of the object from the side.

[0062] Additionally, the terms "overlapping" or "overlapping" mean that the first object may be on top of, below, or to the side of the second object, and vice versa. Furthermore, the term "overlapping" may include layering, stacking, facing, extending over, covering, or partially covering, or any other suitable terminology that will be understood and appreciated by one of ordinary skill in the art. The terms "facing" and "facing" mean that the first element may be directly or indirectly opposite the second element. In the case where a third element is located between the first and second elements, the first and second elements may be understood as being indirectly opposite each other, but still facing each other. When an element is described as "not overlapping" or "will not overlap" with another element, this may include elements spaced apart from each other, offset from each other, or adjacent to each other, or any other suitable terminology that will be understood and appreciated by one of ordinary skill in the art.

[0063] For ease of description, the spatial relative terms “below,” “under,” “down,” “above,” “up,” etc., may be used herein to describe the relationship between one element or component and another element or component illustrated in the figures. It will be understood that, in addition to the orientation depicted in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or operation. For example, in the case of flipping the device illustrated in the figures, a device located “below” or “under” another device may be placed “above” another device. Therefore, the interpretative term “below” can include both a lower position and an upper position. The device may also be oriented in other directions, and therefore the spatial relative terms may be interpreted differently depending on the orientation.

[0064] Considering the measurements discussed and the errors associated with a particular number of measurements (i.e., limitations of the measurement system), the terms “about” or “approximately” as used herein include the stated values ​​and the average of the values ​​within an acceptable range of deviations for a particular value, as determined by one of ordinary skill in the art. For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±5% of the stated values.

[0065] In the specification and claims, for the purposes of their meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in the sense of conjunctions or antonymous conjunctions and are understood to be equivalent to "and / or". In the specification and claims, for the purposes of their meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group consisting of...". For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0066] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having the same meaning as they have in the context of the relevant field and will not be interpreted in an idealized or overly formal sense unless clearly defined in the specification.

[0067] When different implementation methods are implemented, the specific process sequence may differ from the described sequence. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description.

[0068] It will be understood that when a layer, region, or element is referred to as being "connected" to another layer, region, or element, the layer, region, or element may be directly connected to the other layer, region, or element or may be indirectly connected to the other layer, region, or element, with an intermediate layer, region, or element between the layer, region, or element and the other layer, region, or element. For example, when a layer, region, or element is electrically connected to another layer, region, or element, the layer, region, or element may be directly electrically connected to the other layer, region, or element or may be indirectly electrically connected to the other layer, region, or element, with an intermediate layer, region, or element between the layer, region, or element and the other layer, region, or element.

[0069] In the following examples, the x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0070] Examples of display devices for displaying images may include liquid crystal displays, electrophoretic displays, organic light-emitting displays, inorganic electroluminescent (EL) displays, field emission displays, surface conduction electron emitter displays, plasma displays, and cathode ray tube displays.

[0071] Although an organic light-emitting display can be described as a display device according to an embodiment, this disclosure is not limited thereto, and various display devices may be applicable within the spirit and scope of this disclosure.

[0072] Figure 1 This is a plan view of the display device 1 according to the embodiment. Figure 2A and Figure 2B To illustrate the equivalent circuit diagram of the pixels included in the display device 1 according to the embodiment, Figure 3 To explain Figure 1 Part III plan view, Figure 4 For along Figure 3 Explanation of the IVA-IVB line segment Figure 1 A cross-sectional view of the pixels included in the display device 1, and Figure 5 For along Figure 3 The lines IVA-IVB and Figure 1 The VA-VB line is a cross-sectional view of display device 1.

[0073] refer to Figure 1 The display device 1 may include a substrate 100, which includes a display area DA. The display area DA may include pixels P, each pixel P being connected to a data line DL extending in a first direction and a scan line SL extending in a second direction. The second direction may intersect with the first direction. Each pixel P may be connected to a driving voltage line PL extending in the first direction.

[0074] A pixel P may emit light, such as red, green, blue, or white light, and may include, for example, an organic light-emitting diode. Each pixel P may include devices such as thin-film transistors (TFTs) and capacitors.

[0075] The display area DA can provide one or more predetermined images through the light emitted by pixel P, and the non-display area NDA can be placed or positioned outside the display area DA. For example, the non-display area NDA can surround or be located around the display area DA. The non-display area NDA can be on the outer periphery or periphery of the display area DA.

[0076] The non-display area NDA, where pixel P may not be placed or set, may not provide an image. A first power supply voltage line 10 and a second power supply voltage line 20 may be placed or set in the non-display area NDA, and the second power supply voltage line 20 may provide a voltage different from that of the first power supply voltage line 10.

[0077] The first power supply voltage line 10 may include a first main voltage line 11 and a first connecting line 12 placed or disposed on a side of the display area DA. For example, when the display area DA has a rectangular shape, the first main voltage line 11 may be placed or disposed corresponding to one side of the display area DA. The first connecting line 12 may extend from the first main voltage line 11 in a first direction. In an embodiment, the first direction may be the direction from the display area DA to the terminal unit 30 near the end portion of the substrate 100 (or at a predetermined distance from the end portion of the substrate 100). The first connecting line 12 may be connected to a first terminal 32 of the terminal unit 30.

[0078] The second power supply voltage line 20 may include a second main voltage line 21 and a second connecting line 22. The second main voltage line 21 partially surrounds the two end portions of the first main voltage line 11 and the display area DA. The second connecting line 22 extends from the second main voltage line 21 in a first direction. For example, when the display area DA has a rectangular shape, the second main voltage line 21 may extend along the end portion (or both end portions) of the first main voltage line 11 and the sides of the display area DA, excluding the sides adjacent to the first main voltage line 11. The second connecting line 22 may extend in the first direction parallel to the first connecting line 12 and may be connected to the second terminal 33 of the terminal unit 30. The second power supply voltage line 20 may be bent to surround the end portion of the first power supply voltage line 10.

[0079] Terminal unit 30 may be placed or disposed on the end portion of substrate 100 and may include terminals (e.g., third terminal 31, first terminal 32, and second terminal 33). Terminal unit 30 may be exposed, i.e., not covered by an insulating layer. Terminal unit 30 may be electrically connected to a controller (not shown), such as a flexible printed circuit board or a driver integrated circuit (IC) chip.

[0080] The controller can convert external image signals into image data signals and transmit the image data signals to the display area DA via the third terminal 31. The controller can receive vertical synchronization signals, horizontal synchronization signals, and clock signals, generate control signals to control the operation of the first gate driver (not shown) and the second gate driver (not shown), and transmit the control signals to the terminal (not shown).

[0081] The controller can apply different voltages to the first power supply voltage line 10 and the second power supply voltage line 20 through the first terminal 32 and the second terminal 33, respectively.

[0082] The first power supply voltage line 10 can deliver the first power supply voltage ELVDD (see...). Figure 2A and Figure 2B The second power supply voltage line 20 supplies the second power supply voltage ELVSS to each pixel P, and the second power supply voltage line 20 can supply the second power supply voltage ELVSS (see... Figure 2Aand Figure 2B ) is supplied to each pixel P.

[0083] For example, a first power supply voltage ELVDD can be applied to each pixel P via a drive voltage line PL that can be connected to the first power supply voltage line 10. A second power supply voltage ELVSS can be applied to the organic light-emitting device OLED provided in each pixel P (see...). Figure 2A and Figure 2B The cathode of the OLED. In this case, the second main voltage line 21 of the second power supply voltage line 20 can be connected to the cathode of the organic light-emitting device OLED in the non-display area NDA.

[0084] although Figures 1 to 5 Not shown, but the scan driver that can apply scan signals to the scan line SL of each pixel P and the data driver that can apply data signals to the data line DL can be placed or set in the non-display area NDA.

[0085] The first baffle portion 110, the second baffle portion 120, and the third baffle portion 130 surrounding the display area DA can be placed or disposed in the non-display area NDA. The first baffle portion 110, the second baffle portion 120, and the third baffle portion 130 can be spaced apart from each other.

[0086] When an organic encapsulation layer 420, comprising organic materials such as monomers, can be formed using inkjet technology (see...), it is possible to use inkjet technology to form such an organic encapsulation layer 420. Figure 4 When the organic material flows to the edge of the substrate 100, the first baffle portion 110 and the second baffle portion 120 can act as baffles to prevent the organic material from flowing to the edge of the substrate 100. Therefore, due to the organic encapsulation layer 420 at the edge of the substrate 100, the formation of edge tails can be prevented. The first baffle portion 110 and the second baffle portion 120 can be disposed adjacent to each other and disposed on their outer sides.

[0087] Even with or despite the presence of the first baffle portion 110 and the second baffle portion 120, the organic material of the organic encapsulation layer 420 can still flow across the first baffle portion 110 and the second baffle portion 120 to the edge of the substrate 100. For example, when the second baffle portion 120 can be positioned or configured to be closer to the first baffle portion 110 from the edge of the substrate 100 to reduce the area of ​​the dead space when viewed from the outside, or when the first baffle portion 110 can be positioned or configured to be closer to the second baffle portion 120 to increase the display area DA, the spacing between the first baffle portion 110 and the second baffle portion 120 can be reduced, and the organic material of the organic encapsulation layer 420 can flow across the second baffle portion 120. When the organic material overflows, an edge tail can be formed. The edge tail can become a path that can introduce external impurities and can cause defects in the organic light-emitting device OLED. Therefore, as the dead space decreases, reducing the overflow of organic material and controlling the amount of overflowing organic material becomes more important. A third baffle portion 130, placed or positioned between the display area DA and the first baffle portion 110, can reduce the backflow rate of the organic material and reduce the amount of organic material flowing to the first baffle portion 110. It should be understood that the designations for the first, second, and third baffle portions are arbitrary and for ease of description. Without departing from the spirit and scope of this disclosure, the baffle portion may be any one of the first, second, and third baffle portions. Baffle portions 110, 120, and 130 can be used as barriers, containers, or reservoirs for reducing or preventing the spillage of organic material.

[0088] refer to Figure 2A Each pixel P may include a pixel circuit PC connected to a scan line SL and a data line DL, and an organic light-emitting device OLED connected to the pixel circuit PC.

[0089] The pixel circuit PC may include a driving TFT T1, a switching TFT T2, and a storage capacitor Cst. The switching TFT T2 can transmit the data signal Dm, which is input through the data line DL, to the driving TFT T1 according to the first scan signal Sn input through the scan line SL.

[0090] The storage capacitor Cst can be connected to the switch TFT T2 and the drive voltage line PL, and can store the voltage corresponding to the difference between the voltage received from the switch TFT T2 and the first power supply voltage ELVDD (or drive voltage) applied to the drive voltage line PL.

[0091] The driving TFT T1 can be connected to the driving voltage line PL and the storage capacitor Cst, and can control the driving current flowing from the driving voltage line PL to the organic light-emitting device OLED in response to the value of the voltage stored in the storage capacitor Cst. Due to the driving current, the organic light-emitting device OLED can emit light with a predetermined brightness.

[0092] Despite Figure 2A The intermediate pixel circuit PC includes two TFTs and a storage capacitor, but this disclosure is not limited thereto.

[0093] refer to Figure 2B The pixel circuit PC may include a driving TFT T1, a switching TFT T2, a compensation TFT T3, a first initialization TFT T4, a first emission control TFT T5, a second emission control TFT T6, and a second initialization TFT T7.

[0094] Despite Figure 2B The system may provide signal lines (e.g., a first scan line SLn, a second scan line SLn-1, an emit control line EL, and a data line DL), an initialization voltage line VL, and a drive voltage line PL for each pixel P, but this disclosure is not limited thereto. In embodiments, at least one of the signal lines and the initialization voltage line VL may be shared by neighboring pixels.

[0095] The drain electrode of the driving TFT T1 can be electrically connected to the organic light-emitting device (OLED) via the second emission control TFT T6. The driving TFT T1 can receive the data signal Dm according to the switching operation of the switching TFT T2 and apply the driving current to the OLED.

[0096] The gate electrode of the switching TFT T2 can be connected to the first scan line SLn, and the source electrode of the switching TFT T2 can be connected to the data line DL. The drain electrode of the switching TFT T2 can be connected to the source electrode of the driving TFT T1, and can be connected to the driving voltage line PL through the first emitter control TFT T5.

[0097] The switch TFT T2 can be turned on according to the first scan signal Sn received through the first scan line SLn, and can perform a switching operation to transmit the data signal Dm transmitted to the data line DL to the source electrode of the driving TFT T1.

[0098] The gate electrode of the compensation TFT T3 can be connected to the first scan line SLn. The source electrode of the compensation TFT T3 can be connected to the drain electrode of the driving TFT T1, and can be connected to the pixel electrode of the organic light-emitting device OLED via the second emission control TFT T6. The drain electrode of the compensation TFT T3 can be connected to one electrode of the storage capacitor Cst, the source electrode of the first initialization TFT T4, and the gate electrode of the driving TFT T1. The compensation TFT T3 can be turned on according to the first scan signal Sn received through the first scan line SLn, and can be diode-connected to the driving TFT T1 by connecting the gate electrode and the drain electrode of the driving TFT T1.

[0099] The gate electrode of the first initialization TFT T4 can be connected to the second scan line SLn-1 (e.g., the previous scan line). The drain electrode of the first initialization TFT T4 can be connected to the initialization voltage line VL. The source electrode of the first initialization TFT T4 can be connected to one electrode of the storage capacitor Cst, the drain electrode of the compensation TFT T3, and the gate electrode of the driving TFT T1. The first initialization TFT T4 can be turned on according to the second scan signal Sn-1 received through the second scan line SLn-1, and the initialization operation of the voltage initialization of the gate electrode of the driving TFT T1 can be performed by supplying the initialization voltage VINT to the gate electrode of the driving TFT T1.

[0100] The gate electrode of the first emission control TFT T5 can be connected to the emission control line EL. The source electrode of the first emission control TFT T5 can be connected to the drive voltage line PL. The drain electrode of the first emission control TFT T5 can be connected to the source electrode of the driving TFT T1 and the drain electrode of the switching TFT T2.

[0101] The gate electrode of the second emission control TFT T6 can be connected to the emission control line EL. The source electrode of the second emission control TFT T6 can be connected to the drain electrode of the driving TFT T1 and the source electrode of the compensation TFT T3. The drain electrode of the second emission control TFT T6 can be electrically connected to the pixel electrode of the organic light-emitting device (OLED). The first emission control TFT T5 and the second emission control TFT T6 can be turned on according to the emission control signal En received through the emission control line EL. A first power supply voltage ELVDD can be applied to the organic light-emitting device (OLED), and a driving current can flow through the organic light-emitting device (OLED).

[0102] The gate electrode of the second initialization TFT T7 can be connected to the second scan line SLn-1. The source electrode of the second initialization TFT T7 can be connected to the pixel electrode of the organic light-emitting device (OLED). The drain electrode of the second initialization TFT T7 can be connected to the initialization voltage line VL. The second initialization TFT T7 can be turned on according to the second scan signal Sn-1 received through the second scan line SLn-1, and can initialize the pixel electrode of the organic light-emitting device (OLED).

[0103] Despite Figure 2B The first initialization TFT T4 and the second initialization TFT T7 can be connected to the second scan line SLn-1, but this disclosure is not limited thereto. In an embodiment, the first initialization TFT T4 can be connected to the second scan line SLn-1, i.e., the previous scan line, and can be driven according to the second scan signal Sn-1. The second initialization TFT T7 can be connected to a separate signal line (e.g., the next scan line) and can be driven according to the signal passed to the next scan line.

[0104] One electrode of the storage capacitor Cst can be connected to the drive voltage line PL. The other electrode of the storage capacitor Cst can be connected to the gate electrode of the driving TFT T1, the drain electrode of the compensation TFT T3, and the source electrode of the first initialization TFT T4.

[0105] The counter electrode (e.g., cathode) of an organic light-emitting device (OLED) can receive a second power supply voltage ELVSS (or a common power supply voltage). The OLED can receive a driving current from a driving TFT T1 and emit light.

[0106] The number of TFTs and storage capacitors, as well as the circuit design of the pixel circuit PC, are not limited to... Figure 2A and Figure 2B Those as explained herein, and may be modified in various ways within the spirit and scope of this disclosure.

[0107] refer to Figure 3 and Figure 4 This will be described in more detail. Figure 1 Part III and Figure 2A and Figure 2B Each pixel P has a pixel circuit PC consisting of a driving TFT T1, a switching TFT T2, and a storage capacitor Cst.

[0108] refer to Figure 3 Pixel P can be placed or set in Figure 1 In part III, pixel P may be surrounded by pixel defining film 113, and one or more spacers 115 may be placed or disposed on pixel defining film 113.

[0109] Despite Figure 3 The image describes pixel P as a quadrilateral shape with the same or similar dimensions, but this is just an example. Pixel P can have different dimensions and different shapes.

[0110] Spacers 115 (or multiple spacers 115) may be placed or disposed between some pixels P of a plurality of pixels P (or a predetermined number of pixels P). In the process of depositing intermediate layer 320 by using a mask, spacers 115 can prevent intermediate layer 320 from being damaged or scratched by the mask by maintaining a gap between the mask and the substrate 100.

[0111] Spacer 115 may comprise the same or similar material as the pixel defining film 113. Spacer 115 and pixel defining film 113 may comprise the same or similar material. When pixel defining film 113 can be formed using a halftone mask, spacer 115 may be formed to have a height different from that of pixel defining film 113.

[0112] refer to Figure 4The buffer layer 101 can be placed or disposed on the substrate 100, and the driving TFT T1, the switching TFT T2 and the storage capacitor Cst can be placed or disposed on the buffer layer 101.

[0113] The substrate 100 can be formed from any of various materials, such as glass, metal, or plastic. For example, the substrate 100 can be a flexible substrate including polymer resins such as polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), or cellulose acetate propionate (CAP).

[0114] Buffer layer 101 may be made of silicon oxide (SiO2) x ) and / or silicon nitride (SiN) x This is formed to prevent the penetration of impurities that may be provided or introduced onto the substrate 100.

[0115] The driving TFT T1 may include a driving semiconductor layer A1 and a driving gate electrode G1, and the switching TFT T2 may include a switching semiconductor layer A2 and a switching gate electrode G2. A first gate insulating layer 103 may be placed or disposed between the driving semiconductor layer A1 and the driving gate electrode G1, and between the switching semiconductor layer A2 and the switching gate electrode G2. The first gate insulating layer 103 may include an inorganic insulating material, such as SiO2. x SiN x Or silicon oxynitride (SiON).

[0116] Each of the driving semiconductor layer A1 and the switching semiconductor layer A2 may comprise amorphous silicon or polycrystalline silicon. In an embodiment, each of the driving semiconductor layer A1 and the switching semiconductor layer A2 may comprise at least one oxide, said at least one element selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn).

[0117] The driving semiconductor layer A1 may overlap with the driving gate electrode G1, and may include a driving channel region without impurities, and driving source regions and driving drain regions that are placed or disposed on two sides (or opposite sides) of the driving channel region and are doped with impurities. The driving source electrode S1 and the driving drain electrode D1 may be connected to the driving source region and the driving drain region, respectively.

[0118] The switching semiconductor layer A2 may overlap with the switching gate electrode G2, and may include a switch channel region without impurities, and a switch source region and a switch drain region that are doped and disposed on two sides (or opposite sides) of the switch channel region. The switch source electrode S2 and the switch drain electrode D2 may be connected to the switch source region and the switch drain region, respectively.

[0119] Each of the driving gate electrode G1 and the switching gate electrode G2 may include molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may have a single-layer structure or a multi-layer structure.

[0120] In one embodiment, the storage capacitor Cst may overlap with the driving TFT T1. In this case, the area of ​​each of the storage capacitor Cst and the driving TFT T1 can be increased, and a high-quality image can be provided or achieved. For example, the driving gate electrode G1 may be a first storage capacitor plate CE1 of the storage capacitor Cst. A second storage capacitor plate CE2 may overlap with the first storage capacitor plate CE1, and a second gate insulating layer 105 is placed between the second storage capacitor plate CE2 and the first storage capacitor plate CE1. The second gate insulating layer 105 may comprise an inorganic insulating material, such as SiO2. x SiN x Or SiON.

[0121] A portion of the driving TFT T1, the switching TFT T2, and the storage capacitor Cst may be covered by the interlayer insulating layer 107.

[0122] Interlayer insulation layer 107 can be made of SiON, SiO x and / or SiN x An inorganic layer is formed.

[0123] The data line DL can be placed or disposed on the interlayer insulating layer 107, and can be connected to the switching semiconductor layer A2 of the switching TFT T2 through contact holes formed in the interlayer insulating layer 107. The data line DL can function as the switching source electrode S2.

[0124] The driving source electrode S1, driving drain electrode D1, switching source electrode S2, and switching drain electrode D2 can be placed or disposed on the interlayer insulating layer 107, and can be connected to the driving semiconductor layer A1 or the switching semiconductor layer A2 through contact holes formed in the interlayer insulating layer 107.

[0125] Although not explicitly stated, the data line DL, drive source electrode S1, drive drain electrode D1, switch source electrode S2, and switch drain electrode D2 can be covered by an inorganic protective layer.

[0126] Inorganic protective layers may include SiN x and SiO xThe structure can be a single layer or a multi-layer structure. The inorganic protective layer prevents some exposed wiring in the non-display area NDA (e.g., wiring formed in the same process as the data line DL) from being damaged by the etchant used during the patterning of the pixel electrode 310.

[0127] The driving voltage line PL and the data line DL can be placed or disposed on different layers. When "A and B are placed or disposed on different layers", it means that at least one insulating layer can be placed or disposed between A and B, such that one of A and B can be placed or disposed below or below at least one insulating layer, and the other can be placed or disposed above or above at least one insulating layer. The first planarization film 109 can be placed or disposed between the driving voltage line PL and the data line DL, and the driving voltage line PL can be covered by the second planarization film 111.

[0128] The driving voltage line PL may have a single-layer or multi-layer structure comprising at least one of Al, Cu, Ti, or alloys thereof. In an embodiment, the driving voltage line PL may have a three-layer structure comprising Ti / Al / Ti.

[0129] Despite Figure 4 In this embodiment, the driving voltage line PL can be placed or disposed on the first planarization film 109, but this disclosure is not limited thereto. In an embodiment, the driving voltage line PL can be connected to a lower additional voltage line (not shown) formed on the same layer as the data line DL through a through-hole (not shown) formed in the first planarization film 109, in order to reduce resistance.

[0130] Each of the first planarization film 109 and the second planarization film 111 may have a single-layer structure or a multi-layer structure.

[0131] Each of the first planarization film 109 and the second planarization film 111 may include an organic insulating material. For example, the organic insulating material may include organic insulating materials such as general polymers (e.g., polymethyl methacrylate (PMMA) or polystyrene (PS)), polymer derivatives having phenolic groups, acrylic polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, or vinyl alcohol polymers.

[0132] Furthermore, each of the first planarization film 109 and the second planarization film 111 may include an inorganic insulating material. For example, the inorganic insulating material may include SiON, SiO. x or SiN x .

[0133] An organic light-emitting device (OLED) including a pixel electrode 310, a counter electrode 330, and an intermediate layer 320 placed or disposed between the pixel electrode 310 and the counter electrode 330, and including an emission layer, can be placed or disposed on a second planarization film 111.

[0134] The pixel electrode 310 can be connected to the connection wiring CL formed on the first planarization film 109, and the connection wiring CL can be connected to the driving drain electrode D1 of the driving TFT T1.

[0135] The pixel electrode 310 can be a transparent electrode or a reflective electrode.

[0136] When the pixel electrode 310 is a transparent electrode, the pixel electrode 310 may include a transparent conductive layer. The transparent conductive layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). In addition to the transparent conductive layer, the pixel electrode 310 may also include a semi-transparent layer for improving light efficiency, and the semi-transparent layer may include at least one selected from the group consisting of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), and ytterbium (Yb), and may be formed as a film with a thickness in the range of about a few micrometers to tens of micrometers (μm).

[0137] When the pixel electrode 310 is a reflective electrode, the pixel electrode 310 may include a reflective film formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr or compounds thereof, and a transparent conductive layer that may be placed or disposed above or above and / or below or beneath the reflective film. The transparent conductive layer may include at least one selected from the group consisting of ITO, IZO, ZnO, In2O3, IGO and AZO.

[0138] This disclosure is not limited thereto, and various modifications are possible. For example, the pixel electrode 310 may be formed of any of a variety of materials and may have a single-layer or multi-layer structure.

[0139] The pixel limiting film 113 can be placed or disposed on the pixel electrode 310.

[0140] The pixel defining film 113 may have an opening through which the pixel electrode 310 can be exposed, and the pixel defining film 113 may define the pixel P. The pixel defining film 113 may prevent arcing at the edge portion of the pixel electrode 310 by increasing the distance between the edge of the pixel electrode 310 and the counter electrode 330. The pixel defining film 113 may be formed of an organic material, such as PI or hexamethyldisiloxane (HMDSO).

[0141] The intermediate layer 320 may include low molecular weight materials or high molecular weight materials.

[0142] When the intermediate layer 320 comprises a low molecular weight material, it may have a single or stacked structure comprising a hole injection layer, a hole transport layer, an emission layer, an electron transport layer, and an electron injection layer. The intermediate layer 320 may comprise any of various organic materials, such as copper phthalocyanine (CuPc), N,N'-di(naphthyl-1-yl)-N,N'-diphenylbenzidine (NPB), or aluminum tri-8-hydroxyquinoline (Alq3). For example, the intermediate layer 320 may be formed using any of various methods, such as vapor deposition.

[0143] When the intermediate layer 320 comprises a high molecular weight material, the intermediate layer 320 may have a structure including a hole transport layer and an emitter layer. For example, the hole transport layer may comprise poly(3,4-ethylenedioxythiophene) (PEDOT), and the emitter layer may comprise a high molecular weight material, such as poly(p-phenyleneacetylene) (PPV) or polyfluorene. For example, the intermediate layer 320 may be formed using any of various methods, such as screen printing, inkjet printing, or laser-induced thermal imaging.

[0144] The intermediate layer 320 may be integrally formed on the pixel electrode 310, or it may be formed as a layer patterned to correspond to each of the pixel electrodes 310.

[0145] The counter electrode 330 can be placed or disposed on the display area DA to cover the display area DA. For example, the counter electrode 330 can be integrally formed on the organic light-emitting device OLED and can correspond to the pixel electrode 310. The counter electrode 330 can be electrically connected to the second power supply voltage line 20.

[0146] The counter electrode 330 may be a transparent electrode or a reflective electrode. When the counter electrode 330 is a transparent electrode, it may include at least one material selected from Ag, Al, Mg, Li, Ca, Cu, LiF / Ca, LiF / Al, MgAg and CaAg, and may be formed as a thin film with a thickness in the range of about a few micrometers to tens of micrometers (μm).

[0147] When the counter electrode 330 is a reflective electrode, the counter electrode 330 may be formed of at least one material selected from the group consisting of Ag, Al, Mg, Li, Ca, Cu, LiF / Ca, LiF / Al, MgAg, and CaAg. However, the construction or structure and material of the counter electrode 330 are not limited thereto, and various modifications may be made within the spirit and scope of this disclosure.

[0148] The spacer 115 may be placed or disposed on the pixel defining film 113. The spacer 115 may protrude from the pixel defining film 113 to the thin film encapsulation layer 400, and in a process of depositing an intermediate layer 320 including an emission layer using a mask, the intermediate layer 320 may be prevented from being damaged or scratched by the mask by maintaining a gap between the mask and the substrate 100.

[0149] The spacer 115 may be formed of an organic material, such as PI or HMDSO. The spacer 115 may be placed or disposed on at least one of the first to third baffle portions 110, 120 and 130, and may be used to prevent moisture penetration and to form a stepped portion of the baffle portion.

[0150] Because OLEDs are easily damaged by external moisture or oxygen, they can be covered and protected by a thin-film encapsulation layer 400.

[0151] The thin-film encapsulation layer 400 may cover the display area DA and may extend to the outside of the display area DA. The thin-film encapsulation layer 400 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. In an embodiment, the thin-film encapsulation layer 400 may include a first inorganic encapsulation layer 410, an organic encapsulation layer 420, and a second inorganic encapsulation layer 430.

[0152] The first inorganic encapsulation layer 410 may cover (or completely cover) the counter electrode 330, and may include SiO2. x SiN x And / or SiON.

[0153] For example, other layers, such as a capping layer (not shown), may be placed or disposed between the first inorganic encapsulation layer 410 and the counter electrode 330. For instance, to improve optical efficiency, the capping layer may include SiO2 or SiN. x The end-capping layer comprises at least one organic or inorganic material selected from zinc oxide (ZnO2), titanium oxide (TiO2), zirconium oxide (ZrO2), ITO, IZO, Alq3, CuPc, 4,4'-bis(N-carbazolyl)-1,1'-biphenyl (CBP), and NPB. In an embodiment, the end-capping layer can induce plasmon resonance for the light generated by the organic light-emitting device (OLED). For example, the end-capping layer may comprise nanoparticles. The end-capping layer prevents damage to the OLED from heat or plasma generated during the sputtering or chemical vapor deposition process used to form the thin-film encapsulation layer 400. For example, the end-capping layer may comprise an epoxy resin material, including at least one selected from bisphenol-type epoxy resin, epoxidized butadiene resin, fluorinated epoxy resin, and phenolic epoxy resin.

[0154] As an example, a layer including LiF (not shown) may be placed or disposed between the first inorganic encapsulation layer 410 and the end capping layer.

[0155] Because the first inorganic encapsulation layer 410 can be formed along a lower structure that may have various layers or be uneven, for example, as Figure 4 and Figure 5 As explained in the text, the top surface of the first inorganic encapsulation layer 410 may be non-flat. An organic encapsulation layer 420 may cover the first inorganic encapsulation layer 410. The organic encapsulation layer 420 may have a flat top surface. The organic encapsulation layer 420 may be formed such that the portion corresponding to the display area DA may have a top surface.

[0156] The organic encapsulation layer 420 may include PET, PEN, PC, PI, polyethylene sulfonate, polyoxymethylene, polyarylate, HMDSO, acrylic resin (e.g., PMMA or polyacrylic acid) or combinations thereof.

[0157] The second inorganic encapsulation layer 430 may cover the organic encapsulation layer 420 and may include SiO2. x SiN x And / or SiON. The second inorganic encapsulation layer 430 may be deposited on the edge portion of the display device 1 to contact (or directly contact) the first inorganic encapsulation layer 410, thereby preventing the organic encapsulation layer 420 from being exposed to the outside of the display device 1.

[0158] refer to Figure 5 The left view illustrates the structure of pixel P, and the right view shows the structure along... Figure 1 A schematic cross-sectional view of the line VA-VB.

[0159] exist Figure 5 In the right view, the buffer layer 101, the first gate insulating layer 103, the second gate insulating layer 105, the interlayer insulating layer 107, and the first planarization film 109 extending in the display area DA can be placed or disposed on the substrate 100. The star-shaped wiring SPL can be placed or disposed between the second gate insulating layer 105 and the interlayer insulating layer 107. The first conductive layer 10a and the third conductive layer 20a can be placed or disposed on the interlayer insulating layer 107, and the second conductive layer 10b and the fourth conductive layer 20b can be placed or disposed on the first planarization film 109.

[0160] The first conductive layer 10a and the second conductive layer 10b can be connected to each other through the first contact hole CNT1 formed in the first planarization film 109, and can be configured to transmit the first power supply voltage ELVDD (see Figure 2A and Figure 2B A first power supply voltage line 10 is supplied to each pixel P. Because the first power supply voltage line 10 can be formed with a two-layer structure, the width of the first power supply voltage line 10 can be reduced and the dead space can be reduced. Although in Figure 5 The example may illustrate two first contact holes CNT1, but this is only an example, and the number of first contact holes CNT1 may be one, three or more.

[0161] The third conductive layer 20a and the fourth conductive layer 20b can be connected to each other through the second contact hole CNT2 formed in the first planarization film 109, and can be configured to transmit the second power supply voltage ELVSS (see Figure 2A and Figure 2B A second power supply voltage line 20 is supplied to each pixel P. Because the second power supply voltage line 20 can be formed with a two-layer structure, the width of the second power supply voltage line 20 can be reduced and the dead space can be reduced. Although in Figure 5 The example may illustrate two second contact holes CNT2, but this is only an example, and the number of second contact holes CNT2 may be one, three or more.

[0162] The first conductive layer 10a and the third conductive layer 20a may be formed of the same or similar material as the data line DL. The first conductive layer 10a, the third conductive layer 20a, and the data line DL may include the same or similar materials. The second conductive layer 10b and the fourth conductive layer 20b may be formed of the same or similar material as the drive voltage line PL. The second conductive layer 10b, the fourth conductive layer 20b, and the drive voltage line PL may include the same or similar materials.

[0163] The second planarization film 111 may be placed or disposed on the second conductive layer 10b, and the pixel defining film 113 may be placed or disposed on the second planarization film 111 to overlap with the first power supply voltage line 10. The counter electrode 330 extending in the display area DA may be placed or disposed on the pixel defining film 113.

[0164] The third baffle portion 130, the first baffle portion 110, and the second baffle portion 120, which extend to the end portion of the substrate 100 in the display area DA, can be placed or disposed sequentially to overlap with the second power supply voltage line 20.

[0165] The third baffle portion 130 may include a first layer 111c formed of a material that is the same as or similar to the material of the second planarization film 111, and a second layer 113c formed of a material that is the same as or similar to the material of the pixel defining film 113. The first layer 111c and the second planarization film 111 may include the same or similar materials. The second layer 113c and the pixel defining film 113 may include the same or similar materials. The second layer 113c of the third baffle portion 130 may cover the top surface and one or more side surfaces of the first layer 111c, and may ensure process margin during the patterning of the second layer 113c in the photolithography process, thereby stably ensuring the height of the second layer 113c.

[0166] A portion of the third baffle portion 130 may overlap with a portion of the counter electrode 330 extending in the display area DA. Because the end portion of the counter electrode 330 extends to the second power supply voltage line 20, noise that could affect the wiring of the touch sensing layer (not shown) formed on the thin film encapsulation layer 400 can be avoided.

[0167] The first baffle portion 110 may include a first layer 111a formed of a material that is the same as or similar to the material of the second planarization film 111, or may include a portion of the second planarization film 111. It may also include a second layer 113a formed of a material that is the same as or similar to the material of the pixel defining film 113, or may include a portion of the pixel defining film 113. The first layer 111a and the second planarization film 111 may include the same or similar materials. The second layer 113a and the pixel defining film 113 may include the same or similar materials. The second layer 113a of the first baffle portion 110 may cover the top surface and one or more side surfaces of the first layer 111a, and during the patterning of the second layer 113a in the photolithography process, process margins may be ensured, thereby stably ensuring the height of the second layer 113a.

[0168] The second baffle portion 120 may include a first layer 111b formed of a material that is the same as or similar to the material of the second planarization film 111, a second layer 113b formed of a material that is the same as or similar to the material of the pixel defining film 113, and a third layer 115b formed of a material that is the same as or similar to the material of the spacer 115. The first layer 111b and the second planarization film 111 may include the same or similar materials. The second layer 113b and the pixel defining film 113 may include the same or similar materials. The third layer 115b and the spacer 115 may include the same or similar materials. The second layer 113b of the second baffle portion 120 may cover the top surface and one or more side surfaces of the first layer 111b, and may ensure process margin during the patterning of the second layer 113b in the photolithography process, thereby stably ensuring the height of the second layer 113b.

[0169] Despite Figure 5 In the second baffle portion 120, the third layer 115b may cover the top surface and side surfaces or multiple side surfaces of the second layer 113b, but this disclosure is not limited thereto. Because the second layer 113b and the third layer 115b of the second baffle portion 120 can be formed using a process utilizing the same mask, the second layer 113b and the third layer 115b can be formed such that the width of the top surface of the second layer 113b and the width of the bottom surface of the third layer 115b can be substantially the same.

[0170] Because the second baffle portion 120, the first baffle portion 110, and the third baffle portion 130 can be configured such that the height of the second baffle portion 120 is greater than the height of each of the first baffle portion 110 and the third baffle portion 130, the organic material of the organic encapsulation layer 420 can be prevented from flowing across the second baffle portion 120 and forming an edge tail. Because the gap between the mask and the substrate 100 can be maintained during the process of depositing the intermediate layer 320 using a mask, the intermediate layer 320 can be prevented from being damaged or scratched by the mask.

[0171] In an embodiment, the width W2 of the second power supply voltage line 20 may be greater than the width W1 of the first power supply voltage line 10 to reduce voltage drop, and the third baffle portion 130, the first baffle portion 110 and the second baffle portion 120 may be stably placed or configured to overlap with the second power supply voltage line 20.

[0172] The first layer 111b of the second baffle portion 120 may cover the end portion or the third end portion ES0 of the fourth conductive layer 20b and may prevent damage to the fourth conductive layer 20b during wet etching of the second planarization film 111. In the schematic cross-sectional view, the end portion or the third end portion ES0 of the fourth conductive layer 20b may be in a direction that extends with the first baffle portion 110 and the second baffle portion 120 (second direction, see...). Figure 1 It extends in a basically parallel direction (the second direction).

[0173] The first layer 111c of the third baffle portion 130, the first layer 111a of the first baffle portion 110, and the first layer 111b of the second baffle portion 120 can be connected to each other without being separated by the connecting layer 111d. For example, the top surface of the fourth conductive layer 20b can be covered (or completely covered) by the connecting layer 111d. Each of the first layer 111c of the third baffle portion 130, the first layer 111a of the first baffle portion 110, the first layer 111b of the second baffle portion 120, and the connecting layer 111d can be formed of the same or similar material as the material of the second planarization film 111. The connecting layer 111d and the second planarization film 111 can include the same or similar materials.

[0174] Figure 6 To explain Figure 1 A magnified plan view of part of AR1, Figure 7A For along Figure 6 A schematic cross-sectional view taken from lines VIIA-VIIB, and Figure 7B For along Figure 6 The cross-sectional view taken from line VIIA'-VIIB'. For ease of explanation, in Figure 6 The thin-film encapsulation layer 400 is not shown in the plan view.

[0175] refer to Figure 6 , Figure 7A and Figure 7B The fourth conductive layer 20b of the second power supply voltage line 20 may be placed or disposed on the first planarization film 109, and the connecting layer 111d, which may be formed of the same or similar material as the second planarization film 111, may be placed or disposed on the fourth conductive layer 20b.

[0176] The connecting layer 111d can be formed to have a height smaller than that of the second planarization film 111. When the pattern of the second planarization film 111 can be formed using a halftone mask, the connecting layer 111d can be formed to have a height smaller than that of the second planarization film 111 by etching more portions of the second planarization film 111 corresponding to the connecting layer 111d.

[0177] refer to Figure 6 and Figure 7A At the second connection line 22 of the second power supply voltage line 20 placed or disposed outside the second baffle portion 120, the top surface TS and the first end portion ES1 and the second end portion ES2, which may be the two end portions of the fourth conductive layer 20b, can both be covered by the connecting layer 111d, and the connecting layer 111d can be covered by the first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430. Outside the first end portion ES1 and the second end portion ES2 of the fourth conductive layer 20b, the second planarization film 111 and the connecting layer 111d may be in contact with each other or may be in direct contact with each other, the connecting layer 111d and the first inorganic encapsulation layer 410 may be in contact with each other or may be in direct contact with each other, and the first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430 may be in contact with each other or may be in direct contact with each other.

[0178] In the plan view, the first end portion ES1 and the second end portion ES2 of the fourth conductive layer 20b can extend in the same direction as the first baffle portion 110 and the second baffle portion 120 (second direction, see...). Figure 1 Extend in the direction of intersection (first direction).

[0179] The fourth conductive layer 20b may be formed of the same or similar material as the driving voltage line PL. The fourth conductive layer 20b and the driving voltage line PL may comprise the same or similar materials. In embodiments, the fourth conductive layer 20b may have a single-layer or multi-layer structure comprising at least one of Al, Cu, Ti, or alloys thereof. For example, the fourth conductive layer 20b may be formed by stacking a first layer 20b1 comprising Ti, a second layer 20b2 comprising Al, and a third layer 20b3 comprising Ti.

[0180] The pattern of the fourth conductive layer 20b can be formed using dry etching, and the pattern of the second planarization film 111 can be formed using wet etching. When the second layer 20b2 comprises Al and the first layer 20b1 and the third layer 20b3 comprise Ti, undercutting may not be formed in the first end portion ES1 and the second end portion ES2 of the fourth conductive layer 20b while the pattern of the fourth conductive layer 20b can be formed using dry etching. However, while the pattern of the second planarization film 111 can be formed using wet etching, undercutting may be formed in the first end portion ES1 and the second end portion ES2 of the fourth conductive layer 20b exposed to the etchant due to the etching rate difference between the second layer 20b2 and the first layer 20b1 and the third layer 20b3. However, in this embodiment, because the top surface TS of the fourth conductive layer 20b and the first end portion ES1 and the second end portion ES2 can be covered by the connecting layer 111d and a portion of the remaining second planarization film 111, or can be completely covered by the connecting layer 111d and a portion of the remaining second planarization film 111, undercuts can be avoided in the first end portion ES1 and the second end portion ES2 of the fourth conductive layer 20b. Because undercuts can be avoided, the step coverage of the first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430 can be improved, and moisture penetration can be prevented.

[0181] refer to Figure 6 and Figure 7B At the second main voltage line 21 of the second power supply voltage line 20, between the first baffle portion 110 and the second baffle portion 120, the top surface TS and the second end portion ES2 of the fourth conductive layer 20b can be covered by the connecting layer 111d, and the connecting layer 111d can be covered by the first inorganic encapsulation layer 410, the organic encapsulation layer 420, and the second inorganic encapsulation layer 430. Outside the second end portion ES2 of the fourth conductive layer 20b, the second planarization film 111 and the connecting layer 111d can be in contact with each other or directly in contact with each other; the connecting layer 111d and the first inorganic encapsulation layer 410 can be in contact with each other or directly in contact with each other; the first inorganic encapsulation layer 410 and the organic encapsulation layer 420 can be in contact with each other or directly in contact with each other; and the organic encapsulation layer 420 and the second inorganic encapsulation layer 430 can be in contact with each other or directly in contact with each other.

[0182] and Figure 7ASimilarly, because the top surface TS and the second end portion ES2 of the fourth conductive layer 20b, which can be stacked and includes a first layer 20b1 of Ti, a second layer 20b2 of Al, and a third layer 20b3 of Ti, can be covered by the connecting layer 111d and a portion of the remaining second planarization film 111, or can be completely covered by the connecting layer 111d and a portion of the remaining second planarization film 111, an undercut can be avoided in the second end portion ES2 of the fourth conductive layer 20b while the pattern of the second planarization film 111 can be formed using wet etching. Because an undercut can be avoided, the step coverage of the first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430 can be improved, and moisture penetration can be prevented.

[0183] Figure 8 To illustrate the enlarged plan view of AR2 based on the comparative example, and Figure 9 For along Figure 8 A schematic cross-sectional view taken from line IXA-IXB. For ease of explanation, in... Figure 8 The thin-film encapsulation layer 400 is not shown in the plan view.

[0184] refer to Figure 8 and Figure 9 The connecting layer 111d may be formed of the same or similar material as the second planarization film 111. The connecting layer 111d and the second planarization film 111 may comprise the same or similar materials. The connecting layer 111d may not be formed on the fourth conductive layer 20b, and the first inorganic encapsulation layer 410 may be formed on or directly on the fourth conductive layer 20b. The second inorganic encapsulation layer 430 may be formed on or directly on the first inorganic encapsulation layer 410.

[0185] When a fourth conductive layer 20b, in which a first layer 20b1 comprising Ti, a second layer 20b2 comprising Al, and a third layer 20b3 comprising Ti can be stacked, while the pattern of the second planarization film 111 can be formed by wet etching, due to the difference in etching rates between the second layer 20b2 and the first layer 20b1 and the third layer 20b3, undercuts can be formed in the first end portion ES1 and the second end portion ES2, which are both end portions of the fourth conductive layer 20b exposed to the etchant. When the first inorganic encapsulation layer 410 is formed in a state where undercuts can be formed, cavities 410a can be formed between the first end portion ES1 and the second end portion ES2 of the fourth conductive layer 20b and the first inorganic encapsulation layer 410, and cavities 430a can be formed between the two end portions of the first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430. Undercutting and cavities 410a and 430a can reduce the step coverage of the first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430, causing cracks, and the cracks can act as penetration paths, thereby reducing the reliability of the display device 1.

[0186] However, according to the implementation method, because Figure 7A The top surface TS of the fourth conductive layer 20b and the first end portion ES1 and the second end portion ES2 or Figure 7B The top surface TS and the second end portion ES2 of the fourth conductive layer 20b can be covered by the connecting layer 111d and a portion of the remaining second planarization film 111, or can be completely covered by the connecting layer 111d and a portion of the remaining second planarization film 111 to prevent undercutting. Therefore, the step coverage of the first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430 can be improved, and moisture penetration can be prevented. The connecting layer 111d covering the top surface TS of the fourth conductive layer 20b and the first end portion ES1 and / or the second end portion ES2 can be a covering layer.

[0187] Reference Figures 10 to 12B Describe the implementation method. Figure 10 This is a schematic cross-sectional view of the display device 2 according to the embodiment. Figure 11 To illustrate some of the enlarged planar views of AR3, Figure 12A For along Figure 11 A schematic cross-sectional view of the line XIIA-XIIB, and Figure 12B For along Figure 11 A schematic cross-sectional view taken from line XIIA'-XIIB'. For ease of explanation, in... Figure 11 The thin-film encapsulation layer 400 is not shown in the plan view. The following description will focus on the differences from the embodiment described above.

[0188] refer to Figure 10 The left view illustrates the structure of pixel P, and the right view shows the structure along... Figure 1 A schematic cross-sectional view of the line VA-VB.

[0189] exist Figure 10 In the right view, the buffer layer 101, the first gate insulating layer 103, the second gate insulating layer 105, the interlayer insulating layer 107, and the first planarization film 109 extending in the display area DA can be placed or disposed on the substrate 100. The star-shaped wiring SPL can be placed or disposed between the second gate insulating layer 105 and the interlayer insulating layer 107, the first conductive layer 10a and the third conductive layer 20a can be placed or disposed on the interlayer insulating layer 107, and the second conductive layer 10b and the fourth conductive layer 20b can be placed or disposed on the first planarization film 109.

[0190] The first conductive layer 10a and the second conductive layer 10b can be connected to each other through the first contact hole CNT1 formed in the first planarization film 109, and can be configured to transmit the first power supply voltage ELVDD (see Figure 2A and Figure 2BThe first power supply voltage line 10 is supplied to each pixel P. The third conductive layer 20a and the fourth conductive layer 20b can be connected to each other through the second contact hole CNT2 formed in the first planarization film 109, and can be configured to supply the second power supply voltage ELVSS (see Figure 2A and Figure 2B The second power supply voltage line 20 is supplied to each pixel P.

[0191] The second planarization film 111 may be placed or disposed on the second conductive layer 10b, and the pixel defining film 113 may be placed or disposed on the second planarization film 111 to overlap with the first power supply voltage line 10. The counter electrode 330 extending in the display area DA may be placed or disposed on the pixel defining film 113.

[0192] A third baffle portion 130, a first baffle portion 110, and a second baffle portion 120 extending to the end portion of the substrate 100 in the display area DA can be sequentially placed or disposed to overlap with the second power supply voltage line 20. The third baffle portion 130 may include a first layer 111c formed of a material that is the same as or similar to the material of the second planarization film 111, and a second layer 113c formed of a material that is the same as or similar to the material of the pixel defining film 113. The first layer 111c and the second planarization film 111 may include the same as or similar to the material of the second planarization film 111. The first baffle portion 110 may include a first layer 111a formed of a material that is the same as or similar to the material of the second planarization film 111, and a second layer 113a formed of a material that is the same as or similar to the material of the pixel defining film 113. The second baffle portion 120 may include a first layer 111b formed of a material that is the same as or similar to the material of the second planarization film 111, a second layer 113b formed of a material that is the same as or similar to the material of the pixel defining film 113, and a third layer 115b formed of a material that is the same as or similar to the material of the spacer 115. The third layer 115b and the spacer 115 may include the same or similar materials.

[0193] and Figure 5 Unlike other embodiments, the first layer 111c of the third baffle portion 130, the first layer 111a of the first baffle portion 110, and the first layer 111b of the second baffle portion 120 can be separated from each other. That is, the connecting layer 111d may not be formed on a portion of the fourth conductive layer 20b on which the first baffle portions may not be placed or disposed to each of the third baffle portions 110, 120, and 130. However, referring to... Figure 11 , Figure 12A and Figure 12B The first end portion ES1 and the second end portion ES2 of the fourth conductive layer 20b can be covered by the connecting layer 111d.

[0194] refer to Figure 11 and Figure 12A The fourth conductive layer 20b of the second power supply voltage line 20 can be placed or disposed on the first planarization film 109, and outside the second baffle portion 120, the first end portion ES1 and the second end portion ES2 of the fourth conductive layer 20b can be covered by a connecting layer 111d formed of a material that is the same as or similar to the material of the second planarization film 111. Because the first end portion ES1 and the second end portion ES2 of the fourth conductive layer 20b, which can be undercut while the pattern of the second planarization film 111 is formed by wet etching, can be covered by the connecting layer 111d, the formation of undercuts in the first end portion ES1 and the second end portion ES2 of the fourth conductive layer 20b can be prevented. The step coverage of the first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430 can be improved. In this case, the top surface TS of the fourth conductive layer 20b, which may not be undercut, may not be covered by the connecting layer 111d.

[0195] refer to Figure 11 and Figure 12B The fourth conductive layer 20b of the second power supply voltage line 20 can be placed or disposed on the first planarization film 109, and between the first baffle portion 110 and the second baffle portion 120, the second end portion ES2 of the fourth conductive layer 20b can be covered by a connecting layer 111d formed of a material that is the same as or similar to the material of the second planarization film 111. Because the second end portion ES2 of the fourth conductive layer 20b, which can be undercut while the pattern of the second planarization film 111 is formed by using wet etching, can be covered by the connecting layer 111d, the formation of undercut in the second end portion ES2 of the fourth conductive layer 20b can be prevented. Therefore, the step coverage of the first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430 can be improved. The top surface TS of the fourth conductive layer 20b, which may not be undercut, may not be covered by the connecting layer 111d.

[0196] Reference Figure 13 Describe the implementation method. Figure 13 This is a schematic cross-sectional view of the display device 3 according to an embodiment. The following description will focus on the differences from the display device 1.

[0197] refer to Figure 13 The left view illustrates Figure 4 The structure of pixel P, and the right view is along Figure 1 A schematic cross-sectional view of the line VA-VB.

[0198] exist Figure 13In the right view, unlike display device 1 where the star wiring SPL can be placed or disposed between the second gate insulating layer 105 and the interlayer insulating layer 107, in this embodiment, the star wiring SPL can be placed or disposed between the first gate insulating layer 103 and the second gate insulating layer 105. The star wiring SPL can extend from the drive circuit unit (not shown) to the terminal unit 30 (see...). Figure 1 ), and they can be separated from each other.

[0199] According to the implementation, because the design freedom of the star wiring SPL can be increased, and unlike the display device 1, the thickness of the insulating layer between the star wiring SPL and the first conductive layer 10a and the third conductive layer 20a can be increased, and the interference that may occur between the star wiring SPL and the first conductive layer 10a and the third conductive layer 20a can be reduced.

[0200] Reference Figure 14 and Figure 15 Description of embodiments of this disclosure. Figure 14 This is a plan view of the display device 4 according to the embodiment, and Figure 15 For along Figure 3 The lines IVA-IVB and Figure 14 The diagram below shows a schematic cross-sectional view of the display device 4 according to the embodiment, taken along lines XVA-XVB. The following description will focus on the differences from the display device 1.

[0201] refer to Figure 14 and Figure 15 In the non-display area NDA, the first baffle portion 110, the second baffle portion 120, and the third baffle portion 130 surrounding or around the display area DA can be separated from each other.

[0202] Unlike the display device 1 in which the third baffle portion 130, the first baffle portion 110, and the second baffle portion 120 can all overlap with the second power supply voltage line 20, in the display device 4 of the embodiment, the third baffle portion 130 can overlap with the first power supply voltage line 10, and the first baffle portion 110 and the second baffle portion 120 can overlap with the second power supply voltage line 20.

[0203] Similar to display device 1, the first layer 111a of the first baffle portion 110 and the first layer 111b of the second baffle portion 120 can be connected to each other via the connecting layer 111d, rather than being separated from each other. For example, the top surface of the fourth conductive layer 20b can be covered by the connecting layer 111d or can be completely covered by the connecting layer 111d.

[0204] although Figure 14 and Figure 15 Not shown in the image, but related to... Figure 7A and Figure 7BSimilarly, because the top surface TS of the fourth conductive layer 20b and the first end portion ES1 and the second end portion ES2, or the top surface TS of the fourth conductive layer 20b and the second end portion ES2, can be covered by the connecting layer 111d and a portion of the remaining second planarization film 111, or can be completely covered by the connecting layer 111d and a portion of the remaining second planarization film 111, undercutting in the first end portion ES1 and / or the second end portion ES2 of the fourth conductive layer 20b can be prevented, thereby improving the step coverage of the first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430 and preventing moisture penetration.

[0205] Because the third baffle portion 130 can overlap with the first power supply voltage line 10 in the embodiment, the design flexibility is increased. Since the third baffle portion 130 can be placed or configured to be closer to the display area DA, when an organic encapsulation layer 420 including organic materials, such as monomers, can be formed, the organic material can be prevented from flowing to the edge of the substrate 100.

[0206] Reference Figure 16 Describe the implementation method. Figure 16 This is a schematic cross-sectional view of the display device 5 according to an embodiment. The following description will focus on... Figure 15 The difference between display devices 4 and 4.

[0207] Similar to display device 4, in display device 5 of the embodiment, the third baffle portion 130 may overlap with the first power supply voltage line 10, and the first baffle portion 110 and the second baffle portion 120 may overlap with the second power supply voltage line 20. However, in the embodiment, the number of third baffle portions 130 that may overlap with the first power supply voltage line 10 may be two. For example, the third baffle portion 130 includes a first portion 131 of the third baffle portion 130, which may be placed or configured closer to the display area DA, and a second portion 132 of the third baffle portion 130, which may be closer to the first baffle portion 110. The first portion 131 may include a first layer 111c1 and a second layer 113c1. The second portion 132 may include a first layer 111c2 and a second layer 113c2. However, this disclosure is not limited to this, and the number of third baffle portions 130 may be increased. When the number of third baffle portions 130 is increased, organic material can be more effectively prevented from flowing to the edge of the substrate 100.

[0208] In the implementation, since the width W1 of the first power supply voltage line 10 can be greater than the width W2 of the second power supply voltage line 20, the voltage drop can be reduced and the third baffle portion 130 can be stably placed or configured to overlap with the first power supply voltage line 10.

[0209] According to one or more embodiments, because the second power supply voltage line may include two conductive layers and the end portion of the upper conductive layer may be covered by a covering layer, undercutting in the upper conductive layer can be prevented. Cavities formed due to undercutting and cracks caused by reduced step coverage can be prevented. Due to the power supply voltage line with reduced voltage drop, a display device for providing high-quality images can be provided.

[0210] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and are not intended to be limiting. The description of features or aspects in each embodiment should generally be considered as other similar features or aspects that may be used in other embodiments. Although one or more embodiments have been described with reference to the figures, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

Claims

1. A display device, the display device comprising: substrate; A display area is disposed on the substrate and includes a plurality of pixels; A non-display area, wherein the non-display area is located outside the display area; A first power supply voltage line, the first power supply voltage line comprising: A first conductive layer is disposed in the non-display area; and A second conductive layer disposed on the first conductive layer; A second power supply voltage line, disposed in the non-display area, includes: A third conductive layer separated from the first conductive layer; and A fourth conductive layer is disposed on the third conductive layer; The first baffle portion surrounds the display area and overlaps with the second power supply voltage line; The second baffle portion is disposed adjacent to the first baffle portion; A covering layer that covers a first end portion of the fourth conductive layer, the first end portion of the fourth conductive layer being formed in a direction intersecting the extending directions of the first baffle portion and the second baffle portion; and A first planarization film is disposed between the third conductive layer and the fourth conductive layer, the third conductive layer and the fourth conductive layer being electrically connected to each other through a second contact hole formed in the first planarization film.

2. The display device according to claim 1, wherein, The first planarization film is disposed in the display area and the non-display area. The display device further includes: A second planarization film, wherein the second planarization film is disposed on the first planarization film; and A pixel defining film is disposed on the second planarization film, wherein... The first baffle portion includes: A first layer, the first layer comprising a portion of the second planarization film; and The second layer includes a portion of the pixel-defining film, and The second baffle portion includes: A first layer, the first layer comprising a portion of the second planarization film; and The second layer includes a portion of the pixel-defining film.

3. The display device according to claim 2, wherein, The coating layer and the second planarization film comprise the same material.

4. The display device according to claim 2, wherein, The first planarization film is further disposed between the first conductive layer and the second conductive layer, and The first conductive layer and the second conductive layer are electrically connected to each other through a first contact hole formed in the first planarization film.

5. The display device according to claim 2, further comprising: A third baffle portion, wherein the third baffle portion is disposed between the display area and the first baffle portion, the third baffle portion comprising: A first layer, the first layer comprising a portion of the second planarization film; and The second layer includes a portion of the pixel-defining film.

6. The display device according to claim 5, wherein, Each of the plurality of pixels includes: First electrode; An emission layer, wherein the emission layer is disposed on the first electrode; and The second electrode is disposed on the emission layer, wherein... The second electrode is disposed on the plurality of pixels, and The second electrode extends into the non-display area and covers a portion of the third baffle portion.

7. The display device according to claim 6, further comprising a spacer disposed on the pixel defining film, wherein, The pixel defining film is disposed on the second planarization film and covers the end portion of the first electrode. The second baffle portion further includes a third layer formed on the second layer including the portion of the pixel defining film, and The third layer of the second baffle portion and the spacer are made of the same material.

8. The display device according to claim 7, wherein, The height of the second baffle portion is greater than the height of each of the first baffle portion and the third baffle portion.

9. The display device according to claim 5, wherein, The first baffle portion, the second baffle portion, and the third baffle portion overlap with the second power supply voltage line.

10. The display device according to claim 5, wherein, The third baffle portion overlaps with the first power supply voltage line, and The first baffle portion and the second baffle portion overlap with the second power supply voltage line.

11. The display device according to claim 10, wherein, The third baffle portion includes: The first part is disposed adjacent to the display area; and The second part is disposed adjacent to the first baffle portion.

12. The display device according to claim 11, wherein, The width of the first power supply voltage line is greater than the width of the second power supply voltage line.

13. The display device according to claim 2, wherein, The second planarization film covers the third end portion of the fourth conductive layer, and the third end portion of the fourth conductive layer is formed in a direction parallel to the direction in which the first baffle portion and the second baffle portion extend.

14. The display device according to claim 1, wherein, The first conductive layer and the third conductive layer comprise the same material, and The second conductive layer and the fourth conductive layer comprise the same material.

15. The display device according to claim 1, wherein, Between the first baffle portion and the second baffle portion, the covering layer covers the top surface of the fourth conductive layer and the first end portion.

16. The display device according to claim 1, wherein, The fourth conductive layer further includes a second end portion, the second end portion facing the first end portion outside the second baffle portion, and, The covering layer covers the top surface of the fourth conductive layer outside the second baffle portion, as well as the first end portion and the second end portion.

17. The display device according to claim 1, wherein, Between the first baffle portion and the second baffle portion, the covering layer covers the first end portion of the fourth conductive layer, and Between the first baffle portion and the second baffle portion, the covering layer does not cover at least a portion of the top surface of the fourth conductive layer.

18. The display device according to claim 1, wherein, The fourth conductive layer further includes a second end portion, the second end portion facing the first end portion outside the second baffle portion. The covering layer covers the first end portion and the second end portion outside the second baffle portion, and The covering layer does not cover at least a portion of the top surface of the fourth conductive layer outside the second baffle portion.

19. The display device of claim 1, further comprising a plurality of star-shaped wirings between the substrate and the first conductive layer and the third conductive layer, the plurality of star-shaped wirings being spaced apart from each other in a direction intersecting the directions in which the first conductive layer and the third conductive layer extend.

20. The display device of claim 19, further comprising at least two insulating layers extending to the display area between the plurality of star-shaped wirings and the first conductive layer and the third conductive layer.

21. The display device according to claim 5, further comprising a thin-film encapsulation layer, the thin-film encapsulation layer comprising: A first inorganic encapsulation layer covers the display area; An organic encapsulation layer is disposed on the first inorganic encapsulation layer; as well as A second inorganic encapsulation layer is disposed on the organic encapsulation layer. The thin-film encapsulation layer covers the third baffle portion and the first baffle portion.

22. The display device according to claim 21, wherein, The first inorganic encapsulation layer and the second inorganic encapsulation layer are in contact with each other on the outer side of the second baffle portion.

23. A display device, the display device comprising: The display area includes a plurality of pixels; A non-display area, wherein the non-display area is located outside the display area; The first power supply voltage line is located outside the non-display area; The second power supply voltage line is separated from the first power supply voltage line; The first baffle portion surrounds the display area and overlaps with the second power supply voltage line; The second baffle portion is disposed adjacent to the first baffle portion; The third baffle portion is disposed between the display area and the first baffle portion; as well as An insulating layer that forms part of the first baffle portion and part of the second baffle portion. The insulating layer covers a first end portion and a third end portion of the second power supply voltage line. The first end portion of the second power supply voltage line is formed in a direction intersecting the direction extending from the first baffle portion to the third baffle portion, and the third end portion of the second power supply voltage line is formed in a direction parallel to the direction extending from the first baffle portion to the third baffle portion. The second power supply voltage line includes a conductive layer disposed therebetween with a first planarization film and electrically connected to each other through a second contact hole formed in the first planarization film.

24. The display device according to claim 23, wherein, Between the first end portion and the third end portion, the insulating layer further covers the top surface of the second power supply voltage line.

Images