Transistor with low leakage current and method for manufacturing the same

Abstract

The present invention discloses a transistor with low leakage current and a method for manufacturing the same. The transistor includes a substrate, a gate, multiple spacer layers, multiple liner dielectric layers, a source, and a drain. The gate has a first dielectric constant. The multiple spacer layers have a second dielectric constant. The multiple liner dielectric layers have a third dielectric constant. The source and the drain are adjacent to the multiple spacer layers and are arranged in opposite directions relative to the gate. The first dielectric constant, the second dielectric constant, and the third dielectric constant are different from each other. Therefore, compared with the prior art, the present invention can more effectively reduce gate-induced drain leakage current, short channel effect, off current, or junction leakage current.

Description

Technical Field

[0001] The present invention relates to a transistor and a manufacturing method thereof, and in particular to a transistor with low leakage current and a manufacturing method thereof. Background Art

[0002] Systems based on germanium (Ge) or silicon (Si) semiconductor technology are becoming increasingly smaller and requiring lower power consumption to meet a variety of applications. The most competitive existing technology that can meet these requirements is complementary metal oxide semiconductor (CMOS) fin field-effect transistor (FinFET) technology. However, in the existing technology, the biggest problem faced by FinFET technology is the so-called short-channel effect (SEC), which includes gate-induced drain leakage (GIDL), band-to-band (BTB) tunneling leakage current, and source / drain to substrate leakage current under high operating temperature environments. Traditional CMOS devices are mainly manufactured using bulk germanium or silicon substrates. When the gate length of CMOS devices is reduced to less than 30 to 40 nanometers, CMOS devices fabricated using bulk germanium or silicon substrates exhibit characteristics that are sensitive to manufacturing conditions. Furthermore, the performance of CMOS devices with a channel length of approximately 30 nanometers is clearly insufficient in high-performance circuits such as mobile computing or fifth-generation wireless systems (5G) network communications.

[0003] Because the spacers formed on both sides of the CMOS gate cannot be scaled down using conventional FinFET device technology, there is only a small margin to increase integration density by reducing the actual area occupied by a single device, at the risk of resulting in a tall and fragile fin-like active region.

[0004] Many studies have been published on the characteristics of traditional FinFET device structures, such as using Silicon On Insulator (SOI) substrates instead of bulk substrates. However, the parasitic resistance of the source / drain regions of the traditional FinFET device becomes very large due to the film thickness, so it is necessary to grow a substantially uniform selective epitaxial (SEG) layer in the source / drain region to reduce the parasitic resistance. Without new inventions, the characteristics of the traditional FinFET device structure will not be greatly improved as it is further reduced to achieve low Gate-Induced Drain Leakage (GIDL) and junction leakage current, thereby achieving the goal of reducing its size and improving its performance.

[0005] When the physical channel length of a complementary metal oxide semiconductor (CMOS) device is reduced to 20 nanometers, 10 nanometers, or even smaller, the problem of suppressing the short channel effect faced by the complementary metal oxide semiconductor device becomes more important and difficult than ever before.

[0006] Faced with these challenges, conventional FinFETs have become the current semiconductor process technology of choice due to their attractive device structure, channel charge controllability, and high drive current performance. Compared to silicon-on-insulator (SOI) FinFETs or other device structures, conventional metal-oxide-semiconductor (MOS) FETs (FinFETs), particularly bulk-junction triple- and double-gate FETs, offer advantages such as bulk substrate heat dissipation, low chip cost, and low defect density. However, gate-induced drain leakage (GIDL) or junction leakage can significantly deteriorate in various FinFET structures. In particular, degraded GIDL or junction leakage significantly negatively impacts standby power consumption and active power dissipation, resulting in a higher total cost of ownership (TCO), while also deviating from current green ecosystem requirements. Especially in applications such as mobile communications, the Internet of Things (IoT), artificial intelligence (AI), and fifth-generation wireless systems (5G) communications, which have increasingly lower requirements for standby power consumption and active power dissipation, deteriorated gate-induced drain leakage (GIDL) or junction leakage will have a serious impact.

[0007] Therefore, when FinFET technology is scaled down to approximately 20 nanometers, gate-induced drain leakage (GIDL) or junction leakage will become the fundamental scaling limitation of FinFET technology, both physically and structurally. Therefore, how to reduce gate-induced drain leakage (GIDL) and junction leakage in future Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) devices that will be further scaled down to below 10 nanometers has become a critical issue. Summary of the Invention

[0008] The present invention discloses a transistor with low leakage current, such as a planar transistor, a fin field-effect transistor (FinFET), a gate-all-around (GAA) transistor, or other fin-shaped transistor. In one embodiment of the present invention, the transistor is a fin field-effect transistor (FinFET). The FinFET includes a substrate, a gate, multiple spacer layers, multiple liner dielectric layers, a source, and a drain. The gate is formed on a gate dielectric layer, wherein the gate dielectric layer has a first dielectric constant. The multiple spacer layers have a second dielectric constant. The multiple liner dielectric layers are formed below the multiple spacer layers and have a third dielectric constant. The source and the drain are formed in the substrate, wherein the source and the drain are adjacent to the multiple spacer layers and are arranged in opposite directions relative to the gate. The first dielectric constant, the second dielectric constant, and the third dielectric constant are different from each other.

[0009] In another embodiment of the present invention, the gate dielectric layer is formed on a fin-shaped active region, the fin-shaped active region is formed on the surface of the substrate, the fin-shaped active region includes a semiconductor material, and the liner dielectric layer is formed between the multiple spacer layers and the fin-shaped active region.

[0010] In another embodiment of the present invention, the source and the drain are respectively formed in the first groove and the second groove of the substrate and coupled to the fin-shaped active region, and the upper surfaces of the source and the drain are higher than the upper surface of the fin-shaped active region.

[0011] In another embodiment of the present invention, a bottom of at least one of the first groove and the second groove is filled with an isolation layer, and an isolation layer / substrate junction exists between the isolation layer and the substrate.

[0012] In another embodiment of the present invention, the transistor further includes a first contact and a second contact. The first contact is formed on the source, wherein a first distance exists between the first contact and a corresponding spacer layer among the plurality of spacer layers; the second contact is formed on the drain, wherein a second distance exists between the second contact and another corresponding spacer layer among the plurality of spacer layers, and the second distance is greater than the first distance; and upper surfaces of the first contact and the second contact are 5 nanometers to 400 nanometers higher than an upper surface of the fin-shaped active region.

[0013] Those skilled in the art will appreciate that source / drain junction doping of a metal oxide semiconductor field effect transistor can be formed by ion implantation, epitaxial doping, or atomic layer deposition (ALD) doping methods, wherein thermal or random doping diffusion effects cause the doping concentration of the source / drain to exhibit a gradual distribution, and it is impossible to form two different doping concentration profiles within the source or drain. In another embodiment of the present invention, during the formation of the source and drain, a controllable doping method including at least two different doping concentration levels (i.e., a doping recipe) is employed to provide at least one of the source and drain with a controllable doping concentration profile, wherein the distribution direction of the controllable doping concentration profile is horizontal or vertical.

[0014] In another embodiment of the present invention, the controllable doping concentration distribution includes a first doping concentration and a second doping concentration, the first doping concentration corresponding to the first region of the at least one and the second doping concentration corresponding to the second region of the at least one, the second doping concentration being between 10 17 atoms / cm3 and 10 21 atoms / cubic centimeter, the first doping concentration is more than twice the second doping concentration, and the first resistance of the first region is less than the second resistance of the second region.

[0015] In another embodiment of the present invention, in addition to the gate dielectric layer being interposed between the gate and the fin-shaped active region, the gate dielectric layer is also interposed between the gate and the plurality of spacer layers.

[0016] In another embodiment of the present invention, in addition to the gate dielectric layer being between the gate and the fin-shaped active region, the gate dielectric layer is also between the gate and the multiple spacer layers, wherein at least one of the multiple liner dielectric layers has multiple thicknesses.

[0017] In another embodiment of the present invention, the fin-shaped active region is a channel of the transistor.

[0018] In another embodiment of the present invention, the gate has a sidewall directly coupled to at least one of the multiple spacer layers, the edge of the gate dielectric layer has a circular structure, and the circular structure is between the gate and the multiple spacer layers, wherein the outer curvature radius of the circular structure is greater than the thickness of the gate dielectric layer.

[0019] In another embodiment of the present invention, the first dielectric constant is greater than the second dielectric constant, and the second dielectric constant is greater than the third dielectric constant, and the third dielectric constant is between 1 and 4.

[0020] In another embodiment of the present invention, the thickness of each liner dielectric layer is smaller than the thickness of each spacer layer in the plurality of spacer layers.

[0021] In another embodiment of the present invention, the gate is made of p+ doped or n+ doped polysilicon material or a metal-containing material.

[0022] In another embodiment of the present invention, the thickness of at least one of the plurality of spacer layers is controllable, the size of the source is controllable, and the size of the drain is controllable, wherein the size of the source is different from the size of the drain.

[0023] In another embodiment of the present invention, the thickness of each of the plurality of liner dielectric layers is between 1 nm and 15 nm.

[0024] In another embodiment of the present invention, the third dielectric constant (ie, relative permittivity) is between 1 and 4.

[0025] Another embodiment of the present invention discloses a transistor. The transistor includes a substrate, a gate, a first region, and a second region. The substrate has a surface. The gate is formed on a gate dielectric layer. The first region is coupled to one side of the gate, wherein the first region includes a first spacer layer, a first liner dielectric layer, and a first conductive region, and the first liner dielectric layer is located below the first spacer layer. The second region is coupled to the other side of the gate, wherein the second region includes a second spacer layer, a second liner dielectric layer, and a second conductive region, and the second liner dielectric layer is located below the second spacer layer. The first region and the second region are asymmetric.

[0026] In another embodiment of the present invention, the first conductive region at least extends downward from the surface and the second conductive region at least extends downward from the surface.

[0027] In another embodiment of the present invention, the first region further includes an isolation layer, wherein the isolation layer is adjacent to the first conductive region and is located below the first conductive region.

[0028] In another embodiment of the present invention, the first spacer layer and the second spacer layer are asymmetric.

[0029] In another embodiment of the present invention, the transistor is a fin field effect transistor, and the first conductive region and the second conductive region are asymmetric.

[0030] Another embodiment of the present invention discloses a method for fabricating a transistor. The method includes preparing a substrate having a surface; forming a gate dielectric layer on the surface; forming a gate of the transistor on the gate dielectric layer; and forming a first region coupled to one side of the gate and a second region coupled to the other side of the gate; the first region and the second region being asymmetrical.

[0031] In another embodiment of the present invention, forming the first region includes forming a first spacer layer and a first conductive region coupled to the one side of the gate, and forming the second region includes forming a second spacer layer and a second conductive region coupled to the other side of the gate, wherein the first conductive region or the second conductive region includes a formula for forming a controllable doping concentration distribution and forming a distribution direction of the controllable doping concentration distribution, wherein the distribution direction is horizontal or vertical.

[0032] The present invention discloses a fin field-effect transistor (FinFET) with low leakage current. Because the FinFET utilizes at least one of different dielectric layers, controllable doping concentrations of the source and drain of the FinFET, different gate dielectric layers, different junctions between the source and drain, different thicknesses of the source and drain, and different sizes of the source and drain to reduce gate-induced drain leakage (GIDL), short-channel effect (SEC), off-current, or junction leakage, the present invention can more effectively reduce gate-induced drain leakage, short-channel effect, off-current, or junction leakage compared to the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1A is a schematic diagram of a cross section of a fin field effect transistor with low leakage current disclosed in the first embodiment of the present invention.

[0034] Figure 1B is a schematic diagram of a cross section of a fin field effect transistor disclosed in another embodiment of the present invention.

[0035] Figure 2 is a schematic diagram of a cross section of a fin field effect transistor disclosed in a second embodiment of the present invention.

[0036] Figure 3 is a schematic diagram of a cross section of a fin field effect transistor disclosed in a third embodiment of the present invention.

[0037] Figure 4 is a schematic diagram of a cross section of a fin field effect transistor disclosed in a fourth embodiment of the present invention.

[0038] Figure 5 is a schematic diagram of a cross section of a fin field effect transistor disclosed in a fifth embodiment of the present invention.

[0039] Figure 6 This is a flow chart of a method for manufacturing a transistor disclosed in a sixth embodiment of the present invention.

[0040] The description of the accompanying drawings is as follows:

[0041] 100, 150, 200, 300, 400, 500 FinFETs

[0042] 102 substrate

[0043] 104 gate

[0044] 1061, 1062 spacer layer

[0045] 1081, 1082, 1581, 1582 pad dielectric layer

[0046] 110 Source

[0047] 112 Drain

[0048] 114 gate dielectric layer

[0049] 116 First Groove

[0050] 118 Second groove

[0051] 120 First Contact

[0052] 122 Second Contact

[0053] 10612, 10622, 10616, 10626 oxide layer

[0054] 10614, 10624 nitride layer

[0055] 1102 First Area

[0056] 1104 Second Area

[0057] 1124 Third Area

[0058] 1122 Fourth Area

[0059] 302 circular structure

[0060] 402 Isolation Layer

[0061] D1 First distance

[0062] D2 Second distance

[0063] H1, H2 height

[0064] TH1, TH2 thickness

[0065] Steps 600-610 DETAILED DESCRIPTION

[0066] The present invention discloses a transistor with low leakage current, such as a planar transistor, a fin field-effect transistor (FinFET), a gate-all-around (GAA) transistor or other fin-shaped transistor. The following embodiments will be described using a fin field-effect transistor as an example. Please refer to Figure 1A . Figure 1A FIG1 is a schematic diagram of a cross-section of a fin field-effect transistor (FinFET) 100 with low leakage current disclosed in a first embodiment of the present invention, wherein the FinFET 100 includes a substrate 102, a gate 104, spacers 1061, 1062, pad dielectric layers 1081, 1082, a source 110, and a drain 112, and the substrate 102 is a P-type substrate. Each of the spacer layers 1061 and 1062 may be a multi-layer structure (for example, each of the spacer layers may be a three-layer structure. That is, the spacer layer 1061 may be composed of an oxide layer 10612, a nitride layer 10614, and an oxide layer 10616, and the spacer layer 1062 may be composed of an oxide layer 10622, a nitride layer 10624, and an oxide layer 10626. Of course, the present invention is not limited to the spacer layers 1061 and 1062 being the three-layer structure. That is, the spacer layers 1061 and 1062 may be a double-layer structure or a multi-layer structure. In addition, as Figure 1AAs shown, a first region includes a spacer layer 1062, a liner dielectric layer 1082 under the spacer layer 1062, and a source 110 (i.e., a first conductive region), and the first region is coupled to one side of the gate 104; similarly, a second region includes a spacer layer 1061, a liner dielectric layer 1081 under the spacer layer 1061, and a drain 112 (i.e., a second conductive region), and the second region is coupled to the other side of the gate 104.

[0067] The gate 104 is formed on a gate dielectric layer 114. The gate dielectric layer 114 is further interposed between the gate 104 and the spacer layers 1061, 1062. The pad dielectric layers 1081, 1082 are formed under the spacer layers 1061, 1062 and between the spacer layers 1061, 1062 and a fin-like active region (not shown). Figure 1A ), the source 110 and the drain 112 are respectively formed in a first groove 116 in the substrate 102 and a second groove 118 in the substrate 102, wherein the source 110 and the drain 112 are adjacent to the spacer layers 1061, 1062 and are arranged in the opposite direction relative to the gate 104, the upper surfaces of the source 110 and the drain 112 are higher than the upper surface of the fin-shaped active region, a source / substrate junction exists between the source 110 and the substrate 102, a drain / substrate junction exists between the drain 112 and the substrate 102, and the fin-shaped active region is the channel of the FinFET 100.

[0068] Furthermore, the gate dielectric layer 114 has a first dielectric constant (i.e., relative permittivity), the spacer layers 1061 and 1062 have a second dielectric constant, and the liner dielectric layers 1081 and 1082 have a third dielectric constant. Furthermore, because the FinFET 100 includes a fin structure, which is well known to those skilled in the art, those skilled in the art will appreciate that the gate dielectric layer 114 is formed on the fin active region, which is formed on the surface of the substrate 102, and the source 110 and drain 112 are coupled to the fin active region. Furthermore, the liner dielectric layers 1082 and 1081 are formed between the spacer layers 1061 and 1062 and the fin active region. In addition, the fin-shaped active region includes a semiconductor material (for example, the fin-shaped active region may include a monocrystalline silicon material, a compound semiconductor material, or a polysilicon material).

[0069] like Figure 1A As shown, FinFET 100 further includes a first contact 120 and a second contact 122. First contact 120 is formed above source 110, and second contact 122 is formed above drain 112. A first distance D1 exists between first contact 120 and spacer 1062 (i.e., a corresponding spacer layer), and a second distance D2 exists between second contact 122 and spacer 1061 (i.e., another corresponding spacer layer). Second distance D2 is greater than first distance D1. Furthermore, top surfaces of first contact 120 and second contact 122 are 5 to 400 nanometers higher than the top surface of the fin active region.

[0070] Because the liner dielectric layers 1081 and 1082 are formed below the spacer layers 1061 and 1062 and between the spacer layers 1081 and 1082 and the fin active region, the first dielectric constant is greater than the second dielectric constant, the second dielectric constant is greater than the third dielectric constant, and the thickness of each of the liner dielectric layers 1081 and 1082 is greater than or less than the thickness of the gate dielectric layer 114, the liner dielectric layers 1081 and 1082 can maintain a higher potential drop and reduce the electric field strength on the upper surface of the fin active region. The reduced electric field strength can reduce band-to-band (BTB) tunneling leakage current on the upper surface of the fin active region when the channel dimension of the FinFET 100 is further reduced, thereby achieving very low gate-induced drain leakage (GIDL) or very low off current. That is, the FinFET 100 utilizes the liner dielectric layers 1081 , 1082 with a relatively low dielectric constant and a selected thickness to effectively suppress tip discharge leakage current and gate-induced drain leakage (GIDL) on the upper surface of the fin active region.

[0071] In addition, the thickness of each of the liner dielectric layers 1081, 1082 is between 1 nanometer and 15 nanometers and is less than the thickness of each of the spacer layers 1061, 1062, the third dielectric constant is between 1 and 4, and the gate 104 is composed of a p+ doped or n+ doped polysilicon material or a metal-containing material.

[0072] In addition, because the top surfaces of the first contact 120 and the second contact 122 are 5 nm to 400 nm higher than the top surface of the fin active region, the gate-to-drain overlap region is increased, resulting in reduced gate-induced drain leakage (GIDL), short-channel effect (SEC), off current, or junction leakage current, and further enabling the FinFET 100 to be scaled down.

[0073] Please refer to Figure 1B . Figure 1B FIG. 1 is a schematic diagram of a cross-section of a FinFET 150 according to another embodiment of the present invention, wherein the difference between the FinFET 150 and the FinFET 100 is that each of the liner dielectric layers 1581 and 1582 has multiple thicknesses. For example, Figure 1B As shown, the liner dielectric layer 1581 includes a first region having a thickness TH1 and a second region having a thickness TH2, wherein the thickness TH1 is less than the thickness TH2, and the second region having the thickness TH2 can further reduce gate-induced drain leakage (GIDL). Furthermore, the present invention is not limited to the liner dielectric layers 1581 and 1582 having multiple thicknesses. That is, in another embodiment of the present invention, at least one of the liner dielectric layers 1581 and 1582 has multiple thicknesses. Furthermore, the remaining operating principles of the FinFET 150 can refer to the operating principles of the FinFET 100 and will not be further described here.

[0074] Please refer to Figure 2 . Figure 2 FIG2 is a schematic diagram of a cross-section of a FinFET 200 disclosed in accordance with a second embodiment of the present invention. FinFET 200 differs from FinFET 100 in that at least one of source 110 and drain 112 has a controllable doping concentration profile, and the distribution direction of the controllable doping concentration profile is horizontal or vertical. For example, source 110 has a first controllable doping concentration profile and drain 112 has a second controllable doping concentration profile, wherein the first controllable doping concentration profile is vertically distributed, and the second controllable doping concentration profile is horizontally distributed.

[0075] In addition, during the formation of the source 110 and the drain 112, a controllable doping method including at least two different doping concentration levels (i.e., a doping recipe) is used, so that the source 110 can have the first controllable doping concentration profile and the drain 112 can have the second controllable doping concentration profile. The first controllable doping concentration profile includes a first doping concentration and a second doping concentration, wherein the first doping concentration corresponds to the first region 1102 of the source 110 and the second doping concentration corresponds to the second region 1104 of the source 110, and the second doping concentration is between 10 and 10. 17 Atoms / cm^3 and 10 21 atoms / cubic centimeter, the first doping concentration is more than twice the second doping concentration, and the first resistance of the first region 1102 is lower than the second resistance of the second region 1104; the second controllable doping concentration profile also includes the first doping concentration and the second doping concentration, the first doping concentration corresponds to the third region 1124 of the drain 112, the second doping concentration corresponds to the fourth region 1122 of the drain 112, and the third resistance of the third region 1124 is lower than the fourth resistance of the fourth region 1122. Therefore, when the first contact 120 and the second contact 122 are made into good ohmic contacts, the gate-induced drain leakage (GIDL) or short-channel effect (SEC) of the fin field effect transistor 100 can be reduced. Therefore, the technical features can help improve the yield of semiconductor manufacturing while reducing costs.

[0076] In addition, in one embodiment of the present invention, the source 110 and the drain 112 can be formed by injecting different ion doping concentrations (that is, the first controllable doping concentration distribution and the second controllable doping concentration distribution) or by selective epitaxial growth with different doping, wherein the first controllable doping concentration distribution and the second controllable doping concentration distribution are intentionally controlled.

[0077] like Figure 2As shown, because the source 110 has the first controllable doping concentration profile and the drain 112 has the second controllable doping concentration profile, the junction electric field between the first region 1102 and the second region 1104 and the junction electric field between the third region 1124 and the fourth region 1122 can be reduced to form multiple-serial resistivity between the fin active region and the first contact 120 and between the fin active region and the second contact 122, resulting in a reduction in gate-induced drain leakage (GIDL), short-channel effect (SEC), OFF current, or junction leakage current. That is, the fin field effect transistor 200 can effectively alleviate the electric field and potential gradient (potential gradient) on the upper surface of the fin-shaped active region near the source 110 and the drain 112 by selecting the doping concentration levels of the first doping concentration and the second doping concentration or by adopting a controllable doping method including at least two different doping concentration levels (that is, doping recipes) during the formation of the source 110 and the drain 112 to reduce the gate-induced drain leakage (GIDL), short-channel effect (SEC), off current, or junction leakage current.

[0078] In addition, the present invention is not limited to the first controllable doping concentration distribution being vertical and the second controllable doping concentration distribution being horizontal. That is, in another embodiment of the present invention, the first controllable doping concentration distribution and the second controllable doping concentration distribution can be both vertical and horizontal. The remaining operating principles of the FinFET 200 can refer to the operating principles of the FinFET 100 and will not be further described here.

[0079] Please refer to Figure 3 . Figure 3FIG3 is a schematic diagram of a cross-section of a FinFET 300 disclosed in a third embodiment of the present invention. FinFET 300 differs from FinFET 100 in that gate 104 has sidewalls directly coupled to spacers 1061, 1062, and the edge of gate dielectric layer 114 has a rounded structure 302. Rounded structure 302 is located between gate 104 and spacers 1061, 1062, and the outer radius of curvature of rounded structure 302 is greater than the thickness of gate dielectric layer 114. Furthermore, because gate 104 has sidewalls directly coupled to spacers 1061, 1062, the length of gate 104 in FinFET 300 is shorter than that of gate 104 in FinFET 100. FinFET 300 can also reduce gate-induced drain leakage (GIDL), short-channel effect (SEC), off-current, or junction leakage. Furthermore, in another embodiment of the present invention, only one sidewall of gate 104 is directly coupled to spacer 1061 (or spacer 1062). The remaining operating principles of FinFET 300 can be referenced to those of FinFET 100 and are not further described here.

[0080] Please refer to Figure 4 . Figure 4FIG4 is a schematic diagram of a cross-section of a FinFET 400 disclosed in accordance with a fourth embodiment of the present invention. FinFET 400 differs from FinFET 100 in that the bottom of at least one of the first recess 116 and the second recess 118 is filled with an isolation layer (e.g., an insulating material), and an isolation layer-substrate junction exists between the isolation layer 402 and the substrate 102. For example, the bottom of the second recess 118 is filled with an isolation layer 402, and an isolation layer-substrate junction exists between the isolation layer 402 and the substrate 102. This means that, compared to the source 110, the drain 112 not only has a drain-substrate junction but also has the aforementioned isolation layer-substrate junction. Therefore, the FinFET 400 can further utilize the mismatch between the source 110 and drain 112 junctions to reduce gate-induced drain leakage (GIDL), short-channel effect (SEC), OFF current, or junction leakage current, thereby achieving higher speed with lower AC switching power loss (C*V^2*F), where C is the parasitic capacitance of the FinFET 400, V is the operating voltage of the FinFET 400, and F is the operating frequency of the FinFET 400. The remaining operating principles of the FinFET 400 can be referred to the operating principles of the FinFET 100 and will not be further described here.

[0081] Please refer to Figure 5 . Figure 5FIG2 is a schematic diagram of a cross-section of a FinFET 500 according to a fifth embodiment of the present invention. FinFET 500 differs from FinFET 100 in that the thickness of at least one of the spacer layers 1061 and 1062 is controllable. For example, the thickness of spacer layer 1061 is greater than the thickness of spacer layer 1062. Therefore, FinFET 500 can further utilize the uneven thickness of spacer layers 1061 and 1062 to reduce gate-induced drain leakage (GIDL), short-channel effect (SEC), off-state current, or junction leakage current. Furthermore, in another embodiment of the present invention, not only is the thickness of at least one of the spacer layers 1061 and 1062 controllable, but the dimensions (e.g., length, height) of at least one of the source 110 and drain 112 are also controllable. For example, the height H1 of the source 110 is less than the height H2 of the drain 112. Therefore, the FinFET 500 can further utilize the inconsistency between the thickness of the spacer layers 1061, 1062 and the dimensions of the source 110 and drain 112 to reduce gate-induced drain leakage (GIDL), short-channel effect (SEC), OFF current, or junction leakage current, thereby achieving higher speed with lower AC switching power loss. Furthermore, in another embodiment of the present invention, the dimensions (e.g., length, height) of at least one of the source 110 and drain 112 are also controllable. The remaining operating principles of the FinFET 500 can refer to the operating principles of the FinFET 100 and are not further described here.

[0082] Please refer to Figure 6 , Figure 6 This is a flow chart of a method for manufacturing a transistor disclosed in a sixth embodiment of the present invention. Figure 6 The manufacturing method is to use Figure 2 FinFET 200, Figure 4 The FinFET 400 and Figure 5 The FinFET 500 is described in detail as follows:

[0083] Step 600: Start;

[0084] Step 602: Prepare the substrate 102;

[0085] Step 604: Forming a gate dielectric layer 114 on the surface of the substrate 102;

[0086] Step 606: Forming the gate 104 of the transistor on the gate dielectric layer 114;

[0087] Step 608: Form a first region coupled to one side of the gate 104 and a second region coupled to the other side of the gate 104;

[0088] Step 610: End.

[0089] In step 608, taking the FinFET 200 as an example, Figure 2 As shown, the first region includes a spacer layer 1062, a liner dielectric layer 1082, and a source 110 (i.e., the first conductive region), and the first region is coupled to one side of the gate 104. Similarly, the second region includes a spacer layer 1061, a liner dielectric layer 1081, and a drain 112 (i.e., the second conductive region), and the second region is coupled to the other side of the gate 104. In addition, during the formation of the source 110 and the drain 112, a controllable doping method including at least two different doping concentration levels (i.e., a doping recipe) is used, so that the source 110 can have the first controllable doping concentration profile and the drain 112 can have the second controllable doping concentration profile. The first controllable doping concentration distribution includes the first doping concentration and the second doping concentration, the first doping concentration corresponds to the first region 1102 of the source 110 and the second doping concentration corresponds to the second region 1104 of the source 110, so the distribution direction of the first controllable doping concentration distribution is vertical; the second controllable doping concentration distribution also includes the first doping concentration and the second doping concentration, the first doping concentration corresponds to the third region 1124 of the drain 112, and the second doping concentration corresponds to the fourth region 1122 of the drain 112, so the distribution direction of the second controllable doping concentration distribution is horizontal. Figure 2 As shown, because the distribution direction of the first controllable doping concentration distribution is vertical and the distribution direction of the second controllable doping concentration distribution is horizontal, the first region (including the source 110) and the second region (including the drain 112) are not symmetrical.

[0090] In step 608, taking the FinFET 400 as an example, Figure 4As shown, the bottom of the second recess 118 is filled with the isolation layer 402, and the isolation layer-substrate junction exists between the isolation layer 402 and the substrate 102. In other words, compared to the source 110, the drain 112 has not only the drain-substrate junction, but also the isolation layer-substrate junction. Because the bottom of the second recess 118 is filled with the isolation layer 402, the first region (including the source 110) and the second region (including the drain 112) are also asymmetrical.

[0091] In step 608, taking the FinFET 500 as an example, Figure 5 As shown, because the thickness of the spacer layer 1061 is greater than the thickness of the spacer layer 1062, and the height H1 of the source 110 is less than the height H2 of the drain 112, the first region (including the source 110 and the spacer layer 1062 (that is, the first spacer layer)) and the second region (including the drain 112 and the spacer layer 1061 (that is, the second spacer layer)) are also asymmetrical.

[0092] In addition, the FinFETs 100 , 200 , 300 , 400 , and 500 can be applied to logic integrated circuits with embedded memory intellectual property (IP) / library circuits, wherein the embedded memory IP / library circuits include emulation circuits, dynamic random access memory (DRAM), high bandwidth memory (HBM), static random access memory (SRAM), flash memory, magnetoresistive random access memory (MRAM), resistive random access memory (RRAM), chalcogenide random access memory (CRAM), phase-change memory (PSRAM), read-only memory (ROM), one-time programmable memory (OPT), and electronic fuses (e-fuses).

[0093] In addition, the FinFETs 100, 200, 300, 400, and 500 can also be applied to logic intellectual property / library circuits with low power consumption, wherein the low power logic intellectual property / library circuits include input / output circuits, electrostatic discharge (ESD) circuits, double data rate (DDR) port physical layer (PHY), high-bandwidth memory port physical layer, mobile industry processor interface (MIPI), serializer / deserializer (SerDes), universal serial bus (USB), and high-speed interface, etc.

[0094] Furthermore, FinFETs 100, 200, 300, 400, and 500 may also be used in logic integrated circuits with embedded analog intellectual property (IP) / library circuits, including phase-locked loops (PLLs), delay-locked loops (DLLs), radio frequency (RF), high voltage circuits, display drivers, camera sensors, micro-electro-mechanical systems (MEMS), ultra-high-speed (10 GHz to 100 GHz) circuits, ultra-low power circuits, ultra-low leakage circuits, or mixed-mode circuits.

[0095] In addition, the FinFETs 100 , 200 , 300 , 400 , and 500 can also be applied to logic integrated circuits of two-dimensional or three-dimensional stacked chips with low-power applications, wherein the low-power applications include the Internet of Things (IoT), fifth-generation wireless systems (5G), artificial intelligence (AI), mobile communications, autonomous driving, high-performance computing (HPC), and cloud computing.

[0096] In summary, because the FinFET can utilize at least one of different dielectric layers, controllable doping concentrations of the source and drain, different gate dielectric layers, different junctions of the source and drain, different thicknesses of the source and drain, and different sizes of the source and drain to reduce gate-induced drain leakage (GIDL), short-channel effect (SEC), off-current, or junction leakage, the present invention can more effectively reduce gate-induced drain leakage, short-channel effect, off-current, or junction leakage compared to the prior art, thereby achieving higher speed with lower AC switching power (C*V^2*F) losses.

[0097] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A transistor with low leakage current, comprising: a substrate; a gate formed on a gate dielectric layer, wherein the gate dielectric layer has a first dielectric constant; A plurality of spacer layers having a second dielectric constant; a plurality of liner dielectric layers formed below the plurality of spacer layers and having a third dielectric constant, wherein at least one of the plurality of liner dielectric layers has a plurality of thicknesses, the first dielectric constant is greater than the second dielectric constant, and the second dielectric constant is greater than the third dielectric constant; and A source electrode and a drain electrode are formed in the substrate, wherein the source electrode and the drain electrode are adjacent to the plurality of spacer layers and are arranged in an opposite direction relative to the gate electrode.

2. The transistor according to claim 1, wherein The gate dielectric layer is formed on a fin-shaped active region formed on a surface of the substrate, the fin-shaped active region comprises a semiconductor material, and the liner dielectric layer is formed between the plurality of spacer layers and the fin-shaped active region.

3. The transistor according to claim 2, wherein The source and the drain are respectively formed in the first groove of the substrate and the second groove of the substrate and coupled to the fin-shaped active region, and upper surfaces of the source and the drain are higher than an upper surface of the fin-shaped active region.

4. The transistor according to claim 3, wherein : A bottom of at least one of the first groove and the second groove is filled with an isolation layer, and an isolation layer / substrate junction exists between the isolation layer and the substrate.

5. The transistor according to claim 3, wherein Also includes: a first contact formed on the source, wherein a first distance exists between the first contact and a corresponding spacer layer among the plurality of spacer layers; and a second contact formed on the drain, wherein a second distance exists between the second contact and another corresponding spacer layer of the plurality of spacer layers, and the second distance is greater than the first distance; The upper surfaces of the first contact and the second contact are higher than the upper surface of the fin-shaped active region by 5 nanometers to 400 nanometers.

6. The transistor according to claim 3, wherein At least one of the source and the drain has a controllable doping concentration distribution, and a distribution direction of the controllable doping concentration distribution is horizontal or vertical.

7. The transistor according to claim 6, wherein The controllable doping concentration distribution includes a first doping concentration and a second doping concentration, wherein the first doping concentration corresponds to the first region of the at least one and the second doping concentration corresponds to the second region of the at least one, and the second doping concentration is between 10 17 atoms / cm3 and 10 21 atoms / cubic centimeter, the first doping concentration is more than twice the second doping concentration, and the first resistance of the first region is less than the second resistance of the second region.

8. The transistor according to claim 2, wherein The gate dielectric layer is located between the gate and the fin-shaped active region, and is also located between the gate and the plurality of spacer layers.

9. The transistor according to claim 2, wherein The gate dielectric layer is located between the gate and the fin-shaped active region, and is also located between the gate and the plurality of spacer layers.

10. The transistor according to claim 2, wherein The fin-shaped active region is the channel of the transistor.

11. The transistor according to claim 1, wherein :The gate has a sidewall directly coupled to at least one of the multiple spacer layers, the edge of the gate dielectric layer has a circular structure, and the circular structure is between the gate and the multiple spacer layers, wherein the outer curvature radius of the circular structure is greater than the thickness of the gate dielectric layer.

12. The transistor according to claim 1, wherein : The first dielectric constant is greater than the second dielectric constant, and the second dielectric constant is greater than the third dielectric constant, wherein the third dielectric constant is between 1 and 4.

13. The transistor according to claim 1, wherein : The thickness of each liner dielectric layer is smaller than the thickness of each spacer layer in the plurality of spacer layers.

14. The transistor according to claim 1, wherein The gate is composed of a p+ doped or n+ doped polysilicon material or a metal-containing material.

15. The transistor according to claim 1, wherein : The thickness of at least one of the plurality of spacer layers is controllable, the size of the source electrode is controllable, and the size of the drain electrode is controllable, wherein the size of the source electrode is different from the size of the drain electrode.

16. The transistor according to claim 1, wherein : The thickness of each of the plurality of liner dielectric layers is between 1 nm and 15 nm.

17. The transistor according to claim 1, wherein : The third dielectric constant is between 1 and 4.

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