Low power dot matrix wave filter system and method

Abstract

Systems and methods for low power lattice wave filters include an input operable to receive a digital input signal having a first sample rate, a first processing branch including a first delay element operable to receive the digital input signal and output a delayed digital input signal, a second processing branch including a first summer operable to receive the digital input signal and subtract a delayed feedback signal to produce a difference signal, a second summer operable to combine the delayed digital input signal and the difference signal to produce an output signal, and wherein the second processing branch further includes a feedback path including a second delay element operable to receive the output signal and output the delayed feedback signal. In a multi-stage topology, registers are provided between each stage and clocked to reduce ripple power.

Description

Technical Field

[0001] This application generally relates to systems and methods for digital signal processing, and more specifically to sampling rate conversion of digital samples in, for example, adaptive noise cancellation systems. Background Technology

[0002] It is well known to convert digital signals into different sampling rates suitable for various digital components and processes. Digital signal processing systems use different sampling rates in various system components depending on the desired signal quality, noise density, required bandwidth, latency requirements, processing economics, available silicon area, and other considerations. In conventional systems, cascaded integrator comb (CIC), finite impulse response (FIR), and infinite impulse response (IIR) filters are commonly used in multiple stages to perform sampling rate conversion to save power; for example, depending on whether the operation is decimation or interpolation, each successive stage will use a lower or higher sampling rate. There is a persistent need to reduce the power consumption of the sampling rate conversion structure, reduce the latency within the sampling rate conversion structure, and reduce the silicon area required to implement the sampling rate conversion structure. Summary of the Invention

[0003] According to various embodiments, the systems and methods disclosed herein provide low-power lattice wave filters. Sampling rate conversion of digital signals using the disclosed low-power lattice wave filters can be used in a variety of applications, such as in oversampled data converters or for bridging systems utilizing different sampling rates. Compared to conventional solutions, the lattice wave filter solutions disclosed herein have a lower silicon coverage area, lower power consumption, and achieve efficient coefficient modification.

[0004] In some embodiments, a system and method for a low-power lattice wave filter includes: an input operable to receive a digital input signal having a first sampling rate; a first processing branch including a first delay element operable to receive the digital input signal and output a delayed digital input signal; a second processing branch including a first adder operable to receive the digital input signal and subtract a delayed feedback signal to generate a difference signal; a second adder operable to combine the delayed digital input signal and the difference signal to generate an output signal, wherein the second processing branch further includes a feedback path including a second delay element operable to receive the output signal and output a delayed feedback signal. In a multi-stage topology, registers are provided between each stage and clocked to reduce ripple power.

[0005] The scope of this invention is defined by the claims, which are incorporated herein by reference. A more thorough understanding of embodiments of the invention and their additional advantages will be given to those skilled in the art by considering the following detailed description of one or more embodiments. Reference will be made to the accompanying drawings, which will first be briefly described. Attached Figure Description

[0006] A better understanding of aspects and advantages of this disclosure can be achieved by referring to the following accompanying drawings and the subsequent detailed description. It should be understood that similar reference numerals are used to identify one or more similar elements shown in the drawings, which are illustrated in the drawings for the purpose of illustrating embodiments of this disclosure and not for the purpose of limiting this disclosure. Components in the drawings are not necessarily drawn to scale; the emphasis is on clearly illustrating the principles of this disclosure.

[0007] Figure 1 A conventional fifth-order lattice wave filter is shown.

[0008] Figure 2 A portion of a dot matrix wave filter according to one or more embodiments of the present disclosure is shown.

[0009] Figure 3 An example dot matrix wave filter according to one or more embodiments of the present disclosure is shown, the example dot matrix wave filter including multiple delays within the filter to reduce ripple power.

[0010] Figure 4 An example fifth-order lattice wave filter is shown.

[0011] Figure 5 An example fifth-order lattice wave filter according to one or more embodiments of the present disclosure is shown.

[0012] Figure 6A -D illustrates an example of a thirteenth-order lattice wave filter according to various embodiments of this disclosure.

[0013] Figure 7 An example adaptive noise cancellation system utilizing a low-power lattice wave filter is shown according to one or more embodiments of the present disclosure.

[0014] Figure 8 This is a flowchart illustrating an example process for operating a low-power lattice wave filter according to one or more embodiments of the present disclosure. Detailed Implementation

[0015] According to various embodiments, improved systems and methods for sampling rate conversion of digital signals using low-power lattice-wave filters are disclosed. Compared to previous solutions, the embodiments disclosed herein require a lower silicon coverage area and can process multiple sampling rates within a single section. In some embodiments, lattice-wave filters with lower power consumption than conventional solutions and facilitating efficient changes in coefficients are disclosed. Lower power consumption may be due to fewer arithmetic operations, fewer switching during state changes, and fewer register operations in some embodiments. The solutions disclosed herein are fully compatible with existing architectures and provide the same arithmetic range.

[0016] Lattice-wave filters have a simple structure, making them suitable for decimation and interpolation. These filters are low-sensitivity to coefficient changes and therefore enable multiplication with shorter coefficient lengths, or alternatively, addition and subtraction using canonical signed digital (CSD) logic. In various embodiments, low-power lattice-wave filters incorporate novel methods for implementing the various parts, thereby reducing the number of arithmetic operations. In some embodiments, multiple delays are provided internally within the lattice-wave filter to reduce ripple power. In other embodiments, simplified high-order lattice-wave filters using novel topologies are disclosed, which reduce both power and silicon area. In some embodiments, the lattice-wave filter design is characterized by simplified use of registers, saving adders and registers in the system.

[0017] refer to Figure 1 The conventional reflector section 100 of a typical lattice wave filter will now be described. The reflector section 100 receives a digital input signal at input node 102, which is provided to a first adder 104. The first adder 104 combines the digital input signal with a feedback signal X2D to generate a signal X1. X1 is provided to a subtractor 106, which subtracts the filtered signal X3 to generate a difference signal X2. The filtered signal X3 is generated by applying filter coefficients 108 to signal X1 and adding the result to the delayed difference signal X2 by a second adder 110. The difference signal X2 is delayed by a delay element 112, which delays the difference signal X2 by two samples. This structure is suitable for bi-reciprocal lattice wave filters. In general, the delay may include one or more unit delays.

[0018] refer to Figure 2 According to one or more embodiments of this application, alternative methods for implementing various parts of a lattice wave filter will now be described. The illustrated embodiments offer numerous advantages over conventional systems, including a reduction in the number of arithmetic operations.

[0019] What is observed is that individual parts of the lattice wave filter have a transfer function:

[0020] ,or

[0021] It can be simplified to

[0022] .

[0023] Based on this transfer function, the following is derived: Figure 2 The alternative topology shown.

[0024] Figure 2 A portion 200 of a low-power lattice wave filter according to one or more embodiments of the present disclosure is shown. Input 202 is configured to receive a digital data signal for sampling rate conversion. The digital data signal is provided to subtractor 204 in a first processing path, which subtracts a feedback signal. The digital data signal is also provided to a second processing path, which includes a first delay element 206 (e.g., a z-transform component) configured to delay the digital data signal by two samples and output the delayed digital data signal to adder 208. Adder 208 produces an output signal, which is output through output node 214 for further processing. The output signal is fed back through a second delay element 212 configured to provide a two-sample delay and is then subtracted from the input digital data signal by subtractor 204. Filter coefficients 210 (γ) are applied to the difference signal and added to the delayed digital data signal by adder 208 to produce the output signal. In general, the delay element may include one or more unit delays.

[0025] As shown, the lattice-wave filter 200 uses two adders and four registers, which is the basic structure for an all-pass filter. In various embodiments, the lattice-wave filter 200 includes two or more registers, but one or fewer adders. The registers can be replaced with a single register operating at half the input sampling rate, and the register outputs can be reused, thereby further reducing the original register requirements.

[0026] refer to Figure 3 An example lattice wave filter is shown, which includes multiple delays within the filter to reduce ripple power. (Example:) Figure 3As shown, it is possible to reduce the power consumption of multiple oversampling interpolation or decimation filters by inserting registers between stages, thereby avoiding / reducing switching at the output of the final section. An example filter structure is described in co-pending U.S. Application No. 16 / 177,308, filed October 31, 2018, entitled “LOW DELAY DECIMATOR AND INTERPOLATOR FILTERS,” which is incorporated herein by reference. In some embodiments, including a single register, such as register 314b as shown in the figures, in the middle may be sufficient, as this register is clocked on opposite or skewed clock edges, thereby significantly reducing switching without increasing the overall delay of the filter. By including registers between multiple stages, the additional power consumption associated with multiple ripple carry operations can be significantly reduced.

[0027] As shown, the multi-stage dot-matrix filter 300 includes an input node configured to receive a digital input signal 302. In this embodiment, the input signal is an 8-bit signal, but it should be understood that other input signals can be used. The input signal passes through a series of dot-matrix filters, including dot-matrix filters 310a (N=1), 310b (N=2), 310c (N=4), and 310d (N=8), where each stage doubles the sampling rate, and N is the number of unit delay elements in the structure. To reduce the power consumption of the multi-stage oversampling filter, registers are inserted between successive stages, thereby avoiding / reducing switching at the output of the final section 310d. In the illustrated embodiment, each register is implemented as a D-type flip-flop (DFF) and includes DFF 314a, DFF 314b, and DFF 314c. Dot-matrix filters 310a-d and registers DFF 314a-c are controlled by a delay clock controller 330. Clock signal 332 (3.072MHz) provides the clock input for DFFs 314a-c. High-speed clock 334 provides the clock input for the positive-edge triggered DFF 336, which is also coupled to clock signal 332 and provides clock control for the dot matrix filter stages 310a-310d. The output signal is provided to output node 350 for further processing.

[0028] refer to Figure 4An example fifth-order dual-reversible lattice wave filter, implemented as a decimation filter 400, will now be described. As shown, the decimation filter 400 receives a digital input signal at its input 402. The decimation filter 400 includes two data paths for processing the input digital stream. In the first processing path, the input digital stream is provided to a downsampler 406, which downsamples the input digital stream by a factor of two to produce an output X0. The signal X0 is combined with a feedback signal X2D by a first adder 408 to produce a signal X1. In the illustrated embodiment, a coefficient γ1 having a value of 1 / 8 (0.125) is applied to X1, and the result is added to the feedback signal X2D by a second adder 410 to produce an output signal X3. X3 is subtracted from X1 by a subtractor 412 to produce a difference signal X2. The difference signal X2 is delayed by a factor of two samples by the delay element 414 and fed back to the first adder 408 and the second adder 410.

[0029] In the second processing path, the input digital stream is fed to a delay element 420, which delays the input digital stream by one sample, and then downsampled by a factor of 2 by a downsampler 422 to produce an output Y0. Signal Y0 is combined with a feedback signal Y2D by a third adder 424 to produce signal Y1. In the illustrated embodiment, a coefficient γ2 having a value of 1 / 16 plus half (0.5625) is applied to Y1, and the result is added to the feedback signal Y2D by a fourth adder 426 to produce an output signal Y3. Y3 is subtracted from Y1 by a second subtractor 430 to produce a difference signal Y2. The difference signal Y2 is delayed by two samples by the delay element 432 and fed back to the third adder 424 and the fourth adder 426. The output signal X3 from the first processing path and the output signal Y3 from the second processing path are combined by a fifth adder 450, fed through a divider 452, and sent to output 460 (OUT).

[0030] refer to Figure 5An improved dot-matrix wave filter will now be described according to one or more embodiments of the present disclosure. As shown, a decimation filter 500 receives a digital input signal at its input 502. The decimation filter 500 includes two data paths for processing the input digital stream. In a first processing path, the input digital stream is provided to a downsampler 504, which downsamples the input digital stream by a factor of two to produce a downsampled signal X0. Signal X0 is combined with a feedback signal X3D by a subtractor 506 to produce signal X1. In the illustrated embodiment, a coefficient γ1 having a value of 1 / 8 (0.125) is applied to X1 by component 508 to produce X2, which is provided to a first adder 510. The downsampled signal X0 is also provided to a delay element 514, which delays the signal by a factor of two samples to produce a delayed signal X0D, which is combined with signal X2 by the first adder 510. The first adder 510 outputs signal X3 to the second adder 512, and a copy of X3 is fed back to the first adder 506 through a delay element 516, which delays signal X3 by a factor of two samples to generate a feedback signal X3D.

[0031] In the second processing path, the input digital stream is fed to a delay element 520, which delays the input digital stream by one sample, and is then downsampled by a downsampler 522 at twice the sample size to produce an output Y0. The signal Y0 is combined with a feedback signal Y3D by a second subtractor 524 to produce a signal Y1. In the illustrated embodiment, a coefficient γ2 having a value of 1 / 8 (0.125) is applied to Y1 by component 526 to produce Y2, which is then provided to a third adder 528. The downsampled signal Y0 is also provided to a delay element 530, which delays the signal by a factor of two samples to produce a delayed signal Y0D, which is then combined with the signal Y2 by the third adder 528. The second subtractor 524 outputs signal Y3 to the second adder 512, and a copy of Y3 is fed back to the second subtractor 524 via a delay element 532, which delays signal Y3 by a factor of two samples to generate a feedback signal Y3D. The output from the second adder 512 is provided to the divider 540 and then to the output 550 for further processing.

[0032] Figure 6A -D illustrates an example of a 13th-order lattice wave filter structure according to various embodiments of this disclosure. Reference Figure 6A The dot-matrix wave filter 600A includes three reflector stages 602a-c on the first processing branch and three reflector stages 602d-f on the second processing branch. It can be used in... Figure 2 and5 The previously disclosed structure is used to implement level 602a-f.

[0033] refer to Figure 6B Now will describe Figure 6A Further simplification of the 13th-order lattice wave filter 600A. It is observed that registers and / or other components in the lattice wave filter 600A can be reduced. For example, some filter nodes have the same value, which allows for the elimination of certain registers feeding these nodes. It is observed that, for example, (i) the output value (A) is the same, taking into account the removal of delay element 610, (ii) the output value (B) is the same, taking into account the removal of delay element 612, (iii) the output value (C) is the same, taking into account the removal of delay element 614, (iv) the output value (D) is the same, taking into account the removal of delay element 616, and (v) the output value (E) is the same, taking into account the removal of delay element 618. Figure 6C The simplified lattice wave filter 600C with redundant delay elements is shown in the figure.

[0034] Furthermore, it was observed that the output value (E) could be as follows: Figure 6D The image shown is further eliminated. Figure 6D A simplified embodiment of a 13th-order lattice wave 600D is shown. The lattice wave 600D receives an input signal 630 after passing through two processing branches. In the first processing branch, the input signal 630 is downsampled by a downsampler 632 at twice the sample size, and the downsampled input signal is provided to a delay element 634 and a first subtractor 636. The first subtractor 636 subtracts the feedback signal (A) received from the second stage from the downsampled input signal, producing a difference signal. At component 638, the coefficient γ1 is multiplied by the difference signal, and the result is combined by a first adder 640 with the delayed downsampled input signal. The resulting output is then fed to the next stage.

[0035] In the second processing branch, the input signal 630 is delayed by one sample by the delay element 650 and downsampled by twice by the downsampler 652. The delayed and downsampled input signal is provided to the delay element 654 and the second subtractor 656. The second subtractor 656 subtracts the feedback signal (C) received from the second stage from the delayed, downsampled input signal and produces a difference signal. At component 658, the coefficient γ2 is multiplied by the difference signal, and the result is combined by the second adder 660 with the delayed, downsampled input signal, and the resulting output is fed to the next stage. It can be seen that when comparing the original... Figure 6A With the new 6D, the number of delay elements has been reduced from 13 to 9. This assumes that the delay is implemented using a single register operating at half the input sampling rate to save register space and power.

[0036] The low-power lattice wave filter disclosed herein can be used to facilitate sample conversion in a variety of multirate systems. For example, noise cancellation and noise reduction techniques are used in various applications to improve the user experience in noisy environments. In one approach, a listening device such as headphones, headsets, or earbuds includes one or more audio sensors and adaptive noise cancellation processing circuitry. The audio sensors are used to pick up ambient noise, while the adaptive noise cancellation processing circuitry is used to generate an anti-noise signal to cancel or reduce ambient noise for the user. Ideally, the generated anti-noise signal is equal to the inverse of the noise interference (thus eliminating the noise), while the desired audio (such as playback from a high-fidelity audio source) is provided with minimal interference. To achieve the desired attenuation of ambient noise, the ANC system is designed for low-latency processing of the received noise signal to generate an inverted output signal with minimal phase shift relative to the original noise signal, thereby achieving wide-bandwidth noise cancellation.

[0037] In some embodiments, the low-power dot-matrix filter disclosed herein is used in a noise cancellation system that utilizes a sampling converter in a high-quality audio playback system. In one embodiment, a delta-sigma analog-to-digital converter (ADC) and a digital-to-analog converter (DAC) are used for audio signal processing. Compared to Nyquist sampling rate converters, delta-sigma converters utilize higher sampling rates and are generally cheaper to implement because they require lower precision in analog signal components. Therefore, from both a cost and processing perspective, performing noise cancellation at a higher sampling rate than required by the Nyquist criterion is generally advantageous, and this can be used to obtain a wider noise cancellation bandwidth.

[0038] One complexity of using multi-rate signal processing is the increased possibility of delay. In ANC systems, it is desirable to provide a time-accurate reference for the active noise processing system (for both the measured noise (the unwanted signal) and the high-fidelity audio (the desired signal)) in order to generate an anti-noise signal that is in phase with the ambient noise to be eliminated. The low-power lattice wave filter disclosed herein has low sensitivity to coefficient changes and can be used to achieve low delay even in designs with higher filter orders.

[0039] Now refer to Figure 7 A system 700 for performing adaptive noise cancellation (ANC) according to embodiments of the present disclosure is described. Figure 7The embodiments provide a time-accurate reference for the ANC system, while also providing a low-latency path for the ANC signal and a high-fidelity signal path for the reference audio signal. System 700 can be implemented in noise-canceling headphones, earbuds, mobile phones, or other systems that sense noise from the environment and generate a noise-canceling signal. System 700 includes at least one microphone 702 or other audio sensor to sense ambient noise from one or more noise sources and generate a corresponding electrical signal representing the sensed noise. In various embodiments, at least one microphone 702 may be arranged in a feedforward, feedback, or combined feedforward / feedback ANC system. The output of microphone 702 may be a digital oversampled bitstream, such as the output from a single-bit digital microphone, or an analog signal provided to a preamplifier and delta-sigma converter (single-bit or multiple-bit) to generate a digitally oversampled audio signal. The digital audio signal is decimated to a lower sampling rate by a low-latency decimator 704 (such as a low-power multi-stage dot matrix filter of this disclosure) for input to a low-latency ANC processor 706.

[0040] The low-latency ANC processor 706 generates an anti-noise signal corresponding to the ambient noise sensed by the microphone 702. The ANC processor 706 also receives a time-accurate down-converted (via 718) audio playback signal from a high-quality audio playback processor 708, which is used as an audio reference signal. In various embodiments, the ANC processor 706 adaptively filters ambient noise from the microphone signal using time or frequency updates of internal filter nodes, which may also include desired audio played through the speaker 714. For example, the ANC processor 706 may implement a minimum mean square (FXLMS) filtering algorithm to adaptively modify the filter coefficients to filter out ambient noise. To achieve low latency, an adaptive filter topology is typically used, and filter updates can be performed in the frequency domain to achieve fast adaptation even when there is a significant spread in the power spectrum of the noise. By separating the signal in the frequency domain, this enables fast adaptation even at frequencies with energy content significantly lower than any dominant node. An inverse frequency transform can be used to transform the adapted weights back to the time domain.

[0041] Audio playback processor 708 generates a desired audio signal (also referred to herein as the primary audio signal) for playback via an audio output, such as speaker 714. The desired audio signal may be generated from a source file (e.g., a recorded music or movie file), or from another source such as a near-end microphone, or from an audio signal received from a far-end microphone in an IP-based voice system. Adder 710 combines the desired audio signal with an up-converted (via 720) noise-resistant signal output by ANC processor 706. The summed output of these signals is filtered using low-latency interpolator 712 and output to speaker 714 (sometimes referred to as a receiver).

[0042] It should be understood that, for the sake of simplicity, Figure 7 Some standard components are not shown, such as microphone preamplifiers, possible microphone high-voltage pumps for MEMS microphones, low-noise power supply units, speaker amplifiers, power supplies, and other components of system 700. These components are known to those skilled in the art and will be included in various practical system implementations, but have been omitted here for the sake of clearly illustrating the processing path.

[0043] In various embodiments of System 700, both the high-fidelity audio signal and the ANC output signal are represented at the same low sampling rate (e.g., 192 kHz) and are therefore affected by the same low-fidelity interpolation filter—if low latency in the processing path is a design goal. While it is possible to increase the processing sampling rate, this would significantly increase power consumption and the physical size of the design. Therefore, it is desirable to be able to simultaneously combine a high-quality interpolation filter for audio playback and a low-latency filter path for ANC processing (also referred to herein as an adaptive noise cancellation path), such as... Figure 7 As shown in the image.

[0044] A high-quality audio playback processor 708 generates a high-quality audio signal, which is fed to a high-quality interpolator 716 (i.e., a high-fidelity interpolation filter). To avoid problems such as high power consumption, excessive complexity, or differences in delay, the high-fidelity oversampled output of the high-quality interpolation filter is decimated by a factor of N by a decimator 718, which operates without filtering (i.e., selecting every Nth sample). No filtering (e.g., anti-aliasing) is required because out-of-band signals are removed by the high-quality interpolator 716, and therefore the signal bandwidth remains unchanged, i.e., there is no aliasing. The output signal (anti-noise signal) of the ANC processor 706 is directly upsampled to a higher frequency by a factor of N in the interpolator 720 to match the frequency of the high-quality audio signal. In one embodiment, the output signal is upsampled to a higher frequency by inserting N-1 samples equal to zero between each original sample. This operation introduces multiple mirror aliasings of the original noise signal. The adder 710 combines the noise-resistant signal with the high-fidelity oversampled output and sends the combined output signal to the low-delay interpolator 712.

[0045] The low-delay interpolator 712 in this embodiment is an oversampling interpolator that operates at a higher sampling rate N times that of the initial audio output and removes the aliased image to be output from the direct interpolated signal from the ANC processor 706, while the original oversampling high-fidelity oversampling audio signal passes through unchanged because the aliased image has been removed by the high-quality interpolator. The oversampling interpolator 712 can be implemented by adding additional delay elements within each filter section, i.e., each filter section includes N, N / 2, N / 4 times the original delay element, to obtain the same frequency response as the original filter configuration operating at N, N / 2, N / 4 times the lower sampling frequency. An example oversampling interpolator structure is described in co-pending U.S. Application No. 16 / 177,308, filed October 31, 2018, entitled “LOW DELAY DECIMATOR AND INTERPOLATOR FILTERS,” which is incorporated herein by reference.

[0046] Furthermore, this filter configuration addresses practical implementation issues because the filter elements are updated at a sampling rate that is N times higher than the original sampling rate, thus achieving optimal group delay for the filter. In this case, theoretical performance can be obtained without introducing additional delay, since the actual register transfer level implementation typically provides delay when transferring values ​​between systems with different sampling rates (i.e., different sampling frequencies).

[0047] In various embodiments, the oversampling interpolation filter has the same input and output sampling frequencies and can also be used as a low-latency decimation filter, thereby further reducing latency by reducing input path delay. It is essentially a low-pass filter with very low latency and wide bandwidth, and may add a second decimation path for high-fidelity applications.

[0048] For various implementations, the filter can be optimized by first designing a filter with a response that is likely ideal from the perspective of out-of-band attenuation, and then further optimized by adjusting the coefficients to improve the actual signal-to-noise ratio (SNR) at the filter output, thus taking into account the actual noise shaping of the delta-sigma converter used. Furthermore, the coefficients can be discretized to remove multiplication in the actual implementation, thereby significantly reducing silicon area, cost, and power consumption.

[0049] refer to Figure 8 An example process 800 according to one or more embodiments will now be described. In step 802, a digital input signal is received at the input of a multi-stage sampling rate converter. In some embodiments, the digital input signal may include any digital sampled signal, such as an audio signal in an audio processing system. In step 804, in a first processing branch, the digital input signal is passed through a delay element to produce a delayed input signal. In step 806, in a second processing branch, the delayed feedback signal is subtracted from the digital input signal, and filter coefficients are applied to produce a difference signal. In step 808, the delayed input signal and the difference signal are combined to produce a feedback signal and an output signal. In step 810, the output signal of the sampling rate converter is output.

[0050] Various structures of low-power, lattice-wave filters have been presented in this disclosure. It should be understood that the embodiments disclosed herein are not limited to the described topologies, but also include other topologies that will be understood by those skilled in the art.

[0051] Where applicable, the various embodiments provided by this disclosure may be implemented using hardware, software, or a combination of hardware and software. Furthermore, where applicable, the various hardware and / or logical components described herein may be combined into composite components comprising software, hardware, and / or both, without departing from the scope of this disclosure. Where applicable, the various hardware and / or logical components described herein may be divided into sub-components comprising software, hardware, or both, without departing from the scope of this disclosure. Furthermore, where applicable, it is contemplated that software components may be implemented as hardware components, and vice versa.

[0052] The foregoing disclosure is not intended to limit this disclosure to the precise forms disclosed or to any particular field of use. Therefore, it is contemplated that various alternative embodiments and / or modifications (whether expressly described or implied herein) are possible based on the teachings of this disclosure. For example, although the low-latency decimators and low-latency interpolators disclosed herein are described with reference to adaptive noise cancellation systems, it should be understood that the low-latency filters disclosed herein can be used in other signal processing systems. Embodiments of this disclosure have been thus described, and those skilled in the art will recognize that changes in form and detail may be made without departing from the scope of this disclosure. Therefore, this disclosure is limited only by the claims.

Claims

1. A system for digital signal processing, comprising: The first filter stage of the multi-stage sampling rate converter includes: The input is operable to receive a digital input signal having a first sampling rate; A first processing branch includes a first delay element, which is operable to receive the digital input signal and output a delayed digital input signal; The second processing branch includes a first adder operable to receive the digital input signal and subtract a delayed feedback signal to generate a difference signal; and A second adder is operable to combine the delayed digital input signal and the difference signal to produce an output signal; The second processing branch further includes a feedback path, which includes a second delay element operable to receive the output signal and output the delayed feedback signal; and A first register electrically coupled between the first filter stage and the second filter stage, wherein the first register is controlled by a first clock signal, and wherein the first filter stage and the second filter stage are controlled by a second clock signal.

2. The system of claim 1, wherein the second processing branch further comprises a filter coefficient component, wherein the output of the first adder is provided to the filter coefficient component, and wherein the filter coefficient component generates the difference signal.

3. The system of claim 1, wherein the first register delays the output signal between the first filter stage and the second filter stage to reduce ripple.

4. The system of claim 1, wherein the first filter stage and the second filter stage include decimators.

5. The system of claim 1, wherein the first filter stage and the second filter stage include interpolators.

6. The system of claim 1, wherein the first register is a D-type flip-flop.

7. The system of claim 1, wherein the first clock signal is clock-controlled on a sloping clock edge or a signal edge opposite to the second clock signal.

8. The system of claim 1, wherein the input further comprises an input node for receiving the digital input signal; and wherein the system further comprises a first downsampler operable to receive the digital input signal from the input node and downsample the digital input signal to the first sampling rate.

9. The system of claim 8, wherein the system further comprises a third delay element coupled to receive the digital input signal and forward the second delayed digital input signal to a second downsampler, the second downsampler being operable to receive the second delayed digital input signal from the input node and downsample the second delayed digital input signal to the first sampling rate; The system further includes: The third processing branch includes a fourth delay element, which is operable to receive the second delayed digital input signal and output a third delayed digital input signal; The fourth processing branch includes a third adder operable to receive the second delayed digital input signal and subtract the second delayed feedback signal to generate a second difference signal. A fifth adder, operable to combine the third delayed digital input signal and the second difference signal to produce a second output signal; and The fourth processing branch further includes a second feedback path, which includes a fifth delay element operable to receive the second output signal and output the second delayed feedback signal.

10. The system of claim 9, further comprising a sixth adder operable to combine the output signal and the second output signal.

11. A method for digital signal processing, comprising: The digital input signal is received at the first filter stage of the multi-stage sampling rate converter; In the first processing branch of the first filter stage, the digital input signal is delayed to generate a delayed digital input signal; In the second processing branch of the first filter stage, the delayed feedback signal is subtracted from the digital input signal to generate the difference signal; The delayed input signal and the difference signal are combined to generate an output signal from the first filter stage; The delayed feedback signal is output by feeding back the delayed signal to the output signal through a delay element; The output signal is received at a first register electrically coupled between the first filter stage and the second filter stage; The first register is controlled using the first clock signal; as well as The first filter stage and the second filter stage are controlled by a second clock signal.

12. The method of claim 11, further comprising, in the second processing branch, applying filter coefficients to the difference signal to generate the difference signal.

13. The method of claim 11, wherein receiving the output signal at the first register includes delaying the output signal between the first filter stage and the second filter stage to reduce ripple.

14. The method of claim 13, further comprising forwarding the output signal from the first register to a second filter stage.

15. The method of claim 14, wherein the first register is a D-type flip-flop.

16. The method of claim 14, wherein the first clock signal is clock-controlled on a sloping clock edge or a signal edge opposite to the second clock signal.

17. The method of claim 16, wherein the first register is triggered on the positive edge of the first clock.

18. The method of claim 17, wherein the second filter stage is triggered on the negative edge of the first clock.

19. The method of claim 18, wherein the method includes an extractor and / or an interpolator process.

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