Display devices

Abstract

A display device includes: a display area and a peripheral area outside the display area; a first connection line in the display area, the first connection line including a first portion extending along a first column of the display area and located in the first column, a third portion extending along a second column of the display area and located in the second column, and a second portion connecting the first portion to the third portion; and a second connection line in the peripheral area, connected to the third portion of the first connection line and to a data line in the third column of the display area.

Description

Technical Field

[0001] Aspects of one or more example embodiments relate to a display apparatus. Background Art

[0002] With the rapid development of the display field that visually expresses various electrical signal information, various display devices with excellent characteristics such as thin thickness, light weight, and low power consumption have been introduced. In addition, in recent years, physical buttons and the like have been removed from the front surface of the display device to reduce the dead zone of the display device, and thus the display area is increasing.

[0003] The above information disclosed in the Background section is only for enhancement of understanding of the background technology and therefore the information discussed in the Background section does not necessarily constitute prior art. Summary of the Invention

[0004] Aspects of one or more example embodiments include a display device having a relatively reduced dead zone, which may be able to stably transmit data signals to pixels without increasing manufacturing costs.

[0005] According to one or more example embodiments, a display device includes: a substrate including a display area and a peripheral area outside the display area; a first connection line in the display area, including a first portion extending along a first column of the display area, a third portion extending along a second column of the display area, and a second portion connecting the first portion to the third portion; and a second connection line in the peripheral area, connected to the third portion of the first connection line and a data line in the third column of the display area.

[0006] According to some example embodiments, the first connection line and the second connection line may be on the same layer.

[0007] According to some example embodiments, the first connection line and the second connection line may be on different layers.

[0008] According to some example embodiments, the data line and the first connection line may be on different layers.

[0009] According to some example embodiments, the data line and the second connection line may be on different layers.

[0010] According to some example embodiments, the data line and the second connection line may be on the same layer.

[0011] According to some example embodiments, the display device may further include a third connection line in the peripheral area and connected to the first pad of the pad area located in the peripheral area and the first portion of the first connection line; and a fourth connection line in the peripheral area and connected to the second pad of the pad area and the data line in the first column.

[0012] According to some example embodiments, at least one pad may be further located between the first pad and the second pad.

[0013] According to some example embodiments, the first connection line and the third connection line may be on the same layer.

[0014] According to some example embodiments, the data lines in the first column and the fourth connection lines may be on the same layer.

[0015] According to some example embodiments, the display device may further include a pixel electrode on an upper layer of the first connection line.

[0016] According to some example embodiments, the second column may be immediately adjacent to the first column.

[0017] According to some example embodiments, the second column may be a column spaced apart from the first column by a plurality of columns.

[0018] According to some example embodiments, the third column may be immediately adjacent to the second column.

[0019] According to some example embodiments, the third column may be a column spaced apart from the second column by a plurality of columns.

[0020] According to some example embodiments, the display device may further include a third connection line in the peripheral area and connected to the first pad of the pad area located in the peripheral area and the first portion of the first connection line; and a fourth connection line in the peripheral area and connected to the second pad of the pad area and the data line in the fourth column of the display area.

[0021] According to one or more example embodiments, a display device includes: a substrate including a display area and a peripheral area outside the display area; a plurality of data lines arranged in the display area; a plurality of first connection lines arranged in the display area; and a plurality of second connection lines arranged in the peripheral area, wherein each of the first connection lines includes a first portion and a third portion extending in a first direction and spaced apart from each other by at least one column, and a second portion extending in a second direction different from the first direction and connecting the first portion to the third portion, and each of the second connection lines is connected to the third portion of one of the first connection lines and a data line in a column spaced apart from the third portion of the first connection line by at least one column.

[0022] According to some example embodiments, the second connection lines may be on a different layer from a layer where the first connection lines are arranged.

[0023] According to some example embodiments, each of the second connection lines may be a portion where a corresponding one of the first connection lines is turned to the peripheral area and extended.

[0024] According to some example embodiments, the display device may further include: a plurality of third connection lines arranged in the peripheral area; and a plurality of fourth connection lines arranged in the peripheral area, wherein each of the third connection lines can be connected to a first pad of the pad area located in the peripheral area and a first portion of one of the first connection lines, and each of the fourth connection lines can be connected to a second pad of the pad area and one of the data lines.

[0025] Additional aspects are set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented example embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other aspects, features and characteristics of certain example embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0027] Figure 1 is a plan view of an example of a display panel according to some example embodiments;

[0028] Figure 2A and Figure 2B is an equivalent circuit diagram of a pixel in a display panel according to some example embodiments;

[0029] Figure 3 and Figure 4 yes Figure 1 An example plan view of area A in FIG, and Figure 5 It is along Figure 4 A cross-sectional view taken along line II';

[0030] Figure 6 yes Figure 1 An example plan view of area B in FIG;

[0031] Figure 7 is a diagram of a pixel array according to some example embodiments;

[0032] Figure 8 It is applied Figure 7 The pixel array Figure 1 A plan view of an example of area C in FIG;

[0033] Figure 9A It is along Figure 8 A cross-sectional view taken along line II-II', and Figure 9B It is along Figure 8 A cross-sectional view taken along line III-III';

[0034] Figure 10 and Figure 11 It is applied Figure 7 The pixel array Figure 1 A plan view of another example of area C in FIG;

[0035] 12A to 12C It is along Figure 11 A cross-sectional view taken along line IV-IV';

[0036] Figure 13 is a diagram of a pixel array according to some example embodiments;

[0037] Figure 14 and Figure 15 It is applied Figure 13 The pixel array Figure 1 A plan view of an example of area C in FIG;

[0038] Figure 16 is a diagram of a pixel array according to some example embodiments;

[0039] Figure 17 and Figure 18 It is applied Figure 16 The pixel array Figure 1 A plan view of an example of area C in FIG;

[0040] Figure 19 is a perspective view of a display device including a display panel according to some example embodiments, and Figure 20A and Figure 20B Along Figure 19 A cross-sectional view taken along line V-V';

[0041] 21A to 21D is a cross-sectional view of a display panel according to some example embodiments; and

[0042] 22A to 22D is a cross-sectional view of a display panel according to some example embodiments. DETAILED DESCRIPTION

[0043] Reference will now be made in more detail to various aspects of some embodiments, examples of which are shown in the accompanying drawings, wherein the same reference numerals refer to the same elements throughout. In this regard, the present embodiments may have different forms and should not be construed as being limited to the description set forth herein. Therefore, the following description of example embodiments is provided solely with reference to the accompanying drawings to illustrate various aspects of the present description. The term "and / or" as used herein includes any and all combinations of one or more of the listed associated items. Expressions such as "at least one of..." modify the entire column of elements when following a column of elements, rather than modifying the individual elements in the column.

[0044] It will be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms.

[0045] An expression used in the singular encompasses expressions in the plural unless it has an obviously different meaning in the context.

[0046] It will be further understood that the terms “include” and / or “comprises” used herein specify the presence of stated features or elements, but do not preclude the presence or addition of one or more other features or elements.

[0047] It will be understood that when a layer, region, or element is referred to as being “formed on” another layer, region, or element, it can be directly or indirectly formed on the other layer, region, or element. That is, for example, intervening layers, regions, or elements may be present.

[0048] For the convenience of explanation, the size of the elements in the drawings may be exaggerated. In other words, since the size and thickness of the elements in the drawings are arbitrarily shown for the convenience of description, the following embodiments are not limited thereto.

[0049] Hereinafter, aspects of some example embodiments will be described in more detail with reference to the accompanying drawings. The same reference numerals are used to denote the same elements.

[0050] Figure 1 is a plan view of an example of a display panel 10 according to some example embodiments.

[0051] refer to Figure 1 The display panel 10 according to the embodiment has a display area DA in which an image is displayed and a peripheral area PA located outside the display area DA. It can be understood that the substrate 100 provided in the display panel 10 has the display area DA and the peripheral area PA.

[0052] A plurality of pixels PX and conductive lines capable of applying electrical signals to the plurality of pixels PX may be located in the display area DA.

[0053] Each of the plurality of pixels PX may include a display element and a circuit unit for driving the display element. For example, the display element may include an organic light emitting device, and the circuit unit may include a capacitor and a plurality of transistors.

[0054] Conductive lines that can apply electrical signals to the plurality of pixels PX may include a plurality of scan lines SL and a plurality of data lines DL. Each of the plurality of scan lines SL may extend in the y-direction, and each of the plurality of data lines DL may extend in the x-direction. For example, the plurality of scan lines SL may be arranged in a plurality of rows to transmit scan signals to the pixels PX, and the plurality of data lines DL may be arranged in a plurality of columns to transmit data signals to the pixels PX. Each of the plurality of pixels PX may be connected to a corresponding one of the plurality of scan lines SL and a corresponding one of the plurality of data lines DL.

[0055] In addition, a first connection line 201 for transmitting an electrical signal supplied from the pad area PADA to a conductive line connected to the pixel PX is located in the display area DA. For example, the first connection line 201 may be connected to the data line DL to transmit a data signal supplied from the pad area PADA to the data line DL. The first connection line 201 is connected to the display area DA by referring to FIG. Figure 8 The second connection line 203 , described in more detail, is connected to the data line DL to transmit the data signal supplied from the pad area PADA to the data line DL.

[0056] The first connection line 201 extends in the +x direction (first direction) at approximately the center of the display area DA in the y direction, then bends and extends in the y direction (second direction) perpendicular to the x direction toward the edge of the display area DA, and may bend again and extend in the -x direction (first direction). According to some example embodiments, the conductive line connecting the data line DL to the pad of the pad area PADA is located in the display area DA, thereby reducing the area of ​​the peripheral area PA and expanding the display area DA to reduce the dead zone of the display device.

[0057] The display area DA may be divided into a plurality of areas in the extending direction of the first connection line 201. For example, the display area DA may include a first area S1 in which the first connection line 201 extends in a first direction (+x direction, -x direction), a second area S2 in which the first connection line 201 extends in a second direction (y direction), and a third area S3 other than the first area S1 and the second area S2. Figure 6 As shown, the third area S3 may be an area where the first connection line 201 is not located and the first dummy pattern 300 is located. Each of the first area S1 and the second area S2 may have a plurality of triangular shapes. In more detail, the shape of the central first area S1 may be a triangle. The shapes of the second areas S2 on both sides of the central first area S1 may be inverted triangles. The first area S1 located outside the second area S2 may have a triangular shape.

[0058] The peripheral area PA may surround the display area DA. The peripheral area PA, which is an area where the pixels PX are not located, may include a pad area PADA. The pad area PADA is an area to which various electronic devices or a printed circuit board are electrically attached, and voltage lines for supplying power to drive the display device may be located therein. The plurality of pads of the pad area PADA may be electrically connected to a film on which the data driver D_IC is disposed. Figure 1A chip on film (COF) method is shown in which the data driver D_IC is arranged on a film electrically connected to pads on the substrate 100. According to some example embodiments, the data driver D_IC may be directly positioned on the substrate 100 by using a chip on glass (COG) or chip on plastic (COP) method.

[0059] The display panel 10 may include a fan-out area FOA in the peripheral area PA. The fan-out area FOA may be an area between the pad area PADA and the display area DA. A third connection line 205 and a fourth connection line 207 may be arranged in the fan-out area FOA. The third connection line 205 may be connected to the first connection line 201 to transmit a data signal supplied from the pad area PADA to the first connection line 201. The fourth connection line 207 may be connected to the data line DL to transmit a data signal supplied from the pad area PADA to the data line DL. The second connection line 203 may be arranged in the peripheral area PA.

[0060] Figure 1 It may be a plan view showing the state of the substrate 100, etc. during the manufacturing process of the display device. In a final display device or electronic device such as a smartphone including the display device, a portion of the substrate 100 may be bent to minimize or reduce the area of ​​the peripheral area PA recognized by the user.

[0061] Figure 2A and Figure 2B is an equivalent circuit diagram of a pixel in a display panel according to some example embodiments.

[0062] See also Figure 2A Pixel PX includes a pixel circuit PC and an organic light-emitting diode (OLED) connected to the pixel circuit PC as a display element. The pixel circuit PC may include a first transistor T1, a second transistor T2, and a capacitor Cst. Each pixel PX may emit, for example, red, green, blue, or white light from the organic light-emitting diode OLED. The first transistor T1 and the second transistor T2 may be thin film transistors.

[0063] The second transistor T2, which is a switching transistor, is connected to the scan line SL and the data line DL and can transmit a data signal input to the data line DL to the first transistor T1 according to a switching voltage input to the scan line SL. A capacitor Cst is connected to the second transistor T2 and a power supply voltage line PL and can store a voltage corresponding to the difference between a voltage corresponding to the data signal received from the second transistor T2 and a first power supply voltage ELVDD supplied to the power supply voltage line PL. The power supply voltage line PL can be spaced apart from and parallel to the scan line SL or the data line DL.

[0064] The first transistor T1 is a driving transistor connected to the power supply voltage line PL and the capacitor Cst, and can control the driving current Ioled flowing from the power supply voltage line PL to the organic light emitting diode OLED according to the voltage value stored in the capacitor Cst. The organic light emitting diode OLED can emit light with a specific brightness according to the driving current Ioled. The counter electrode (e.g., cathode) of the organic light emitting diode OLED can be supplied with a second power supply voltage ELVSS.

[0065] Figure 2A The pixel circuit PC is shown to include two transistors and one capacitor, but the present disclosure is not limited thereto. The number of transistors and the number of capacitors may vary depending on the design of the pixel circuit PC.

[0066] Figure 2B The signal lines SL1, SL2, EL, and DL, the initialization voltage line VIL, and the power supply voltage line PL provided for each pixel PX are shown. However, the present disclosure is not limited thereto. According to some example embodiments, at least one of the signal lines SL1, SL2, EL, and DL, the initialization voltage line VIL, and / or the power supply voltage line PL may be shared by adjacent pixels.

[0067] The signal lines include a first scan line SL1 for transmitting a first scan signal GW, a second scan line SL2 for transmitting a second scan signal GI, an emission control line EL for transmitting an emission control signal EM, and a data line DL that crosses the first scan line SL1 and transmits a data signal DATA. The second scan line SL2 can be connected to the first scan line SL1 of the next or previous row, and the second scan signal GI can be the first scan signal GW of the next or previous row.

[0068] The power voltage line PL transmits the first power voltage ELVDD to the first transistor T1 , and the initialization voltage line VIL transmits an initialization voltage VINT for initializing the first transistor T1 and the pixel electrode of the organic light emitting diode OLED.

[0069] The first and second scan lines SL1 and SL2, the emission control line EL, and the initialization voltage line VIL may extend in the y direction and may be spaced apart from each other in each row. The data line DL and the power supply voltage line PL may extend in the x direction and may be spaced apart from each other in each column.

[0070] The pixel circuit PC of the pixel PX may include a plurality of transistors (first to seventh transistors) T1 to T7 and a capacitor Cst. The first to seventh transistors T1 to T7 may be thin film transistors.

[0071] The first transistor T1 is connected to the power supply voltage line PL via the fifth transistor T5 and is electrically connected to the pixel electrode of the organic light emitting diode OLED via the sixth transistor T6. The first transistor T1 functions as a driving transistor and receives a data signal DATA according to the switching operation of the second transistor T2 to supply a driving current Ioled to the organic light emitting diode OLED.

[0072] The second transistor T2 is connected to the first scan line SL1 and the data line DL, and is turned on in response to the first scan signal GW received through the first scan line SL1 to perform a switching operation for transmitting the data signal DATA transmitted to the data line DL to the node N.

[0073] The third transistor T3 is connected to the pixel electrode of the organic light emitting diode OLED via the sixth transistor T6 . The third transistor T3 is turned on in response to a first scan signal GW received through the first scan line SL1 to diode-connect the first transistor T1 .

[0074] The fourth transistor T4 is turned on in response to the second scan signal GI received through the second scan line SL2 to transfer the initialization voltage VINT from the initialization voltage line VIL to the gate electrode of the first transistor T1 , thereby initializing the gate voltage of the first transistor T1 .

[0075] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on in response to the emission control signal EM received through the emission control line EL to form a current path so that the driving current Ioled can flow from the power voltage line PL to the organic light emitting diode OLED.

[0076] The seventh transistor T7 is turned on in response to the second scan signal GI received through the second scan line SL2 to transmit the initialization voltage VINT from the initialization voltage line VIL to the pixel electrode of the organic light emitting diode OLED, thereby initializing the pixel electrode of the organic light emitting diode OLED. The seventh transistor T7 may be omitted.

[0077] Although Figure 2B The fourth transistor T4 and the seventh transistor T7 are connected to the second scan line SL2, but the present disclosure is not limited thereto. According to some example embodiments, the fourth transistor T4 may be connected to the second scan line SL2, and the seventh transistor T7 may be connected to a separate conductive line to be driven according to a signal transmitted to the conductive line.

[0078] The capacitor Cst is connected to the power voltage line PL and the gate electrode of the first transistor T1 and may maintain a voltage applied to the gate electrode of the first transistor T1 by storing and maintaining a voltage corresponding to a difference between voltages across it.

[0079] The organic light emitting diode OLED includes a pixel electrode and a common electrode facing the pixel electrode, and the common electrode thereof can receive the second power voltage ELVSS. The organic light emitting diode OLED receives the driving current Ioled from the first transistor T1 and emits light to display an image.

[0080] Figure 3 and Figure 4 It is schematically shown Figure 1 An example plan view of area A. Figure 5 It is along Figure 4 A cross-sectional view taken along line II'.

[0081] refer to Figure 3 Each of the first connection lines 201 may include a first portion 201a extending in the +x direction in the first region S1, a second portion 201b extending from the first portion 201a in the y direction (-y or +y direction) in the second region S2, and a ( Figure 8 ) Part III 201c.

[0082] The first portion 201a of the first connection line 201 may extend and be positioned in one of the plurality of columns. The third portion 201c of the first connection line 201 may extend and be positioned in a column that is spaced at least one column away from the column where the first portion 201a is located. For example, the first portion 201a and the third portion 201c being spaced at least one column apart may mean that the distance (or gap) between the column of the first portion 201a and the column of the third portion 201c is one column.

[0083] The first pattern area A1 divided between the first portions 201a of adjacent first connecting lines 201 can be located in the first area S1. The first dummy pattern 211, the second dummy pattern 213, and the third dummy pattern 215 can be arranged in the first pattern area A1. The first dummy pattern 211 and the second portion 201b of the first connecting line 201 can be located on an imaginary straight line in the direction in which the second portion 201b extends. The first dummy pattern 211 and the second dummy pattern 213 can be connected to each other by a branch 212 protruding from the first dummy pattern 211. The branch 212 is a part of the first dummy pattern 211 and can be a dummy pattern. The first dummy pattern 211, the branch 212, and the second dummy pattern 213 can be formed integrally. Similarly, the first pattern area A1 divided between the third portions 201c of adjacent first connecting lines 201 can be located in the first area S1.

[0084] The second pattern area A2 divided between the second portions 201b of adjacent first connecting lines 201 may be located in the second area S2. The first dummy pattern 221, the second dummy pattern 223, and the third dummy pattern 225 may be arranged in the second pattern area A2. The first dummy pattern 221 and the first portion 201a of the first connecting line 201 may be located on an imaginary straight line in the direction in which the first portion 201a extends. Similarly, the first dummy pattern 221 and the third portion 201c of the first connecting line 201 may be located on an imaginary straight line in the direction in which the third portion 201c extends. The first dummy pattern 221 and the second dummy pattern 223 may be connected to each other via a branch 222 protruding from the first dummy pattern 211 in the second direction. The branch 222 is a portion of the first dummy pattern 221 and may be a dummy pattern. The first dummy pattern 221, the branch 222, and the second dummy pattern 223 may be formed integrally.

[0085] The first connection line 201, the first dummy pattern 211, the second dummy pattern 213, and the third dummy pattern 215 of the first pattern area A1, and the branch 212, and the first dummy pattern 221, the second dummy pattern 223, and the third dummy pattern 225 of the second pattern area A2, and the branch 222 can be arranged on the same layer. The shapes of the second dummy pattern 213 and the third dummy pattern 215 of the first pattern area A1 are similar to the shapes of the second dummy pattern 223 and the third dummy pattern 225 of the second pattern area A2, respectively.

[0086] Since the reflection characteristics of light in the first and second areas S1 and S2 are similar due to the first and second pattern areas A1 and A2, the first and second areas S1 and S2 may be prevented, minimized, or reduced from being divided and recognized according to the incident angle of light.

[0087] The display element may be located on the first connection line 201. In the following, the display element will be described in more detail. Figure 4 and Figure 5 .

[0088] The display panel 10 includes a substrate 100. The substrate 100 may include various flexible or bendable materials, for example, a polymer resin such as polyethersulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate (PAR), polyimide (PI), polycarbonate (PC), or cellulose acetate propionate (CAP). In addition, the substrate 100 may have a multilayer structure including two layers of polymer resin and a barrier layer between the two layers including an inorganic material (such as silicon oxide, silicon nitride, silicon oxynitride, etc.), and various modifications may be made thereto.

[0089] A plurality of pixels PX may be arranged in the display area DA of the substrate 100. Each pixel PX may have a capacitor Cst, a thin film transistor TFT, and a display element 130 electrically connected to the thin film transistor TFT. The display element 130 may be Figure 2A and Figure 2B Organic light emitting diode OLED. Thin film transistor TFT can be Figure 2A and Figure 2B For example, Figure 5 The thin film transistor TFT shown in FIG can be Figure 2A and Figure 2B The first transistor T1.

[0090] If necessary, a buffer layer 111 may be formed on the substrate 100. The buffer layer 111 may flatten the surface of the substrate 100 or prevent impurities from penetrating into the semiconductor layer thereon. The buffer layer 111 may have a single-layer / multi-layer structure including an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The buffer layer 111 may be omitted.

[0091] The thin film transistor TFT may be on the buffer layer 111. The thin film transistor TFT may include a semiconductor layer 121, a gate electrode 122, a source electrode 123S, and a drain electrode 123D.

[0092] The semiconductor layer 121 may include amorphous silicon, polycrystalline silicon, or an organic semiconductor material. The semiconductor layer 121 may include a source region, a drain region, and a channel region between the source region and the drain region.

[0093] Taking into account adhesion with adjacent layers, surface flatness of layers to be stacked, and processability, the gate electrode 122 can be formed of materials such as aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

[0094] The first insulating layer 112 may be between the semiconductor layer 121 and the gate electrode 122. The second insulating layer 113 and the third insulating layer 114 may be disposed between the gate electrode 122 and the source electrode 123S and the drain electrode 123D. The first insulating layer 112, the second insulating layer 113, and the third insulating layer 114 may include an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride. According to some example embodiments, Figure 2A and Figure 2B The scan lines SL, SL1 and SL2 and the emission control line EL may be on the same layer as the gate electrode 122 , that is, on the first insulating layer 112 .

[0095] The source electrode 123S and the drain electrode 123D may be electrically connected to the source region and the drain region of the semiconductor layer 121 , respectively, through contact holes formed in the first insulating layer 112 , the second insulating layer 113 , and the third insulating layer 114 .

[0096] The source electrode 123S and the drain electrode 123D may include at least one material selected from Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and Cu, and may be a single layer or a multilayer.

[0097] The capacitor Cst includes a lower electrode CE1 and an upper electrode CE2 that overlap each other with a second insulating layer 113 therebetween. The capacitor Cst may overlap with the thin film transistor TFT. In this regard, Figure 5 It is shown that the gate electrode 122 of the thin film transistor TFT is the lower electrode CE1 of the capacitor Cst. According to some example embodiments, the capacitor Cst may not overlap with the thin film transistor TFT, and the lower electrode CE1 of the capacitor Cst may be an independent element separated from the gate electrode 122 of the thin film transistor TFT. The capacitor Cst may be covered with a third insulating layer 114. According to some example embodiments, Figure 2B The initialization voltage line VIL may be on the same layer as the upper electrode CE2 of the capacitor Cst, that is, on the second insulating layer 113 .

[0098] The pixel circuit including the thin film transistor TFT and the capacitor Cst may be covered with a fourth insulating layer 115 and a fifth insulating layer 116. The fourth insulating layer 115 and the fifth insulating layer 116 may be organic insulating layers serving as planarization insulating layers. The fourth insulating layer 115 and the fifth insulating layer 116 may include an organic insulating material such as a general commercial polymer, such as polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative including a phenol group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine-based polymer, a paraxylene-based polymer, a vinyl alcohol polymer, and a mixture thereof. According to some example embodiments, the fourth insulating layer 115 and the fifth insulating layer 116 may include polyimide.

[0099] Meanwhile, various conductive layers may be further arranged on the third insulating layer 114. For example, the data line DL and the power supply voltage line PL may be on the third insulating layer 114, i.e., on the same layer as the source electrode 123S and the drain electrode 123D. The data line DL and the power supply voltage line PL may include the same material as the source electrode 123S and the drain electrode 123D. The data line DL and the power supply voltage line PL may include a conductive material including Mo, Al, Cu, or Ti, and may be formed as a single layer or multiple layers including the above materials. For example, the data line DL and the power supply voltage line PL may have a multilayer structure of Ti / Al / Ti.

[0100] The fourth insulating layer 115 may be on the data line DL and the power voltage line PL. Figure 5 As shown in FIG, the first connection line 201 and the dummy patterns 211, 212, 213, 215, 221, 222, 223, and 225 may be on the fourth insulating layer 115. The first connection line 201 and the dummy patterns 211, 212, 213, 215, 221, 222, 223, and 225 may be a single layer or multiple layers including at least one of Al, Cu, Ti, and alloys thereof. For example, the first connection line 201 and the dummy patterns 211, 212, 213, 215, 221, 222, 223, and 225 may have a multilayer structure of Ti / Al / Ti.

[0101] The fifth insulating layer 116 may be on the first connection line 201 and the dummy patterns 211, 212, 213, 215, 221, 222, 223, and 225. According to some example embodiments, at least a portion of the first portion 201a and the third portion 201c of the first connection line 201 may overlap with the data line DL or the power voltage line PL. At least a portion of the second portion 201b of the first connection line 201 may overlap with one of the scan line SL, the emission control line EL, and the initialization voltage line VIL.

[0102] The display element 130 may be on the fifth insulating layer 116 . The display element 130 may include a pixel electrode 131 , an opposing electrode 135 , and an intermediate layer 133 between the pixel electrode 131 and the opposing electrode 135 .

[0103] The pixel electrode 131 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). According to some example embodiments, the pixel electrode 131 may include a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a compound thereof. According to some example embodiments, the pixel electrode 131 may further include a film formed of ITO, IZO, ZnO, or In2O3 above or below the reflective layer.

[0104] The shielding member 150 may be further above the fifth insulating layer 116. The shielding member 150 extends in the y direction along a portion of the edge of the pixel electrode 131 so as not to overlap with the pixel electrode 131 in a plan view, and may be located above or below a portion of each row. The shielding member 150 may have a straight line shape or a sawtooth shape extending in the second direction according to the arrangement of the pixel electrodes 131 in the same row. The shielding member 150 may include a light-shielding metal. For example, the shielding member 150 may include Mo, Al, Cu, or Ti, etc., and may be a single layer or multiple layers including the above materials. According to some example embodiments, the shielding member 150 may have a multilayer structure of Ti / Al / Ti. The shielding member 150 may include the same material as the pixel electrode 131. The shielding members 150 are spaced apart from each other and may be provided separately for each row. The shielding member 150 may be floating or electrically connected to a constant voltage line (e.g., a power voltage line PL, an initialization voltage line VIL, etc.) to receive a constant voltage.

[0105] The sixth insulating layer 117 covering the edge of the pixel electrode 131 may be on the fifth insulating layer 116. The sixth insulating layer 117 may define the pixel PX by having an opening OP exposing a portion of the pixel electrode 131. The sixth insulating layer 117 may include an organic material such as acryl, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO). Alternatively, the sixth insulating layer 117 may include the inorganic material described above.

[0106] The intermediate layer 133 may be formed on the pixel electrode 131 exposed by the opening OP of the sixth insulating layer 117. The intermediate layer 133 includes a light-emitting layer. The light-emitting layer may include a polymer or a low molecular weight organic material that emits light of a specific color. The light-emitting layer may be a red light-emitting layer, a green light-emitting layer, or a blue light-emitting layer. Alternatively, the light-emitting layer may have a multilayer structure in which a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer are stacked, or may have a single-layer structure including a red light-emitting material, a green light-emitting material, and a blue light-emitting material to emit white light. According to some example embodiments, the intermediate layer 133 may include a first functional layer below the light-emitting layer and / or a second functional layer above the light-emitting layer. The first functional layer and / or the second functional layer may include an integral layer above all the pixel electrodes 131, or may have a layer patterned to correspond to each of the pixel electrodes 131.

[0107] The first functional layer may be a single layer or a multilayer. For example, when the first functional layer comprises a polymer material, the first functional layer may be a hole transport layer (HTL) having a single layer structure and may comprise poly(3,4-ethylenedioxythiophene) (PEDOT) or polyaniline (PANI). When the first functional layer is formed of a low molecular weight material, the first functional layer may comprise a hole injection layer (HIL) and a hole transport layer (HTL).

[0108] The second functional layer may be omitted. For example, when the first functional layer and the light-emitting layer are formed of a polymer material, a second functional layer may be formed to improve the characteristics of the organic light-emitting diode. The second functional layer may be a single layer or a multilayer. The second functional layer may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0109] The counter electrode 135 is arranged to face the pixel electrode 131, with the intermediate layer 133 located therebetween. The counter electrode 135 may include a conductive material having a low work function. For example, the counter electrode 135 may include a (semi-) transparent electrode including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or an alloy thereof. Alternatively, the counter electrode 135 may further include a layer such as ITO, IZO, ZnO, or In2O3 on the (semi-) transparent layer including the above materials.

[0110] Figure 6 yes Figure 1 An example plan view of area B.

[0111] See also Figure 6, the first dummy pattern 300 may be located in the third area S3. The first dummy pattern 300 may include a plurality of first portions 301 extending in the x-direction and spaced apart from each other, and a plurality of second portions 302 extending in the y-direction to intersect with the first portions 301 and spaced apart from each other. The first dummy pattern 300 may have a lattice structure in which the plurality of first portions 301 and the plurality of second portions 302 are connected to each other. The third pattern area A3 may be divided by the first dummy pattern 300 in the third area S3. Branches 312 protruding from the first portions 301, a second dummy pattern 313, and a third dummy pattern 315 may be arranged in the third pattern area A3. The second dummy pattern 313 may be connected to the first dummy pattern 300 via the branches 312. The branches 312 are part of the first dummy pattern 300 and may be dummy patterns. The first dummy pattern 300, the branches 312, and the second dummy pattern 313 may be formed integrally.

[0112] The first dummy pattern 300, the second dummy pattern 313, the third dummy pattern 315, and the branch 312 may be arranged on the same layer. The first dummy pattern 300 may be on the same layer as the first connection line 201. The first dummy pattern 300 may include the same material as the first connection line 201.

[0113] ( Figure 5 A fifth insulating layer 116 is on the first dummy pattern 300 , the second dummy pattern 313 , the third dummy pattern 315 , and the branches 312 , and the display element 130 and the blocking member 150 may be on the fifth insulating layer 116 .

[0114] Figure 7 is a diagram of a pixel array according to some example embodiments.

[0115] refer to Figure 7 In the display area DA1, a plurality of pixels PX may be arranged along columns in the x-direction and rows in the y-direction. The pixels PX may include a plurality of first pixels PX1 displaying a first color, a plurality of second pixels PX2 displaying a second color, and a plurality of third pixels PX3 displaying a third color. According to some example embodiments, the first pixels PX1 may be red pixels R, the second pixels PX2 may be green pixels G, and the third pixels PX3 may be blue pixels B.

[0116] The first pixel PX1 and the third pixel PX3 may be alternately arranged in the x-direction in the first column C1 and electrically connected to the first data line DL1. The second pixel PX2 may be repeatedly arranged in the second column C2 adjacent to the first column C1 and electrically connected to the second data line DL2. In the third column C3 adjacent to the second column C2, the first pixel PX1 and the third pixel PX3 may be alternately arranged in the x-direction and electrically connected to the third data line DL3. The arrangement of the first pixel PX1 and the third pixel PX3 in the third column C3 may be opposite to the arrangement of the first pixel PX1 and the third pixel PX3 in the first column C1. The second pixel PX2 may be repeatedly arranged in the fourth column C4 adjacent to the third column C3 and electrically connected to the fourth data line DL4. The first to fourth columns C1 to C4 may repeat in the y-direction.

[0117] Figure 8 It is applied Figure 7 The pixel array Figure 1 An example plan view of area C in FIG. Figure 9A It is along Figure 8 A cross-sectional view taken along line II-II', and Figure 9B It is along Figure 8 A cross-sectional view taken along line III-III'.

[0118] refer to Figure 8 In the display area DA1, the first data line DL1 may be located in each of the first columns C1, the second data line DL2 may be located in each of the second columns C2, the third data line DL3 may be located in each of the third columns C3, and the fourth data line DL4 may be located in each of the fourth columns C4. The first to fourth data lines DL1 to DL4 may be repeated in the y direction.

[0119] The plurality of connection lines 200 may include a plurality of first connection lines 201 and a plurality of second connection lines 203. The first connection lines 201 may be arranged in the display area DA1, and the second connection lines 203 may be arranged in the peripheral area PA.

[0120] Each of the first connection lines 201 may include a first portion 201a extending in the +x direction, a second portion 201b extending in the y direction, and a third portion 201c extending in the -x direction. The second portion 201b may connect the first portion 201a and the third portion 201c to each other. Each of the first portion 201a and the third portion 201c is located in one of the first to fourth columns C1 to C4, parallel to one of the first to fourth data lines DL1 to DL4. The column where the first portion 201a is located and the column where the third portion 201c is located may be separated by at least one column. For example, in the first connection line 201_1 among the first connection lines 201, the column where the third portion 201c is located may be the column immediately adjacent to the column where the first portion 201a is located. In the first connection lines 201 other than the first connection line 201_1 among the first connection lines 201, the column where the third portion 201c is located may be separated by at least one column from the column where the first portion 201a is located.

[0121] The second connection line 203 may be arranged in the peripheral area PA outside the fan-out area FOA. The second connection line 203 may be the portion where the third portion 201c of the first connection line 201 changes direction and extends from the boundary between the display area DA1 and the peripheral area PA to the first contact portion CNT1. In this case, the second connection line 203 may be formed integrally with the first connection line 201. The second connection line 203 may be connected to the data line DL at the first contact portion CNT1 located in the peripheral area PA. The second connection line 203 may be connected to a data line arranged in a column different from the column where the third portion 201c of the first connection line 201 is located. The column where the data line connected to the second connection line 203 is located and the column where the third portion 201c of the first connection line 201 is connected to the second connection line 203 may be separated by at least one column. For example, the column where the data line connected to the second connection line 203 is located may be the column immediately adjacent to the column where the third portion 201c of the first connection line 201 is connected to the second connection line 203. The two second connection lines 203 may be spaced apart from each other between two adjacent columns.

[0122] Due to the second connection lines 203, the first connection lines 201 do not cross each other in the display area DA1, and the first connection lines 201 can transmit the first to third data signals Dr, Dg and Db to the first to fourth data lines DL1 to DL4 according to the order of the first to third data signals Dr, Dg and Db regularly output by the data driver D_IC.

[0123] The plurality of connection lines 200 may further include a plurality of third connection lines 205 and a plurality of fourth connection lines 207. The third connection lines 205 and the fourth connection lines 207 may be arranged in the peripheral area PA. The third connection lines 205 and the fourth connection lines 207 may be arranged in the fan-out area FOA.

[0124] Each of the third connection lines 205 may be connected to one of the plurality of pads arranged in the pad area PADA and one end (i.e., the first portion 201a) of one of the first connection lines 201. According to some example embodiments, the third connection lines 205 may be formed integrally with the first connection lines 201. According to some example embodiments, the third connection lines 205 may be formed separately from the first connection lines 201 to be electrically connected to the first connection lines 201 by contacting the first connection lines 201 of the same layer. According to some example embodiments, the third connection lines 205 may be connected to the first portion 201a of the first connection lines 201 through a contact hole passing through an insulating layer between the first connection lines 201 and the third connection lines 205 on another layer of the third connection lines 205.

[0125] Each of the fourth connection lines 207 may be connected to one of the plurality of pads arranged in the pad area PADA and one of the plurality of data lines DL. The fourth connection line 207 may be on the same layer as the data line DL. According to some example embodiments, the fourth connection line 207 may be formed integrally with the data line DL. According to some example embodiments, the fourth connection line 207 may be formed separately from the data line DL so as to be electrically connected to the data line DL by contacting the data line DL of the same layer. According to some example embodiments, the fourth connection line 207 may be connected to the data line DL through a contact hole passing through an insulating layer between the data line DL and the fourth connection line 207 on another layer of the fourth connection line 207. The third connection line 205 and the fourth connection line 207 may be on different layers with an insulating layer located therebetween.

[0126] Figure 9A is a cross-sectional view showing a positional relationship between the data line DL, the first connection line 201 and the second connection line 203, and Figure 9B is a cross-sectional view illustrating a positional relationship among the data line DL, the first connection line 201 , the third connection line 205 , and the fourth connection line 207 .

[0127] like Figure 9AAs shown in FIG, the data line DL may be located on the third insulating layer 114, and the second connection line 203 may be located on the fourth insulating layer 115. The second connection line 203 may be electrically connected to the data line DL through a contact hole of the fourth insulating layer 115 in the first contact portion CNT1. The second connection line 203 may be connected to the third portion 201c of the first connection line 201. The first portion 201a and the third portion 201c of the first connection line 201 may at least partially overlap with the data line DL, or may not overlap with the data line DL.

[0128] like Figure 9B As shown in , the fourth connection line 207 may be located on the third insulating layer 114, and the third connection line 205 may be located on the fourth insulating layer 115. Figure 9B In the embodiment, the first portion 201a of the first connection line 201 does not overlap with the data line DL, but according to some example embodiments, the first portion 201a of the first connection line 201 may overlap with the data line DL. Figure 9B In the embodiment, the third connection line 205 does not overlap with the fourth connection line 207 , but according to some example embodiments, the third connection line 205 may overlap with the fourth connection line 207 .

[0129] Reference again Figure 8 , a plurality of pads are arranged in the pad area PADA to transmit the first to third data signals Dr, Dg and Db applied from the data driver D_IC to the third connection line 205 and the fourth connection line 207. The first data signal Dr and the third data signal Db can be alternately applied to the first pad P1, the third pad P3, the fifth pad P5 and the seventh pad P7, etc., which are odd-numbered pads. The second data signal Dg can be applied to the second pad P2, the fourth pad P4, the sixth pad P6 and the eighth pad P8, etc., which are even-numbered pads. In the two pad units, the fourth connection line 207 and the third connection line 205 can be alternately connected to the pads. For example, the fourth connection line 207 can be connected to the first pad P1 and the second pad P2, and the third connection line 205 can be connected to the third pad P3 and the fourth pad P4.

[0130] Hereinafter, for convenience of explanation, the transmission paths of data signals will be described using the first to fourth data lines DL1 to DL4 in the first to fourth column groups CG1 to CG4 from the left, respectively. Figure 8 In the embodiment, the second connection line 203 may be arranged between the first connection line 201 and the data line DL in two columns.

[0131] The first data signal Dr may be applied to the first pixel PX1, the second data signal Dg may be applied to the second pixel PX2, and the third data signal Db may be applied to the third pixel PX3. The first data signal Dr or the third data signal Db may be applied to the first data line DL1 of the first column C1 and the third data line DL3 of the third column C3. The second data signal Dg may be applied to the second data line DL2 of the second column C2 and the fourth data line DL4 of the fourth column C4.

[0132] The first data signal Dr or the third data signal Db can be applied to the first data line DL1 in the third column group CG3 via the fourth connection line 207_1 connected to the first pad P1. The second data signal Dg can be applied to the second data line DL2 in the third column group CG3 via the fourth connection line 207_2 connected to the second pad P2. The first data signal Dr or the third data signal Db can be applied to the third data line DL3 in the second column group CG2 via the third connection line 205_1, the first connection line 201_1, and the second connection line 203_1 connected to the third pad P3. The second data signal Dg can be applied to the fourth data line DL4 in the second column group CG2 via the third connection line 205_2, the first connection line 201_2, and the second connection line 203_2 connected to the fourth pad P4.

[0133] The first data signal Dr or the third data signal Db can be applied to the third data line DL3 in the third column group CG3 via the fourth connection line 207_3 connected to the fifth pad P5. The second data signal Dg can be applied to the fourth data line DL4 in the third column group CG3 via the fourth connection line 207_4 connected to the sixth pad P6. The first data signal Dr or the third data signal Db can be applied to the first data line DL1 in the second column group CG2 via the third connection line 205_3, the first connection line 201_3, and the second connection line 203_3 connected to the seventh pad P7. The second data signal Dg can be applied to the second data line DL2 in the second column group CG2 via the third connection line 205_4, the first connection line 201_4, and the second connection line 203_4 connected to the eighth pad P8.

[0134] Similarly, the first to third data signals Dr, Dg and Db applied to the ninth to sixteenth pads P9 to P16 can be applied to the first to fourth data lines DL1 to DL4 in the fourth column group CG4 and the first column group CG1 through the first to fourth connection lines 201, 203, 205 and 207.

[0135] Figure 10 It is applied Figure 7 The pixel array Figure 11 is a plan view of another example of the region C in FIG. Hereinafter, a detailed description of the same configuration as described above will not be given herein.

[0136] refer to Figure 10 , four second connection lines 203 can be spaced apart from each other between four adjacent columns. The second connection lines 203 can be connected to a data line arranged in a column different from the column where the third portion 201c of the first connection line 201 is located. The column where the data line connected to the second connection line 203 is located and the column where the third portion 201c of the first connection line 201 connected to the second connection line 203 is located can be spaced apart from at least one column. In some of the second connection lines 203 (e.g., second connection lines 203_2 and 203_3), the column where the data line connected to the second connection line 203 is located can be a column adjacent to the column where the third portion 201c of the first connection line 201 connected to the second connection line 203 is located. In some of the second connection lines 203 (e.g., second connection lines 203_1 and 203_4), the column where the data line connected to the second connection line 203 is located can be a column spaced apart from the column where the third portion 201c of the first connection line 201 connected to the second connection line 203 is located by multiple columns (e.g., three columns).

[0137] In the four pad units, the fourth connection line 207 and the third connection line 205 may be alternately connected to the pads. For example, the fourth connection line 207 may be connected to the first to fourth pads P1 to P4, and the third connection line 205 may be connected to the fifth to eighth pads P5 to P8.

[0138] Hereinafter, the transmission paths of data signals will be described using the first to fourth data lines DL1 to DL4 in the first to fourth column groups CG1 to CG4 from the left, respectively. Figure 10 In the embodiment, the number of output channels of the data driver D_IC is four, and the second connection lines 203 may route the first connection lines 201 and the data lines DL between the four columns.

[0139] The first data signal Dr or the third data signal Db can be applied to the first data line DL1 in the third column group CG3 through the fourth connection line 207_1 connected to the first pad P1. The second data signal Dg can be applied to the second data line DL2 in the third column group CG3 through the fourth connection line 207_2 connected to the second pad P2. The first data signal Dr or the third data signal Db can be applied to the third data line DL3 in the third column group CG3 through the fourth connection line 207_3 connected to the third pad P3. The second data signal Dg can be applied to the fourth data line DL4 in the third column group CG3 through the fourth connection line 207_4 connected to the fourth pad P4.

[0140] The first data signal Dr or the third data signal Db can be applied to the first data line DL1 in the second column group CG2 through the third connection line 205_1, the first connection line 201_1, and the second connection line 203_1 connected to the fifth pad P5. The second data signal Dg can be applied to the second data line DL2 in the second column group CG2 through the third connection line 205_2, the first connection line 201_2, and the second connection line 203_2 connected to the sixth pad P6. The first data signal Dr or the third data signal Db can be applied to the third data line DL3 in the second column group CG2 through the third connection line 205_3, the first connection line 201_3, and the second connection line 203_3 connected to the seventh pad P7. The second data signal Dg can be applied to the fourth data line DL4 in the second column group CG2 through the third connection line 205_4, the first connection line 201_4, and the second connection line 203_4 connected to the eighth pad P8.

[0141] Similarly, the first to third data signals Dr, Dg and Db applied to the ninth to sixteenth pads P9 to P16 can be applied to the first to fourth data lines DL1 to DL4 in the fourth column group CG4 and the first column group CG1 through the first to fourth connection lines 201, 203, 205 and 207.

[0142] Figure 11 It is applied Figure 7 The pixel array Figure 1 A plan view of another example of area C in FIG. 12A to 12C It is along Figure 11 A cross-sectional view taken along line IV-IV'. 12A to 12C is a diagram showing the positional relationship between the data line DL, the first connection line 201 and the second connection line 203'. Figure 10 Detailed description of the same configuration in .

[0143] refer to Figure 11 , one end of each of the second connection lines 203 ′ may be connected to the data line DL, and the other end thereof may be connected to the third portion 201 c of the first connection line 201 .

[0144] According to some example embodiments, Figure 12AAs shown in FIG, the second connection line 203′ may be located on the second insulating layer 113, the data line DL may be located on the third insulating layer 114, and the first connection line 201 may be located on the fourth insulating layer 115. One end of the second connection line 203′ may be electrically connected to the data line DL through a contact hole in the third insulating layer 114 in the first contact portion CNT1. The other end of the second connection line 203′ may be electrically connected to the third portion 201c of the first connection line 201 through contact holes in the third insulating layer 114 and the fourth insulating layer 115 in the second contact portion CNT2. The second connection line 203′ may include the same material as that of the upper electrode CE2 of the capacitor Cst.

[0145] According to some example embodiments, Figure 12B As shown in FIG, a second connection line 203′ may be on the first insulating layer 112. One end of the second connection line 203′ may be electrically connected to the data line DL through the contact holes of the second insulating layer 113 and the third insulating layer 114 in the first contact portion CNT1. The other end of the second connection line 203′ may be electrically connected to the third portion 201c of the first connection line 201 through the contact holes of the second insulating layer 113, the third insulating layer 114, and the fourth insulating layer 115 in the second contact portion CNT2. The second connection line 203′ may include the same material as that of the lower electrode CE1 of the capacitor Cst.

[0146] According to some example embodiments, Figure 12C As shown in FIG, the second connection line 203' can be on the same layer as the data line DL, that is, on the third insulating layer 114. One end of the second connection line 203' can be connected to the data line DL, and the other end thereof can be electrically connected to the third portion 201c of the first connection line 201 through the contact hole of the fourth insulating layer 115 in the second contact portion CNT2. The second connection line 203' can be a portion of the data line DL extending to the peripheral area PA. The second connection line 203' can be formed integrally with the data line DL.

[0147] 12A to 12C The arrangement of the data line DL, the first connection line 201 and the second connection line 203' can be similarly applied to Figure 8 Example of .

[0148] Figure 13 is a diagram of a pixel array according to some example embodiments.

[0149] refer to Figure 13In the display area DA2, a plurality of pixels PX may be arranged along columns in the x-direction and rows in the y-direction. The pixels PX may include a plurality of first pixels PX1 displaying a first color, a plurality of second pixels PX2 displaying a second color, and a plurality of third pixels PX3 displaying a third color. According to some example embodiments, the first pixels PX1 may be red pixels R, the second pixels PX2 may be green pixels G, and the third pixels PX3 may be blue pixels B.

[0150] The first pixel PX1 may be repeatedly arranged in the x-direction in the first column C1 and electrically connected to the first data line DL1. The second pixel PX2 may be repeatedly arranged in the x-direction in the second column C2 adjacent to the first column C1 and electrically connected to the second data line DL2. The third pixel PX3 may be repeatedly arranged in the x-direction in the third column C3 adjacent to the second column C2 and electrically connected to the third data line DL3. The first to third columns C1 to C3 may be repeated in the y-direction.

[0151] Figure 14 It is applied Figure 13 The pixel array Figure 1 Hereinafter, the following will mainly describe the example of the area C in FIG. Figure 8 The configuration is different from the configuration.

[0152] refer to Figure 14 In the display area DA2, the first data line DL1 may be located in each of the first columns C1, the second data line DL2 may be located in each of the second columns C2, and the third data line DL3 may be located in each of the third columns C3. The first to third data lines DL1 to DL3 may be repeated in the y direction.

[0153] The plurality of connection lines 200 may include a plurality of first connection lines 201 and a plurality of second connection lines 203. The first connection lines 201 may be arranged in the display area DA2, and the second connection lines 203 may be arranged in the peripheral area PA excluding the fan-out area FOA. The plurality of connection lines 200 may further include a plurality of third connection lines 205 and a plurality of fourth connection lines 207. The third connection lines 205 and the fourth connection lines 207 may be arranged in the peripheral area PA. The third connection lines 205 and the fourth connection lines 207 may be arranged in the fan-out area FOA.

[0154] Each of the first connection lines 201 may include a first portion 201a extending in the +x direction, a second portion 201b extending in the y direction, and a third portion 201c extending in the -x direction. The second portion 201b may connect the first portion 201a and the third portion 201c to each other.

[0155] The six second connection lines 203 can be spaced apart from each other between six adjacent columns. Each of the second connection lines 203 can be connected to a data line arranged in a column different from the column where the third portion 201c of the first connection line 201 is located. The column where the data line connected to the second connection line 203 is located and the column where the third portion 201c of the first connection line 201 connected to the second connection line 203 is located can be spaced apart by at least one column. In some of the second connection lines 203 (for example, second connection lines 203_3 and 203_4), the column where the data line connected to the second connection line 203 is located can be a column immediately adjacent to the column where the third portion 201c of the first connection line 201 connected to the second connection line 203 is located. In some of the second connection lines 203 (for example, second connection lines 203_2 and 203_5 and 203_1 and 203_6), the column where the data line connected to the second connection line 203 is located can be a column that is spaced apart from the column where the third portion 201c of the first connection line 201 connected to the second connection line 203 is located by multiple columns (for example, three columns or five columns).

[0156] Due to the second connection lines 203, the first connection lines 201 do not cross each other in the display area DA2, and the first connection lines 201 can transmit the first to third data signals Dr, Dg and Db to the first to third data lines DL1 to DL3 according to the order of the first to third data signals Dr, Dg and Db regularly output by the data driver D_IC.

[0157] A plurality of pads are arranged in the pad area PADA to transmit the first to third data signals Dr, Dg, and Db applied from the data driver D_IC to the third connection line 205 and the fourth connection line 207. For example, the first data signal Dr can be applied to the first pad P1, the fourth pad P4, and the seventh pad P7, etc. The second data signal Dg can be applied to the second pad P2, the fifth pad P5, and the eighth pad P8, etc. The third data signal Db can be applied to the third pad P3, the sixth pad P6, and the ninth pad P9, etc. In the three pad units, the fourth connection line 207 and the third connection line 205 can be alternately connected to the pads. For example, the fourth connection line 207 can be connected to the first to third pads P1 to P3, and the third connection line 205 can be connected to the fourth to sixth pads P4 to P6.

[0158] Hereinafter, the transmission paths of data signals will be described using the first to third data lines DL1 to DL3 in the first to fourth column groups CG1 to CG4 from the left, respectively. Figure 14 In the embodiment, the number of output channels of the data driver D_IC is three, and the second connection lines 203 may route the first connection lines 201 and the data lines DL between six columns.

[0159] The first data signal Dr may be applied to the first pixel PX1, the second data signal Dg may be applied to the second pixel PX2, and the third data signal Db may be applied to the third pixel PX3. The first data signal Dr may be applied to the first data line DL1 in the first column C1. The second data signal Dg may be applied to the second data line DL2 in the second column C2. The third data signal Db may be applied to the third data line DL3 in the third column C3.

[0160] The first data signal Dr can be applied to the first data line DL1 in the third column group CG3 via the fourth connection line 207_1 connected to the first pad P1. The second data signal Dg can be applied to the second data line DL2 in the third column group CG3 via the fourth connection line 207_2 connected to the second pad P2. The third data signal Db can be applied to the third data line DL3 in the third column group CG3 via the fourth connection line 207_3 connected to the third pad P3. The first data signal Dr can be applied to the first data line DL1 in the first column group CG1 via the third connection line 205_1, the first connection line 201_1, and the second connection line 203_1 connected to the fourth pad P4. The second data signal Dg can be applied to the second data line DL2 in the first column group CG1 via the third connection line 205_2, the first connection line 201_2, and the second connection line 203_2 connected to the fifth pad P5. The third data signal Db may be applied to the third data line DL3 in the first column group CG1 through the third connection line 205_3 connected to the sixth pad P6 , the first connection line 201_3 , and the second connection line 203_3 .

[0161] The first data signal Dr can be applied to the first data line DL1 in the fourth column group CG4 via the fourth connection line 207_4 connected to the seventh pad P7. The second data signal Dg can be applied to the second data line DL2 in the fourth column group CG4 via the fourth connection line 207_5 connected to the eighth pad P8. The third data signal Db can be applied to the third data line DL3 in the fourth column group CG4 via the fourth connection line 207_6 connected to the ninth pad P9. The first data signal Dr can be applied to the first data line DL1 in the second column group CG2 via the third connection line 205_4, the first connection line 201_4, and the second connection line 203_4 connected to the tenth pad P10. The second data signal Dg can be applied to the second data line DL2 in the second column group CG2 via the third connection line 205_5, the first connection line 201_5, and the second connection line 203_5 connected to the eleventh pad P11. The third data signal Db may be applied to the third data line DL3 in the second column group CG2 through the third connection line 205_6 connected to the twelfth pad P12 , the first connection line 201_6 , and the second connection line 203_6 .

[0162] Figure 15 It is applied Figure 13 The pixel array Figure 1 Hereinafter, this paper will not give a plan view of another example of the area C in FIG. Figure 14 Detailed description of the same configuration in .

[0163] refer to Figure 15 , one end of each of the second connection lines 203 ′ may be connected to the data line DL, and the other end thereof may be connected to the third portion 201 c of the first connection line 201 .

[0164] According to some example embodiments, Figure 12A As shown in FIG, one end of the second connection line 203′ can be electrically connected to the data line DL through the contact hole of the third insulating layer 114 in the first contact portion CNT1. The other end of the second connection line 203′ can be electrically connected to the third portion 201c of the first connection line 201 through the contact holes of the third insulating layer 114 and the fourth insulating layer 115 in the second contact portion CNT2. The second connection line 203′ may include the same material as that of the upper electrode CE2 of the capacitor Cst.

[0165] According to some example embodiments, Figure 12B As shown in FIG, one end of the second connection line 203′ can be electrically connected to the data line DL through the contact holes of the second insulating layer 113 and the third insulating layer 114 in the first contact portion CNT1. The other end of the second connection line 203′ can be electrically connected to the third portion 201c of the first connection line 201 through the contact holes of the second insulating layer 113, the third insulating layer 114, and the fourth insulating layer 115 in the second contact portion CNT2. The second connection line 203′ may include the same material as that of the lower electrode CE1 of the capacitor Cst.

[0166] According to some example embodiments, Figure 12C As shown in FIG, one end of the second connection line 203' can be connected to the data line DL, and the other end thereof can be electrically connected to the third portion 201c of the first connection line 201 through the contact hole of the fourth insulating layer 115 in the second contact portion CNT2. The second connection line 203' can be a portion of the data line DL extending to the peripheral area PA. The second connection line 203' can be formed integrally with the data line DL.

[0167] Figure 16 is a diagram of a pixel array according to some example embodiments.

[0168] refer to Figure 16In the display area DA3, a plurality of pixels PX may be arranged along columns in the x-direction and rows in the y-direction. The pixels PX may include a plurality of first pixels PX1 displaying a first color, a plurality of second pixels PX2 displaying a second color, a plurality of third pixels PX3 displaying a third color, and a plurality of fourth pixels PX4 displaying a fourth color. According to some example embodiments, the first pixel PX1 may be a red pixel R, the second pixel PX2 may be a green pixel G, the third pixel PX3 may be a blue pixel B, and the fourth pixel PX4 may be a white pixel W.

[0169] The first pixel PX1 may be repeatedly arranged in the x-direction in the first column C1 and electrically connected to the first data line DL1. The second pixel PX2 may be repeatedly arranged in the x-direction in the second column C2 adjacent to the first column C1 and electrically connected to the second data line DL2. The third pixel PX3 may be repeatedly arranged in the x-direction in the third column C3 adjacent to the second column C2 and electrically connected to the third data line DL3. The fourth pixel PX4 may be repeatedly arranged in the x-direction in the fourth column C4 adjacent to the third column C3 and electrically connected to the fourth data line DL4. The first to fourth columns C1 to C4 may be repeated in the y-direction.

[0170] Figure 17 It is applied Figure 16 The pixel array Figure 1 Hereinafter, the following will mainly describe the example of the area C in FIG. Figure 8 The configuration is different from the configuration.

[0171] refer to Figure 17 In the display area DA3, the first data line DL1 may be located in each of the first column C1, the second data line DL2 may be located in each of the second column C2, the third data line DL3 may be located in each of the third column C3, and the fourth data line DL4 may be located in each of the fourth column C4. The first to fourth data lines DL1 to DL4 may be repeated in the y direction.

[0172] The plurality of connection lines 200 may include a plurality of first connection lines 201 and a plurality of second connection lines 203. The first connection lines 201 may be arranged in the display area DA3, and the second connection lines 203 may be arranged in the peripheral area PA excluding the fan-out area FOA. The plurality of connection lines 200 may further include a plurality of third connection lines 205 and a plurality of fourth connection lines 207. The third connection lines 205 and the fourth connection lines 207 may be arranged in the peripheral area PA. The third connection lines 205 and the fourth connection lines 207 may be arranged in the fan-out area FOA.

[0173] Each of the first connection lines 201 may include a first portion 201a extending in the +x direction, a second portion 201b extending in the y direction, and a third portion 201c extending in the -x direction. The second portion 201b may connect the first portion 201a and the third portion 201c to each other.

[0174] Four second connection lines 203 can be spaced apart from each other between four adjacent columns. Each of the second connection lines 203 can be connected to a data line arranged in a column different from the column where the third portion 201c of the first connection line 201 is located. The column where the data line connected to the second connection line 203 is located and the column where the third portion 201c of the first connection line 201 connected to the second connection line 203 is located can be spaced apart from at least one column. In some of the second connection lines 203 (e.g., second connection lines 203_2 and 203_3), the column where the data line connected to the second connection line 203 is located can be a column that is adjacent to the column where the third portion 201c of the first connection line 201 connected to the second connection line 203 is located. In some of the second connection lines 203 (e.g., second connection lines 203_1 and 203_4), the column where the data line connected to the second connection line 203 is located can be a column that is spaced apart from multiple columns (e.g., three columns) from the column where the third portion 201c of the first connection line 201 connected to the second connection line 203 is located.

[0175] Due to the second connection line 203, the first connection lines 201 do not cross each other in the display area DA3, and the first connection line 201 can transmit the first to fourth data signals Dr, Dg, Db and Dw to the first to fourth data lines DL1 to DL4 according to the order of the first to fourth data signals Dr, Dg, Db and Dw regularly output by the data driver D_IC.

[0176] A plurality of pads are arranged in the pad area PADA to transmit the first to fourth data signals Dr, Dg, Db, and Dw applied from the data driver D_IC to the third connection line 205 and the fourth connection line 207. For example, the first data signal Dr can be applied to the first pad P1, the fifth pad P5, and the ninth pad P9, etc. The second data signal Dg can be applied to the second pad P2, the sixth pad P6, and the tenth pad P10, etc. The third data signal Db can be applied to the third pad P3, the seventh pad P7, and the eleventh pad P11, etc. The fourth data signal Dw can be applied to the fourth pad P4, the eighth pad P8, and the twelfth pad P12, etc. In the four pad units, the fourth connection line 207 and the third connection line 205 can be alternately connected to the pads. For example, the fourth connection line 207 can be connected to the first to fourth pads P1 to P4, and the third connection line 205 can be connected to the fifth to eighth pads P5 to P8.

[0177] Hereinafter, the transmission paths of data signals will be described using the first to fourth data lines DL1 to DL4 in the first to fourth column groups CG1 to CG4 from the left, respectively. Figure 17 In the embodiment, the number of output channels of the data driver D_IC is four, and the second connection lines 203 may route the first connection lines 201 and the data lines DL between the four columns.

[0178] The first data signal Dr may be applied to the first pixel PX1, the second data signal Dg may be applied to the second pixel PX2, the third data signal Db may be applied to the third pixel PX3, and the fourth data signal Dw may be applied to the fourth pixel PX4. The first data signal Dr may be applied to the first data line DL1 of the first column C1. The second data signal Dg may be applied to the second data line DL2 of the second column C2. The third data signal Db may be applied to the third data line DL3 of the third column C3. The fourth data signal Dw may be applied to the fourth data line DL4 of the fourth column C4.

[0179] The first data signal Dr can be applied to the first data line DL1 in the third column group CG3 via the fourth connection line 207_1 connected to the first pad P1. The second data signal Dg can be applied to the second data line DL2 in the third column group CG3 via the fourth connection line 207_2 connected to the second pad P2. The third data signal Db can be applied to the third data line DL3 in the third column group CG3 via the fourth connection line 207_3 connected to the third pad P3. The fourth data signal Dw can be applied to the fourth data line DL4 in the third column group CG3 via the fourth connection line 207_4 connected to the fourth pad P4.

[0180] The first data signal Dr can be applied to the first data line DL1 in the second column group CG2 through the third connection line 205_1, the first connection line 201_1, and the second connection line 203_1 connected to the fifth pad P5. The second data signal Dg can be applied to the second data line DL2 in the second column group CG2 through the third connection line 205_2, the first connection line 201_2, and the second connection line 203_2 connected to the sixth pad P6. The third data signal Db can be applied to the third data line DL3 in the second column group CG2 through the third connection line 205_3, the first connection line 201_3, and the second connection line 203_3 connected to the seventh pad P7. The fourth data signal Dw can be applied to the fourth data line DL4 in the second column group CG2 through the third connection line 205_4, the first connection line 201_4, and the second connection line 203_4 connected to the eighth pad P8.

[0181] Similarly, the first to fourth data signals Dr, Dg, Db and Dw applied to the ninth to sixteenth pads P9 to P16 can be applied to the first to fourth data lines DL1 to DL4 in the fourth column group CG4 and the first column group CG1 through the first to fourth connection lines 201, 203, 205 and 207.

[0182] Figure 18 It is applied Figure 16 The pixel array Figure 1 Hereinafter, this paper will not give a plan view of another example of the area C in FIG. Figure 17 Detailed description of the same configuration in .

[0183] refer to Figure 18 , one end of each of the second connection lines 203 ′ may be connected to the data line DL, and the other end thereof may be connected to the third portion 201 c of the first connection line 201 .

[0184] According to some example embodiments, Figure 12A As shown in FIG, one end of the second connection line 203′ can be electrically connected to the data line DL through the contact hole of the third insulating layer 114 in the first contact portion CNT1. The other end of the second connection line 203′ can be electrically connected to the third portion 201c of the first connection line 201 through the contact holes of the third insulating layer 114 and the fourth insulating layer 115 in the second contact portion CNT2. The second connection line 203′ may include the same material as that of the upper electrode CE2 of the capacitor Cst.

[0185] According to some example embodiments, Figure 12B As shown in FIG, one end of the second connection line 203′ can be electrically connected to the data line DL through the contact holes of the second insulating layer 113 and the third insulating layer 114 in the first contact portion CNT1. The other end of the second connection line 203′ can be electrically connected to the third portion 201c of the first connection line 201 through the contact holes of the second insulating layer 113, the third insulating layer 114, and the fourth insulating layer 115 in the second contact portion CNT2. The second connection line 203′ may include the same material as that of the lower electrode CE1 of the capacitor Cst.

[0186] According to some example embodiments, Figure 12C As shown in FIG, one end of the second connection line 203' can be connected to the data line DL, and the other end thereof can be electrically connected to the third portion 201c of the first connection line 201 through the contact hole of the fourth insulating layer 115 in the second contact portion CNT2. The second connection line 203' can be a portion of the data line DL extending to the peripheral area PA. The second connection line 203' can be formed integrally with the data line DL.

[0187] Figure 19is a perspective view of a display device including a display panel according to some example embodiments, and Figure 20A and Figure 20B Along Figure 19 A cross-sectional view taken along line V-V'.

[0188] refer to Figure 19 The display device 1 includes a first area OA, a display area DA serving as a second area, an intermediate area MA between the first area OA and the display area DA, and a peripheral area PA surrounding the display area DA. The display device 1 can provide a specific image using light emitted from a plurality of pixels arranged in the display area DA. Figure 19 FIG. 4 shows a first area OA located inside the display area DA, wherein the first area OA may be completely surrounded by the display area DA. Figure 20A and Figure 20B , the first area OA may be an area in which components to be described later below are located.

[0189] The middle area MA is positioned as a third area between the first area OA and the display area DA, which is the second area, and the display area DA may be surrounded by the peripheral area PA, which is the fourth area. The middle area MA and the peripheral area PA may be non-display areas in which pixels are not located. The middle area MA may be completely surrounded by the display area DA, and the display area DA may be completely surrounded by the peripheral area PA.

[0190] The display area DA may include an upper display area maintaining a substantially flat surface, and side display areas extending from and connected to the upper display area. The upper display area may include rounded corners. The side display areas may be display areas extending from at least one of the four sides of the upper display area. Each of the side display areas may include a region curved at a given curvature and a region curved approximately vertically.

[0191] refer to Figure 20A The display device 1 may include a display panel 10, an input sensing layer 40 on the display panel 10, and an optical functional layer 50 that may be covered with a window 60. The display device 1 may be various electronic devices such as a mobile phone, a laptop computer, and a smart watch.

[0192] The display panel 10 may be Figure 1 The display panel shown in . Will be referenced later below 21A to 22D The display panel 10 is described.

[0193] The input sensing layer 40 may be on the display panel 10. The input sensing layer 40 obtains coordinate information based on external input (e.g., a touch event). The input sensing layer 40 may include sensing electrodes (or touch electrodes) and traces connected to the sensing electrodes. The input sensing layer 40 may sense external input using a mutual capacitance method and / or a self-capacitance method.

[0194] The input sensing layer 40 may be formed directly on the display panel 10, or may be formed separately and then coupled to the display panel 10 via an adhesive layer such as an optically clear adhesive. For example, the input sensing layer 40 may be formed continuously after the process of forming the display panel 10. In this case, the input sensing layer 40 may be part of the display panel 10, and the adhesive layer may not be between the input sensing layer 40 and the display panel 10. Although Figure 20A The input sensing layer 40 is shown between the display panel 10 and the optical functional layer 50 , but according to some example embodiments, the input sensing layer 40 may be on the optical functional layer 50 .

[0195] The optical functional layer 50 may include an anti-reflection layer. The anti-reflection layer may reduce the reflectivity of light (external light) incident from the outside through the window 60 toward the display panel 10. The anti-reflection layer may include a retarder and a polarizer. The retarder may be a film type or a liquid crystal coating type, and may include a λ / 2 retarder and / or a λ / 4 retarder. The polarizer may also be a film type or a liquid crystal coating type. The film type polarizer may include a stretched synthetic resin film, and the liquid crystal coating type polarizer may include liquid crystals arranged in a specific arrangement. The retarder and the polarizer may further include a protective film. The protective film of the retarder and the polarizer may be defined as a base layer of the anti-reflection layer.

[0196] According to some example embodiments, the anti-reflection layer may include a black matrix and a color filter. The color filter may be arranged in consideration of the color of light emitted from each pixel of the display panel 10. Each of the color filters may include a red, green, or blue pigment or dye. Alternatively, in addition to the above-mentioned pigments or dyes, each of the color filters may further include quantum dots. Alternatively, some of the color filters may not include the above-mentioned pigments or dyes, and may include scattering particles such as titanium oxide.

[0197] According to some example embodiments, the anti-reflection layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer located on the respective layers. The first reflected light and the second reflected light respectively reflected by the first reflective layer and the second reflective layer may generate destructive interference, thereby reducing the external light reflectivity.

[0198] The optical function layer 50 may include a lens layer. The lens layer may improve the light efficiency of light emitted from the display panel 10 or reduce color deviation. The lens layer may include a layer having a concave lens shape or a convex lens shape, and / or may include multiple layers having different refractive indices. The optical function layer 50 may include all or any one of the above-mentioned antireflection layer and lens layer.

[0199] According to some example embodiments, the optical function layer 50 may be formed continuously after the process of forming the display panel 10 and / or the input sensing layer 40. In this case, an adhesive layer may not be present between the optical function layer 50 and the display panel 10 and / or the input sensing layer 40.

[0200] The display panel 10, the input sensing layer 40 and / or the optical function layer 50 may include an opening. In this regard, Figure 20A The display panel 10, the input sensing layer 40, and the optical functional layer 50 are shown to include first to third openings 10H, 40H, and 50H, respectively, and the three openings (i.e., the first to third openings 10H, 40H, and 50H) overlap each other. The first to third openings 10H, 40H, and 50H are positioned corresponding to the first area OA. According to some example embodiments, one or more of the display panel 10, the input sensing layer 40, and the optical functional layer 50 may not include an opening. For example, any one or two elements selected from the display panel 10, the input sensing layer 40, and the optical functional layer 50 may not include an opening. Alternatively, the display panel 10, the input sensing layer 40, and the optical functional layer 50 may not include an opening, as Figure 20B As shown in .

[0201] As described above, the first area OA may be a component area (eg, a sensor area, a camera area, a speaker area, etc.) where components 20 for adding various functions to the display device 1 are located. Figure 20A As shown in FIG, the component 20 may be located in the first to third openings 10H, 40H and 50H. Alternatively, as shown in FIG. Figure 20B As shown in , component 20 may be below display panel 10 .

[0202] The component 20 may include an electronic component. For example, the component 20 may be an electronic component that uses light or sound. For example, the electronic component may include a sensor that outputs and / or receives light, such as an infrared sensor, a camera that captures an image by receiving light, a sensor that outputs and detects light or sound to measure distance or recognize a fingerprint, a small lamp that outputs light, and a speaker that outputs sound. In the case of an electronic component that uses light, light of various wavelengths, such as visible light, infrared light, and ultraviolet light, may be used. In some embodiments, the first area OA may be a transmission area in which light and / or sound output from the component 20 to the outside or from the outside to the component 20 may be transmitted.

[0203] According to some example embodiments, when the display device 1 is used as a smart watch or a vehicle dashboard, the component 20 may be a hand such as a clock hand or a hand indicating specific information (e.g., vehicle speed, etc.). When the display device 1 includes a clock hand or a vehicle dashboard, the component 20 may be exposed to the outside through the window 60, and the window 60 may include an opening corresponding to the first area OA.

[0204] The member 20 may include elements associated with the functions of the display panel 10 as described above, or may include elements such as accessories that increase the aesthetics of the display panel 10. According to some example embodiments, an optically clear adhesive may be between the window 60 and the optical functional layer 50.

[0205] 21A to 21D is a cross-sectional view of a display panel according to some example embodiments.

[0206] refer to Figure 21A , the display panel 10 includes a display layer 400 on a substrate 100 . The display layer 400 may include a layer between the substrate 100 and the thin film encapsulation layer 500 .

[0207] The substrate 100 may include a glass material or a polymer resin. When the substrate 100 includes a polymer resin, the substrate 100 may be formed into multiple layers. For example, Figure 21A As shown in the enlarged view of , the substrate 100 may include a first base layer 101 , a second barrier layer 102 , a second base layer 103 and a second barrier layer 104 .

[0208] Each of the first substrate layer 101 and the second substrate layer 103 may include a polymer resin. For example, the first substrate layer 101 and the second substrate layer 103 may include a polymer resin such as PES, PAR, PEI, PEN, PET, PPS, PI, PC, TAC, and CAP. Each of the first substrate layer 101 and the second substrate layer 103 may include a transparent polymer resin.

[0209] Each of the first barrier layer 102 and the second barrier layer 104 is a barrier layer for preventing penetration of external foreign substances, and may include a single layer or a multilayer including an inorganic material such as silicon nitride and / or silicon oxide.

[0210] The display layer 400 includes a plurality of pixels. The display layer 400 may include a display element layer 400A including a display element arranged for each pixel, and a pixel circuit layer 400B including a pixel circuit and an insulating layer arranged for each pixel. Each pixel circuit may include a transistor and a capacitor, and each display element may include an organic light emitting diode (OLED).

[0211] The display element of the display layer 400 may be covered by an encapsulation member such as a thin film encapsulation layer 500, and the thin film encapsulation layer 500 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. When the display panel 10 includes the substrate 100 including a polymer resin and the thin film encapsulation layer 500 including the inorganic encapsulation layer and the organic encapsulation layer, the flexibility of the display panel 10 may be improved.

[0212] The display panel 10 may include a first opening 10H passing through the display panel 10. The first opening 10H may be located in the first area OA, in which case the first area OA may be a type of opening area. Figure 21A The substrate 100 and the thin film encapsulation layer 500 are shown to include through holes 100H and 500H, respectively corresponding to the first opening 10H of the display panel 10. The display layer 400 may also include a through hole 400H corresponding to the first area OA.

[0213] According to some example embodiments, Figure 21B As shown in , the substrate 100 may not include a through hole corresponding to the first area OA. The display layer 400 may further include a through hole 400H corresponding to the first area OA. The thin film encapsulation layer 500 may not include a through hole corresponding to the first area OA. According to some example embodiments, as Figure 21C As shown in , the display layer 400 may not include the through hole 400H corresponding to the first area OA, and the display element layer 400A is not located in the first area OA.

[0214] Figures 21A to 21C The display element layer 400A is shown not to be located in the first area OA, but the present disclosure is not limited thereto. According to some example embodiments, as shown in FIG. Figure 21D As shown in , the auxiliary display element layer 400C may be located in the first area OA. The auxiliary display element layer 400C may include display elements that have a different structure and / or operate differently from the display elements of the display element layer 400A.

[0215] According to some example embodiments, each pixel of the display element layer 400A may include an active organic light-emitting diode, and the auxiliary display element layer 400C may include a pixel including a passive organic light-emitting diode. When the auxiliary display element layer 400C includes a display element including a passive organic light-emitting diode, no elements constituting a pixel circuit may exist below the passive organic light-emitting diode. For example, the portion of the pixel circuit layer 400B below the auxiliary display element layer 400C does not include a transistor or a capacitor.

[0216] According to some example embodiments, the auxiliary display element layer 400C may include a display element of the same type as the display element layer 400A (e.g., an active organic light emitting diode), but may have a different pixel circuit structure underneath. For example, the pixel circuit below the auxiliary display element layer 400C (e.g., a pixel circuit having a light-shielding film between the substrate 100 and the transistor) may include a structure different from that of the pixel circuit below the display element layer 400A. Alternatively, the display element of the auxiliary display element layer 400C may be operated according to a control signal different from the control signal of the display element of the display element layer 400A. Components that do not require relatively high transmittance (e.g., infrared sensors, etc.) may be located in the first area OA where the auxiliary display element layer 400C is located. In this case, the first area OA may be a component area and an auxiliary display area.

[0217] 22A to 22D is a cross-sectional view of a display panel according to some example embodiments. 21A to 21D The display panel 10 described includes a thin film encapsulation layer 500. 22A to 22D The display panel 10 ′ may include an encapsulation substrate 500A and a sealant 540 .

[0218] like Figures 22A to 22C As shown in FIG, one or more of the substrate 100, the display layer 400, and the encapsulation substrate 500A may have through holes 100H, 400H, and 500AH corresponding to the first area OA. The display element layer 400A may not be located in the first area OA, or as shown in FIG. Figure 22D As shown in FIG, the auxiliary display element layer 400C may be located in the first area OA. Figure 21D The auxiliary display element layer 400C is described.

[0219] When first connection lines 201 are directly connected to data lines DL without second connection lines 203, data driver D_IC needs to output data signals according to the arrangement of first connection lines 201. In this case, the first to third data signals Dr, Dg, and Db output by data driver D_IC in the y-direction may not repeat regularly, and the order of the first to third data signals Dr, Dg, and Db may be altered. Therefore, it may be difficult to perform regular gamma correction on the first to third data signals Dr, Dg, and Db in data driver D_IC, and the cost of developing data driver D_IC for gamma correction may increase.

[0220] In an embodiment of the present disclosure, each data line connected to the first connection line 201 can be re-routed using the second connection line 203. Using the second connection line 203, the first connection line 201 can be electrically connected to the first to fourth data lines DL1 to DL4 according to the order of the first to third data signals Dr, Dg, and Db output by the data driver D_IC, or the order of the first to fourth data signals Dr, Dg, Db, and Dw. Therefore, since the order of the first to third data signals Dr, Dg, and Db output by the data driver D_IC or the order of the first to fourth data signals Dr, Dg, Db, and Dw can be regular, the display device can be manufactured without the cost increase caused by the development of the data driver D_IC.

[0221] The embodiment of the present disclosure is not limited to the above arrangement of the second connection line 203, and the second connection line 203 can be arranged twice as many as the output channel of the data driver D_IC to lay out the first connection line 201 and the data line DL. Figure 7 and Figure 16 In a display device with a pixel array (four output channels), the second connection line 203 can be arranged between eight adjacent columns of the first connection line 201 and the data line DL. Figure 13 In a display device with a pixel array (three output channels), the second connection lines 203 may be arranged between the first connection lines 201 and the data lines DL between twelve adjacent columns.

[0222] According to an embodiment of the present disclosure, as the data lines to be connected to the connection lines of the display area are rerouted, a display device capable of stably transmitting data signals to pixels without increasing manufacturing costs while reducing the dead zone of the display device can be provided. However, the scope of the present disclosure is not limited to this effect.

[0223] It should be understood that the exemplary embodiments described herein should be considered for descriptive purposes only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more exemplary embodiments have been described with reference to the accompanying drawings, those skilled in the art will appreciate that various changes in form and details may be made without departing from the spirit and scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: A substrate comprising a display area and a peripheral area outside the display area, wherein the peripheral area comprises a pad area and a fan-out area between the display area and the pad area; a plurality of data lines arranged in a plurality of columns in the display area; a first connection line in the display area, the first connection line comprising a first portion extending along a first column of the display area, a third portion extending along a second column of the display area, and a second portion connecting the first portion to the third portion; a second connection line in an area of ​​the peripheral area excluding the fan-out area and the pad area, and connected to the third portion of the first connection line and the data line in the third column of the display area; as well as A third connection line is in the fan-out region in the peripheral region and is connected to a first pad in the pad region in the peripheral region and the first portion of the first connection line. 2 . The display device according to claim 1 , wherein the first connection line and the second connection line are on the same layer. 3 . The display device according to claim 1 , wherein the first connection line and the second connection line are on different layers. The display device according to claim 1 , wherein the data line and the first connection line are on different layers. The display device according to claim 1 , wherein the data line and the second connection line are on different layers. The display device according to claim 1 , wherein the data line and the second connection line are on the same layer.

7. The display device according to claim 1, further comprising: A fourth connection line is in the peripheral area and is connected to the second pad in the pad area and the data line in the first column. 8 . The display device according to claim 7 , wherein at least one pad is further located between the first pad and the second pad. 9 . The display device according to claim 7 , wherein the first connection line and the third connection line are on the same layer. 10 . The display device according to claim 7 , wherein the data lines and the fourth connection lines in the first column are on the same layer.

11. The display device according to claim 1 , further comprising: A pixel electrode is provided on an upper layer of the first connecting line.

12. The display device of claim 1, wherein the second column is immediately adjacent to the first column.

13. The display device of claim 1, wherein the second column is spaced apart from the first column by a plurality of columns. The display device according to claim 1 , wherein the third column is immediately adjacent to the second column.

15. The display device of claim 1, wherein the third column is spaced apart from the second column by a plurality of columns.

16. The display device according to claim 1, further comprising: A fourth connection line is in the peripheral area and is connected to the second pad in the pad area and the data line in the fourth column of the display area.

17. A display device comprising: A substrate comprising a display area and a peripheral area outside the display area, wherein the peripheral area comprises a pad area and a fan-out area between the display area and the pad area; a plurality of data lines in the display area and arranged in a plurality of columns; a plurality of first connection lines in the display area; a plurality of second connection lines in an area other than the fan-out area and the pad area in the peripheral area; as well as a plurality of third connection lines in the fan-out region in the peripheral region, Each of the plurality of first connecting lines includes: a first portion and a third portion extending in a first direction and spaced apart from each other by at least one column, and a second portion extending in a second direction different from the first direction and connecting the first portion to the third portion. Each of the plurality of second connection lines is connected to a third portion of one of the plurality of first connection lines and a data line of the plurality of data lines in a column spaced apart from the third portion of the one of the plurality of first connection lines by at least one column, and Each of the plurality of third connection lines is connected to a first pad of the pad area in the peripheral area and a first portion of one of the plurality of first connection lines.

18. The display device according to claim 17, wherein: The second connection lines are on a layer different from the layer where the first connection lines are arranged. 19 . The display device according to claim 17 , wherein each of the plurality of second connection lines is a portion of a corresponding one of the plurality of first connection lines extending from the display area to the peripheral area.

20. The display device according to claim 17, further comprising: a plurality of fourth connection lines in the peripheral area, Each of the plurality of fourth connection lines is connected to the second pad of the pad region and one of the plurality of data lines.

Images