Electronic device

Abstract

Embodiments of the present disclosure relate to current sharing schemes in current mode control for multi-phase DC-DC converters. Schemes for providing current sharing among parallel converters in a multi-phase configuration are disclosed. In certain embodiments, based on current sharing errors among the parallel converters, a cycle-by-cycle, on-the-fly correction to compensate signal offsets is provided to enable improved on-the-fly current sharing performance.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 857,175, filed June 4, 2019, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This embodiment generally relates to DC-DC converters, and more particularly to a scheme for providing current sharing between parallel converters configured in a multiphase configuration. Background Technology

[0004] In conventional techniques, current sharing in a multiphase DC-DC converter configuration is attempted by connecting the voltage loop error amplifier outputs of the parallel converters together. In other words, the peak current loop references of the parallel converters are linked together. However, inherent component offsets, slope compensation offsets, and mismatched ramp slewrates can lead to current sharing errors between the parallel converters. Therefore, solutions are needed to address these and other issues. Summary of the Invention

[0005] This embodiment generally relates to DC-DC converters, and more particularly to a scheme for providing current sharing between parallel converters configured in a multiphase configuration. In some embodiments, based on the current sharing error between the parallel converters, a cycle-by-cycle instantaneous correction of the compensation signal offset is provided to achieve improved instantaneous current sharing performance. Attached Figure Description

[0006] These and other aspects and features of this embodiment will become apparent to those skilled in the art from the following description of specific embodiments in conjunction with the accompanying drawings, wherein:

[0007] Figure 1 This diagram illustrates the traditional current sharing mechanism in peak current mode control.

[0008] Figure 2 This is a timing diagram illustrating the problem of conventional current sharing in peak current mode control.

[0009] Figure 3 This is a schematic diagram illustrating an example method of an instantaneous active current circuit according to this embodiment.

[0010] Figure 4A This is a timing diagram illustrating the simulated operating conditions of a circuit designed according to this embodiment and operating under no-load conditions.

[0011] Figure 4BThis is a timing diagram illustrating the simulation operating conditions of a circuit designed according to this embodiment with a 10A load.

[0012] Figure 5A The illustration includes, for example Figure 3 The timing diagram shows the simulation operating conditions of the burst mode of the circuit shown in this embodiment.

[0013] Figure 5B The illustration includes, for example Figure 3 Another timing diagram of the simulation operating conditions for the burst mode of the circuit shown in this embodiment. Detailed Implementation

[0014] This embodiment will now be described in detail with reference to the accompanying drawings, which are provided as illustrative examples of the embodiments to enable those skilled in the art to practice the embodiments and alternatives that will be obvious to them. It is important to note that the drawings and examples below are not intended to limit the scope of this embodiment to a single embodiment, but rather other embodiments are possible by interchangeing some or all of the elements described or illustrated. Furthermore, where some elements of this embodiment may be implemented partially or entirely using known components, only those portions of these known components necessary for understanding this embodiment will be described, and detailed descriptions of other portions of these known components will be omitted so as not to obscure the embodiment. Embodiments described as being implemented in software should not be considered limiting, but may include embodiments implemented in hardware or a combination of software and hardware, unless otherwise indicated herein, as will be obvious to those skilled in the art, and vice versa. In this specification, embodiments showing a single component should not be considered limiting; rather, unless otherwise expressly stated herein, this disclosure is intended to cover other embodiments including a plurality of identical components, and vice versa. Furthermore, unless expressly stated otherwise, the applicant does not intend to assign any term in the specification or claims to an uncommon or particular meaning. Furthermore, this embodiment covers current and future known equivalents of known components mentioned herein by way of illustration.

[0015] Figure 1 This diagram illustrates a method for current sharing in a conventional multiphase configuration. It should be noted that, when... Figure 1 Arranging parallel converters in a multiphase configuration to share the current output when supplying current to the load has several advantages. First, the shared current reduces the stress on the converters and increases component lifespan. Additionally, the parallel converters provide fault protection; if one module fails in the two-phase example, another module can quickly increase its current output from 50% to 100% of the supplied current, minimizing downtime or load interruption.

[0016] Figure 1 Two converters 100-1 and 100-2, representing two corresponding phases, are depicted connected together in a multiphase configuration. In each converter or phase, loop 101 is a current loop, while loop 106 is a voltage loop. In current loop 101, current 103... I L This represents the current in inductor 102. The inductor current 103 is sensed by a current-sensing operational amplifier 104, which generates one of the inputs to comparator 105. The current-sensing operational amplifier 104 measures the current and outputs a voltage that can be multiplied by a gain as the current-sensing signal 110. In the voltage loop 106, a resistor divider senses the output voltage and compares this output voltage with a reference voltage using an error amplifier 108. The output of the error amplifier 108 is the signal Vcomp 109.

[0017] A current sensing signal 110 is added to a ramp signal 111 from a ramp generator 116, and the sum of 110 and 111 is compared with a compensation signal Vcomp 109 by a comparator 105. The output signal from the comparator 105 serves as a reset for a trigger 112, which is set by a clock signal, resulting in a pulse width modulator (PWM) signal with a frequency determined by the clock signal. The pulse width of the PWM signal generated by the output of the trigger 112 is controlled by the output of the comparator 105. The output PWM signal drives a high / low switching pair 113 (e.g., a power MOSFET) to control the voltage supplied to the inductor 102, which then modulates the inductor current 103.

[0018] The output of comparator 105 thus modulates the duty cycle of the PWM signal that controls the inductor current. If the load requires a larger current or voltage, the duty cycle will be higher (i.e., the PWM signal will be controlled to be on for a longer period relative to its off time). Conversely, if the load requires a smaller current or voltage, the duty cycle will be lower (i.e., the PWM signal will be on for a shorter period relative to its off time). Traditionally, as... Figure 1 As shown in the example, current can be shared between two parallel converters by connecting the Vcomp signals 109 of the two converters 100-1 and 100-2 together.

[0019] Theoretically, connecting the Vcomp signals across two parallel converters together achieves the goal of sharing equal current between phases according to the PWM signal modulation scheme described above. However, in practice, component tolerances lead to problems resulting in unequal current sharing. Due to component tolerances, even if all components are designed identically, many operating characteristics of the parallel converters will differ from one another. For example, the output voltages of the converters will not be exactly the same due to component tolerances. As indicated by the inverse current-voltage relationship in the well-known power equation "current = power / voltage", a small difference in voltage can lead to a larger difference in current. Therefore, even small component mismatches can cause serious problems, and the converters between phases may generate current unevenly.

[0020] Several problems can arise when one converter draws more current to the load than another. For example, the converter providing more current may experience higher stress and reduced reliability. This can shorten the converter's lifespan. Additionally, a large amount of current drawn from one converter may trigger its overcurrent protection, shutting it down. Furthermore, drawing the majority of current from one converter instead of another can create hot spots. Finally, if the parallel converters disproportionately supply current to the load, and the converter supplying the majority of the current fails, the converter supplying the minimum current (e.g., 5% of the current) must drastically increase its current output from 5% to 100%. This contrasts sharply with the current-sharing scheme discussed above, where both converters supply current equally and minimize any disturbance to the load. In this scenario, the load may experience performance degradation due to the converters needing to compensate for variations in current generation.

[0021] Figure 2 It is illustrated in, for example Figure 1 The timing diagram illustrates the problems with conventional current-sharing techniques in a multiphase configuration. (Reference) Figure 1 The output signal 111 from the ramp generator 116 is in Figure 2 The signal shown is labeled Vslope_comp. The sum of this signal and the inductor current signal 110 is... Figure 2 The signal 201, labeled Vslope_comp + VIL, is shown in the diagram. As described above, comparator 105 compares this signal 201 with the compensation signal Vcomp 109. Furthermore, as... Figure 2 As shown, compared to the current sensing signal 110, the amplitude of the summation signal 201 mainly depends on the ramp signal 111.

[0022] although Figure 1 The conventional technology shown leads to Figure 2The Vcomp signal 109 shown is the same in each phase, but current sharing still occurs. For example, each component in each converter (e.g., ramp generator 116) has its own device and performance characteristics. These differences affect offset 202 and slope 203, and thus determine the overall characteristics of signal 111. Matching the operating characteristics of each comparator, component, and / or IC between phases is challenging, if not impossible. Therefore, each comparator, component, and / or IC has mismatched characteristics, and thus each phase has a mismatched component used to perform the comparison with the Vcomp signal during the generation of the PWM signal in each phase. As mentioned above, these mismatched characteristics can cause substantial differences in how the converters share the current allocated to the load. Therefore, the parallel converters will not share the current equally.

[0023] Figure 3 This is a circuit diagram illustrating an example method of active current sharing according to this embodiment. This embodiment will be described in conjunction with an example peak current mode control configuration; however, this is not limiting, and alternative embodiments can be included in other control schemes, such as in a valley current mode control configuration. Furthermore, it should be noted that although this embodiment has been described in conjunction with an exemplary two-phase configuration, this embodiment is not limited to this example, and embodiments can be included in other multiphase configurations such as three-phase, four-phase, etc.

[0024] Figure 3 Two converters 300-1 and 300-2 are depicted connected together in a two-phase configuration. To achieve current sharing according to this embodiment, the converters are further connected in two ways: via a compensation signal 109 and via a shared bus 301. As will become more apparent below, the shared bus 301 creates an additional closed loop that allows the converters to share current more evenly than conventional methods. The signal on the shared bus 301 represents the average current of all converters in the parallel converter. This current sharing technique is designed to match the output current to the average current. Using this diagram for circuit analysis helps illustrate how the circuit distributes voltage and current, and how the output current is adjusted to match the average current. IMON 302 is an external resistor.

[0025] As in Figure 3 As further illustrated in the example, to facilitate the inclusion of average current information via the shared bus 301, the converter 300 includes several new components, each in the path between the shared bus 301, the current sensing amplifier 104, and the comparator 105. These components include, respectively, a buffer 330, a current sensing amplifier 104, and a comparator 105 with gain G. ISH The first offset amplifier 332 has a gain G ERRThe second offset amplifier 334, the current sensing control pair 336, and the first offset current source 338, the second offset current source 340, and the third offset current source 342 are included. In normal operation, the added new components form an instantaneous active current sharing feedback loop to force the inductor current of the parallel converter to follow the average current set by the shared bus 301.

[0026] Using well-known circuit analysis techniques, it can be done as shown in Equation 1. Figure 3 The components and values ​​shown describe the voltage values ​​on the shared bus 301 between parallel converters. V ISH .

[0027] = , in

[0028] Equation 1

[0029] Next, assuming = = 0 (e.g., through design and / or control) Figure 3 (Components in the process). Using this assumption and the voltage shared between parallel converters as illustrated in Equation 1. V ISH and substitute I AVG and V ISH The value of the current sensing signal of the inductor can be calculated. The voltage of the current sensing signal of inductor 1 (i.e., V IL1 As shown in equation (2) below.

[0030] ×

[0031]

[0032] Equation 2

[0033] To further simplify, assume... = 1 (e.g., through design and / or control) Figure 3 (Components in the text). About Figure 3 The circuit elements in V IL1 The simplified equation is shown in Equation 3 below.

[0034]

[0035] Equation 3

[0036] Considering Equation 3 above, it is clear that if at any time > This will lead to V IL1 and I L1 and I AVG The difference between them is proportional (i.e., proportional to the difference in Equation 3 above). I L1 - I AVG The value increases proportionally. In the absence of shared bus 301 and the circuitry of this invention, V IL1 The increase is greater than otherwise will V IL1 The increase reflected in the middle. In this case, as combined with the above. Figure 1 As described, the converter will cause the duty cycle of the PWM signal fed to switch 113 to decrease, making Reduce to get closer to I AVG Alternative locations, if < ,but Reduce this additional amount, and then increase the duty cycle to make Increase to get closer In this way, each converter will be independently designed to deliver the same amount of current during each PWM cycle. This enables "active" and / or "instantaneous" current sharing between phases on a cycle-by-cycle basis.

[0037] A small filter, including resistor 304 and capacitor 303, can be used to dilute the computational... High-frequency ripples may occur at times.

[0038] In an alternative embodiment, in addition to connecting the input voltage, output voltage, and feedback voltage together, this current sharing scheme can be extended to multiphase applications by connecting the compensation signal 109 of all parallel converters configured in a multiphase configuration and the shared bus 301 together.

[0039] Table 1 below reproduces the simulation results of the current sharing technology according to this embodiment. Table 1 below compares the simulation results of the circuit designed according to this embodiment with the simulation results of the circuit designed according to the conventional current sharing method. The values ​​in the table represent the current sharing technology designed according to this embodiment. The calculated current error. As indicated in the corresponding row, for R IMONVarious values ​​of the output current were used to obtain the current error values. In all cases, the current error values ​​were obtained under the conditions that the difference between the VCOMP offsets of the two converters was 300 mV and the difference in charging current of the conversion rate between the ramp generators in the two converters was 100 nA. The values ​​in the first column are simulation results for the current error values ​​of the converter with the current sharing circuit according to this embodiment, and the values ​​in the second column are simulation results for the current error values ​​of the converter with the conventional current sharing circuit.

[0040] Table 1

[0041]

[0042] It can be seen that in the conventional method, the current error between the two converters is very large, while that with the external resistor... R IMON Irrelevant. Specifically, when R IMON At 19.2kΩ and 18kΩ respectively, the current error is 16.5A. Additionally, the current sharing error remains the same at 16.5A regardless of whether the output is 20A or 0A. Conversely, when the circuit implementing this embodiment was simulated, the current error remained a very small 1.9A during each of the five simulations. Regardless of adjustments... R IMON Alternatively, adjust the output current, and control the current error within + / - 5%.

[0043] Figure 4A This is a timing diagram illustrating the simulated operating conditions of a circuit designed according to this embodiment and operating under no-load conditions. For example... Figure 4A As shown, the converters operate together to jointly provide the regulated voltage output represented by waveform 401. According to an aspect of the embodiment, the current supplied by the two converters is substantially the same during these conditions, although the current is quite small during no-load conditions (approximately 41mA per phase in this example). Figure 4A In the diagram, waveform 402-1 represents the current output by one converter (e.g., 300-1), and waveform 402-2 represents the current output by another converter (e.g., 300-2). Waveform 403 represents the PWM signal in the first phase. It is also evident that converters 300-1 and 300-2 implement phase interleaving.

[0044] Figure 4B This is a timing diagram illustrating the simulated operating conditions of a circuit designed according to this embodiment and operating under full load. For example... Figure 4BAs shown, and in the previous example, the converters operate together to jointly provide the regulated voltage output represented by waveform 405. Also according to an aspect of the embodiment, during these conditions, the current supplied by the two converters is combined to provide a full-load current of 10A in this example. Figure 4B In the diagram, waveform 406-1 represents the current output by one converter (e.g., 300-1), and waveform 406-2 represents the current output by another converter (e.g., 300-2). It is also evident, and according to the current sharing aspect of the embodiment, that the currents provided by converters 300-1 and 300-2 are substantially equal (e.g., within + / - 1%).

[0045] Figure 5A and Figure 5B This is a timing diagram showing the simulation results of an embodiment of the present invention in burst mode. Specifically, Figure 5B yes Figure 5A An enlarged version, thus focusing on the relatively short duration of the burst mode.

[0046] Burst mode can be used when there is a light load, high input voltage, and a small duty cycle. In some cases, it is difficult to generate and maintain a small duty cycle when there is a high input voltage. During bust-off mode, the switches and transistors can be idle, causing the output voltage to drop. When the output voltage reaches a certain threshold, the switches and transistors turn on to allow the output voltage to reach its expected value again. This idle-burst approach reduces conduction and switching losses.

[0047] like Figure 5A and Figure 5B As shown, even in burst mode, and based on the "instantaneous" and "active" current sharing characteristics of this embodiment, the circuit designed according to this embodiment performs well and shares current equally. Figure 5A As shown, during burst mode, the output voltage, represented by waveform 501, jumps for a very short duration, during which a large current, represented by waveform 502, is generated. Also as... Figure 5B As shown, even under these burst mode conditions, the relative currents generated by each parallel converter in the parallel converter (shown by waveforms 502-1 and 502-2) are substantially the same and interleaved. For completeness, the PWM signal for the first phase corresponding to waveform 502-1 is provided as waveform 503.

[0048] Although this embodiment has been specifically described with reference to preferred examples, it will be apparent to those skilled in the art that changes and modifications in form and detail may be made without departing from the spirit and scope of this disclosure. It is intended that the appended claims cover such changes and modifications.

[0049] The technical solutions described herein sometimes illustrate different components contained within or connected to different other components. It should be understood that the architectures depicted are illustrative, and many other architectures that achieve the same functionality can actually be implemented. Conceptually, any arrangement of components that achieve the same functionality is effectively “associated” to achieve the desired functionality. Therefore, any two components combined herein to achieve a particular function can be considered “associated” with each other to achieve the desired functionality, regardless of the architecture or intermediate components. Similarly, any two components so associated can also be considered “operably connected” or “operably coupled” to each other to achieve the desired functionality, and any two components that can be so associated can also be considered “operably coupled” to each other to achieve the desired functionality. Specific examples of operable coupling include, but are not limited to, physically matable and / or physically interacting components and / or wirelessly interactive and / or logically interactive and / or logically interactive components.

[0050] Regarding the use of plural and / or singular terms in this document, those skilled in the art can adapt the conversion of plural to singular and / or singular to plural to the context and / or application. For clarity, various singular / plural substitutions may be explicitly described herein.

[0051] Those skilled in the art will understand that, generally, the terms used herein, particularly in the appended claims (e.g., the body of the appended claims), are generally intended to be used as “open” terms (e.g., the term “comprising” should be interpreted as “including but not limited to”, the term “having” should be interpreted as “at least having”, the term “comprising” should be interpreted as “including but not limited to”, etc.).

[0052] Although the accompanying drawings and descriptions may illustrate a specific order of method steps, the order of these steps may differ from the order depicted and described unless otherwise specified above. Furthermore, unless otherwise specified above, two or more steps may be performed simultaneously or partially simultaneously. Such variations may depend, for example, on the chosen software and hardware system and the designer's choices. All such variations are within the scope of this disclosure. Similarly, standard programming techniques with rule-based logic and other logic can be used to implement the described methods in software to perform various connection steps, processing steps, comparison steps, and decision steps.

[0053] Those skilled in the art will also understand that if a claim description is intended to introduce a specific number of claims, this intention will be explicitly stated in the claims, and without such a statement, this intention does not exist. For example, to aid understanding, the appended claims below may contain the use of the introductory phrases “at least one” and “one or more” to introduce the description of the claims. However, the use of such phrases should not be construed as implying that a claim description introduced by the indefinite article “a” or “an” limits any particular claim containing such an introductory claim description to an invention containing only one such description, even if the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an” (e.g., “a” and / or “an” should generally be interpreted as “at least one” or “one or more”); the same applies to the use of definite articles for introducing the description of the claims. Additionally, even if a claim description explicitly describes a specific number of claims, those skilled in the art will recognize that such a description should generally be interpreted as meaning at least the number described (e.g., the bare description of “two descriptions” generally means at least two descriptions, or two or more descriptions, in the absence of other modifiers).

[0054] Furthermore, in cases where conventions such as "at least one of A, B, and C" are used, such wording is generally intended to convey the meaning of the convention in a manner that will be understood by a person skilled in the art (e.g., "a system having at least one of A, B, and C" includes, but is not limited to, systems having A alone, having B alone, having C alone, having A and B together, having A and C together, having B and C together, and / or having A, B, and C together). In cases where conventions such as "at least one of A, B, or C" are used, such wording is generally intended to convey the meaning of the convention in a manner that will be understood by a person skilled in the art (e.g., "a system having at least one of A, B, and C" includes, but is not limited to, systems having A alone, having B alone, having C alone, having A and B together, having A and C together, having B and C together, and / or having A, B, and C together). A person skilled in the art will also understand that, in practice, any separate words and / or phrases presenting two or more alternative terms, whether in the specification, claims, or drawings, should be understood to contemplate the possibility of including one of the terms, any one of the two terms, or both of them. For example, the phrase “A or B” would be understood to include the possibility of “A” or “B” or “A and B”.

[0055] Furthermore, unless otherwise stated, the use of words such as “approximately,” “about,” “around,” “basically,” etc., implies plus or minus ten percent.

[0056] For purposes of illustration and description, the foregoing description of illustrative embodiments has been presented. It is not intended to be exhaustive or limiting with respect to the precise forms disclosed, and modifications and variations are possible, or may be obtained, from practice of the disclosed embodiments in light of the foregoing teachings. It is intended that the scope of the invention be defined by the appended claims and their equivalents.

Claims

1. An electronic device, comprising: A first voltage regulator, the first voltage regulator including a first phase, the first phase including a first buffer amplifier, a first offset amplifier having an input coupled to the output of the first buffer amplifier, and a first current sensing control pair, the first current sensing control pair including a first pair of amplifiers, the first pair of amplifiers including a first output coupled to the input of the first buffer amplifier and a second output coupled to the output of the first offset amplifier; as well as A second voltage regulator includes a second phase, the second phase including a second buffer amplifier, a second offset amplifier having an input coupled to the output of the second buffer amplifier, and a second current sensing control pair, the second current sensing control pair including a second pair of amplifiers, the second pair of amplifiers including a first output coupled to the input of the second buffer amplifier and a second output coupled to the output of the second offset amplifier. The first voltage regulator and the second voltage regulator are configured to achieve current sharing based on a current sharing configuration, which is based on matching the output current of the first voltage regulator and the output current of the second voltage regulator with an average current.

2. The electronic device of claim 1, wherein the current sharing configuration is based on adjusting the voltage of a current sensing signal for a first inductor among a plurality of inductors, the voltage of the current sensing signal being adjusted based on a comparison of an average current with a first inductor current, wherein the first inductor current is determined by a pulse width modulation signal.

3. The electronic device of claim 2, wherein the adjustment of the voltage of the current sensing signal for the first inductor is performed during a pulse width modulation period.

4. The electronic device of claim 1, wherein the current sharing configuration further comprises: A first electrical connection is made, which connects the first voltage regulator and the second voltage regulator via a compensation signal; as well as A second electrical connection is provided, which connects the first voltage regulator and the second voltage regulator via a shared bus.

5. The electronic device of claim 4, wherein the shared bus transmits an average current, and the average current on the shared bus is determined using the first buffer amplifier and the second buffer amplifier, the first offset amplifier and the second offset amplifier, one or more current sources, and the first current sensing control pair and the second current sensing control pair.

6. The electronic device of claim 4, wherein the compensation signal is an output signal from an error amplifier that outputs the signal measuring the error between a reference voltage and a system output voltage, the system output voltage being sensed by a resistor divider.

7. The electronic device of claim 1, wherein the first phase is configured by a first inductor, and the current from the first inductor is controlled in a peak current mode.

8. The electronic device of claim 1, wherein the second phase is configured by a second inductor, and the current from the second inductor is controlled in a peak current mode.

9. The electronic device of claim 1, wherein the first phase is configured by a first inductor, and the current from the first inductor is controlled in a valley current mode.

10. The electronic device of claim 1, wherein the second phase is configured by a second inductor, and the current from the second inductor is controlled in a valley current mode.

11. The electronic device of claim 1, wherein the device is further configured to support multiphase applications.

12. The electronic device of claim 11, wherein the multiphase application is provided by one or more parallel voltage regulators, each of the one or more parallel voltage regulators comprising one or more phases.

13. The electronic device of claim 12, wherein the one or more parallel voltage regulators are electrically connected via a compensation signal, a shared bus, an input voltage, a system output voltage, and a feedback voltage, wherein the compensation signal is an output signal from an error amplifier that outputs the output signal measuring the error between a reference voltage and the system output voltage, wherein the system output voltage is sensed by a resistor divider, wherein the shared bus transmits an average current, and wherein the feedback voltage is input to the error amplifier.

14. The electronic device of claim 1, wherein the first voltage regulator and the second voltage regulator each include at least a voltage loop and a current loop.

15. The electronic device of claim 14, wherein the current loop further comprises an inductor coupled to a current-sensing operational amplifier, the current-sensing operational amplifier being coupled to a comparator.

16. The electronic device of claim 15, wherein the current-sensing operational amplifier measures current based on the inductor and outputs a current-sensing voltage, wherein the current-sensing voltage is input to the comparator.

17. The electronic device of claim 16, wherein the voltage sensed by the current sensed operational amplifier is multiplied by the gain.

18. The electronic device of claim 14, wherein the voltage loop further includes a resistor divider configuration coupled to an error amplifier, the error amplifier being coupled to a comparator.

19. The electronic device of claim 18, wherein the resistive voltage divider senses the system output voltage, wherein the system output voltage is compared with a reference voltage via the error amplifier to generate a compensation signal, the compensation signal being input to the comparator.

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