Light emitting device, display device having the same, and method for manufacturing the same

Abstract

The light emitting device may include: a substrate including a plurality of unit light emitting regions; and a first insulating layer to a fourth insulating layer sequentially arranged on the substrate. Each unit light emitting region may include: one or more light emitting diodes arranged on the first insulating layer and having a first end and a second end in the length direction; a first dam portion and a second dam portion arranged on the substrate and positioned at a fixed distance; a first electrode arranged on the first dam portion and a second electrode arranged on the second dam portion; a first contact electrode arranged on the first electrode and connecting the first electrode and the first end of the light emitting diode; a second contact electrode arranged on the second electrode and connecting the second electrode and the second end of the light emitting diode; and a conductive pattern arranged between the first insulating layer and the first contact electrode and surrounding the first electrode and the second electrode when viewed in a plane.

Description

Technical Field

[0001] The present invention relates to a light emitting device, a display device having the light emitting device, and a method for manufacturing the display device. Background Art

[0002] Light emitting diodes (hereinafter, referred to as LEDs) exhibit relatively satisfactory durability even under severe environmental conditions and have excellent performance in terms of life span and brightness. Recently, research for applying such LEDs to various display devices has been actively conducted.

[0003] As part of such research, a technology has been developed to manufacture micro-strip LEDs as small as micrometers or nanometers using an inorganic crystal structure (e.g., a structure in which a nitride-based semiconductor is grown). For example, the strip LEDs can be manufactured to a size small enough to constitute pixels of a self-luminous display device or the like. Summary of the invention

[0004] Technical issues

[0005] An object of the present invention is to provide a light emitting device having a stripe-type LED, a display device having the light emitting device, and a method for manufacturing the display device.

[0006] Technical Solution

[0007] According to aspects of the present invention, a light-emitting device is provided, which includes: a substrate, including a plurality of unit light-emitting regions; and a first insulating layer to a fourth insulating layer, which are sequentially arranged on the substrate, wherein each unit light-emitting region includes: at least one light-emitting element, which is arranged on the first insulating layer, and the at least one light-emitting element has a first end and a second end in its length direction; a first dam portion and a second dam portion, which are located on the substrate, and the first dam portion and the second dam portion are spaced apart from each other; a first electrode and a second electrode, the first electrode being located on the first dam portion, and the second electrode being located on the second dam portion; a first contact electrode, which is located on the first electrode, and the first contact electrode connects the first electrode and the first end of the light-emitting element; a second contact electrode, which is located on the second electrode, and the second contact electrode connects the second electrode and the second end of the light-emitting element; and a conductive pattern, which is arranged between the first insulating layer and the first contact electrode, and when viewed on a plane, the conductive pattern surrounds the first electrode and the second electrode.

[0008] In an embodiment of the present invention, the conductive pattern may be provided in a unit light emitting region corresponding to the light emitting element.

[0009] In an embodiment of the present invention, each unit light emitting region may further include: a first connection line connected to the first electrode, the first connection line extending in the first direction of the substrate; and a second connection line connected to the second electrode, the second connection line extending in the first direction. The first electrode may include a 1-1 electrode and a 1-2 electrode, the 1-1 electrode and the 1-2 electrode branching from the first connection line to be spaced apart from each other, and the second electrode is placed between the 1-1 electrode and the 1-2 electrode.

[0010] In the embodiment of the present invention, the conductive pattern may partially overlap the 1-1th electrode and the 1-2th electrode when viewed on a plane.

[0011] In an embodiment of the present invention, a first insulating layer may be provided between the substrate and the light emitting element and between the conductive pattern and the first electrode.

[0012] In an embodiment of the present invention, the first insulating layer disposed between the substrate and the light emitting element may support the light emitting element, and the first insulating layer disposed between the conductive pattern and the first electrode may protect the first electrode.

[0013] In an embodiment of the present invention, the light emitting device may further include: a first covering layer located on the first electrode to cover the first electrode; and a second covering layer located on the second electrode to cover the second electrode.

[0014] In an embodiment of the present invention, a second insulating layer may be disposed over the light emitting element to expose the first end and the second end of the light emitting element, a third insulating layer may be disposed over the first contact electrode to protect the first contact electrode, and a fourth insulating layer may be disposed over the second contact electrode to protect the second contact electrode.

[0015] In an embodiment of the present invention, the light emitting element may include: a first semiconductor layer doped with a first conductive dopant; a second semiconductor layer doped with a second conductive dopant; and an active layer disposed between the first semiconductor layer and the second semiconductor layer.

[0016] In an embodiment of the present invention, the light emitting element may include a micrometer-scale or nanometer-scale cylindrical or polygonal columnar light emitting diode.

[0017] According to one or more embodiments of the present invention, a display device having a light-emitting device includes: a substrate including a display area and a non-display area; a pixel circuit layer arranged in the display area, the pixel circuit layer including at least one transistor; and a display element layer including a first insulating layer to a fourth insulating layer sequentially arranged on the pixel circuit layer and a plurality of unit light-emitting areas emitting light therefrom, wherein each unit light-emitting area includes: at least one light-emitting element located on the first insulating layer, the at least one light-emitting element having a first end and a second end in a length direction thereof; a first dam portion and a second dam portion located on the pixel circuit layer, the first dam portion and the second dam portion being spaced apart from each other; a first electrode and a second electrode, the first electrode being located on the first dam portion and the second electrode being located on the second dam portion; a first contact electrode located on the first electrode, the first contact electrode connecting the first electrode and the first end of the light-emitting element; a second contact electrode located on the second electrode, the second contact electrode connecting the second electrode and the second end of the light-emitting element; and a conductive pattern arranged between the first insulating layer and the first contact electrode, the conductive pattern surrounding the first electrode and the second electrode when viewed on a plane.

[0018] According to one or more embodiments of the present invention, a method for manufacturing a display device includes: providing a substrate including a plurality of unit light-emitting areas; forming a first dam portion and a second dam portion spaced apart from each other by a certain distance in each unit light-emitting area; forming a first electrode, a second electrode spaced apart from the first electrode on the same plane, a first alignment line connected to the first electrode, and a second alignment line connected to the second electrode on the substrate on which the first dam portion and the second dam portion are formed; forming a first insulating material layer on the first electrode and the second electrode; forming a conductive pattern overlapping the first electrode on the first insulating material layer; self-aligning the plurality of light-emitting elements between the first electrode and the second electrode by dropping a solution including the plurality of light-emitting elements onto the first insulating material layer and applying a voltage to each of the first alignment line and the second alignment line; forming a conductive pattern by patterning the first insulating material layer so as to make the first electrode A first insulating material pattern exposing a portion of the electrode; forming a second insulating material pattern exposing the first end of each light emitting element, a portion of the first electrode and the conductive pattern by coating a second insulating material layer on the first insulating material pattern and then patterning the second insulating material layer; removing the first alignment line and the second alignment line on the substrate; forming a first contact electrode connecting the exposed first end of each light emitting element and the first electrode; forming a third insulating layer covering the first contact electrode on the first contact electrode, and forming a first insulating layer and a second insulating layer exposing the second end of each light emitting element and the second electrode by patterning the first insulating material pattern and the second insulating material pattern; forming a second contact electrode connecting the exposed second end of each light emitting element and the second electrode; and forming a fourth insulating layer covering the second contact electrode on the second contact electrode.

[0019] Beneficial Effects

[0020] According to aspects of embodiments of the present invention, a light emitting device capable of minimizing defects while improving light efficiency, a display device having the light emitting device, and a method of manufacturing the display device may be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a perspective view showing a light emitting element according to an embodiment of the present invention.

[0022] Figure 2a and Figure 2b is a circuit diagram showing a unit light emitting area of ​​a light emitting device according to an embodiment of the present invention.

[0023] Figure 3 It is shown that Figure 1 A plan view of a unit light emitting area of ​​a light emitting device of a light emitting element.

[0024] Figure 4 It is along Figure 3 A cross-sectional view taken along line II'.

[0025] Figure 5 shows a display device according to an embodiment of the present invention, Figure 5 is used Figure 1 Schematic plan view of a display device in which the light-emitting element shown in FIG. 1 is used as a light source.

[0026] Figure 6 It is shown Figure 5 An equivalent circuit diagram of one pixel among the pixels shown in .

[0027] Figure 7 yes Figure 5 An enlarged plan view of area EA1.

[0028] Figure 8 It is along Figure 7 A cross-sectional view taken along line II-II'.

[0029] Figure 9a to Figure 9h 1 is a schematic plan view sequentially illustrating a method of manufacturing a display device including a plurality of unit light emitting regions.

[0030] Figure 10a to Figure 10m is shown sequentially Figure 8 A cross-sectional view of a method for manufacturing a display device shown in FIG.

[0031] Fig.11 Shows Figure 8 Another form of the first dam portion and the second dam portion shown in Figure 8 is corresponding to Figure 7Cross-sectional view along line II-II'. DETAILED DESCRIPTION

[0032] The present invention can be applied to various changes and different shapes, so only some specific examples are described in detail. However, the examples described do not limit the present invention to any specific shape, but are applicable to all changes and equivalent materials and changes. The included drawings can be shown so that the drawings are enlarged or exaggerated for ease of understanding.

[0033] The same reference numerals always represent the same elements. In the accompanying drawings, for the sake of clarity, the thickness of certain lines, layers, components, elements or features may be exaggerated. It will be understood that although the terms "first", "second", etc. may be used here to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present invention, the "first" element discussed below may also be referred to as the "second" element. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form.

[0034] It will also be understood that when the term "comprising" and / or variations thereof are used in this specification, it indicates the presence of the stated features, wholes, steps, operations, elements and / or components, but does not exclude the presence and / or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In addition, the statement that an element such as a layer, region, substrate or plate is placed "on" or "above" another element not only indicates the situation in which the element is "directly" placed "on" the other element or the element is placed "directly above" the other element, but also indicates the situation in which another element is placed between the element and the other element. Similarly, the statement that an element such as a layer, region, substrate or plate is placed "under" or "below" another element not only indicates the situation in which the element is "directly" placed "under" the other element or the element is placed "directly below" the other element, but also indicates the situation in which another element is placed between the element and the other element.

[0035] Here, some exemplary embodiments of the present invention will be described in further detail with reference to the accompanying drawings.

[0036] Figure 1 1 is a perspective view showing a light emitting element according to an embodiment of the present invention. Figure 1 4 shows a cylindrical light emitting element LD, but the present invention is not limited thereto.

[0037] Reference Figure 1The light emitting element LD according to the embodiment of the present invention may include a first semiconductor layer 11 , a second semiconductor layer 13 , and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13 .

[0038] In the example, the light emitting element LD may be implemented as a stacked structure in which the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 are sequentially stacked. According to an embodiment of the present invention, the light emitting element LD may be provided in a strip shape extending in a certain direction. When it is assumed that the extending direction of the light emitting element LD is the length direction, the light emitting element LD may have one end and the other end along the length direction.

[0039] In an embodiment of the present invention, one of the first semiconductor layer 11 and the second semiconductor layer 13 may be disposed at one end, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 may be disposed at the other end.

[0040] In an embodiment of the present invention, the light emitting element LD may be arranged in a cylindrical shape. However, the term "strip type" may include a rod-like shape or a strip-like shape that is long in its length direction (i.e., its aspect ratio is greater than 1), such as a cylinder or a polygonal column. For example, the light emitting element LD may have a length greater than its diameter.

[0041] The light emitting element LD may be manufactured small enough to have a diameter and / or a length of, for example, a micrometer-order or nanometer-order level.

[0042] However, the size of the light emitting element LD according to the embodiment of the present invention is not limited thereto, and the size of the light emitting element LD may be changed to correspond to required conditions of a display device to which the light emitting element LD is applied.

[0043] The first semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For example, the first semiconductor layer 11 may include at least one semiconductor material among InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a semiconductor layer doped with a first conductive dopant such as Si, Ge, or Sn.

[0044] However, the material constituting the first semiconductor layer 11 is not limited thereto, and any one of various materials may be included in the first semiconductor layer 11 .

[0045] The active layer 12 is formed on the first semiconductor layer 11 and can be formed as a single quantum well structure or a multi-quantum well structure. According to an embodiment of the present invention, a cladding layer (not shown) doped with a conductive dopant can be formed on the top and / or bottom of the active layer 12. In an example, the cladding layer can be implemented as an AlGaN layer or an InAlGaN layer. In addition, it will be apparent that materials such as AlGaN or InAlGaN can also be used for the active layer 12.

[0046] When an electric field having a predetermined voltage or more is applied to both ends of the light emitting element LD, the light emitting element LD emits light due to the combination of electron-hole pairs in the active layer 12 .

[0047] The second semiconductor layer 13 is formed on the active layer 12 and may include a semiconductor layer having a type different from that of the first semiconductor layer 11. In an example, the second semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 may include at least one semiconductor material among InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a semiconductor layer doped with a second conductive dopant such as Mg.

[0048] However, the material constituting the second semiconductor layer 13 is not limited thereto, and any one of various materials may be included in the second semiconductor layer 13 .

[0049] According to an embodiment of the present invention, in addition to the first semiconductor layer 11, the active layer 12 and the second semiconductor layer 13, the light emitting element LD may also include another phosphor layer, another active layer, another semiconductor layer and / or another electrode layer on the top and / or bottom of each layer.

[0050] In addition, the light emitting element LD may further include an insulating film 14. However, according to an embodiment of the present invention, the insulating film 14 may be omitted or provided to cover only a portion of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0051] For example, the insulating film 14 may be provided at a portion other than both end portions of the light emitting element LD so that both end portions of the light emitting element LD may be exposed.

[0052] For ease of description, Figure 1 A state in which a part of the insulating film 14 is removed is shown. In an actual light emitting element LD, the entire side surface of the cylinder may be surrounded by the insulating film 14 .

[0053] The insulating film 14 may be disposed to surround at least a portion of an outer circumferential surface of the first semiconductor layer 11, the active layer 12, and / or the second semiconductor layer 13. In an example, the insulating film 14 may be disposed to surround at least an outer circumferential surface of the active layer 12.

[0054] According to an embodiment of the present invention, the insulating film 14 may include a transparent insulating material. For example, the insulating film 14 may include a transparent insulating material made of SiO 2 、Si 3 N 4 、Al 2 O 3 and TiO 2 However, the present invention is not limited thereto, and any one of various materials having insulating properties may be used.

[0055] When the insulating film 14 is provided in the light emitting element LD, the active layer 12 can be prevented from being short-circuited with the first electrode (not shown) and / or the second electrode (not shown).

[0056] In addition, when the insulating film 14 is formed, surface defects occurring in the light emitting element LD can be minimized, so that the life and efficiency of the light emitting element LD can be improved. In addition, when a plurality of light emitting elements LD are densely arranged, the insulating film 14 can prevent undesirable short circuits that may occur between the light emitting elements LD.

[0057] The above-mentioned light emitting element LD can be used as a light source of any of various display devices. In an example, the light emitting element LD can be used for a lighting device or a self-luminous display device.

[0058] Figure 2a and Figure 2b is a circuit diagram showing a unit light emitting area of ​​a light emitting device according to an embodiment of the present invention.

[0059] Specifically, Figure 2a and Figure 2b An example of a pixel constituting an active light emitting display panel is shown. In an embodiment of the present invention, a unit light emitting area may include one pixel.

[0060] Reference Figure 2a , the pixel PXL may include at least one LED LD and a driving circuit 144 connected to the light emitting element LD to drive the light emitting element LD.

[0061] A first electrode (eg, an anode electrode) of the light emitting element LD is connected to a first driving voltage VDD via the driving circuit 144, and a second electrode (eg, a cathode electrode) of the light emitting element LD is connected to a second driving voltage VSS.

[0062] The first driving voltage VDD and the second driving voltage VSS may have different potentials. In an example, the second driving voltage VSS may have a potential lower than the first driving voltage VDD by a threshold voltage of the light emitting element LD.

[0063] The light emitting element LD may emit light having brightness corresponding to the driving current controlled by the driving circuit 144 .

[0064] At the same time, despite Figure 2a An embodiment in which only one light emitting element LD is included in the pixel PXL is shown, but the present invention is not limited thereto. For example, the pixel PXL may include a plurality of light emitting elements LD connected in parallel to each other.

[0065] According to an embodiment of the present invention, the driving circuit 144 may include a first transistor M1, a second transistor M2 and a storage capacitor Cst. However, the structure of the driving circuit 144 is not limited to Figure 2a The embodiment shown in .

[0066] A first electrode of a first transistor (switching transistor) M1 is connected to a data line Dj, and a second electrode of the first transistor M1 is connected to a first node N1. The first electrode and the second electrode of the first transistor M1 are different electrodes. For example, when the first electrode is a source electrode, the second electrode may be a drain electrode. In addition, a gate electrode of the first transistor M1 is connected to a scan line Si.

[0067] When a voltage (e.g., a low voltage) that can turn on the first transistor M1 is supplied from the scan line Si, the first transistor M1 is turned on to electrically connect the data line Dj and the first node N1. The data signal of the corresponding frame is supplied to the data line Dj. Therefore, the data signal is transmitted to the first node N1. The data signal transmitted to the first node N1 is charged into the storage capacitor Cst.

[0068] A first electrode of the second transistor (driving transistor) M2 is connected to the first driving voltage VDD, and a second electrode of the second transistor M2 is connected to the first electrode of the light emitting element LD. In addition, a gate electrode of the second transistor M2 is connected to the first node N1. The second transistor M2 controls the amount of driving current supplied to the light emitting element LD corresponding to the voltage of the first node N1.

[0069] One electrode of the storage capacitor Cst is connected to the first driving voltage VDD, and the other electrode of the storage capacitor Cst is connected to the first node N1. The storage capacitor Cst charges a voltage corresponding to the data signal supplied to the first node N1 and maintains the charged voltage until a data signal of the next frame is supplied.

[0070] For convenience, Figure 2aA driving circuit 144 having a relatively simple structure is shown, which includes a first transistor M1 for transmitting a data signal to the inside of the pixel PXL, a storage capacitor Cst for storing the data signal, and a second transistor M2 for supplying a driving current corresponding to the data signal to the light emitting element LD.

[0071] However, the present invention is not limited thereto, and the structure of the driving circuit 144 may be modified and implemented differently. In an example, it will be apparent that the driving circuit 144 may further include at least one transistor element such as a transistor element for compensating for the threshold voltage of the second transistor M2, a transistor element for initializing the first node N1, and / or a transistor for controlling the light emitting time of the light emitting element LD, or other circuit elements such as a boosting capacitor for boosting the voltage of the first node N1.

[0072] although Figure 2a It is shown that both transistors (eg, the first transistor M1 and the second transistor M2) included in the driving circuit 144 are implemented as P-type transistors, but the present invention is not limited thereto. That is, at least one of the first transistor M1 and the second transistor M2 may be implemented as an N-type transistor.

[0073] Reference Figure 2b According to an embodiment of the present invention, the first transistor M1 and the second transistor M2 can be implemented as N-type transistors. In addition to the connection positions of some components being changed due to the change of transistor types, Figure 2b The construction and operation of the drive circuit 144 shown in FIG. Figure 2a The configuration and operation of the driving circuit 144 are similar. Therefore, a detailed description thereof will be omitted.

[0074] Figure 3 It is shown that Figure 1 A plan view of a unit light emitting area of ​​a light emitting device of a light emitting element, Figure 4 It is along Figure 3 A cross-sectional view taken along line II'.

[0075] exist Figure 3 In the embodiment, for the convenience of description, the light emitting elements are shown to be arranged in a horizontal direction, but the arrangement of the light emitting elements is not limited thereto. For example, the light emitting elements may be arranged between the first electrode and the second electrode in an inclined direction. Figure 3 In the embodiment, the unit light emitting area may be a pixel area of ​​each of a plurality of pixels included in the light emitting display panel.

[0076] In addition, despite Figure 3 , an embodiment in which one light emitting element is disposed in a unit light emitting region is shown, but the present invention is not limited thereto. For example, a plurality of light emitting elements may be disposed in a unit light emitting region.

[0077] Reference Figures 1 to 4 The light emitting device according to the embodiment of the present invention may include a substrate SUB, a barrier layer BRL, a plurality of light emitting elements LD, first and second dams PW1 and PW2, first and second electrodes REL1 and REL2, and first and second contact electrodes CNE1 and CNE2.

[0078] The substrate SUB may include an insulating material such as glass, an organic polymer, or quartz. In addition, the substrate SUB may be made of a material having flexibility to be bendable or foldable, and have a single-layer or multi-layer structure.

[0079] For example, the substrate SUB may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. However, the material constituting the substrate SUB may be variously changed.

[0080] The barrier layer BRL may prevent impurities from diffusing into the light emitting element LD.

[0081] Each of the light emitting elements LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 disposed between the first semiconductor layer 11 and the second semiconductor layer 13. In some embodiments, the light emitting element LD may further include an electrode layer (not shown) disposed on top of the second semiconductor layer 13.

[0082] The electrode layer may include a metal or a metal oxide. For example, the electrode layer may be formed of one or a mixture of chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), ITO, and oxides or alloys thereof, but the present invention is not limited thereto.

[0083] When the electrode layer is included, the second semiconductor layer 13 and the second electrode REL2 may be joined at a temperature lower than a temperature required in a process of forming the second contact electrode CNE2 at the junction of the second semiconductor layer 13 and the second electrode REL2 .

[0084] The light emitting element LD may include a first end portion EP1 and a second end portion EP2 along the first direction DR1. One of the first semiconductor layer 11 and the second semiconductor layer 13 may be disposed at the first end portion EP1, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 may be disposed at the second end portion EP2. In an embodiment of the present invention, each light emitting element LD may emit light of any one color of red, green, blue, and white.

[0085] A second insulating layer INS2 covering a portion of the upper surface of the light emitting element LD may be disposed over the light emitting element LD. Therefore, both end portions EP1 and EP2 of the light emitting element LD may be exposed to the outside.

[0086] In an embodiment of the present invention, the light emitting element LD may include a first light emitting element LD1 disposed at one side of the second electrode REL2 and a second light emitting element LD2 disposed at the other side of the second electrode REL2. When viewed on a plane, the first light emitting element LD1 and the second light emitting element LD2 may be spaced apart from each other with the second electrode REL2 interposed therebetween.

[0087] The first dam portion PW1 and the second dam portion PW2 may define a unit light emitting region in one pixel PXL. The first dam portion PW1 and the second dam portion PW2 may be disposed on the substrate SUB to be spaced apart from each other by a distance equal to or greater than the length of one light emitting element LD.

[0088] The first dam portion PW1 and the second dam portion PW2 may include an insulating material including an inorganic material or an organic material, but the present invention is not limited thereto. The first dam portion PW1 and the second dam portion PW2 may have a trapezoidal shape whose side surface is inclined at a predetermined angle. However, the present invention is not limited thereto, and the first dam portion PW1 and the second dam portion PW2 may have any one of various shapes such as a semi-elliptical shape, a circular shape, and a quadrilateral shape.

[0089] In an embodiment of the present invention, the first dam portion PW1 may include a 1-1 th dam portion PW1_1 disposed at one side of the second dam portion PW2 and a 1-2 th dam portion PW1_2 disposed at the other side of the second dam portion PW2 .

[0090] When viewed on a plane, the 1-1th dam portion PW1_1 and the 1-2th dam portion PW1_2 may be spaced apart from each other with the second dam portion PW2 interposed therebetween.

[0091] The 1-1 th dam portion PW1_1 , the second dam portion PW2 , and the 1-2 th dam portion PW1_2 may be disposed on the same plane on the substrate SUB and have the same height.

[0092] The first electrode REL1 may be disposed on the first dam PW1 . The first electrode REL1 is disposed adjacent to one of the first end portion EP1 and the second end portion EP2 of each light emitting element LD and may be electrically connected to the corresponding light emitting element LD through the first contact electrode CNE1 .

[0093] When viewed on a plane, the first electrode REL1 may include a 1-1 electrode REL1_1 and a 1-2 electrode REL1_2 branched to one side and the other side of the second electrode REL2. The second electrode REL2 may be disposed between the 1-1 electrode REL1_1 and the 1-2 electrode REL1_2.

[0094] The 1-1 electrode REL1_1 and the 1-2 electrode REL1_2 may have a bar shape along a second direction DR2 crossing the first direction DR1. The 1-1 electrode REL1_1 and the 1-2 electrode REL1_2 may be connected to a 1-1 connection line CNL1_1 extending along the first direction DR1.

[0095] The second electrode REL2 may be disposed between the first light emitting element LD1 and the second light emitting element LD2 on the substrate SUB. The second electrode REL2 may be electrically connected to the 2-1 th connection line CNL2_1 extending along the first direction DR1.

[0096] The first electrode REL1 and the second electrode REL2 may be provided in shapes corresponding to the first dam PW1 and the second dam PW2. Therefore, the first electrode REL1 may have a slope corresponding to the gradient of the first dam PW1, and the second electrode REL2 may have a slope corresponding to the gradient of the second dam PW2.

[0097] In an embodiment of the present invention, the first electrode REL1 and the second electrode REL2 may be made of a conductive material having a constant reflectivity. The first electrode REL1 and the second electrode REL2 may allow light emitted from both ends EP1 and EP2 of the light emitting element LD to advance in a direction (eg, a front direction) in which an image is displayed.

[0098] Specifically, since the first electrode REL1 and the second electrode REL2 have shapes corresponding to the shapes of the first dam portion PW1 and the second dam portion PW2, respectively, light emitted from both ends EP1 and EP2 of each light emitting element LD is reflected by the first electrode REL1 and the second electrode REL2 to further advance in the front direction. Therefore, the efficiency of light emitted from the light emitting element LD can be improved.

[0099] In the embodiment of the present invention, the first and second dams PW1 and PW2 together with the first and second electrodes REL1 and REL2 disposed on the top thereof may function as a reflective member for improving the efficiency of light emitted from each light emitting element LD.

[0100] Any one of the first electrode REL1 and the second electrode REL2 may be an anode electrode, and the other of the first electrode REL1 and the second electrode REL2 may be a cathode electrode. In an embodiment of the present invention, the first electrode REL1 may be an anode electrode, and the second electrode REL2 may be a cathode electrode.

[0101] The first electrode REL1 and the second electrode REL2 may be disposed on the same plane and may have the same height. When the first electrode REL1 and the second electrode REL2 have the same height, the light emitting element LD may be more stably connected to the first electrode REL1 and the second electrode REL2.

[0102] Although the case where the first and second electrodes REL1 and REL2 are directly disposed on the substrate SUB is shown for ease of description, the present invention is not limited thereto. For example, a component for driving the light emitting device in a passive matrix manner or an active matrix manner may be further disposed between the first and second electrodes REL1 and REL2 and the substrate SUB.

[0103] When the light emitting device is driven in an active matrix manner, a signal line, an insulating layer and / or a transistor may be disposed between the first and second electrodes REL1 and REL2 and the substrate SUB.

[0104] The signal line may include a scan line, a data line, a power line, etc. The transistor is connected to the signal line, and may include a gate electrode, a semiconductor layer, a source electrode, and a drain electrode.

[0105] One of the source electrode and the drain electrode of the transistor can be connected to any one of the first electrode REL1 and the second electrode REL2, and the data signal of the data line can be applied to one of the first electrode REL1 and the second electrode REL2 through the transistor. It will be apparent that the signal line, the insulating layer and / or the transistor can be provided in various numbers and configurations.

[0106] In an embodiment of the present invention, the first electrode REL1 may be connected to the 1-1th connection line CNL1_1. The 1-1th connection line CNL1_1 may be integrally provided with the first electrode REL1.

[0107] The 1-1th connection line CNL1_1 may be electrically connected to the transistor through a contact hole (not shown). Therefore, a signal provided to the transistor may be applied to the first electrode REL1 through the 1-1th connection line CNL1_1.

[0108] The second electrode REL2 may be connected to the 2-1th connection line CNL2_1. The 2-1th connection line CNL2_1 may be integrally disposed with the second electrode REL2 and extend in the first direction DR1.

[0109] When the light emitting device is driven in an active matrix manner, the 2-1st connection line CNL2_1 may be electrically connected to the signal line through a contact hole (not shown). Therefore, the voltage of the signal line may be applied to the second electrode REL2 through the 2-1st connection line CNL2_1. For example, when the second driving voltage VSS is applied to the signal line, the second driving voltage VSS may be applied to the second electrode REL2 through the 2-1st connection line CNL2_1.

[0110] The first and second electrodes REL1 and REL2 and the 1-1th and 2-1th connection lines CNL1_1 and CNL2_1 may be made of a conductive material. The conductive material may include a metal (such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr) or any alloy thereof, a conductive oxide (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO)), a conductive polymer (such as PEDOT), etc.

[0111] In addition, the first and second electrodes REL1 and REL2 and the 1-1 and 2-1 connection wires CNL1_1 and CNL2_1 may be formed as a single layer. However, the present invention is not limited thereto, and the first and second electrodes REL1 and REL2 and the 1-1 and 2-1 connection wires CNL1_1 and CNL2_1 may be formed as a multilayer in which two or more materials among metals, alloys, conductive oxides, and conductive polymers are stacked.

[0112] However, the materials of the first and second electrodes REL1 and REL2 and the 1-1 and 2-1 connecting wires CNL1_1 and CNL2_1 are not limited to the above materials. For example, the first and second electrodes REL1 and REL2 and the 1-1 and 2-1 connecting wires CNL1_1 and CNL2_1 may be made of a conductive material having a constant reflectivity to allow light emitted from both ends EP1 and EP2 of each light emitting element LD to advance in a direction (e.g., a front direction) in which an image is displayed.

[0113] A first contact electrode CNE1 for stably connecting the first electrode REL1 and any one of both end portions EP1 and EP2 of each light emitting element LD electrically and / or physically may be disposed on the first electrode REL1 .

[0114] The first contact electrode CNE1 may be made of a transparent conductive material so that light emitted from each of the light emitting elements LD and then reflected by the first electrode REL1 in the front direction may advance in the front direction without loss. For example, the transparent conductive material may include any one of ITO, IZO, ITZO, etc. However, the material of the first contact electrode CNE1 is not limited to the above materials.

[0115] When viewed on a plane, the first contact electrode CNE1 may cover and overlap the first electrode REL1. In addition, the first contact electrode CNE1 may partially overlap one of both end portions EP1 and EP2 of each light emitting element LD.

[0116] In an embodiment of the present invention, the first contact electrode CNE1 may include a 1-1th contact electrode CNE1_1 disposed on the 1-1th electrode REL1_1 and a 1-2th contact electrode CNE1_2 disposed on the 1-2th electrode REL1_2 .

[0117] The 1-1th contact electrode CNE1_1 may overlap the first end EP1 of the first light emitting element LD1 and the 1-1th electrode REL1_1 when viewed on a plane. Also, the 1-2th contact electrode CNE1_2 may overlap the second end EP2 of the second light emitting element LD2 and the 1-2th electrode REL1_2 when viewed on a plane.

[0118] A third insulating layer INS3 covering the first contact electrode CNE1 may be disposed on the first contact electrode CNE1. The third insulating layer INS3 allows the first contact electrode CNE1 not to be exposed to the outside, so that corrosion of the first contact electrode CNE1 may be prevented.

[0119] The third insulating layer INS3 may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. The third insulating layer INS3 may be provided as a single layer as shown in the drawings. However, the present invention is not limited thereto, and the third insulating layer INS3 may be provided as a multilayer.

[0120] When the third insulating layer INS3 is provided as a multilayer, the third insulating layer INS3 may have a structure in which a plurality of inorganic insulating layers and a plurality of organic insulating layers are alternately stacked. For example, the third insulating layer INS3 may have a structure in which a first inorganic insulating layer, an organic insulating layer, and a second inorganic insulating layer are sequentially stacked.

[0121] The second contact electrode CNE2 may be disposed on the second electrode REL2. When viewed on a plane, the second contact electrode CNE2 may cover the second electrode REL2 and overlap the second electrode REL2. In addition, the second contact electrode CNE2 may overlap each of the second end EP2 of the first light emitting element LD1 and the first end EP1 of the second light emitting element LD2.

[0122] The second contact electrode CNE2 may be made of the same material as that of the first contact electrode CNE1, but the present invention is not limited thereto.

[0123] A fourth insulating layer INS4 covering the second contact electrode CNE2 may be disposed on the second contact electrode CNE2.

[0124] The fourth insulating layer INS4 allows the second contact electrode CNE2 not to be exposed to the outside, so that corrosion of the second contact electrode CNE2 can be prevented. The fourth insulating layer INS4 may be configured as any one of an inorganic insulating layer and an organic insulating layer.

[0125] An overcoat layer OC may be disposed on the fourth insulating layer INS4.

[0126] The overcoat layer OC may be a planarization layer for reducing a step difference generated by the first and second dams PW1 and PW2, the first and second electrodes REL1 and REL2, the first and second contact electrodes CNE1 and CNE2, etc. disposed on the bottom thereof. In addition, the overcoat layer OC may be an encapsulation layer for preventing oxygen, moisture, etc. from penetrating into the light emitting element LD.

[0127] In some embodiments, the overcoat layer OC may be omitted. When the overcoat layer OC is omitted, the fourth insulating layer INS4 may function as an encapsulation layer for preventing oxygen, moisture, etc. from penetrating into the light emitting element LD.

[0128] As described above, the first end EP1 of the first light emitting element LD1 may be connected to the 1-1th electrode REL1_1, and the second end EP2 of the first light emitting element LD1 may be connected to one side of the second electrode REL2. For example, the first semiconductor layer 11 of the first light emitting element LD1 may be connected to the 1-1th electrode REL1_1, and the second semiconductor layer 13 of the first light emitting element LD1 may be connected to one side of the second electrode REL2.

[0129] Therefore, the first semiconductor layer 11 and the second semiconductor layer 13 of the first light emitting element LD1 may be applied with a predetermined voltage through the 1-1 electrode REL1_1 and the second electrode REL2. When an electric field having a predetermined voltage or more is applied to both ends EP1 and EP2 of the first light emitting element LD1, the first light emitting element LD1 emits light while electron-hole pairs are combined in the active layer 12.

[0130] In addition, the first end EP1 of the second light emitting element LD2 may be connected to the other side of the second electrode REL2, and the second end EP2 of the second light emitting element LD2 may be connected to the 1-2 electrode REL1_2. For example, the first semiconductor layer 11 of the second light emitting element LD2 may be connected to the 1-2 electrode REL1_2, and the second semiconductor layer 13 of the second light emitting element LD2 may be connected to the other side of the second electrode REL2.

[0131] Therefore, the first semiconductor layer 11 and the second semiconductor layer 13 of the second light emitting element LD2 can be applied with a predetermined voltage through the 1-2 electrode REL1_2 and the second electrode REL2. When an electric field having a predetermined voltage or more is applied to both ends EP1 and EP2 of the second light emitting element LD2, the second light emitting element LD2 emits light while electron-hole pairs are combined in the active layer 12.

[0132] In addition, each unit light emitting region of the light emitting device may further include a first cover layer CPL1, a second cover layer CPL2, and a conductive pattern CP.

[0133] The first cover layer CPL1 may be disposed on the first electrode REL1. The first cover layer CPL1 may prevent damage to the first electrode REL1 due to defects that may occur in a manufacturing process of the light emitting device, and further strengthen adhesion between the first electrode REL1 and the substrate SUB.

[0134] The first cover layer CPL1 may be made of a transparent conductive material such as IZO to minimize the loss of light emitted from each light emitting element LD and then reflected by the first electrode REL1 in a front direction.

[0135] In an embodiment of the present invention, the first cover layer CPL1 may include a 1-1th cover layer CPL1_1 and a 1-2th cover layer CPL1_2. The 1-1th cover layer CPL1_1 may be disposed on the 1-1th electrode REL1_1, and the 1-2th cover layer CPL1_2 may be disposed on the 1-2th electrode REL1_2.

[0136] The 1-1st and 1-2nd cover layers CPL1_1 and CPL1_2 may be connected to the 1-2nd connection line CNL1_2 extending in the first direction DR1. The 1-2nd connection line CNL1_2 may be integrally provided with the 1-1st and 1-2 cover layers CPL1_1 and CPL1_2 and include the same material as those of the 1-1st and 1-2 cover layers CPL1_1 and CPL1_2.

[0137] The 1-2 connection line CNL1_2 may be disposed on the 1-1 connection line CNL1_1 and overlap the 1-1 connection line CNL1_1 when viewed on a plane. The 1-1 connection line CNL1_1 and the 1-2 connection line CNL1_2 may constitute a first connection line CNL1 in the unit light emitting region.

[0138] The second cover layer CPL2 may be disposed on the second electrode REL2. The second cover layer CPL2 may prevent damage to the second electrode REL2 due to defects that may occur in a manufacturing process of the light emitting device, and further strengthen adhesion between the second electrode REL2 and the substrate SUB.

[0139] The second cover layer CPL2 may be disposed in the same layer as the first cover layer CPL1 and include the same material as the first cover layer CPL1. The second cover layer CPL2 may be connected to the 2-2nd connection line CNL2_2 extending in the first direction DR1. The 2-2nd connection line CNL2_2 may be integrally disposed with the second cover layer CPL2 and include the same material as the second cover layer CPL2.

[0140] The 2-2nd connection line CNL2_2 may be disposed on the 2-1st connection line CNL2_1 and overlap the 2-1st connection line CNL2_1 when viewed on a plane. The 2-1st connection line CNL2_1 and the 2-2nd connection line CNL2_2 may constitute a second connection line CNL2 in the unit light emitting region.

[0141] The conductive pattern CP may be provided in a shape surrounding the first electrode REL1 and the second electrode REL2 in the unit light emitting region. When viewed on a plane, the conductive pattern CP may partially overlap the first electrode REL1 and the first contact electrode CNE1.

[0142] The conductive pattern CP is used to allow the light emitting element LD to be aligned in the unit light emitting region. That is, the conductive pattern CP may allow the light emitting element LD to be misaligned in an unnecessary region (eg, outside the unit light emitting region).

[0143] The conductive pattern CP may eliminate an electric field generated between two adjacent unit light emitting regions to allow the light emitting element LD to be misaligned outside the corresponding unit light emitting region.

[0144] The conductive pattern CP may be in a floating state in which it is electrically isolated, but the present invention is not limited thereto.

[0145] In an embodiment of the present invention, the conductive pattern CP may be disposed on the first electrode REL1 with the first insulating layer INS1 interposed therebetween. The first contact electrode CNE1 may be disposed on the conductive pattern CP.

[0146] Here, we will refer to Figure 3 and Figure 4 The structure of the light emitting device according to the embodiment of the present invention is described along a stacking order.

[0147] The first dam PW1 and the second dam PW2 may be disposed on the substrate SUB on which the barrier layer BRL is disposed. The first dam PW1 and the second dam PW2 may be disposed on the barrier layer BRL to be spaced a distance apart from each other.

[0148] The first electrode REL1 may be disposed on the first dam PW1, and the second electrode REL2 may be disposed on the second dam PW2. Each of the first electrode REL1 and the second electrode REL2 may be disposed on the same plane as the corresponding dam to have a shape corresponding to that of the corresponding dam.

[0149] The first cover layer CPL1 may be disposed on the first electrode REL1 , and the second cover layer CPL2 may be disposed on the second electrode REL2 .

[0150] The first insulating layer INS1 may be disposed on the substrate SUB including the first cover layer CPL1 and the second cover layer CPL2. The first insulating layer INS1 may overlap a portion of the first cover layer CPL1 and may be disposed between the substrate SUB and one light emitting element LD.

[0151] Here, for convenience of description, the first insulating layer INS1 disposed between the substrate SUB and one light emitting element LD may be referred to as an 'insulating pattern'.

[0152] The insulating pattern INS1 may fill in a space between the substrate SUB and one light emitting element LD, stably support the one light emitting element LD, and prevent the one light emitting element LD from being separated.

[0153] The insulating pattern INS1 may cover one end portion of the first cover layer CPL1 and be spaced apart from the first electrode REL1. In addition, the insulating pattern INS1 may cover one end portion of the second cover layer CPL2 and be spaced apart from the second electrode REL2.

[0154] In an embodiment of the present invention, the first insulating layer INS1 may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material.

[0155] The first insulating layer INS1 and the first and second cover layers CPL1 and CPL2 may cover the first and second electrodes REL1 and REL2 to protect the first and second electrodes REL1 and REL2. The first insulating layer INS1 may prevent the first and second electrodes REL1 and REL2 from being damaged due to defects that may occur in the manufacturing process of the light emitting device.

[0156] The conductive pattern CP may be disposed on the substrate SUB having the first insulating layer INS1 disposed thereon. The conductive pattern CP may be disposed on the first cover layer CPL1 and the first electrode REL1 with the first insulating layer INS1 interposed therebetween.

[0157] The light emitting element LD may be aligned on the substrate SUB including the conductive pattern CP. The light emitting element LD may be self-aligned by an electric field formed between the first electrode REL1 and the second electrode REL2 to be disposed on the first insulating pattern INS1 between the first electrode REL1 and the second electrode REL2.

[0158] A second insulating layer INS2 covering a portion of an upper surface of the light emitting element LD may be disposed on the light emitting element LD. The second insulating layer INS2 may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material.

[0159] The first contact electrode CNE1 may be disposed on the substrate SUB having the second insulating layer INS2 disposed thereon. The first contact electrode CNE1 may cover the first cover layer CPL1 and be electrically connected to the first electrode REL1 through the first cover layer CPL1.

[0160] In some embodiments, when the first cover layer CPL1 is omitted, the first contact electrode CNE1 may be disposed directly on the first electrode REL1 to be directly connected to the first electrode REL1.

[0161] The third insulating layer INS3 may be disposed on the substrate SUB on which the first contact electrode CNE1 is disposed. The third insulating layer INS3 may be disposed on the substrate SUB to cover the first contact electrode CNE1 and the second insulating layer INS2.

[0162] The second contact electrode CNE2 may be disposed on the substrate SUB on which the third insulating layer INS3 is disposed. The second contact electrode CNE2 may cover the second cover layer CPL2 and be connected to the second electrode REL2 through the second cover layer CPL2.

[0163] In some embodiments, when the second cover layer CPL2 is omitted, the second contact electrode CNE2 may be disposed directly on the second electrode REL2 to be directly connected to the second electrode REL2.

[0164] A fourth insulating layer INS4 may be disposed on the substrate SUB on which the second contact electrode CNE2 is disposed.

[0165] An overcoat layer OC may be disposed on the fourth insulating layer INS4.

[0166] Figure 5shows a display device according to an embodiment of the present invention, Figure 5 is used Figure 1 Schematic plan view of a display device in which the light-emitting element shown in FIG. 1 is used as a light source.

[0167] Reference Figure 1 and Figure 5 , a display device according to the present invention may include a substrate SUB, pixels PXL disposed on the substrate SUB, a driving unit disposed on the substrate SUB and driving the pixels PXL, and a line unit (not shown) connecting the pixels PXL and the driving unit.

[0168] The substrate SUB may include a display area DA and a non-display area NDA.

[0169] The display area DA may be an area in which pixels PXL for displaying an image are disposed. The non-display area NDA may be an area in which a driving unit for driving the pixels PXL and a portion of a line unit (not shown) connecting the pixels PXL and the driving unit are disposed.

[0170] The display area DA may have any of various shapes. For example, the display area DA may be set to any of various shapes such as a closed polygon including linear edges, a circle including curved edges, an ellipse, etc., and a semicircle including linear edges and curved edges, a semiellipse, etc.

[0171] When the display area DA includes a plurality of regions, each region may also be set to any one of various shapes (such as a closed polygon including linear edges, a circle including curved edges, an ellipse, etc., and a semicircle including linear edges and curved edges, a semiellipse, etc.). In addition, the areas of the plurality of regions may be the same as or different from each other.

[0172] In the embodiment of the present invention, the case where the display area DA is provided as one area having a quadrilateral shape including linear sides is described as an example.

[0173] The non-display area NDA may be disposed at at least one side of the display area DA. In an embodiment of the present invention, the non-display area NDA may surround the periphery of the display area DA.

[0174] The pixels PXL may be disposed in the display area DA on the substrate SUB. Each of the pixels PXL is a minimum unit for displaying an image, and may be provided in plural.

[0175] Each pixel PXL may emit light of any one color among red, green, and blue, but the present invention is not limited thereto. For example, the pixel PXL may emit light of any one color among cyan, magenta, yellow, and white.

[0176] The pixels PXL may be provided in plural to be arranged in a matrix along rows extending in a first direction DR1 and columns extending in a second direction DR2 crossing the first direction DR1. However, the arrangement form of the pixels PXL is not particularly limited, and the pixels PXL may be arranged in any of various forms.

[0177] The driving unit provides a signal to each pixel PXL through the line unit, so that the driving of the pixel PXL can be controlled. Figure 5 In the figure, for the convenience of description, the line unit is omitted.

[0178] The driving unit may include a scan driver SDV for providing a scan signal to the pixel PXL through a scan line, an emission driver EDV for providing an emission control signal to the pixel PXL through an emission control line, a data driver DDV for providing a data signal to the pixel PXL through a data line, and a timing controller (not shown). The timing controller may control the scan driver SDV, the emission driver EDV, and the data driver DDV.

[0179] Figure 6 It is shown Figure 5 An equivalent circuit diagram of one of the pixels shown in FIG. Figure 6 , for convenience of description, a pixel PXL connected to a j-th data line Dj, an i-1-th scan line Si-1, an i-th scan line Si, and an i+1-th scan line Si+1 is shown.

[0180] Reference Figure 5 and Figure 6 , the pixel PXL according to the embodiment of the present invention may include a light emitting element LD, first to seventh transistors T1 to T7 , and a storage capacitor Cst.

[0181] One end of the light emitting element LD is connected to the first transistor T1 via the sixth transistor T6, and the other end of the light emitting element LD is connected to the second driving voltage VSS. The light emitting element LD may generate light having a predetermined brightness corresponding to the amount of current supplied from the first transistor T1.

[0182] The source electrode of the first transistor (driving transistor) T1 is connected to the first driving voltage VDD via the fifth transistor T5, and the drain electrode of the first transistor T1 is connected to one end of the light emitting element LD via the sixth transistor T6. The first transistor T1 controls the amount of current flowing from the first driving voltage VDD to the second driving voltage VSS via the light emitting element LD corresponding to the voltage of the first node N1 as its gate electrode.

[0183] The second transistor (switching transistor) T2 is connected between the j-th data line Dj and the source electrode of the first transistor T1. In addition, the gate electrode of the second transistor T2 is connected to the i-th scan line Si. When the scan signal is supplied to the i-th scan line Si, the second transistor T2 is turned on to electrically connect the j-th data line Dj and the source electrode of the first transistor T1.

[0184] The third transistor T3 is connected between the drain electrode of the first transistor T1 and the first node N1. In addition, the gate electrode of the third transistor T3 is connected to the i-th scan line Si. When the scan signal is supplied to the i-th scan line Si, the third transistor T3 is turned on to electrically connect the drain electrode of the first transistor T1 and the first node N1. Therefore, when the third transistor T3 is turned on, the first transistor T1 is diode-connected.

[0185] The fourth transistor T4 is connected between the first node N1 and the initialization power supply Vint. In addition, the gate electrode of the fourth transistor T4 is connected to the i-1th scan line Si-1. When the scan signal is supplied to the i-1th scan line Si-1, the fourth transistor T4 is turned on to supply the voltage of the initialization power supply Vint to the first node N1. The initialization power supply Vint is set to a voltage lower than the data signal.

[0186] The fifth transistor T5 is connected between the first driving voltage VDD and the source electrode of the first transistor T1. In addition, the gate electrode of the fifth transistor T5 is connected to the i-th emission control line Ei. When the emission control signal is supplied to the i-th emission control line Ei, the fifth transistor T5 is turned off, otherwise the fifth transistor T5 is turned on.

[0187] The sixth transistor T6 is connected between the drain electrode of the first transistor T1 and one end of the light emitting element LD. In addition, the gate electrode of the sixth transistor T6 is connected to the i-th emission control line Ei. When the emission control signal is supplied to the i-th emission control line Ei, the sixth transistor T6 is turned off, otherwise the sixth transistor T6 is turned on.

[0188] The seventh transistor T7 is connected between the initialization power supply Vint and one end of the light emitting element LD. In addition, the gate electrode of the seventh transistor T7 is connected to the i+1th scan line Si+1. When the scan signal is supplied to the i+1th scan line Si+1, the seventh transistor T7 is turned on to supply the voltage of the initialization power supply Vint to one end of the light emitting element LD.

[0189] The storage capacitor Cst is connected between the first driving voltage VDD and the first node N1. The storage capacitor Cst stores a voltage corresponding to the data signal and a threshold voltage of the first transistor T1.

[0190] Meanwhile, when the light emitting element LD is aligned in the pixel PXL, a first alignment line (not shown) is connected to the second node N2, and a second alignment line (not shown) is connected to the other end of the light emitting element LD.

[0191] A ground voltage may be applied to the first alignment line, and an AC voltage may be applied to the second alignment line. When predetermined voltages having different voltage levels are applied to the first alignment line and the second alignment line, respectively, an electric field may be formed between the second node N2 and the other end of the light emitting element LD. The light emitting element LD may be aligned in a desired region in the pixel PXL by the electric field.

[0192] Figure 7 yes Figure 5 An enlarged plan view of area "EA1" Figure 8 It is along Figure 7 A cross-sectional view taken along line II-II'.

[0193] exist Figure 7 In the figure, for the convenience of description, a case in which a plurality of light emitting elements are arranged in a horizontal direction is shown, but the arrangement of the light emitting elements is not limited thereto.

[0194] In addition, Figure 7 In the figure, for the convenience of description, illustration of transistors connected to light emitting elements and signal lines connected to the transistors will be omitted.

[0195] In this embodiment, the parts different from those of the above-described embodiment will be mainly described to avoid redundancy. The parts not specifically described in this embodiment follow those of the above-described embodiment. In addition, the same reference numerals represent the same components, and similar reference numerals represent similar components. Figure 7 and Figure 8 In the embodiment, the unit light emitting area may be a pixel area set in one pixel.

[0196] Reference Figures 1 to 8 The display device according to the embodiment of the present invention may include a substrate SUB on which first to third pixels PXL1 to PXL3 are disposed. Each of the first to third pixels PXL1 to PXL3 is a pixel region in which an image is displayed and may be a unit light emitting region from which light is emitted.

[0197] Each of the first to third pixels PXL1 to PXL3 may include a substrate SUB, a pixel circuit layer PCL disposed on the substrate SUB, and a display element layer DPL disposed on the pixel circuit layer PCL.

[0198] The substrate SUB may include an insulating material such as glass, an organic polymer, or quartz. The substrate SUB may be made of a material having flexibility so as to be bendable or foldable. The substrate SUB may have a single-layer or multi-layer structure.

[0199] The pixel circuit layer PCL may include a buffer layer BFL disposed on the substrate SUB, first and second transistors T1 and T2 disposed on the buffer layer BFL, and a driving voltage line DVL.

[0200] The buffer layer BFL may prevent impurities from diffusing into the first transistor T1 and the second transistor T2. Although the buffer layer BFL may be provided as a single layer, the buffer layer BFL may be provided as a multilayer including at least two layers.

[0201] When the buffer layer BFL is provided as a plurality of layers, the layers may be formed of the same material or may be formed of different materials. The buffer layer BFL may be omitted according to the material of the substrate SUB and process conditions.

[0202] The first transistor T1 may be a driving transistor electrically connected to some of the plurality of light emitting elements LD provided in the display element layer DPL to drive the corresponding light emitting elements LD, and the second transistor T2 may be a switching transistor for switching the first transistor T1.

[0203] Each of the first and second transistors T1 and T2 may include a semiconductor layer SCL, a gate electrode GE, and first and second terminals EL1 and EL2.

[0204] The semiconductor layer SCL may be disposed on the buffer layer BFL. The semiconductor layer SCL may include a first region in contact with the first terminal EL1 and a second region in contact with the second terminal EL2. The region between the first region and the second region may be a channel region. In an embodiment of the present invention, the first region may be one of the source region and the drain region, and the second region may be the other of the source region and the drain region.

[0205] The semiconductor layer SCL may be a semiconductor pattern made of polysilicon, amorphous silicon, oxide semiconductor, etc. The channel region is a semiconductor pattern not doped with impurities and may be an intrinsic semiconductor. The first region and the second region are semiconductor patterns doped with impurities.

[0206] The gate electrode GE may be disposed on the semiconductor layer SCL with the gate insulating layer GI interposed therebetween.

[0207] The first and second terminals EL1 and EL2 may respectively contact the first and second regions of the semiconductor layer SCL through contact holes penetrating the interlayer insulating layer ILD and the gate insulating layer GI.

[0208] The driving voltage line DVL may be disposed on the gate insulating layer GI to be connected to the bridge pattern BRP through a contact hole penetrating the interlayer insulating layer ILD.

[0209] A protection layer PSV may be disposed on the first and second transistors T1 and T2 and the driving voltage line DVL.

[0210] The display element layer DPL of each of the first to third pixels PXL1 to PXL3 may include first and second dams PW1 and PW2 disposed on the protection layer PSV, first and second electrodes REL1 and REL2 , a light emitting element LD, and first and second contact electrodes CNE1 and CNE2 .

[0211] The light emitting element LD may include a first light emitting element LD1 and a second light emitting element LD2. Each of the first light emitting element LD1 and the second light emitting element LD2 may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 disposed between the first semiconductor layer 11 and the second semiconductor layer 13. In addition, each of the first light emitting element LD1 and the second light emitting element LD2 may include a first end portion EP1 and a second end portion EP2 along a length direction thereof.

[0212] The first end portion EP1 and the second end portion EP2 of each of the first light emitting element LD1 and the second light emitting element LD2 may be exposed to the outside by the second insulating layer INS2 covering a portion of the upper surface of each of the first light emitting element LD1 and the second light emitting element LD2 .

[0213] Each of the first light emitting element LD1 and the second light emitting element LD2 may emit colored light and / or white light.

[0214] The first dam PW1 and the second dam PW2 may be spaced apart from each other on the protection layer PSV. The first dam PW1 and the second dam PW2 may have a trapezoidal shape whose side surfaces are inclined at a predetermined angle, but the present invention is not limited thereto.

[0215] When viewed on a plane, the first dam portion PW1 may include a 1-1 th dam portion PW1_1 and a 1-2 th dam portion PW1_2 which are spaced a certain distance apart from each other with the second dam portion PW2 interposed therebetween.

[0216] The first electrode REL1 may be disposed on the first dam PW1, and the second electrode REL2 may be disposed on the second dam PW2. The first electrode REL1 may have a shape corresponding to that of the first dam PW1, and the second electrode REL2 may have a shape corresponding to that of the second dam PW2.

[0217] The first electrode REL1 may include a 1-1 electrode REL1_1 disposed on the 1-1 dam PW1_1 and a 1-2 electrode REL1_2 disposed on the 1-2 dam PW1_2. The 1-1 electrode REL1_1 and the 1-2 electrode REL1_2 may be connected to a 1-1 connection line CNL1_1 extending in the first direction DR1.

[0218] The 1-1 electrode REL1_1 may be disposed adjacent to the first end EP1 of the first light emitting element LD1, and the 1-2 electrode REL1_2 may be disposed adjacent to the second end EP2 of the second light emitting element LD2. When viewed on a plane, the 1-1 electrode REL1_1 and the 1-2 electrode REL1_2 may be spaced a certain distance apart from each other with the second electrode REL2 interposed therebetween.

[0219] The second electrode REL2 may be disposed on the second dam PW2 , and when viewed on a plane, the second electrode REL2 may be disposed between the first light emitting element LD1 and the second light emitting element LD2 .

[0220] One side of the second electrode REL2 may be disposed adjacent to the second end portion EP2 of the first light emitting element LD1 , and the other side of the second electrode REL2 may be disposed adjacent to the first end portion EP1 of the second light emitting element LD2 .

[0221] The second electrode REL2 may be connected to the 2-1 th connection line CNL2_1 extending in the first direction DR1.

[0222] In an embodiment of the present invention, the 1-1th connection wire CNL1_1 may be a wire for applying a voltage to the first electrode REL1 in alignment with the corresponding light emitting element LD. The 2-1th connection wire CNL2_1 may be a wire for applying a voltage to the second electrode REL2 in alignment with the corresponding light emitting element LD.

[0223] In an embodiment of the present invention, the first electrode REL1 and the 1-1th connection line CNL1_1 may be integrally provided, and the second electrode REL2 and the 2-1th connection line CNL2_1 may be integrally provided.

[0224] A first contact electrode CNE1 for stably connecting the first electrode REL1 and the light emitting element LD electrically and / or physically may be disposed on the first electrode REL1 .

[0225] The first contact electrode CNE1 may include a 1-1th contact electrode CNE1_1 disposed on the 1-1th electrode REL1_1 and a 1-2th contact electrode CNE1_2 disposed on the 1-2th electrode REL1_2 .

[0226] The 1-1st contact electrode CNE1_1 may ohmically contact each of the first end portion EP1 of the first light emitting element LD1 and the 1-1st electrode REL1_1. The 1-2nd contact electrode CNE1_2 may ohmically contact each of the second end portion EP2 of the second light emitting element LD2 and the 1-2nd electrode REL1_2.

[0227] The third insulating layer INS3 may be disposed on the first contact electrode CNE1. The third insulating layer INS3 may cover the first contact electrode CNE1 disposed on the bottom thereof so that the first contact electrode CNE1 is not exposed to the outside.

[0228] A second contact electrode CNE2 for stably connecting the second electrode REL2 and the first and second light emitting elements LD1 and LD2 electrically and / or physically may be disposed on the second electrode REL2 .

[0229] One side of the second contact electrode CNE2 may ohm-contact each of one side of the second electrode REL2 and the second end EP2 of the first light emitting element LD1. The other side of the second contact electrode CNE2 may ohm-contact each of the other side of the second electrode REL2 and the first end EP1 of the second light emitting element LD2.

[0230] The fourth insulating layer INS4 may be disposed on the second contact electrode CNE2. The fourth insulating layer INS4 may cover the second contact electrode CNE2 disposed on the bottom thereof so that the second contact electrode CNE2 is not exposed to the outside.

[0231] An overcoat layer OC may be disposed on the fourth insulating layer INS4.

[0232] In addition, the display element layer DPL of each of the first to third pixels PXL1 to PXL3 may further include a first cover layer CPL1 , a second cover layer CPL2 , and a conductive pattern CP.

[0233] The first cover layer CPL1 may be disposed on the first electrode REL1. The first cover layer CPL1 may include a 1-1th cover layer CPL1_1 disposed on the 1-1th electrode REL1_1 and a 1-2th cover layer CPL1_2 disposed on the 1-2th electrode REL1_2.

[0234] The 1-1th cover layer CPL1_1 and the 1-2th cover layer CPL1_2 may be connected to the 1-2th connection line CNL1_2 extending in the first direction DR1.

[0235] The 1-2nd connection line CNL1_2 may be disposed on the 1-1st connection line CNL1_1 and overlap the 1-1st connection line CNL1_1 when viewed on a plane. Therefore, the 1-2nd connection line CNL1_2 together with the 1-1st connection line CNL1_1 may constitute the first connection line CNL1 of each of the first to third pixels PXL1 to PXL3.

[0236] The first connection line CNL1 may be electrically connected to the pixel circuit layer PCL of each of the first to third pixels PXL1 to PXL3 through the contact hole CH.

[0237] The second cover layer CPL2 may be disposed on the second electrode REL2. The second cover layer CPL2 may be connected to the 2-2 th connection line CNL2_2 extending in the first direction DR1.

[0238] The 2-2nd connection line CNL2_2 may be disposed on the 2-1st connection line CNL2_1 and overlap the 2-1st connection line CNL2_1 when viewed on a plane. Therefore, the 2-2nd connection line CNL2_2 together with the 2-1st connection line CNL2_1 may constitute the second connection line CNL2.

[0239] The conductive pattern CP may be provided in a shape surrounding the first electrode REL1 and the second electrode REL2 in a unit light emitting region of each of the first to third pixels PXL1 to PXL3 .

[0240] The conductive pattern CP of each of the first to third pixels PXL1 to PXL3 is used to allow the light emitting element LD to be aligned in the unit light emitting area of ​​the corresponding pixel PXL. That is, the conductive pattern CP of each of the first to third pixels PXL1 to PXL3 can allow the light emitting element LD to be misaligned outside the unit light emitting area of ​​the corresponding pixel PXL.

[0241] For example, the conductive pattern CP of the second pixel PXL2 may eliminate an electric field generated between the 1-1 electrode REL1_1 of the second pixel PXL2 and the 1-2 electrode REL1_2 of the first pixel PXL1 adjacent to the second pixel PXL2. Therefore, the light emitting element LD may be misaligned between the first pixel PXL1 and the second pixel PXL2.

[0242] Furthermore, the conductive pattern CP of the second pixel PXL2 can eliminate an electric field generated between the 1-2 electrode REL1_2 of the second pixel PXL2 and the 1-1 electrode REL1_1 of the third pixel PXL3 adjacent to the second pixel PXL2. Therefore, the light emitting element LD can be misaligned between the second pixel PXL2 and the third pixel PXL3.

[0243] The conductive pattern CP of each of the first to third pixels PXL1 to PXL3 may be in a floating state in which it is electrically isolated, but the present invention is not limited thereto.

[0244] Here, we will refer to Figure 7 and Figure 8 The structure of the light emitting device according to the embodiment of the present invention is described along a stacking order.

[0245] A buffer layer BFL may be disposed on the substrate 101 .

[0246] The semiconductor layer SCL of each of the first transistor T1 and the second transistor T2 may be disposed on the buffer layer BFL.

[0247] The gate insulating layer GI may be disposed on the substrate SUB on which the semiconductor layer SCL is disposed.

[0248] A gate electrode GE of each of the first transistor T1 and the second transistor T2 and the driving voltage line DVL may be disposed on the gate insulating layer GI. A second driving voltage VSS may be applied to the driving voltage line DVL.

[0249] The interlayer insulating layer ILD may be disposed on the substrate SUB on which the gate electrode GE and the like are disposed.

[0250] The first and second terminals EL1 and EL2 of each of the first and second transistors T1 and T2 and the bridge pattern BRP may be disposed on the interlayer insulating layer ILD.

[0251] The first terminal EL1 and the second terminal EL2 are different electrodes. For example, when the first terminal EL1 is a drain electrode, the second terminal EL2 may be a source electrode.

[0252] The bridge pattern BRP may be electrically connected to the driving voltage line DVL through a contact hole penetrating the interlayer insulating layer ILD.

[0253] The protection layer PSV may be disposed on the substrate SUB on which the bridge pattern BRP, etc. are disposed. The protection layer PSV may include a contact hole exposing the first terminal EL1 of the first transistor T1 and a contact hole exposing the bridge pattern BRP.

[0254] The first dam PW1 and the second dam PW2 may be disposed on the protection layer PSV. The first dam PW1 and the second dam PW2 may be spaced a distance apart from each other on the protection layer PSV.

[0255] The 1-1st electrode REL1_1, the 1-2nd electrode REL1_2, the second electrode REL2, the 1-1st connection line CNL1_1, and the 2-1st connection line CNL2_1 may be disposed on the substrate SUB on which the first dam PW1 and the second dam PW2 are disposed.

[0256] The 1-1 electrode REL1_1 , the 1-2 electrode REL1_2 , and the second electrode REL2 may be spaced apart from each other by a certain distance on the substrate SUB.

[0257] The 1-1th electrode REL1_1 may be connected to the first terminal EL1 of the first transistor T1 through a contact hole of the protection layer PSV exposing the first terminal EL1 of the first transistor T1. Therefore, a voltage applied to the first terminal EL1 of the first transistor T1 may be applied to the 1-1th electrode REL1_1.

[0258] The second electrode REL2 may be connected to the bridge pattern BRP through a contact hole of the protection layer PSV exposing the bridge pattern BRP. Therefore, the second driving voltage VSS of the driving voltage line DVL may be applied to the second electrode REL2 through the bridge pattern BRP.

[0259] The 1-1st cover layer CPL1_1, the 1-2nd cover layer CPL1_2, the second cover layer CPL2, the 1-2nd connection line CNL1_2, and the 2-2nd connection line CNL2_2 may be disposed on the substrate SUB on which the 1-1st electrode REL1_1 and the like are disposed.

[0260] The first insulating layer INS1 may be disposed on the substrate SUB on which the 1-1st cover layer CPL1_1 and the like are disposed. The first insulating layer INS1 may overlap a portion of the first cover layer CPL1 of each of the first to third pixels PXL1 to PXL3 to cover the portion of the first cover layer CPL1. In addition, the first insulating layer INS1 may be disposed between the substrate SUB and one light emitting element LD in each of the first to third pixels PXL1 to PXL3.

[0261] The insulating pattern INS1 disposed between the substrate SUB and the one light emitting element LD may stably support the one light emitting element LD and prevent separation of the one light emitting element LD.

[0262] The conductive pattern CP may be disposed on the substrate SUB on which the first insulating layer INS1 is disposed. The conductive pattern CP may partially overlap the first electrode REL1 of each of the first to third pixels PXL1 to PXL3.

[0263] The light emitting element LD may be aligned on the substrate SUB on which the conductive pattern CP is disposed. The light emitting element LD may be self-aligned by an electric field formed between the first electrode REL1 and the second electrode REL2 of each of the first to third pixels PXL1 to PXL3 to be disposed between the first electrode REL1 and the second electrode REL2 of the corresponding pixel PXL.

[0264] A second insulating layer INS2 covering a portion of an upper surface of each light emitting element LD may be disposed on the substrate SUB on which the light emitting element LD is disposed.

[0265] The 1-1 th contact electrode CNE1_1 and the 1-2 th contact electrode CNE1_2 may be disposed on the substrate SUB having the second insulating layer INS2 disposed thereon.

[0266] The 1-1st contact electrode CNE1_1 may be disposed on the 1-1st electrode REL1_1 and the first end portion EP1 of the first light emitting element LD1 to be electrically connected to each of the 1-1st electrode REL1_1 and the first end portion EP1 of the first light emitting element LD1.

[0267] Therefore, the first end EP1 of the first light emitting element LD1 may be connected to the 1-1th electrode REL1_1. The 1-1th electrode REL1_1 is connected to the first transistor T1 of each of the first to third pixels PXL1 to PXL3, so the voltage applied to the first transistor T1 may be finally applied to the first end EP1 of the first light emitting element LD1.

[0268] The 1-2 th contact electrode CNE1_2 may be disposed on the 1-2 th electrode REL1_2 and the second end portion EP2 of the second light emitting element LD2 to be electrically connected to each of the 1-2 th electrode REL1_2 and the second end portion EP2 of the second light emitting element LD2.

[0269] Therefore, the second end EP2 of the second light emitting element LD2 can be connected to the 1-2 electrode REL1_2. The 1-2 electrode REL1_2 can be electrically connected to a signal line (not shown) provided in the pixel circuit layer PCL of the corresponding pixel PXL. Therefore, the voltage applied to the signal line can be applied to the second end EP2 of the second light emitting element LD2 through the 1-2 electrode REL1_2.

[0270] The third insulating layer INS3 may be disposed on the substrate SUB on which the 1-1 th contact electrode CNE1_1 and the 1-2 th contact electrode CNE1_2 are disposed.

[0271] The second contact electrode CNE2 may be disposed on the substrate SUB on which the third insulating layer INS3 is disposed.

[0272] The second contact electrode CNE2 may be disposed on the second electrode REL2 , the second end portion EP2 of the first light emitting element LD1 , and the first end portion EP1 of the second light emitting element LD2 .

[0273] One side of the second contact electrode CNE2 may be electrically connected to one side of the second electrode REL2 and each of the second end portion EP2 of the first light emitting element LD1 .

[0274] Therefore, the second end EP2 of the first light emitting element LD1 may be electrically connected to one side of the second electrode REL2. The second electrode REL2 is connected to the driving voltage line DVL, so the second driving voltage VSS applied to the driving voltage line DVL may be finally applied to the second end EP2 of the first light emitting element LD1.

[0275] Therefore, an electric field having a predetermined voltage or more is applied to each of the first end portion EP1 and the second end portion EP2 of the first light emitting element LD1 , so that the first light emitting element LD1 emits light.

[0276] In addition, the other side of the second contact electrode CNE2 may be electrically connected to each of the other side of the second electrode REL2 and the first end portion EP1 of the second light emitting element LD2 .

[0277] Therefore, the first end EP1 of the second light emitting element LD2 may be electrically connected to the other side of the second electrode REL2. The second electrode REL2 is connected to the driving voltage line DVL, so the second driving voltage VSS applied to the driving voltage line DVL may be finally applied to the first end EP1 of the second light emitting element LD2.

[0278] Therefore, an electric field having a predetermined voltage or more is applied to each of the first end portion EP1 and the second end portion EP2 of the second light emitting element LD2, so that the second light emitting element LD2 emits light.

[0279] A fourth insulating layer INS4 and an overcoat layer OC may be disposed on the substrate SUB on which the second contact electrode CNE2 is disposed.

[0280] As described above, in the display device according to the embodiment of the present invention, the light emitting element LD is aligned only in the unit light emitting region of the corresponding pixel PXL using the conductive pattern CP. Therefore, the light emitting element LD can be prevented from being aligned in an unnecessary region.

[0281] In addition, in the display device according to the embodiment of the present invention, the first insulating layer INS1 is disposed between the substrate SUB and one light emitting element LD in the unit light emitting region of the corresponding pixel PXL to stably support one light emitting element LD. Therefore, separation of one light emitting element LD can be prevented.

[0282] In addition, in the display device according to the embodiment of the present invention, the first cover layer CPL1 and the second cover layer CPL2 are respectively disposed on the first electrode REL1 and the second electrode REL2 in the unit light emitting area of ​​the corresponding pixel PXL to protect the first electrode REL1 and the second electrode REL2. Therefore, the adhesion between the first electrode REL1 and the second electrode REL2 and the substrate SUB can be further improved.

[0283] In the display device according to the embodiment of the present invention, the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed in different layers in the unit light emitting region of the corresponding pixel PXL.

[0284] Therefore, a process of connecting one of the two ends EP1 and EP2 of each light emitting element LD to the first electrode REL1 may be performed first, and then a process of connecting the other of the two ends EP1 and EP2 of each light emitting element LD to the second electrode REL2 may be performed. That is, the processes of electrically connecting the electrodes respectively corresponding to the two ends EP1 and EP2 of each light emitting element LD may be separated.

[0285] Therefore, in the display device according to the embodiment of the present invention, both end portions EP1 and EP2 of each light emitting element LD and the electrodes corresponding thereto are stably in contact with each other, so that contact defects of the light emitting element LD can be minimized.

[0286] Figure 9a to Figure 9h 1 is a schematic plan view sequentially illustrating a method of manufacturing a display device including a plurality of unit light emitting regions.

[0287] exist Figure 9a to Figure 9h In the figure, for the convenience of description, the illustration of the pixel circuit layer and the signal lines connected to the pixel circuit layer will be omitted. Figure 9a to Figure 9h In the drawings, for convenience of description, a case in which a plurality of light emitting elements are arranged in a horizontal direction is shown, but the arrangement of the light emitting elements is not limited thereto.

[0288] In addition, Figure 9a to Figure 9h In the figure, for convenience of description, a case is shown in which three pixels are provided in the display area of ​​the substrate, but actually three or more pixels are provided in the display area of ​​the substrate.

[0289] Reference Figures 1 to 9a , a first dam portion PW1 and a second dam portion PW2 extending along the second direction DR2 are formed on the substrate SUB.

[0290] The substrate SUB may include a display area DA and a non-display area NDA. A first dam PW1 and a second dam PW2 may be provided in the display area DA of the substrate SUB.

[0291] The first dam portion PW1 may include a 1-1 th dam portion PW1_1 and a 1-2 th dam portion PW1_2 which are spaced a certain distance apart from each other on the substrate SUB with the second dam portion PW2 interposed therebetween.

[0292] The pixel circuit layer PCL may be disposed on the bottom of the substrate SUB. A contact hole CH for electrically connecting the substrate SUB to the pixel circuit layer PCL may be disposed in the display area DA of the substrate SUB.

[0293] Then, refer to Figures 1 to 9b , first and second electrodes REL1 and REL2, a 1-1 metal layer MTL1_1, a 2-1 metal layer MTL2_1, a first alignment line ARL1, and a second alignment line ARL2 are formed on a substrate SUB on which the first and second dams PW1 and PW2 are disposed.

[0294] First and second electrodes REL1 and REL2, 1-1th metal layer MTL1_1, and 2-1th metal layer MTL2_1 may be disposed in the display area DA of the substrate SUB. First and second alignment lines ARL1 and ARL2 may be disposed in the non-display area NDA of the substrate SUB.

[0295] In an embodiment of the present invention, the first electrode REL1 and the second electrode REL2, the 1-1 metal layer MTL1_1 and the 2-1 metal layer MTL2_1, and the first alignment line ARL1 and the second alignment line ARL2 may be disposed on the same plane. That is, the first electrode REL1 and the second electrode REL2, the 1-1 metal layer MTL1_1 and the 2-1 metal layer MTL2_1, and the first alignment line ARL1 and the second alignment line ARL2 may be disposed in the same layer.

[0296] The first and second electrodes REL1 and REL2, the 1-1 and 2-1 metal layers MTL1_1 and MTL2_1, and the first and second alignment lines ARL1 and ARL2 may include the same material. For example, the first and second electrodes REL1 and REL2, the 1-1 and 2-1 metal layers MTL1_1 and MTL2_1, and the first and second alignment lines ARL1 and ARL2 may include a conductive material having a constant reflectivity.

[0297] The first electrode REL1, the 1-1 metal layer MTL1_1, and the first alignment line ARL1 may be integrally provided to be electrically and physically connected to each other. In addition, the second electrode REL2, the 2-1 metal layer MTL2_1, and the second alignment line ARL2 may be integrally provided to be electrically and physically connected to each other.

[0298] When viewed on a plane, the 1-1 metal layer MTL1_1 and the 2-1 metal layer MTL2_1 may extend along the first direction DR1 crossing the second direction DR2. The first alignment line ARL1 and the second alignment line ARL2 may extend along the second direction DR2.

[0299] The first electrode REL1 connected to the 1-1th metal layer MTL1_1 may include a 1-1th electrode REL1_1 and a 1-2th electrode REL1_2 branched to one side and the other side of the second electrode REL2, respectively.

[0300] Therefore, the 1-1 electrode REL1_1 and the 1-2 electrode REL1_2 and the second electrode REL2 may be alternately disposed on the substrate SUB. Specifically, when viewed on a plane, the second electrode REL2 may be disposed between the 1-1 electrode REL1_1 and the 1-2 electrode REL1_2.

[0301] The 1-1st electrode REL1_1 may overlap the 1-1st dam PW1_1, the 1-2nd electrode REL1_2 may overlap the 1-2nd dam PW1_2, and the second electrode REL2 may overlap the second dam PW2.

[0302] In an embodiment of the present invention, one 1-1 electrode REL1_1, one 1-2 electrode REL1_2, and one second electrode REL2 disposed between the 1-1 electrode REL1_1 and the 1-2 electrode REL1_2 may implement a unit light emitting region of each of the first to third pixels PXL1 to PXL3 on the substrate SUB. That is, each of the first to third pixels PXL1 to PXL3 may include a unit light emitting region.

[0303] In an embodiment of the present invention, the first electrode REL1 may be an anode electrode, and the second electrode REL2 may be a cathode electrode. The first electrode REL1 as an anode electrode may be electrically and physically connected to the first alignment line ARL1, and the second electrode REL2 as a cathode electrode may be electrically and physically connected to the second alignment line ARL2.

[0304] The 1-1th metal layer MTL1_1 and the 2-1th metal layer MTL2_1 may be commonly provided for the first to third pixels PXL1 to PXL3 .

[0305] Therefore, the first electrode REL1 disposed in the unit light emitting region of each of the first to third pixels PXL1 to PXL3 may be connected to the first electrode REL1 disposed in the unit light emitting region of an adjacent pixel through the 1-1 metal layer MTL1_1. In addition, the second electrode REL2 disposed in the unit light emitting region of each of the first to third pixels PXL1 to PXL3 may be connected to the second electrode REL2 disposed in the unit light emitting region of an adjacent pixel through the 2-1 metal layer MTL2_1.

[0306] Then, refer to Figures 1 to 9c , a first cover layer CPL1, a second cover layer CPL2, a 1-2 metal layer MTL1_2, and a 2-2 metal layer MTL2_2 are formed in the display area DA of the substrate SUB on which the first electrode REL1 and the like are disposed.

[0307] In an embodiment of the present invention, the first and second cover layers CPL1 and CPL2 and the 1-2 and 2-2 metal layers MTL1_2 and MTL2_2 may be disposed in the same layer.

[0308] The first and second cover layers CPL1 and CPL2 and the 1-2 and 2-2 metal layers MTL1_2 and MTL2_2 may include the same material. For example, the first and second cover layers CPL1 and CPL2 and the 1-2 and 2-2 metal layers MTL1_2 and MTL2_2 may include a transparent conductive material.

[0309] In an embodiment of the present invention, the first cover layer CPL1 and the 1-2 metal layer MTL1_2 may be integrally provided to be electrically and physically connected to each other. In addition, the second cover layer CPL2 and the 2-2 metal layer MTL2_2 may be integrally provided to be electrically and physically connected to each other.

[0310] The first cover layer CPL1 connected to the 1-2 metal layer MTL1_2 may include a 1-1 cover layer CPL1_1 and a 1-2 cover layer CPL1_2 branched to one side and the other side of the second cover layer CPL2. The second cover layer CPL2 may be disposed between the 1-1 cover layer CPL1_1 and the 1-2 cover layer CPL1_2.

[0311] When viewed on a plane, the 1-1st cover layer CPL1_1 may overlap the 1-1st electrode REL1_1, the 1-2nd cover layer CPL1_2 may overlap the 1-2nd electrode REL1_2, and the second cover layer CPL2 may overlap the second electrode REL2.

[0312] The 1-2 metal layer MTL1_2 may extend in the first direction DR1 and overlap the 1-1 metal layer MTL1_1. The 2-2 metal layer MTL2_2 may extend in the first direction DR1 and overlap the 2-1 metal layer MTL2_1.

[0313] A first insulating material layer (not shown) may be formed on the substrate SUB on which the first cover layer CPL1 and the like are disposed.

[0314] Reference Figures 1 to 9d , a conductive pattern CP is formed on the substrate SUB on which the first insulating material layer is disposed.

[0315] When viewed on a plane, the conductive pattern CP may be provided in a shape surrounding edges of the first electrode REL1 and the second electrode REL2 in a unit light emitting region of a corresponding pixel.

[0316] The conductive pattern CP may partially overlap the first electrode REL1 in the unit light emitting region of the corresponding pixel. Specifically, the conductive pattern CP partially overlaps the 1-1th electrode REL1_1 and may partially overlap the 1-2th electrode REL1_2 in the unit light emitting region of the corresponding pixel.

[0317] In an embodiment of the present invention, the conductive pattern CP may define an alignment region of the light emitting element LD to be described later in the unit light emitting region of each of the first pixel PXL1 to the third pixel PXL3. Specifically, the conductive pattern CP may play a role in allowing the light emitting element LD to be aligned only in a desired region of the light emitting element LD (e.g., the unit light emitting region of the corresponding pixel) in the process of aligning the light emitting element LD.

[0318] The conductive pattern CP may be made of a conductive material such as molybdenum Mo, and be in a floating state in which it is electrically isolated.

[0319] Reference Figures 1 to 9e , a voltage is applied to the first alignment line ARL1 and the second alignment line ARL2 so that an electric field is formed between the first electrode REL1 and the second electrode REL2.

[0320] In an embodiment of the present invention, predetermined voltages having different levels may be applied to the first alignment line ARL1 and the second alignment line ARL2, respectively. For example, a ground voltage may be applied to the first alignment line ARL1, and an AC voltage may be applied to the second alignment line ARL2.

[0321] When predetermined voltages having different levels may be applied to the first and second alignment lines ARL1 and ARL2 , respectively, an electric field may be formed between the first and second electrodes REL1 and REL2 .

[0322] A ground voltage is applied to the first electrode REL1 to switch on the transistor (see FIG. 1 ) included in the pixel circuit layer PCL connected to the first electrode REL1. Figure 6 The electrical characteristics of T1 to T7) are not affected.

[0323] Specifically, the first electrode REL1 is an anode electrode electrically connected to the pixel circuit layer PCL. Therefore, when an AC or DC voltage having a predetermined voltage level is applied to the first electrode REL1 instead of a ground voltage, since the transistors T1 to T7 are affected by the voltage applied to the first electrode REL1, the threshold voltages of the transistors T1 to T7 may change. Therefore, since the electrical characteristics of the transistors T1 to T7 are changed, the pixel circuit layer PCL may malfunction.

[0324] In an embodiment of the present invention, in order to prevent malfunction of the pixel circuit layer PCL, a ground voltage may be applied to the first electrode REL1 , and a voltage having a predetermined voltage level may be applied to the second electrode REL2 .

[0325] As described above, the light emitting elements LD may be dispersed on the substrate SUB in a state where an electric field is applied between the first electrode REL1 and the second electrode REL2 .

[0326] Inkjet printing technology can be used as a non-limiting example of a technology for dispersing the light emitting element LD. In the example, the light emitting element LD can be dispersed in the display area DA by providing a nozzle on the corresponding substrate SUB and dropping a solution including the light emitting element LD. However, the technology for dispersing the light emitting element LD on the substrate SUB is not limited thereto.

[0327] When the light emitting element LD is dropped, the light emitting element LD can be self-aligned due to the electric field formed between the first electrode REL1 and the second electrode REL2. When a voltage is applied to each of the first electrode REL1 and the second electrode REL2, the light emitting element LD can be self-aligned between the first electrode REL1 and the second electrode REL2 by the electric field formed between the first electrode REL1 and the second electrode REL2.

[0328] The light emitting element LD may be aligned in the unit light emitting region of the corresponding pixel by the conductive pattern CP. Specifically, the light emitting element LD may be aligned between the first electrode REL1 and the second electrode REL2 in the unit light emitting region of each of the first to third pixels PXL1 to PXL3.

[0329] The light emitting element LD may include a first light emitting element LD1 aligned between the 1-1 electrode REL1_1 and the second electrode REL2 in the unit light emitting area of ​​the corresponding pixel and a second light emitting element LD2 aligned between the second electrode REL2 and the 1-2 electrode REL1_2 in the unit light emitting area of ​​the corresponding pixel.

[0330] As described above, voltages having different levels are respectively applied to the first alignment line ARL1 and the second alignment line ARL2 , so that the light emitting element LD can be easily aligned on the substrate SUB.

[0331] After aligning the light emitting element LD, a first insulating pattern (not shown) exposing a portion of the first cover layer CPL1 to the outside may be formed by patterning the first insulating material layer.

[0332] Reference Figures 1 to 9f , the first alignment line ARL1 and the second alignment line ARL2 are removed on the substrate SUB on which the light emitting element LD is aligned.

[0333] Meanwhile, a 1-1 th connection line CNL1_1 is formed by removing a portion of the 1-1 th metal layer MTL1_1 electrically connected to the first alignment line ARL1 in the display area DA of the substrate SUB.

[0334] The 1-2 connection line CNL1_2 may also be formed by removing a portion of the 1-2 metal layer MTL1_2 together with the portion of the 1-1 metal layer MTL1_1. The 1-1 connection line CNL1_1 together with the 1-2 connection line CNL1_2 may constitute a first connection line CNL1.

[0335] When the second alignment line ARL2 is removed, the 2-1 metal layer MTL2_1 electrically and physically connected to the second alignment line AR2 may become a 2-1 connection line CNL2_1.

[0336] The 2-2nd metal layer MTL2_2 may become the 2-2nd connection line CNL2_2. The 2-1st connection line CNL2_1 and the 2-2nd connection line CNL2_2 together may constitute the second connection line CNL2.

[0337] A second insulating pattern (not shown) exposing a portion of the first cover layer CPL1 and one end of the light emitting element LD may be formed by forming a second insulating material layer (not shown) on the substrate SUB having the first and second connection lines CNL1 and CNL2 disposed thereon and patterning the second insulating material layer.

[0338] Reference Figures 1 to 9g, a first contact electrode CNE1 is formed on a substrate SUB on which a second insulating pattern and the like are disposed.

[0339] The first contact electrode CNE1 may overlap the first electrode REL1 when viewed on a plane. The first contact electrode CNE1 may include a 1-1st contact electrode CNE1_1 formed on the 1-1st electrode REL1_1 and a 1-2nd contact electrode CNE1_2 formed on the 1-2nd electrode REL1_2.

[0340] The 1-1st contact electrode CNE1_1 may electrically and / or physically connect one end EP1 of the first light emitting element LD1 and the 1-1st electrode REL1_1. In addition, the 1-2nd contact electrode CNE1_2 may electrically and / or physically connect the other end EP2 of the second light emitting element LD2 and the 1-2nd electrode REL1_2.

[0341] Subsequently, a third insulating layer INS3 covering the first contact electrode CNE1 is formed by forming a third insulating material layer (not shown) on the substrate SUB having the first contact electrode CNE1 formed thereon and patterning the third insulating material layer.

[0342] Meanwhile, the first and second insulating layers INS1 and INS2 exposing the other end portion of each of the light emitting elements LD and the second cover layer CPL2 to the outside are formed by patterning the first and second insulating patterns.

[0343] Reference Figure 1 to Figure 9h , the second contact electrode CNE2 is formed on the substrate SUB on which the first contact electrode CNE1 and the like are provided.

[0344] The second contact electrode CNE2 may overlap the second electrode REL2 when viewed on a plane. In addition, the second contact electrode CNE2 may overlap the other end EP2 of the first light emitting element LD1 and one end EP1 of the second light emitting element LD2 when viewed on a plane.

[0345] The second contact electrode CNE2 may electrically and / or physically connect one side of the second electrode REL2 and the other end EP2 of the first light emitting element LD1. In addition, the second contact electrode CNE2 may electrically and / or physically connect the other side of the second electrode REL2 and one end EP1 of the second light emitting element LD2.

[0346] Figure 10a to Figure 10m is shown sequentially Figure 8 A cross-sectional view of a method for manufacturing a display device shown in FIG.

[0347] Reference Figures 1 to 10a, a pixel circuit layer PCL is formed on the substrate SUB. The pixel circuit layer PCL may include first and second transistors T1 and T2, a driving voltage line DVL, a bridge pattern BRP connected to the driving voltage line DVL, and a protection layer PSV.

[0348] The protection layer PSV may include a contact hole (herein, referred to as a 'first contact hole') exposing the first terminal EL1 of the first transistor T1 and a contact hole (herein, referred to as a 'second contact hole') exposing the bridge pattern BRP.

[0349] Reference Figures 1 to 10b , a first dam portion PW1 and a second dam portion PW2 are formed on the pixel circuit layer PCL.

[0350] The first dam PW1 and the second dam PW2 may be spaced apart from each other by a certain distance on the protection layer PSV. In an embodiment of the present invention, the first dam PW1 and the second dam PW2 may include an organic insulating layer.

[0351] The first dam portion PW1 may include a 1-1 th dam portion PW1_1 and a 1-2 th dam portion PW1_2 which are spaced apart from each other by a certain distance and the second dam portion PW2 is interposed therebetween.

[0352] Reference Figures 1 to 10c , a first electrode REL1 and a second electrode REL2 including a conductive material having a high reflectivity are formed on the protective layer PSV on which the first dam portion PW1 and the second dam portion PW2 are provided.

[0353] The first electrode REL1 may be formed on the first dam PW1, and the second electrode REL2 may be formed on the second dam PW2. The first electrode REL1 may include a 1-1 electrode REL1_1 formed on the 1-1 dam PW1_1 and a 1-2 electrode REL1_2 formed on the 1-2 dam PW1_2.

[0354] The 1-1th electrode REL1_1 may be connected to the first terminal EL1 of the first transistor T1 through a first contact hole penetrating the protective layer PSV. The second electrode REL2 may be connected to the bridge pattern BRP through a second contact hole penetrating the protective layer PSV.

[0355] Each of the first electrode REL1 and the second electrode REL2 may have a shape corresponding to that of the corresponding dam. That is, the first electrode REL1 may have a shape corresponding to that of the first dam PW1, and the second electrode REL2 may have a shape corresponding to that of the second dam PW2.

[0356] Reference Figures 1 to 10dA first cover layer CPL1 and a second cover layer CPL2 including a transparent conductive material are formed on the protection layer PSV on which the first electrode REL1 and the second electrode REL2 are formed.

[0357] Reference Figures 1 to 10e A first insulating material layer INS1 ′ is deposited on the entire protection layer PSV on which the first cover layer CPL1 and the second cover layer CPL2 are disposed.

[0358] The first insulating material layer INS1 ′ may be an inorganic insulating layer including an inorganic material. The first insulating material layer INS1 ′ together with the first and second cover layers CPL1 and CPL2 may cover the first and second electrodes REL1 and REL2 and protect the first and second electrodes REL1 and REL2.

[0359] Reference Figures 1 to 10f , a conductive pattern CP made of a conductive material is formed on the first insulating material layer INS1 ′.

[0360] The conductive pattern CP may partially overlap the first cover layer CPL1 and the first electrode REL1 disposed on the bottom thereof. The conductive pattern CP serves to allow a light emitting element LD, which will be described later, to be aligned in a unit light emitting region of a corresponding pixel.

[0361] Reference Figures 1 to 10g After a predetermined voltage is applied to the first electrode REL1 and the second electrode REL2 through the first alignment line ARL1 and the second alignment line ARL2 respectively to form an electric field between the first electrode REL1 and the second electrode REL2, the light emitting element LD is dispersed on the first insulating material layer INS1'.

[0362] When the light emitting elements LD are dispersed, an electric field is formed between the 1-1 electrode REL1_1 and the second electrode REL2 and between the second electrode REL2 and the 1-2 electrode REL1_2 , and thus the light emitting elements LD can be self-aligned.

[0363] In an embodiment of the present invention, the light emitting element LD may include a first light emitting element LD1 aligned between the 1-1 electrode REL1_1 and the second electrode REL2 and a second light emitting element LD2 aligned between the second electrode REL2 and the 1-2 electrode REL1_2.

[0364] Each of the first light emitting element LD1 and the second light emitting element LD2 may include a first end portion EP1 and a second end portion EP2.

[0365] Reference Figure 1 to Figure 10h The first insulating material layer INS1' is patterned by a mask process or the like to form a first insulating pattern INS1" exposing a portion of the first cover layer CPL1.

[0366] Reference Figures 1 to 10i A second insulating material layer (not shown) is coated on the protective layer PSV on which the first insulating pattern INS1" and the like are disposed. Subsequently, a second insulating pattern INS2' exposing a portion of the first cover layer CPL1, the first end portion EP1 of the first light emitting element LD1, and the second end portion EP2 of the second light emitting element LD2 is formed by a mask process or the like.

[0367] At the same time, the first and second alignment lines ARL1 and ARL2 are removed, and the first and second connection lines CNL1 and CNL2 are formed.

[0368] Reference Figures 1 to 10j The first contact electrode CNE1 including the 1-1th contact electrode CNE1_1 and the 1-2th contact electrode CNE1_2 is formed on the protection layer PSV having the second insulating pattern INS2 ′ formed thereon.

[0369] The 1-1st contact electrode CNE1_1 may cover the 1-1st electrode REL1_1 and the first end portion EP1 of the first light emitting element LD1, and the 1-2nd contact electrode CNE1_2 may cover the 1-2nd electrode REL1_2 and the second end portion EP2 of the second light emitting element LD2.

[0370] Reference Figure 1 to Figure 10k A third insulating material layer (not shown) is coated on the protective layer PSV on which the first contact electrode CNE1 is disposed. Subsequently, a third insulating layer INS3 covering the first contact electrode CNE1 and exposing the second electrode REL2 to the outside is formed using a mask process or the like.

[0371] When the third insulating layer INS3 is provided as a multi-layer including a plurality of insulating layers, the plurality of insulating layers may be patterned simultaneously or individually through a mask process so that the second electrode REL2 is exposed to the outside.

[0372] The second insulating pattern INS2' may be patterned together with a plurality of insulating layers by a mask process to become a second insulating layer INS2 exposing the second cover layer CPL2, the second end portion EP2 of the first light emitting element LD1, and the first end portion EP1 of the second light emitting element LD2. The second insulating layer INS2 is disposed at a portion of the upper surface of each of the first light emitting element LD1 and the second light emitting element LD2 to expose both end portions EP1 and EP2 of each of the first light emitting element LD1 and the second light emitting element LD2 to the outside.

[0373] In addition, the first insulating pattern INS1 ″ may be patterned together with the plurality of insulating layers to become the first insulating layer INS1 disposed only on the bottom of each of the first and second light emitting elements LD1 and LD2 and a portion of the first cover layer CPL1 .

[0374] The first insulating layer INS1 disposed on the bottom of each of the first light emitting element LD1 and the second light emitting element LD2 may play a role of supporting the first light emitting element LD1 and the second light emitting element LD2 and preventing the first light emitting element LD1 and the second light emitting element LD2 from being separated.

[0375] Reference Figures 1 to 101 , a second contact electrode CNE2 is formed on the protection layer PSV on which the third insulating layer INS3 is formed.

[0376] The second contact electrode CNE2 may cover the second electrode REL2 , the second end portion EP2 of the first light emitting element LD1 , and the first end portion EP1 of the second light emitting element LD2 .

[0377] Reference Figure 1 to Figure 10m A fourth insulating layer INS4 is formed on the entire protection layer PSV including the second contact electrode CNE2. Subsequently, an overcoat layer OC is formed on the fourth insulating layer INS4.

[0378] Fig.11 Shows Figure 8 Another form of the first dam portion and the second dam portion shown in Figure 8 is corresponding to Figure 7 ' is a cross-sectional view of the line II-II'. In this embodiment, the parts different from the parts of the above-mentioned embodiment will be mainly described to avoid redundancy. The parts not specifically described in this embodiment can follow the parts of the above-mentioned embodiment. In addition, the same reference numerals represent the same components, and similar reference numerals represent similar components.

[0379] In addition to the first dam portion and the second dam portion having a semicircular shape, Fig.11 The display device shown in FIG. 1 may have Figure 7 and Figure 8 The display device has the same or similar construction.

[0380] Reference Figure 7 and Figure 8 , a display device according to an embodiment of the present invention may include a substrate SUB, a pixel circuit layer PCL disposed on the substrate SUB, and a display element layer DPL disposed on the pixel circuit layer PCL.

[0381] The pixel circuit layer PCL may include a buffer layer BFL disposed on the substrate SUB, first and second transistors T1 and T2 disposed on the buffer layer BFL, and a driving voltage line DVL.

[0382] The display element layer DPL may include first and second dams PW1 and PW2 , first and second electrodes REL1 and REL2 , a light emitting element LD, and first and second contact electrodes CNE1 and CNE2 disposed on the pixel circuit layer PCL.

[0383] The first and second dams PW1 and PW2 may have a shape protruding from the protection layer PSV of the pixel circuit layer PCL, and a surface of each of the first and second dams PW1 and PW2 may be provided in a semicircular shape having a predetermined curvature. However, the present invention is not limited thereto.

[0384] The first dam PW1 and the second dam PW2 may be organic insulating layers including an organic material, but the present invention is not limited thereto.

[0385] The first electrode REL1 and the second electrode REL2 may be provided to correspond to the shapes of the first dam PW1 and the second dam PW2. That is, the first electrode REL1 may have a curvature corresponding to the shape of the first dam PW1, and the second electrode REL2 may have a curvature corresponding to the shape of the second dam PW2.

[0386] In an embodiment of the present invention, the first electrode REL1 and the second electrode REL2 may be made of a conductive material having a constant reflectivity. The first electrode REL1 and the second electrode REL2 may allow light emitted from both ends EP1 and EP2 of each of the light emitting elements LD to advance in a direction (eg, a front direction) in which an image is displayed.

[0387] As described above, since the first and second electrodes REL1 and REL2 have a shape having a certain curvature, light emitted from both ends EP1 and EP2 of each of the light emitting elements LD and then reflected by the first and second electrodes REL1 and REL2 can further advance in the front direction.

[0388] The display device according to the embodiment of the present invention can be used in any of various electronic devices. For example, the display device can be applied to televisions, notebook computers, cellular phones, smart phones, smart tablets, PMPs, PDAs, navigators, various wearable devices such as smart watches, etc.

[0389] Although the present invention has been described in conjunction with certain exemplary embodiments, those skilled in the art will appreciate that various modifications and changes can be made thereto without departing from the spirit and scope of the invention as set forth in the following claims.

[0390] Thus, the scope of the invention should not be limited by the specific embodiments described herein, but should be defined by the appended claims and their equivalents.

Claims

1. A light emitting device, comprising: A substrate including a plurality of unit light emitting areas; as well as The first insulating layer to the fourth insulating layer are arranged on the substrate, Wherein, each of the plurality of unit light emitting areas comprises: At least one light-emitting element is directly located on the first insulating layer, the at least one light-emitting element comprises a first end and a second end in a length direction thereof, and the second insulating layer, the third insulating layer and the fourth insulating layer are sequentially arranged on the at least one light-emitting element; a first dam portion and a second dam portion, located on the substrate, the first dam portion and the second dam portion being spaced apart from each other; a first electrode and a second electrode, the first electrode being located on the first dam portion, and the second electrode being located on the second dam portion; a first contact electrode, located on the first electrode, the first contact electrode connecting the first electrode and the first end of the light emitting element; a second contact electrode, located on the second electrode, the second contact electrode connecting the second electrode and the second end of the light emitting element; and a conductive pattern, located between the first insulating layer and the first contact electrode, and when viewed on a plane, the conductive pattern surrounds the first electrode and the second electrode, Wherein, the first insulating layer is disposed between the conductive pattern and the first electrode.

2. The light emitting device according to claim 1, wherein: The conductive pattern is disposed in a unit light emitting region corresponding to the light emitting element.

3. The light emitting device according to claim 2, wherein: Each of the plurality of unit light emitting areas further includes: a first connection line connected to the first electrode, the first connection line extending in a first direction of the substrate; and a second connection line connected to the second electrode, the second connection line extending in the first direction, The first electrode includes a 1-1 electrode and a 1-2 electrode, the 1-1 electrode and the 1-2 electrode branch off from the first connection line to be spaced apart from each other, and the second electrode is located between the 1-1 electrode and the 1-2 electrode.

4. The light emitting device according to claim 3, wherein: When viewed on a plane, the conductive pattern partially overlaps the 1-1 electrode and the 1-2 electrode.

5. The light emitting device according to claim 3, wherein: The first insulating layer is disposed between the substrate and the light emitting element and between the conductive pattern and the first electrode.

6. The light emitting device according to claim 5, wherein: The first insulating layer disposed between the substrate and the light emitting element supports the light emitting element, and the first insulating layer disposed between the conductive pattern and the first electrode protects the first electrode.

7. The light emitting device according to claim 6, further comprising: a first covering layer, located on the first electrode to cover the first electrode; as well as The second covering layer is located on the second electrode to cover the second electrode.

8. The light emitting device according to claim 2, wherein: The second insulating layer is disposed on the light emitting element so as to expose the first end and the second end of the light emitting element. The third insulating layer is disposed on the first contact electrode to protect the first contact electrode, and The fourth insulating layer is disposed on the second contact electrode to protect the second contact electrode.

9. The light emitting device according to claim 2, wherein: The light emitting element comprises: a first semiconductor layer doped with a first conductive dopant; a second semiconductor layer doped with a second conductive dopant; and The active layer is arranged between the first semiconductor layer and the second semiconductor layer.

10. The light emitting device according to claim 9, wherein: The light emitting element includes a micrometer-sized or nanometer-sized columnar light emitting diode.

11. A display device, comprising: A substrate, including a display area and a non-display area; A pixel circuit layer, located in the display area, wherein the pixel circuit layer includes at least one transistor; as well as The display element layer includes a first insulating layer to a fourth insulating layer disposed on the pixel circuit layer and a plurality of unit light emitting regions emitting light therefrom, Wherein, each of the plurality of unit light emitting areas comprises: At least one light-emitting element is located on the first insulating layer, the at least one light-emitting element includes a first end and a second end in a length direction thereof, and the second insulating layer, the third insulating layer and the fourth insulating layer are sequentially arranged on the at least one light-emitting element; A first dam portion and a second dam portion are located on the pixel circuit layer, and the first dam portion and the second dam portion are spaced a certain distance from each other; a first electrode and a second electrode, the first electrode being located on the first dam portion, and the second electrode being located on the second dam portion; a first contact electrode, located on the first electrode, the first contact electrode connecting the first electrode and the first end of the light emitting element; a second contact electrode, located on the second electrode, the second contact electrode connecting the second electrode and the second end of the light emitting element; and The conductive pattern is located between the first insulating layer and the first contact electrode, and when viewed in a plane, the conductive pattern surrounds the first electrode and the second electrode.

12. The display device according to claim 11, wherein: The conductive pattern is disposed in a unit light emitting region corresponding to the light emitting element.

13. The display device according to claim 12, wherein: Each of the plurality of unit light emitting areas further includes: a first connection line connected to the first electrode, the first connection line extending in a first direction of the substrate; and a second connection line connected to the second electrode, the second connection line extending in the first direction, The first electrode includes a 1-1 electrode and a 1-2 electrode, the 1-1 electrode and the 1-2 electrode branch out from the first connection line to be spaced apart from each other by a certain distance, and the second electrode is located between the 1-1 electrode and the 1-2 electrode.

14. The display device according to claim 13, wherein: When viewed on a plane, the conductive pattern partially overlaps the 1-1 electrode and the 1-2 electrode.

15. The display device according to claim 13, wherein: The first insulating layer is disposed between the substrate and the light emitting element and between the conductive pattern and the first electrode.

16. The display device according to claim 15, wherein: The first insulating layer disposed between the substrate and the light emitting element supports the light emitting element, and the first insulating layer disposed between the conductive pattern and the first electrode protects the first electrode.

17. The display device according to claim 16, further comprising: a first covering layer, located on the first electrode to cover the first electrode; as well as The second covering layer is located on the second electrode to cover the second electrode.

18. The display device according to claim 12, wherein: The second insulating layer is disposed on the light emitting element so as to expose the first end and the second end of the light emitting element. The third insulating layer is disposed on the first contact electrode to protect the first contact electrode, and The fourth insulating layer is disposed on the second contact electrode to protect the second contact electrode.

19. The display device according to claim 12, wherein: The light emitting element comprises: a first semiconductor layer doped with a first conductive dopant; a second semiconductor layer doped with a second conductive dopant; and The active layer is located between the first semiconductor layer and the second semiconductor layer.

20. The display device according to claim 19, wherein: The light emitting element includes a micrometer-sized or nanometer-sized columnar light emitting diode.

21. A method for manufacturing a display device, the method comprising: providing a substrate including a plurality of unit light emitting regions; forming a first dam portion and a second dam portion spaced apart from each other by a certain distance in each of the plurality of unit light emitting regions; forming a first electrode, a second electrode spaced apart from the first electrode on the same plane, a first alignment line connected to the first electrode, and a second alignment line connected to the second electrode on the substrate on which the first dam and the second dam are formed; forming a first insulating material layer on the first electrode and the second electrode; forming a conductive pattern overlapping the first electrode on the first insulating material layer; self-aligning the plurality of light emitting elements between the first electrode and the second electrode by dropping a solution including the plurality of light emitting elements onto the first insulating material layer and applying a voltage to each of the first alignment lines and the second alignment lines; forming a first insulating material pattern exposing a portion of the first electrode by patterning the first insulating material layer; forming a second insulating material pattern exposing a first end portion of each of the plurality of light emitting elements, a portion of the first electrode, and the conductive pattern by coating a second insulating material layer on the first insulating material pattern and then patterning the second insulating material layer; removing the first alignment line and the second alignment line on the substrate; forming a first contact electrode connecting the exposed first end portion of each of the plurality of light emitting elements and the first electrode; forming a third insulating layer covering the first contact electrode on the first contact electrode, and forming a first insulating layer and a second insulating layer exposing a second end portion of each of the plurality of light emitting elements and the second electrode by patterning the first insulating material pattern and the second insulating material pattern; forming a second contact electrode connecting the exposed second end portion of each of the plurality of light emitting elements and the second electrode; as well as A fourth insulating layer covering the second contact electrode is formed on the second contact electrode.

22. The method according to claim 21, wherein: The steps of forming the first electrode and the second electrode and the first alignment line and the second alignment line include: forming a first connecting line and a second connecting line, the first connecting line is integrally arranged with the first electrode to connect the first electrode to the first alignment line, and the second connecting line is integrally arranged with the second electrode to connect the second electrode to the second alignment line.

23. The method according to claim 22, wherein: In the step of removing the first alignment line and the second alignment line, a portion of the first connection line disposed between two adjacent unit light emitting regions is removed.

24. The method according to claim 21, wherein: In the step of self-aligning the plurality of light emitting elements, a voltage applied to the first alignment line and a voltage applied to the second alignment line have different levels, and A ground voltage is applied to the first alignment line. 25 . The method according to claim 21 , further comprising forming a first covering layer on the first electrode to cover the first electrode, and simultaneously forming a second covering layer on the second electrode to cover the second electrode.

26. The method according to claim 21, wherein: The step of providing the substrate comprises: forming at least one transistor for driving the plurality of light emitting elements on a substrate; and A protection layer is formed over the transistor.

Images