Stage in emission control driver and display device including the same

Abstract

Provided is a stage in an emission control driver and a display device including the same, the stage comprising: an input unit, controlling the voltages of a first node and a second node in response to a first input signal supplied from a first input terminal and a second input signal supplied from a second input terminal; a first controller, controlling the voltages of a third node and a fourth node in response to the voltage of a third input signal supplied from a third input terminal and the voltage of the second node; a second controller, controlling the voltage of the fourth node in response to the voltage of the first node; and an output unit, supplying the voltage of a first power supply or a second power supply to an output terminal in response to the voltage of the third node or the voltage of the fourth node. The first controller comprises: a first transistor and a second transistor, connected between the first power supply and a third node; and a third transistor, connected between the first node and the third node, the third transistor being turned on in response to the voltage of the second power supply.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0068932, filed on Jun. 11, 2019, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0002] Exemplary embodiments of the invention generally relate to an emission control driver for a display device, and more particularly to an emission control driver having a stage for supplying an emission control signal to a pixel and a display device including the emission control driver. Background Art

[0003] The display device displays an image using pixels provided in a display unit. The pixels are connected to scan lines and data lines and are driven by scan signals and data signals supplied through the scan lines and data lines.

[0004] The pixel may also be connected to an emission control line, and the emission period of the pixel may be controlled by an emission control signal supplied to the emission control line. In this case, the display device may include an emission control driver for generating the emission control signal.

[0005] The emission control driver includes a stage for supplying each of the emission control signals to each of the emission control lines. The stage outputs a gate-on voltage to the emission control line connected to the corresponding pixel during the emission period of the pixel arranged in each horizontal row, and outputs an emission control signal of a gate-off voltage to the emission control line during other periods, thereby preventing the emission of the pixel.

[0006] The above information disclosed in this Background section is only for understanding the background of the inventive concept and therefore it may contain information that does not constitute the prior art. Summary of the invention

[0007] Applicants have discovered that internal voltages (eg, node voltages) in a stage of an emission control driver in a display device may be unstable at the start of driving of the display device, which may make it difficult to control the emission of pixels as desired.

[0008] An emission control driving stage constructed according to the principles of the invention and exemplary embodiments and a display device including the same can stably control the emission of pixels even in the initial stage of driving the display device.

[0009] For example, a stage in an emission control driver constructed according to an exemplary embodiment of the invention prevents electrical characteristics of transistors connected to a first node and a second node included in the stage from changing, and an emission control signal of a gate-off voltage is stably supplied to an emission control line even in an initial stage of driving a display device, so that the output quality of the emission control driver is improved, and unexpected flicker due to emission of pixels can be reduced or eliminated.

[0010] Additional features of the inventive concepts will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the inventive concepts.

[0011] According to one aspect of the invention, a stage in an emission control driver of a display device includes: an input unit, which controls the voltages of a first node and a second node in response to a first input signal supplied from a first input terminal and a second input signal supplied from a second input terminal; a first controller, which controls the voltages of a third node and a fourth node in response to the voltage of a third input signal supplied from a third input terminal and the voltage of the second node; a second controller, which controls the voltage of the fourth node in response to the voltage of the first node; and an output unit, which supplies the voltage of a first power supply or a second power supply to an output terminal in response to the voltage of the third node or the voltage of the fourth node. The first controller includes: a first transistor and a second transistor, which are connected between the first power supply and a third node; and a third transistor, which is connected between the first node and the third node, and the third transistor is turned on in response to the voltage of the second power supply.

[0012] The second transistor may have one electrode directly connected to the third node without passing through the third transistor.

[0013] The first transistor may have a gate electrode connected to the second node, and the second transistor may have a gate electrode connected to the third input terminal.

[0014] The first controller may further include a first capacitor connected between the third node and the third input terminal.

[0015] The voltage of the first power supply may be set as a gate-off voltage, and the voltage of the second power supply may be set as a gate-on voltage.

[0016] The output unit may include: a fourth transistor connected between the first power supply and the output terminal, the fourth transistor having a gate electrode connected to a fourth node; and a fifth transistor connected between the output terminal and the second power supply, the fifth transistor having a gate electrode connected to a third node.

[0017] The first input signal may be a start pulse or an output signal of a previous stage, and the second input signal and the third input signal may be a first clock signal and a second clock signal, respectively.

[0018] The first clock signal and the second clock signal may alternately have a gate-on voltage. The start pulse or the output signal of the previous stage may be supplied to overlap with at least one gate-on voltage period of the first clock signal.

[0019] The input unit may include: a sixth transistor connected between the first input terminal and the first node, the sixth transistor having a gate electrode connected to the second input terminal; a seventh transistor connected between the second node and the second input terminal, the seventh transistor having a gate electrode connected to the first node; and an eighth transistor connected between the second node and the second power supply, the eighth transistor having a gate electrode connected to the second input terminal.

[0020] The first controller may also include: a ninth transistor connected between the second node and the fifth node, the ninth transistor being turned on in response to the voltage of the second power supply; a second capacitor connected between the fifth node and the sixth node; a tenth transistor connected between the fourth node and the sixth node, the tenth transistor having a gate electrode connected to the third input terminal; and an eleventh transistor connected between the sixth node and the third input terminal, the eleventh transistor having a gate electrode connected to the fifth node.

[0021] The second controller may include: a twelfth transistor connected between the first power supply and the fourth node, the twelfth transistor having a gate electrode connected to the first node or the third node; and a third capacitor connected between the first power supply and the fourth node.

[0022] According to another aspect of the invention, a display device includes: a plurality of pixels connected to a plurality of scan lines, a plurality of data lines, and a plurality of emission control lines; a scan driver for supplying scan signals to the plurality of scan lines; a data driver for supplying data signals to the plurality of data lines; and an emission control driver having a plurality of stages for supplying emission control signals to the plurality of emission control lines. Each of the plurality of stages includes: an input unit for controlling the voltages of a first node and a second node in response to a first input signal supplied from a first input terminal and a second input signal supplied from a second input terminal; a first controller for controlling the voltages of a third node and a fourth node in response to the voltage of a third input signal supplied from a third input terminal and the voltage of the second node, and including a first transistor and a second transistor connected between a first power supply and a third node and a third transistor connected between the first node and the third node, the third transistor being turned on in response to the voltage of the second power supply; a second controller for controlling the voltage of a fourth node in response to the voltage of the first node; and an output unit for supplying the voltage of the first power supply or the voltage of the second power supply to the output terminal in response to the voltage of the third node or the voltage of the fourth node.

[0023] The second transistor may have one electrode directly connected to the third node without passing through the third transistor.

[0024] The first transistor may have a gate electrode connected to the second node, and the second transistor may have a gate electrode connected to the third input terminal.

[0025] The first controller may further include a first capacitor connected between the third input terminal and the third node.

[0026] The voltage of the first power source may be set as a gate-off voltage, and the voltage of the second power source may be set as a gate-on voltage.

[0027] The output unit may include: a fourth transistor connected between the first power supply and the output terminal, the fourth transistor having a gate electrode connected to a fourth node; and a fifth transistor connected between the output terminal and the second power supply, the fifth transistor having a gate electrode connected to a third node.

[0028] The plurality of stages may include a first stage receiving a start pulse through a first input terminal and other stages receiving an output signal of a previous stage through the first input terminal.

[0029] The plurality of stages may include odd-numbered stages receiving the first clock signal through the second input terminal and the second clock signal through the third input terminal, and even-numbered stages receiving the second clock signal through the second input terminal and the first clock signal through the third input terminal.

[0030] The first clock signal and the second clock signal may alternately have a gate-on voltage.

[0031] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings illustrate exemplary embodiments of the invention and together with the description serve to explain the inventive concept. The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification.

[0033] Figure 1 is a block diagram of an exemplary embodiment of a display device constructed according to the principles of the invention.

[0034] Figure 2A and Figure 2B yes Figure 1 A circuit diagram of a representative pixel of a display device.

[0035] Figure 3is a block diagram of an exemplary embodiment of an emission control driver constructed according to the principles of the invention.

[0036] Figure 4 is Figure 3 A circuit diagram of a first exemplary embodiment of two stages is shown in FIG.

[0037] Figure 5 It is shown in Figure 4 An exemplary timing diagram of an example of a driving method of the stage is shown in FIG.

[0038] Figure 6 It is shown in Figure 4 A block diagram of the refresh path of the first stage is shown in FIG.

[0039] Figure 7 is Figure 3 A circuit diagram of a second exemplary embodiment of two stages is shown in FIG.

[0040] Figure 8 is Figure 3 2 is a circuit diagram of a third exemplary embodiment of two stages shown in FIG. DETAILED DESCRIPTION

[0041] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of various exemplary embodiments or implementations of the invention. "Embodiment" and "implementation" as used herein are interchangeable words as non-limiting examples of devices or methods that adopt one or more inventive concepts disclosed herein. However, it is obvious that various exemplary embodiments can be implemented without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in the form of block diagrams to avoid making various exemplary embodiments unnecessarily obscure. In addition, although various exemplary embodiments may be different, they do not have to be exclusive. For example, without departing from the inventive concept, the specific shape, construction and characteristics of the exemplary embodiment can be used or implemented in another exemplary embodiment.

[0042] Unless otherwise specified, the illustrated exemplary embodiments will be understood as providing exemplary features of the details of variations of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of the various embodiments may be further combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0043] The use of cross hatching and / or shading in the drawings is generally provided to make the boundaries between adjacent elements clear. Thus, unless otherwise specified, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for the specific material, material properties, size, ratio, commonality between the illustrated elements and / or any other characteristics, attributes, properties, etc. of the element. In addition, in the drawings, the size and relative size of the elements may be exaggerated for clarity and / or descriptive purposes. When the exemplary embodiments may be implemented differently, a specific process sequence may be performed in a different order than described. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the order described. In addition, the same reference numerals represent the same elements.

[0044] When an element or layer is referred to as being "on" another element or layer, "connected to" or "bonded to" another element or layer, the element or layer may be directly on, directly connected to or directly bonded to the other element or layer, or there may be an intermediate element or layer. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly bonded to" another element or layer, there is no intermediate element or layer. For this reason, the term "connection" may refer to a physical connection, an electrical connection and / or a fluid connection with or without an intermediate element. In addition, the D1 axis, the D2 axis and the D3 axis are not limited to three axes such as the x-axis, the y-axis and the z-axis of a rectangular coordinate system, but may be interpreted in a broader sense. For example, the D1 axis, the D2 axis and the D3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0045] Although the terms "first", "second", etc. can be used to describe various types of elements here, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the disclosed teachings, the first element discussed below can be named as the second element.

[0046] For descriptive purposes, spatially relative terms such as "under," "below," "below," "down," "above," "up," "above," "higher," "side" (e.g., as in "sidewall"), etc., may be used herein and thereby describe the relationship of one element to another element as shown in the accompanying drawings. Spatially relative terms are intended to include different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is flipped, an element described as "under" or "beneath" other elements or features will subsequently be oriented to be "above" the other elements or features. Thus, the exemplary term "under" can include both above and below orientations. In addition, the device can be oriented otherwise (e.g., rotated 90 degrees or at other orientations), and as such, the spatially relative descriptors used herein are interpreted accordingly.

[0047] The terms used here are for the purpose of describing specific embodiments, and are not intended to be limiting. Unless the context clearly indicates otherwise, as used herein, the singular forms "one (kind / person)" and "said / the" are also intended to include plural forms. In addition, when the terms "comprise", "include" and variations thereof are used in this specification, it is indicated that there are stated features, integers, steps, operations, elements, components and / or their groups, but it is not excluded that there are or add one or more other features, integers, steps, operations, elements, components and / or their groups. It is also noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms and not as degree terms, and are thus used to explain the inherent deviations of measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0048] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this disclosure is a part. Terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0049] Figure 1 is a block diagram of an exemplary embodiment of a display device constructed according to the principles of the invention. Figure 1 A light-emitting display device having a light-emitting element is illustrated as an exemplary embodiment of the display device 1 , but the display device 1 is not limited thereto.

[0050] Reference Figure 1, the display device 1 includes a display unit 10 , a scan driver 20 for driving the display unit 10 , an emission control driver 30 , a data driver 40 , and a timing controller 50 .

[0051] The display unit 10 includes pixels PXL connected to scan lines S1 to Sn, emission control lines E1 to En, and data lines D1 to Dm. In an exemplary embodiment, the term "connection" may include electrical connection and / or physical connection. For example, the pixels PXL may be electrically connected to the scan lines S1 to Sn, the emission control lines E1 to En, and the data lines D1 to Dm.

[0052] The pixels PXL receive scan signals, emission control signals and data signals from scan lines S1 to Sn, emission control lines E1 to En and data lines D1 to Dm, respectively. In addition, the pixels PXL also receive driving power such as a first pixel power ELVDD and a second pixel power ELVSS.

[0053] The pixel PXL receives each of the data signals from the data lines D1 to Dm when each of the scan signals is supplied from the scan lines S1 to Sn, and emits light having brightness corresponding to the data signal. Thus, an image corresponding to the data signal of each frame is displayed in the display unit 10.

[0054] Each pixel PXL may include a light emitting element and a pixel circuit for driving the light emitting element. The pixel circuit controls a driving current corresponding to a data signal to be conducted from a first pixel power source ELVDD to a second pixel power source ELVSS via the light emitting element.

[0055] The scan driver 20 receives a scan drive control signal SCS from the timing controller 50, and supplies a scan signal to the scan lines S1 to Sn in response to the scan drive control signal SCS. For example, the scan driver 20 may sequentially supply the scan signal to the scan lines S1 to Sn. When the scan signal is supplied to the scan lines S1 to Sn, the pixel PXL is selected in units of horizontal rows in response to each scan signal.

[0056] The scan signal may be used to select the pixel PXL in units of horizontal rows. For example, the scan signal may have a gate-on voltage (e.g., a low voltage) at which a transistor of each pixel PXL connected to the data lines D1 to Dm may be turned on, and may be supplied to the pixel PXL disposed on the corresponding horizontal row in each horizontal period.

[0057] The pixel PXL receiving the scan signal may be connected to the data lines D1 to Dm while the scan signal is supplied and may receive each data signal. That is, the scan signal may be supplied to transfer the data signal to the pixel PXL.

[0058] The emission control driver 30 receives the emission driving control signal ECS from the timing controller 50 and supplies the emission control signal to the emission control lines E1 to En in response to the emission driving control signal ECS. For example, the emission control driver 30 may sequentially supply the emission control signal to the emission control lines E1 to En.

[0059] The emission control signal can be used to control the emission period (e.g., emission time point and / or emission duration) of the pixel PXL in units of horizontal lines. For example, the emission control signal may have a gate cut-off voltage (e.g., a high voltage) at which at least one transistor disposed on the current path of each pixel PXL can be cut off. In this case, the pixel PXL receiving the emission control signal can be set to a non-emission state during the period in which the emission control signal is supplied, and can be set to an emission state during other periods. On the other hand, when a data signal corresponding to a black grayscale is supplied to a specific pixel PXL, the pixel PXL can remain in a non-emission state in response to the data signal even if the emission control signal is not supplied.

[0060] The data driver 40 receives the data drive control signal DCS and the image data RGB from the timing controller 50, and supplies the data signal to the data lines D1 to Dm in response to the data drive control signal DCS and the image data RGB. The data signal supplied to the data lines D1 to Dm is supplied to the pixel PXL selected by the scan signal. To this end, the data driver 40 may supply the data signal to the data lines D1 to Dm to synchronize with each scan signal. For example, for each horizontal period, the data driver 40 may output the data signal corresponding to the pixel PXL of the corresponding horizontal row to the data lines D1 to Dm to synchronize with each scan signal.

[0061] The timing controller 50 receives various control signals (e.g., vertical / horizontal synchronization signals, main clock signals, etc.) from the outside (e.g., a host processor), and generates a scan drive control signal SCS, an emission drive control signal ECS, and a data drive control signal DCS in response to the control signals. The scan drive control signal SCS, the emission drive control signal ECS, and the data drive control signal DCS are supplied to the scan driver 20, the emission control driver 30, and the data driver 40, respectively.

[0062] The scan driving control signal SCS includes a start pulse and a clock signal. The start pulse controls the output timing of the first scan signal (eg, the scan signal supplied to the first scan line S1), and the clock signal is used to shift the start pulse.

[0063] The emission driving control signal ECS includes a start pulse and a clock signal. The start pulse controls the output timing of the first emission control signal (eg, the emission control signal supplied to the first emission control line E1), and the clock signal is used to shift the start pulse.

[0064] The data driving control signal DCS includes a source start pulse and a clock signal. The source start pulse controls the sampling start point of the data, and the clock signal is used to control the sampling operation.

[0065] In addition, the timing controller 50 receives input image data from the outside and rearranges the input image data to generate image data RGB. The timing controller 50 supplies the image data RGB to the data driver 40.

[0066] Figure 2A and Figure 2B yes Figure 1 A circuit diagram of a representative pixel of a display device. For example, Figure 2A and Figure 2B Shows that it can be set Figure 1 Different exemplary embodiments of the pixels PXL in the display unit 10. The pixels PXL and PXL' may be arranged in the i-th (i is a natural number) horizontal row and the j-th (j is a natural number) vertical column of the display unit 10 to be connected to the i-th scan line Si, the i-th emission control line Ei, and the j-th data line Dj. According to an exemplary embodiment, the pixels arranged in Figure 1 The pixels PXL or PXL' in the display unit 10 may have substantially the same structure as each other. Hereinafter, the "i-th scan line Si", the "i-th emission control line Ei" and the "j-th data line Dj" are referred to as the "scan line Si", the "emission control line Ei" and the "data line Dj", respectively.

[0067] Reference Figure 2A According to an exemplary embodiment, the pixel PXL includes a light emitting element EL and a pixel circuit PXC for driving the light emitting element EL. According to an exemplary embodiment, the light emitting element EL may be connected between the pixel circuit PXC and the second pixel power source ELVSS, but the position of the light emitting element EL is not limited thereto. For example, in another exemplary embodiment, the light emitting element EL may be connected between the first pixel power source ELVDD and the pixel circuit PXC.

[0068] The light emitting element EL is connected between the first pixel power source ELVDD and the second pixel power source ELVSS in a forward direction. For example, the anode of the light emitting element EL may be connected to the first pixel power source ELVDD via the pixel circuit PXC, and the cathode of the light emitting element EL may be connected to the second pixel power source ELVSS. The first pixel power source ELVDD and the second pixel power source ELVSS may have a potential difference that allows the light emitting element EL to emit light. For example, the first pixel power source ELVDD may be a high potential pixel power source, and the second pixel power source ELVSS may be a low potential pixel power source having a potential lower than the threshold voltage of the light emitting element EL or a voltage greater than the first pixel power source ELVDD.

[0069] The pixel circuit PXC includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst.

[0070] The first transistor T1 is connected between the first pixel power source ELVDD and the light emitting element EL. For example, the first electrode (e.g., source electrode) of the first transistor T1 may be connected to the first pixel power source ELVDD, and the second electrode (e.g., drain electrode) of the first transistor T1 may be connected to the anode of the light emitting element EL via the third transistor T3. In addition, the gate electrode of the first transistor T1 is connected to the tenth node N10. The first transistor T1 controls the driving current from the first pixel power source ELVDD via the third transistor T3 and the light emitting element EL to the second pixel power source ELVSS in response to the voltage of the tenth node N10.

[0071] The second transistor T2 is connected between the data line Dj and the tenth node N10. For example, a first electrode (e.g., a source electrode) of the second transistor T2 may be connected to the data line Dj, and a second electrode (e.g., a drain electrode) of the second transistor T2 may be connected to the tenth node N10. A gate electrode of the second transistor T2 is connected to the scan line Si. The second transistor T2 is turned on when a scan signal (e.g., a low voltage scan signal) is supplied to the scan line Si to transmit the data signal from the data line Dj to the tenth node N10.

[0072] The third transistor T3 is connected between the first transistor T1 and the light emitting element EL. For example, the first electrode (e.g., source electrode) of the third transistor T3 may be connected to the second electrode of the first transistor T1, and the second electrode (e.g., drain electrode) of the third transistor T3 may be connected to the anode of the light emitting element EL. The gate electrode of the third transistor T3 is connected to the emission control line Ei. The third transistor T3 is turned off when an emission control signal (e.g., an emission control signal of a high voltage) is supplied to the emission control line Ei, and is turned on in other cases (e.g., when the supply of the emission control signal stops and the voltage of the emission control line Ei is maintained at the gate-on voltage).

[0073] When the third transistor T3 is turned off, the connection between the first transistor T1 and the light emitting element EL is cut off, so that the current path in the pixel PXL is blocked and the pixel PXL does not emit light. When the third transistor T3 is turned on, the first transistor T1 and the light emitting element EL are electrically connected to each other, so that a current path through which the driving current flows can be formed in the pixel PXL and the pixel PXL can emit light.

[0074] The storage capacitor Cst is connected between the first pixel power source ELVDD and the tenth node N10. The storage capacitor Cst charges a voltage corresponding to the voltage of the tenth node N10.

[0075] The structure of the pixel PXL may be changed in various ways according to specific exemplary embodiments. For example, the structure of the pixel circuit PXC may be changed to Figure 2B Another exemplary embodiment is shown in FIG.

[0076] Reference Figure 2B The pixel PXL' includes a light emitting element EL and a pixel circuit PXC' for driving the light emitting element EL. The pixel circuit PXC' includes first to seventh transistors T1 to T7 and a storage capacitor Cst.

[0077] The anode of the light emitting element EL is connected to the first transistor T1 via the third transistor T3, and the cathode of the light emitting element EL is connected to the second pixel power source ELVSS. When the driving current is supplied from the first transistor T1, the light emitting element EL generates light with brightness corresponding to the current amount of the driving current.

[0078] The first electrode of the first transistor T1 is connected to the first pixel power source ELVDD via the fourth transistor T4, and the second electrode of the first transistor T1 is connected to the anode of the light emitting element EL via the third transistor T3. In addition, the gate electrode of the first transistor T1 may be connected to the tenth node N10. The first transistor T1 controls a driving current flowing from the first pixel power source ELVDD to the second pixel power source ELVSS via the light emitting element EL in response to a voltage of the tenth node N10.

[0079] The second transistor T2 is connected between the data line Dj and the first electrode of the first transistor T1. The gate electrode of the second transistor T2 is connected to the scan line Si. The second transistor T2 is turned on when the scan signal is supplied to the scan line Si and connects the data line Dj to the first electrode of the first transistor T1. Therefore, when the second transistor T2 is turned on, the data signal from the data line Dj can be transmitted to the first electrode of the first transistor T1. On the other hand, during the period in which the second transistor T2 is turned on by the scan signal, the first transistor T1 is turned on in a diode-connected manner through the fifth transistor T5. Therefore, the data signal from the data line Dj can be transmitted to the tenth node N10 via the second transistor T2, the first transistor T1 and the fifth transistor T5. Thus, the storage capacitor Cst is charged with a voltage corresponding to the voltage of the data signal and the threshold voltage of the first transistor T1.

[0080] The third transistor T3 is connected between the first transistor T1 and the light emitting element EL, and a gate electrode of the third transistor T3 is connected to the emission control line Ei. The third transistor T3 is turned off when an emission control signal is supplied to the emission control line Ei, and is turned on in other cases.

[0081] The fourth transistor T4 is connected between the first pixel power source ELVDD and the first transistor T1. A gate electrode of the fourth transistor T4 is connected to the emission control line Ei. The fourth transistor T4 is turned off when the emission control signal is supplied to the emission control line Ei, and is turned on in other cases.

[0082] That is, the third transistor T3 and the fourth transistor T4 can be turned on or off at the same time by the emission control signal. When the third transistor T3 and the fourth transistor T4 are turned on, a current path through which a driving current can flow can be formed in the pixel PXL'. On the contrary, when the third transistor T3 and the fourth transistor T4 are turned off, the current path is blocked and the pixel PXL' does not emit light.

[0083] The fifth transistor T5 is connected between the first transistor T1 and the tenth node N10. The gate electrode of the fifth transistor T5 is connected to the scan line Si. The fifth transistor T5 is turned on when the scan signal is supplied to the scan line Si, so that the second electrode of the first transistor T1 is connected to the tenth node N10. Therefore, when the fifth transistor T5 is turned on, the first transistor T1 is connected in a diode form.

[0084] The sixth transistor T6 is connected between the tenth node N10 and the initialization power supply Vint. The gate electrode of the sixth transistor T6 is connected to the previous scan line (for example, the i-1th scan line Si-1). The sixth transistor T6 is turned on when the scan signal is supplied to the i-1th scan line Si-1 to initialize the voltage of the tenth node N10 using the voltage of the initialization power supply Vint.

[0085] In an exemplary embodiment, the i-1th scan line Si-1 is used as an initialization control line for initializing the gate node (i.e., the tenth node N10 of the first transistor T1), but the exemplary embodiment is not limited thereto. For example, in another exemplary embodiment, another control line such as the i-2th scan line Si-2 may be used as an initialization control line for initializing the gate node of the first transistor T1.

[0086] The voltage of the initialization power supply Vint can be set to a voltage lower than the voltage of the data signal. That is, the voltage of the initialization power supply Vint can be set to be equal to or less than the lowest voltage of the data signal. Therefore, when the voltage of the tenth node N10 charged by the data signal of the previous frame is initialized to the lowest voltage of the data signal or lower voltage before the data signal of the current frame is transmitted to each pixel PXL', during the period in which the scan signal is supplied to the scan line Si, the first transistor T1 is diode-connected in the forward direction, regardless of the data signal of the previous frame. Therefore, the data signal of the current frame can be stably transmitted to the tenth node N10.

[0087] The seventh transistor T7 is connected between the initialization power supply Vint and the anode of the light emitting element EL. The gate electrode of the seventh transistor T7 is connected to the i+1th scan line Si+1. The seventh transistor T7 is turned on when the scan signal is supplied to the i+1th scan line Si+1 to initialize the voltage of the anode of the light emitting element EL to the voltage of the initialization power supply Vint. Therefore, the pixel PXL' can present a uniform brightness characteristic.

[0088] In the exemplary embodiment, the case where the initialization control line connected to the gate electrode of the seventh transistor T7 is the i+1th scan line Si+1 is described as an example, but the exemplary embodiment is not limited thereto. For example, in another exemplary embodiment, the gate electrode of the seventh transistor T7 may be connected to the current scan line (i.e., the scan line Si (or another control line)). In this case, when the scan signal is supplied to the scan line Si, the voltage of the anode of the light emitting element EL may be initialized to the voltage of the initialization power supply Vint.

[0089] The storage capacitor Cst is connected between the first pixel power source ELVDD and the tenth node N10. The storage capacitor Cst charges a voltage corresponding to the voltage of the data signal and the threshold voltage of the first transistor T1.

[0090] On the other hand, the structure of the pixels PXL and PXL' is not limited to Figure 2A and Figure 2B For example, the pixel circuits PXC and PXC' may have various structures currently known.

[0091] Figure 3 is a block diagram of an exemplary embodiment of an emission control driver constructed according to the principles of the invention. For ease of description, Figure 3 Only four stages ST (e.g., first to fourth stages ST1 to ST4) are shown. According to an exemplary embodiment, the emission control driver 30 may include a plurality of stages ST (such as first to fourth stages ST1 to ST4) dependently connected to an input terminal of the start pulse SSP (e.g., the first input terminal 101 of the first stage ST1).

[0092] Reference Figure 3 , the emission control driver 30 according to an exemplary embodiment includes a plurality of stages ST for supplying a plurality of emission control signals to a plurality of emission control lines Ei, respectively. The stage ST is connected to at least one of the emission control lines E1 to E4, and is driven in response to at least one clock signal CLK (e.g., a first clock signal CLK1 and a second clock signal CLK2). For example, the first stage ST1 to the fourth stage ST4 are respectively connected to the first emission control lines E1 to the fourth emission control lines E4, and generate emission control signals using the first clock signal CLK1 and the second clock signal CLK2. The first stage ST1 to the fourth stage ST4 can sequentially output emission control signals to the first emission control lines E1 to the fourth emission control lines E4. According to an exemplary embodiment, the stage ST can have substantially the same circuit structure.

[0093] Each of the stages ST includes a first input terminal 101 , a second input terminal 102 , a third input terminal 103 , and an output terminal 104 .

[0094] The first input terminal 101 receives a first input signal. According to an exemplary embodiment, the first input signal may be a start pulse SSP or an output signal of a previous stage (i.e., an emission control signal of the previous stage). For example, the first stage (hereinafter, referred to as "the first stage ST1") may receive the start pulse SSP through the first input terminal 101, and the other stages ST may receive the output signal of the previous stage through the first input terminal 101.

[0095] The second input terminal 102 and the third input terminal 103 receive the second input signal and the third input signal, respectively. According to an exemplary embodiment, the second input signal and the third input signal of the kth (k is an odd number or an even number) stage STk may be the first clock signal CLK1 and the second clock signal CLK2, respectively. The second input signal and the third input signal of the k+1th stage STk+1 may be the second clock signal CLK2 and the first clock signal CLK1, respectively. For example, the kth stage STk receives the first clock signal CLK1 and the second clock signal CLK2 through the second input terminal 102 and the third input terminal 103, respectively, and the k+1th stage STk+1 receives the second clock signal CLK2 and the first clock signal CLK1 through the second input terminal 102 and the third input terminal 103, respectively.

[0096] The first clock signal CLK1 and the second clock signal CLK2 may alternately have a gate-on voltage. For example, the first clock signal CLK1 and the second clock signal CLK2 may be signals having the same cycle and not overlapping each other in phase. For example, the second clock signal CLK2 may be a clock signal obtained by shifting the first clock signal CLK1 by half a cycle.

[0097] In addition, the stage ST operates using a first power supply VDD and a second power supply VSS. The voltage of the first power supply VDD can be set to a gate-off voltage (e.g., a high voltage), and the voltage of the second power supply VSS can be set to a gate-on voltage (e.g., a low voltage). In this case, the voltage of the first power supply VDD transmitted to the output terminal 104 can be used as an emission control signal for preventing the emission of the pixel PXL (or pixel PXL', hereinafter the pixel PXL can also refer to the pixel PXL').

[0098] Figure 4 is Figure 3 1 is a circuit diagram of a first exemplary embodiment of two stages shown in FIG. According to an exemplary embodiment, a plurality of stages ST forming the emission control driver 30 may have substantially the same circuit structure. Therefore, Figure 4 Only the first stage ST1 and the second stage ST2 are shown as representatives of the stages ST.

[0099] Reference Figure 4, the stage ST according to the exemplary embodiment includes an input unit 210, a first controller 220, a second controller 230, and an output unit 240. The stage ST generates an emission control signal using the first to third input signals supplied through the first to third input terminals 101 to 103, respectively, and supplies the generated emission control signal to the output terminal 104. For example, the stage ST may output each emission control signal by using a start pulse SSP supplied through the first to third input terminals 101 to 103 or an output signal of a previous stage, one of the first and second clock signals CLK1 and CLK2, and the other of the first and second clock signals CLK1 and CLK2.

[0100] In addition, the stage ST is connected to the first power supply VDD and the second power supply VSS respectively through the first power supply terminal 105 and the second power supply terminal 106. The stage ST can control the voltage of the output terminal 104 by using the voltages of the first power supply VDD and the second power supply VSS supplied to the first power supply terminal 105 and the second power supply terminal 106. Hereinafter, for the convenience of description, the circuit structure of each stage ST will be described focusing on the first stage ST1.

[0101] The input unit 210 controls the voltage of the first node N1 and the voltage of the second node N2 in response to the first input signal supplied from the first input terminal 101 and the second input signal supplied from the second input terminal 102. For example, the input unit 210 may control the voltage of the first node N1 and the voltage of the second node N2 in response to the start pulse SSP supplied from the first input terminal 101 and the first clock signal CLK1 supplied from the second input terminal 102. To this end, the input unit 210 includes sixth to eighth transistors M6 to M8.

[0102] The sixth transistor M6 is connected between the first input terminal 101 and the first node N1. In addition, the gate electrode of the sixth transistor M6 is connected to the second input terminal 102. The sixth transistor M6 is turned on when the first clock signal CLK1 of the gate-on voltage (e.g., low voltage) is supplied to the second input terminal 102 to connect the first input terminal 101 to the first node N1.

[0103] The seventh transistor M7 is connected between the second node N2 and the second input terminal 102. In addition, a gate electrode of the seventh transistor M7 is connected to the first node N1. The seventh transistor M7 is turned on or off in response to the voltage of the first node N1.

[0104] The eighth transistor M8 is connected between the second node N2 and the second power supply VSS. In addition, the gate electrode of the eighth transistor M8 is connected to the second input terminal 102. The eighth transistor M8 is turned on when the first clock signal CLK1 of the gate-on voltage is supplied from the second input terminal 102, and supplies the voltage of the second power supply VSS to the second node N2.

[0105] The first controller 220 controls the voltages of the third node N3 and the fourth node N4 in response to the voltage of the third input signal (e.g., the second clock signal CLK2) supplied from the third input terminal 103 and the voltage of the second node N2. To this end, the first controller 220 includes first to third transistors M1 to M3, ninth to eleventh transistors M9 to M11, and first and second capacitors C1 and C2.

[0106] The first transistor M1 and the second transistor M2 are connected to the first power source VDD and the third node N3. For example, the first transistor M1 and the second transistor M2 may be connected in series between the first power source VDD and the third node N3.

[0107] The gate electrodes of the first transistor M1 and the second transistor M2 are connected to different nodes. Therefore, the first transistor M1 and the second transistor M2 are turned on or off in response to the voltage applied to each gate node. For example, the gate electrode of the first transistor M1 can be connected to the second node N2, and the gate electrode of the second transistor M2 can be connected to the third input terminal 103.

[0108] The first transistor M1 is turned on or off in response to the voltage of the second node N2. For example, the first transistor M1 is turned on when the gate-on voltage is supplied to the second node N2 so that the first power source VDD is connected to the second transistor M2.

[0109] The second transistor M2 is turned on or off in response to the voltage of the third input signal supplied to the third input terminal 103. For example, the second transistor M2 is turned on when the second clock signal CLK2 of the gate-on voltage is supplied to the third input terminal 103 to connect the first transistor M1 to the third node N3.

[0110] The first transistor M1 and the second transistor M2 may be turned on together during a period in which the gate-on voltage is supplied to both the second node N2 and the third input terminal 103. When the first transistor M1 and the second transistor M2 are turned on together, the voltage of the first power supply VDD is transmitted to the third node N3. Then, the fifth transistor M5 is turned off due to the voltage of the first power supply VDD.

[0111] In an exemplary embodiment, the second transistor M2 is directly connected to the third node N3 without passing through other circuit elements. For example, one electrode (e.g., drain electrode) of the second transistor M2 is directly connected to the third node N3 without passing through the third transistor M3, etc. Therefore, at the start of driving of the display device 1 (e.g., the time point when the driving power (e.g., the first power supply VDD and the second power supply VSS) and the driving signal (e.g., the start pulse SSP, the first clock signal CLK1 and the second clock signal CLK2) begin to be supplied to the stage ST), the voltage of the first power supply VDD can be quickly transmitted to the third node N3. Therefore, the fifth transistor M5 can be stably maintained in a cut-off state at the start of driving of the display device 1. Therefore, it is possible to prevent the voltage of the second power supply VSS from being transmitted to the emission control line Ei before the emission period of the pixel PXL begins.

[0112] According to an exemplary embodiment, it is possible to prevent abnormal emission of the pixel PXL due to instability of the node voltage inside the stage ST at the start of driving of the display device 1. For example, it is possible to prevent flickering of the pixel PXL when unexpectedly emitting light at the start of driving of the display device 1 by directly connecting the first transistor M1 and the second transistor M2 between the first power supply VDD and the third node N3.

[0113] The third transistor M3 is connected between the first node N1 and the third node N3. In addition, the gate electrode of the third transistor M3 is connected to the second power supply VSS. The third transistor M3 is turned on in response to the voltage of the second power supply VSS during the period in which the second power supply VSS is supplied. For example, the first power supply VDD and the second power supply VSS can be continuously supplied to the emission control driver 30 during the period in which the display device 1 is driven, so that the third transistor M3 can be continuously maintained in the on state during the period in which the emission control driver 30 is driven. For example, the third transistor M3 can always remain in the on state during the period in which the stage ST is driven, so the third transistor M3 can also be called a normally-on transistor (AOT).

[0114] By connecting the third transistor M3 between the first node N1 and the third node N3, the voltage drop width of the first node N1 can be limited. Therefore, the voltage difference between the source electrode and the drain electrode of the sixth transistor M6 can be limited. Therefore, the exemplary embodiment of the invention can prevent the characteristics of the sixth transistor M6 from changing, thereby enhancing the reliability of the sixth transistor M6.

[0115] The ninth transistor M9 is connected between the second node N2 and the fifth node N5. The gate electrode of the ninth transistor M9 is connected to the second power supply VSS. The ninth transistor M9 is turned on in response to the voltage of the second power supply VSS during the period in which the second power supply VSS is supplied. For example, the first power supply VDD and the second power supply VSS are continuously supplied to the emission control driver 30 during the period in which the display device 1 is driven, so that the ninth transistor M9 can be continuously maintained in the on state during the period in which the emission control driver 30 is driven. For example, the ninth transistor M9 can always remain in the on state during the period in which the stage ST is driven, so the ninth transistor M9 can also be called AOT.

[0116] By connecting the ninth transistor M9 between the second node N2 and the fifth node N5, the voltage drop width of the second node N2 can be limited. Therefore, the voltage difference between the source electrode and the drain electrode of the seventh transistor M7 and the voltage difference between the gate electrode and the source electrode of the first transistor M1 or between the gate electrode and the drain electrode of the first transistor M1 can be limited. Therefore, the exemplary embodiment of the invention can prevent the characteristics of the first transistor M1 and the seventh transistor M7 from changing, thereby enhancing the reliability of the first transistor M1 and the seventh transistor M7.

[0117] The tenth transistor M10 is connected between a sixth node N6 and a fourth node N4, and the sixth node N6 is connected to one electrode of the second capacitor C2. In addition, a gate electrode of the tenth transistor M10 is connected to the third input terminal 103. The tenth transistor M10 is turned on when the second clock signal CLK2 of the gate-on voltage is supplied from the third input terminal 103, so that the sixth node N6 is connected to the fourth node N4.

[0118] The eleventh transistor M11 is connected between the sixth node N6 and the third input terminal 103. In addition, a gate electrode of the eleventh transistor M11 is connected to the fifth node N5. The eleventh transistor M11 is turned on or off in response to a voltage of the fifth node N5.

[0119] The first capacitor C1 is connected between the third node N3 and the third input terminal 103. The first capacitor C1 charges the voltage applied to the third node N3. In addition, the first capacitor C1 controls the voltage of the third node N3 in response to the voltage of the second clock signal CLK2 supplied from the third input terminal 103.

[0120] The second capacitor C2 is connected between the fifth node N5 and the sixth node N6. When the second clock signal CLK2 is transmitted to the sixth node N6, the second capacitor C2 controls the voltage of the fifth node N5 in response to the voltage of the second clock signal CLK2.

[0121] The second controller 230 controls the voltage of the fourth node N4 in response to the voltage of the first node N1. To this end, the second controller 230 includes a twelfth transistor M12 and a third capacitor C3.

[0122] The twelfth transistor M12 is connected between the first power supply VDD and the fourth node N4. In addition, the gate electrode of the twelfth transistor M12 is connected to the first node N1. The twelfth transistor M12 is turned on or off in response to the voltage of the first node N1. In another exemplary embodiment, the gate electrode of the twelfth transistor M12 may be directly connected to the third node N3. In this case, the twelfth transistor M12 is turned on or off in response to the voltage of the third node N3.

[0123] The third capacitor C3 is connected between the first power source VDD and the fourth node N4. The third capacitor C3 charges the voltage applied to the fourth node N4. In addition, the third capacitor C3 keeps the voltage of the fourth node N4 stable.

[0124] The output unit 240 supplies the voltage of the first power source VDD or the second power source VSS to the output terminal 104 in response to the voltage of the third node N3 or the voltage of the fourth node N4. To this end, the output unit 240 includes a fourth transistor M4 and a fifth transistor M5.

[0125] The fourth transistor M4 is connected between the first power supply VDD and the output terminal 104. In addition, the gate electrode of the fourth transistor M4 is connected to the fourth node N4. The fourth transistor M4 is turned on or off in response to the voltage of the fourth node N4. When the fourth transistor M4 is turned on, the voltage of the first power supply VDD is transmitted to the output terminal 104, and the voltage of the first power supply VDD is used as an emission control signal for controlling the emission period of the pixel PXL (for example, the pixel PXL set in the first horizontal row of the display unit 10) connected to each of the emission control lines Ei (for example, the first emission control line E1). For example, during the period in which the emission control signal corresponding to the voltage of the first power supply VDD is supplied, the pixel PXL can be set to a non-emission state.

[0126] The fifth transistor M5 is connected between the output terminal 104 and the second power supply VSS. In addition, the gate electrode of the fifth transistor M5 is connected to the third node N3. The fifth transistor M5 is turned on or off in response to the voltage of the third node N3. When the fifth transistor M5 is turned on, the voltage of the second power supply VSS is transmitted to the output terminal 104, so that the pixel PXL can be set to an emission state.

[0127] The first input signal to the third input signal supplied to the first input terminal 101 to the third input terminal 103 in the second stage ST2 is different from the first input signal to the third input signal supplied to the first input terminal 101 to the third input terminal 103 in the first stage ST1, but the circuit structure and operation of the second stage ST2 can be substantially the same as the circuit structure and operation of the first stage ST1. For example, the second stage ST2 can receive the output signal of the first stage ST1 (the first emission control signal supplied to the first emission control line E1), the second clock signal CLK2 and the first clock signal CLK1 through the first input terminal 101 to the third input terminal 103, respectively, and can generate an emission control signal by using the output signal of the first stage ST1, the second clock signal CLK2 and the first clock signal CLK1. The emission control signal generated in the second stage ST2 is supplied to the second emission control line E2.

[0128] The stage ST may sequentially output the emission control signal to each of the emission control lines Ei using the above method. The circuit structure and operation of each of the second stage ST2 and the next stage ST may be substantially the same as the first stage ST1. Therefore, a detailed description thereof will be omitted to avoid redundancy.

[0129] Figure 5 It is shown in Figure 4 For ease of description, Figure 5 The operation process of the first stage ST1 is shown, and the other stages ST2, ST3, and ST4 may also operate in substantially the same method.

[0130] Reference Figure 5 , the first clock signal CLK1 and the second clock signal CLK2 are supplied with a gate-on voltage at different time points. For example, each of the first clock signal CLK1 and the second clock signal CLK2 may have a period of two horizontal periods 2H, and may be supplied with a gate-on voltage in different horizontal periods. For example, the second clock signal CLK2 may be a signal obtained by shifting the first clock signal CLK1 by half a period (i.e., one horizontal period 1H).

[0131] The start pulse SSP supplied to the first input terminal 101 of the first stage ST1 may overlap with at least one gate-on voltage period of the first clock signal CLK1 supplied to the second input terminal 102 of the first stage ST1. Similarly, the output signal of the previous stage supplied to the first input terminal 101 of the other stage ST may overlap with at least one gate-on voltage period of the first clock signal CLK1 or the second clock signal CLK2 supplied to the second input terminal 102.

[0132] To this end, the start pulse SSP may have a width greater than that of the first clock signal CLK1 (e.g., a width corresponding to four horizontal periods 4H). In this case, the first emission control signal supplied to the first input terminal 101 of the second stage ST2 may also overlap with at least one gate-on voltage of the second clock signal CLK2 supplied to the second input terminal 102 of the second stage ST2. For example, the first emission control signal supplied to the first input terminal 101 of the second stage ST2 may have a width corresponding to three horizontal periods 3H.

[0133] The expression that the start pulse SSP (or the output signal of the previous stage) is supplied means that a gate-off voltage (for example, a high voltage of the first power supply VDD) can be supplied to the first input terminal 101. The expression that the start pulse SSP is not supplied means that a gate-on voltage (for example, a low voltage of the second power supply VSS) can be supplied to the first input terminal 101.

[0134] The following will refer to Figure 4 and Figure 5 The operation of the first stage ST1 is described. First, at a first time point t1, a first clock signal CLK1 of a gate-on voltage (eg, a low voltage) is supplied to the second input terminal 102. Therefore, the sixth transistor M6 and the eighth transistor M8 are turned on.

[0135] When the sixth transistor M6 is turned on, the first input terminal 101 and the first node N1 are connected to each other. At this time, since the third transistor M3 is kept in a turned-on state by the voltage of the second power supply VSS, the first input terminal 101 is also connected to the third node N3 via the first node N1 and the third transistor M3. The start pulse SSP is not supplied to the first input terminal 101 at the first time point t1. That is, the gate-on voltage can be applied to the first input terminal 101, so the gate-on voltage (for example, the low voltage of the second power supply VSS) can be supplied to the first node N1 and the third node N3.

[0136] When the gate-on voltage is supplied to the first node N1 and the third node N3, the seventh transistor M7, the fifth transistor M5, and the twelfth transistor M12 are turned on.

[0137] When the twelfth transistor M12 is turned on, the voltage of the first power source VDD is supplied to the fourth node N4, so the fourth transistor M4 is turned off. At this time, the third capacitor C3 is charged with a voltage corresponding to the turn-off voltage of the fourth transistor M4.

[0138] When the fifth transistor M5 is turned on, the voltage of the second power source VSS is supplied to the output terminal 104. Therefore, the voltage of the second power source VSS (ie, the gate-on voltage) is output at the first emission control line E1.

[0139] When the seventh transistor M7 is turned on, the first clock signal CLK1 is supplied to the second node N2. Here, since the ninth transistor M9 maintains a turned-on state, the first clock signal CLK1 is also supplied to the fifth node N5 via the second node N2.

[0140] On the other hand, when the eighth transistor M8 is turned on, the voltage of the second power supply VSS is supplied to the second node N2 and the fifth node N5. Here, the voltage of the first clock signal CLK1 from the first time point t1 to the second time point t2 is set to the gate-on voltage (for example, the voltage of the second power supply VSS). Therefore, the voltage of the second node N2 and the fifth node N5 is stably set to the voltage of the second power supply VSS.

[0141] When the voltages of the second node N2 and the fifth node N5 are set to the voltage of the second power source VSS, the first transistor M1 and the eleventh transistor M11 are turned on.

[0142] When the eleventh transistor M11 is turned on, the second clock signal CLK2 supplied from the third input terminal 103 is supplied to the sixth node N6. The voltage of the second clock signal CLK2 from the first time point t1 to the third time point t3 is set to the gate cut-off voltage (for example, the voltage of the first power supply VDD). Therefore, since the tenth transistor M10 is set to the cut-off state, the fourth node N4 maintains the voltage of the first power supply VDD regardless of the voltages of the fifth node N5 and the sixth node N6.

[0143] When the first transistor M1 is turned on, the voltage of the first power source VDD is supplied to the second transistor M2. At this time, the second transistor M2 is set to a turned-off state due to the gate-off voltage of the second clock signal CLK2, so the third node N3 maintains a low voltage.

[0144] At the second time point t2, the voltage of the first clock signal CLK1 changes to a gate-off voltage (eg, a high voltage). Therefore, the sixth transistor M6 and the eighth transistor M8 are turned off. At this time, the third node N3 and the fourth node N4 maintain the voltage of the previous period through the first capacitor C1 and the third capacitor C3.

[0145] When the third transistor M3 maintains the on state and the third node N3 maintains the low voltage, the voltage of the first node N1 also maintains the low voltage. Therefore, the seventh transistor M7, the fifth transistor M5 and the twelfth transistor M12 maintain the on state.

[0146] When the seventh transistor M7 is turned on, the high voltage of the first clock signal CLK1 is supplied to the second node N2 and the fifth node N5. Then, the first transistor M1 and the eleventh transistor M11 are turned off.

[0147] When the twelfth transistor M12 is turned on, the voltage of the fourth node N4 is maintained at the high voltage of the first power source VDD. Therefore, the fourth transistor M4 is maintained in the off state.

[0148] When the fifth transistor M5 is turned on, the low voltage of the second power source VSS is transmitted to the output terminal 104. Therefore, the voltage of the first emission control line E1 is maintained at a low voltage.

[0149] At the third time point t3, the voltage of the second clock signal CLK2 changes to a gate-on voltage (eg, a low voltage). Therefore, the second transistor M2 and the tenth transistor M10 are turned on.

[0150] When the tenth transistor M10 is turned on, the sixth node N6 is connected to the fourth node N4. At this time, the voltage of the fourth node N4 is maintained at the high voltage of the first power source VDD.

[0151] When the second transistor M2 is turned on, the second electrode (eg, drain electrode) of the first transistor M1 is connected to the third node N3. At this time, since the first transistor M1 is set to an off state, the voltage of the first power supply VDD is not supplied to the first node N1 and the third node N3.

[0152] In addition, when the voltage of the second clock signal CLK2 changes to a low voltage, the voltage of the third node N3 decreases to a voltage lower than the voltage of the second power source VSS through the coupling action of the first capacitor C1. Figure 5 As shown in FIG, when the second clock signal CLK2 is supplied as a low voltage, the third node N3 has a voltage lower than the voltage of the second power supply VSS. Thus, the voltage applied to the gate electrode of the fifth transistor M5 is reduced to a voltage lower than the voltage of the second power supply VSS, thereby improving the driving characteristics of the fifth transistor M5.

[0153] On the other hand, the first node N1 substantially maintains the voltage of the second power supply VSS through the third transistor M3 regardless of the voltage drop of the third node N3. That is, since the voltage of the second power supply VSS is applied to the gate electrode of the third transistor M3, the voltage of the first node N1 substantially maintains the voltage of the second power supply VSS regardless of the voltage drop of the third node N3. In this case, the voltage difference between the source electrode and the drain electrode of the sixth transistor M6 is minimized, thereby preventing the electrical characteristics of the sixth transistor M6 from being changed.

[0154] At the fourth time point t4, a gate-off voltage (eg, a high voltage start pulse SSP) starts to be supplied. At the fourth time point t4, the voltage of the first clock signal CLK1 changes to a gate-on voltage (eg, a low voltage). Therefore, the sixth transistor M6 and the eighth transistor M8 are turned on.

[0155] When the sixth transistor M6 is turned on, the first input terminal 101 is connected to the first node N1 and the third node N3. Therefore, the high voltage of the start pulse SSP is supplied to the first node N1 and the third node N3, so that Figure 5 The first node N1 and the third node N3 both have the same high voltage. When the voltages of the first node N1 and the third node N3 are set to high voltages, the seventh transistor M7, the fifth transistor M5, and the twelfth transistor M12 are turned off.

[0156] When the eighth transistor M8 is turned on, the voltage of the second power source VSS is supplied to the second node N2 and the fifth node N5. Therefore, the first transistor M1 and the eleventh transistor M11 are turned on.

[0157] At this time, since the second transistor M2 is in the off state, even if the first transistor M1 is turned on, the voltage of the third node N3 does not change.

[0158] When the eleventh transistor M11 is turned on, the sixth node N6 is connected to the third input terminal 103. At this time, since the tenth transistor M10 is set to a turned-off state, the voltage of the fourth node N4 is maintained at a high voltage.

[0159] At the fifth time point t5, the voltage of the second clock signal CLK2 changes to a gate-on voltage (e.g., a low voltage). Therefore, the second transistor M2 and the tenth transistor M10 are turned on. In addition, at the fifth time point t5, the voltages of the second node N2 and the fifth node N5 are set to the low voltage of the second power supply VSS, so that the first transistor M1 and the eleventh transistor M11 remain in the turned-on state.

[0160] When the tenth transistor M10 and the eleventh transistor M11 are turned on, the low voltage of the second clock signal CLK2 is supplied to the fourth node N4. Figure 5 As shown, the fourth node N4 has a low voltage, so that the fourth transistor M4 is turned on. When the fourth transistor M4 is turned on, the voltage of the first power supply VDD is supplied to the output terminal 104. The voltage of the first power supply VDD supplied to the output terminal 104 is supplied to the first emission control line E1 as a first emission control signal.

[0161] When the first transistor M1 and the second transistor M2 are turned on, the voltage of the first power source VDD is supplied to the first node N1 and the third node N3. As a result, the fifth transistor M5 and the seventh transistor M7 are stably maintained in a turned-off state.

[0162] On the other hand, when the low voltage of the second clock signal CLK2 is supplied to the sixth node N6, the voltage of the fifth node N5 is reduced to a voltage lower than the voltage of the second power supply VSS through the combined action of the second capacitor C2. That is, when the second clock signal CLK2 is supplied as a low voltage, the sixth node N6 has a voltage lower than the voltage of the second power supply VSS. Thus, the voltage applied to the gate electrode of the eleventh transistor M11 is reduced to a voltage lower than the voltage of the second power supply VSS, thereby improving the driving characteristics of the eleventh transistor M11.

[0163] In addition, the voltage of the second node N2 substantially maintains the voltage of the second power supply VSS through the ninth transistor M9, regardless of the voltage of the fifth node N5. In other words, since the low voltage of the second power supply VSS is applied to the gate electrode of the ninth transistor M9, the second node N2 substantially maintains the voltage of the second power supply VSS, regardless of the voltage drop of the fifth node N5. In this case, the voltage difference between the source electrode and the drain electrode of the seventh transistor M7 can be minimized to prevent the electrical characteristics of the seventh transistor M7 from being changed. In addition, the voltage difference between the gate electrode and the source electrode or the drain electrode of the first transistor M1 can be minimized to prevent the electrical characteristics of the first transistor M1 from being changed.

[0164] At the sixth time point t6, the voltage of the first clock signal CLK1 changes to a low voltage. Therefore, the sixth transistor M6 and the eighth transistor M8 are turned on. At the sixth time point t6, the supply of the start pulse SSP is stopped, and a low voltage may be applied to the first input terminal 101.

[0165] When the sixth transistor M6 is turned on, the first node N1 and the third node N3 are connected to the first input terminal 101. Therefore, a low voltage is supplied to the first node N1 and the third node N3 from the first input terminal 101. When the first node N1 and the third node N3 are set to a low voltage, the seventh transistor M7, the fifth transistor M5, and the twelfth transistor M12 are turned on.

[0166] When the seventh transistor M7 is turned on, the voltage of the first clock signal CLK1 is transmitted to the second node N2 and the fifth node N5.

[0167] When the twelfth transistor M12 is turned on, the voltage of the first power source VDD is supplied to the fourth node N4. As a result, the fourth transistor M4 is turned off.

[0168] When the fifth transistor M5 is turned on, the voltage of the second power source VSS is supplied to the output terminal 104. The voltage of the second power source VSS supplied to the output terminal 104 is supplied to the first emission control line E1. Therefore, the pixel PXL connected to the first emission control line E1 is set to an emission state.

[0169] The second stage ST2 receiving the first emission control signal from the output terminal 104 of the first stage ST1 may also supply the second emission control signal to the second emission control line E2 while repeating the above process. That is, the stage ST of the emission control driver 30 according to the exemplary embodiment may sequentially supply the emission control signal to the emission control lines E1 to En while repeating the above process.

[0170] Each emission control signal may have a width corresponding to the width of the start pulse SSP. For example, when the start pulse SSP is supplied to have a width corresponding to four horizontal periods 4H, an emission control signal having a width corresponding to three horizontal periods 3H may be output to the emission control lines E1 to En in a manner that the emission control signal is sequentially shifted by one horizontal period 1H.

[0171] Therefore, the width of the emission control signal can be controlled by controlling the width of the start pulse SSP. Then, the emission period of the pixel PXL can be controlled by controlling the width of the emission control signal.

[0172] Figure 6 It is shown Figure 4 A block diagram of the first-level refresh path is shown in FIG. For ease of description, Figure 6 The refresh process of the first stage ST1 is shown, and the other stages ST may also be refreshed in substantially the same manner.

[0173] Reference Figure 6 , the fifth transistor M5 can be kept in the off state by supplying the gate-off voltage to the third node N3 at the start of driving of the display device 1. For example, at the start of driving of the display device 1, the start pulse SSP of the high voltage can be continuously supplied during a predetermined time. Therefore, it is possible to prevent the pixel PXL from unexpectedly emitting light before each emission period by stably supplying the emission control signal of the gate-off voltage to the pixel PXL.

[0174] Specifically, in an exemplary embodiment, one electrode of the second transistor M2 is directly connected to the third node N3. Therefore, a refresh path can be formed, which is connected from the first power supply VDD to the third node N3 via the first transistor M1 and the second transistor M2 without passing through the third transistor M3 which can be used as a resistance element.

[0175] When driving of the display device 1 starts (set to be a period before substantial driving of the pixel PXL starts), a start pulse SSP having a gate-off voltage (e.g., a high voltage) is applied to the first input terminal 101 of the first stage ST1, and a first clock signal CLK1 and a second clock signal CLK2 having a gate-on voltage (e.g., a low voltage) are alternately supplied to the second input terminal 102 and the third input terminal 103 of the first stage ST1.

[0176] When the low voltage first clock signal CLK1 is supplied to the second input terminal 102, the sixth transistor M6 and the eighth transistor M8 are turned on. When the sixth transistor M6 is turned on, the high voltage start pulse SSP is supplied to the first node N1. As a result, the seventh transistor M7 and the twelfth transistor M12 are turned off. On the other hand, the high voltage start pulse SSP is also transmitted to the third node N3 via the third transistor M3 after a little time, so that the fifth transistor M5 can maintain the turned-off state.

[0177] When the eighth transistor M8 is turned on, the voltage of the second power source VSS is supplied to the second node N2. Therefore, the first transistor M1 is turned on.

[0178] When the second clock signal CLK2 of low voltage is supplied from the third input terminal 103 after half a cycle (e.g., one horizontal period 1H) of the first clock signal CLK1 and the second clock signal CLK2, the second transistor M2 is turned on. Therefore, the high voltage of the first power supply VDD is quickly transmitted to the third node N3, and a refresh path from the first power supply VDD to the third node N3 via the first transistor M1 and the second transistor M2 is formed. In addition, the high voltage of the first power supply VDD can be transmitted to the third node N3 of the other stage ST in the same way.

[0179] According to the above exemplary embodiment, the speed of refreshing the stage ST can be increased by setting the refresh path not to pass through a circuit element capable of generating a delay such as the third transistor M3. Therefore, even at the start of driving of the display device 1 in which the node voltage inside the stage ST is unstable, the gate-off voltage is quickly transmitted to the third node N3, so that the voltage of the second power supply VSS can be prevented from being supplied to the emission control line Ei. Therefore, according to the exemplary embodiment, the output quality of the emission control driver 30 can be improved, and unexpected flickering due to the emission of the pixel PXL can be prevented.

[0180] On the other hand, when one electrode of the second transistor M2 is connected to the third node N3 via the third transistor M3, the delay caused by the third transistor M3 delays the transmission of the gate-off voltage to the third node N3. At this time, since the voltages of the first clock signal CLK1 and the second clock signal CLK2 are switched at high speed, when the voltage of the third node N3 is not yet stable and the gate-on voltage of the second clock signal CLK2 is supplied to the third input terminal 103, the fifth transistor M5 is turned on, and the voltage of the third node N3 is reduced by the combined action of the first capacitor C1. Therefore, the voltage of the second power supply VSS rises, while the emission control line Ei is connected to the second power supply VSS, and the turn-on time of the third transistor M3 is further delayed. That is, when the refresh path is formed to pass through the third transistor M3, the time when the voltage of the first power supply VDD is transmitted to the third node N3 is delayed, and abnormal emission such as flickering in which the pixel PXL emits light at the same time may occur. On the other hand, in an exemplary embodiment, the second transistor M2 can be directly connected to the third node N3 to prevent abnormal emission of the pixel PXL.

[0181] Figure 7 is Figure 3 A circuit diagram of a second exemplary embodiment of two stages is shown in FIG. Figure 8 is Figure 3 A circuit diagram of a third exemplary embodiment of two stages is shown in FIG. Figure 7 and Figure 8 Shown in Figure 4 Another exemplary embodiment of the stage ST is shown in FIG. Figure 7 and Figure 8 When the exemplary embodiment is compared with the above exemplary embodiments (for example, Figure 4 Components that are the same as or similar to those of the exemplary embodiment of the present invention are denoted by the same reference numerals, and detailed descriptions thereof will be omitted to avoid redundancy.

[0182] Reference Figure 7 , at least one transistor forming each stage ST may be formed by a dual-structure transistor. For example, the seventh transistor M7 may be configured as a plurality of seventh transistors M7_1 and M7_2 connected in series between the second node N2 and the second input terminal 102. The gate electrodes of the seventh transistors M7_1 and M7_2 are commonly connected to the first node N1.

[0183] In the above exemplary embodiment, the plurality of seventh transistors M7_1 and M7_2 are formed to minimize leakage current, and the remaining configurations except for the seventh transistors M7_1 and M7_2 are the same as those of FIG. Figure 4 The exemplary embodiments of are substantially the same. In addition, Figure 4 and Figure 7Operations of the stages ST of the exemplary embodiments may be substantially the same as each other.

[0184] Reference Figure 8 , the position and / or connection structure of at least one transistor forming each stage ST may be changed. For example, the stage ST is formed so that the gate electrode of the twelfth transistor M12 may be directly connected to the third node N3 without passing through the third transistor M3. In this case, the twelfth transistor M12 is turned on or off in response to the voltage of the third node N3, and the remaining configurations and operations other than this may be the same as those of the embodiment of the present invention. Figure 4 The exemplary embodiments of the present invention are substantially the same.

[0185] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but is limited to the broader scope of the appended claims and various obvious modifications and equivalent arrangements as will be apparent to those of ordinary skill in the art.

Claims

1. A stage in an emission control driver of a display device, the stage comprising: an input unit that controls voltages of the first node and the second node in response to a first input signal supplied from the first input terminal and a second input signal supplied from the second input terminal; a first controller that controls voltages of a third node and a fourth node in response to a voltage of a third input signal supplied from a third input terminal and the voltage of the second node; a second controller, responsive to the voltage of the first node, controlling the voltage of the fourth node; as well as an output unit that supplies a voltage of a first power source or a second power source to an output terminal in response to the voltage of the third node or the voltage of the fourth node, The first controller includes: a first transistor and a second transistor connected between the first power supply and the third node; and a third transistor connected between the first node and the third node, the third transistor being turned on in response to the voltage of the second power supply, and The second transistor has an electrode directly connected to the third node without passing through the third transistor.

2. The stage according to claim 1, wherein: The first transistor has a gate electrode connected to the second node, and the second transistor has a gate electrode connected to the third input terminal.

3. The stage according to claim 1, wherein: The first controller also includes a first capacitor connected between the third node and the third input terminal.

4. The stage according to claim 1, wherein: The voltage of the first power supply is set to a gate-off voltage, and The voltage of the second power supply is set to a gate-on voltage.

5. The stage according to claim 4, wherein: The output unit comprises: a fourth transistor connected between the first power source and the output terminal, the fourth transistor having a gate electrode connected to the fourth node; and A fifth transistor is connected between the output terminal and the second power supply, and has a gate electrode connected to the third node.

6. The stage according to claim 1, wherein: The first input signal is a start pulse or an output signal of a previous stage, and The second input signal is a first clock signal, and the third input signal is a second clock signal.

7. The stage according to claim 6, wherein: The first clock signal and the second clock signal alternately have a gate-on voltage, and The start pulse or the output signal of the previous stage is supplied to overlap with at least one gate-on voltage period of the first clock signal.

8. The stage according to claim 6, wherein: The input unit comprises: a sixth transistor connected between the first input terminal and the first node, the sixth transistor having a gate electrode connected to the second input terminal; a seventh transistor connected between the second node and the second input terminal, the seventh transistor having a gate electrode connected to the first node; and An eighth transistor is connected between the second node and the second power supply, and has a gate electrode connected to the second input terminal.

9. The stage of claim 1, wherein: The first controller also includes: a ninth transistor connected between the second node and the fifth node, the ninth transistor being turned on in response to the voltage of the second power supply; a second capacitor connected between the fifth node and the sixth node; a tenth transistor connected between the fourth node and the sixth node, the tenth transistor having a gate electrode connected to the third input terminal; and An eleventh transistor is connected between the sixth node and the third input terminal, and has a gate electrode connected to the fifth node.

10. The stage of claim 1, wherein: The second controller comprises: a twelfth transistor connected between the first power source and the fourth node, the twelfth transistor having a gate electrode connected to the first node or the third node; and The third capacitor is connected between the first power source and the fourth node.

11. A display device, comprising: A plurality of pixels connected to a plurality of scan lines, a plurality of data lines and a plurality of emission control lines; A scan driver for supplying scan signals to the plurality of scan lines; a data driver for supplying data signals to the plurality of data lines; as well as an emission control driver having a plurality of stages to supply emission control signals to the plurality of emission control lines, Wherein, each of the plurality of stages includes: an input unit, which controls the voltages of the first node and the second node in response to a first input signal supplied from a first input terminal and a second input signal supplied from a second input terminal; a first controller, which controls the voltages of the third node and the fourth node in response to the voltage of a third input signal supplied from a third input terminal and the voltage of the second node, and includes a first transistor and a second transistor connected between a first power supply and the third node and a third transistor connected between the first node and the third node, the third transistor being turned on in response to the voltage of the second power supply; a second controller, which controls the voltage of the fourth node in response to the voltage of the first node; and an output unit, which supplies the voltage of the first power supply or the voltage of the second power supply to an output terminal in response to the voltage of the third node or the voltage of the fourth node, and The second transistor has an electrode directly connected to the third node without passing through the third transistor.

12. The display device according to claim 11, wherein: The first transistor has a gate electrode connected to the second node, and The second transistor has a gate electrode connected to the third input terminal.

13. The display device according to claim 11, wherein: The first controller also includes a first capacitor connected between the third input terminal and the third node.

14. The display device according to claim 11, wherein: The voltage of the first power supply is set to a gate-off voltage, and The voltage of the second power supply is set to a gate-on voltage.

15. The display device according to claim 14, wherein: The output unit comprises: a fourth transistor connected between the first power source and the output terminal, the fourth transistor having a gate electrode connected to the fourth node; and A fifth transistor is connected between the output terminal and the second power supply, and has a gate electrode connected to the third node.

16. The display device according to claim 11, wherein: The plurality of stages include a first stage receiving a start pulse through the first input terminal and other stages receiving an output signal of a previous stage through the first input terminal.

17. The display device according to claim 11, wherein: The multiple stages include: an odd-numbered stage receiving a first clock signal through the second input terminal and receiving a second clock signal through the third input terminal; and The even-numbered stages receive the second clock signal through the second input terminal and receive the first clock signal through the third input terminal.

18. The display device according to claim 17, wherein: The first clock signal and the second clock signal alternately have a gate-on voltage.

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