Display device

Abstract

The present disclosure relates to a display device, comprising: a pixel coupled to a first scan line, a second scan line, an emission control line and a data line; a first scan driver configured to supply a first scan signal to each of the first scan lines at a first frequency; a second scan driver configured to supply a second scan signal to each of the second scan lines at a second frequency corresponding to the driving frequency of the pixel; an emission driver configured to supply an emission control signal to each of the emission control lines at the first frequency; a data driver configured to supply a data signal to each of the data lines at the second frequency; and a timing controller configured to control the first scan driver, the second scan driver, the emission driver and the data driver.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2019-0069638, filed on Jun. 12, 2019, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Exemplary embodiments of the present disclosure relate to a display device, and more particularly, to a display device that can be applied to various driving frequencies. Background Art

[0004] The display device may serve as an interface between a user and information.

[0005] The display device may include a plurality of pixels. Each pixel may include a plurality of transistors, a light emitting element electrically coupled to the transistor, and a capacitor. The transistor may be turned on in response to a signal provided by a line such as a scan line and an emission control line. When the transistor is activated, a drive current may be generated to cause the light emitting element to emit light.

[0006] In order to reduce power consumption and improve driving efficiency, a method of driving a display device at a low frequency may be adopted. However, the display quality of a display device operated at a low frequency may be degraded. Summary of the invention

[0007] An exemplary embodiment of the present disclosure may provide a display device, which includes: pixels coupled to a first scan line, a second scan line, an emission control line, and a data line; a first scan driver configured to supply a first scan signal to each first scan line at a first frequency; a second scan driver configured to supply a second scan signal to each second scan line at a second frequency corresponding to a driving frequency of the pixel; an emission driver configured to supply an emission control signal to each emission control line at the first frequency; a data driver configured to supply a data signal to each data line at the second frequency; and a timing controller configured to control operations of the first scan driver, the second scan driver, the emission driver, and the data driver.

[0008] In an exemplary embodiment of the present disclosure, the first frequency may be greater than the second frequency.

[0009] In an exemplary embodiment of the present disclosure, the second frequency is equal to the driving frequency, and the second frequency and the driving frequency may correspond to submultiples of the first frequency.

[0010] In an exemplary embodiment of the present disclosure, the first scan driver may supply the first scan signal to each of the first scan lines at a first frequency that is twice a maximum driving frequency of the display device.

[0011] In an exemplary embodiment of the present disclosure, the emission driver may supply the emission control signal to each emission control line at a first frequency that is twice the maximum driving frequency of the display device.

[0012] In an exemplary embodiment of the present disclosure, when the display device is driven at a driving frequency of a pixel, the second scan driver may supply a second scan signal during a first period of a frame period. When the display device is driven at a driving frequency of a pixel, the second scan driver may not supply a second scan signal during a second period of a frame period.

[0013] In an exemplary embodiment of the present disclosure, when the display device is driven at a maximum driving frequency of the display device, the length of the first period may be equal to the length of the second period.

[0014] In an exemplary embodiment of the present disclosure, the first period may include a display scanning period in which the first scanning driver and the second scanning driver supply the first scanning signal and the second scanning signal to write the data signal to the pixel. The second period may include a self-scanning period in which the characteristics of the driving transistor included in each pixel are changed by supplying the first scanning signal from the first scanning driver.

[0015] In an exemplary embodiment of the present disclosure, when the driving frequency of the pixel decreases, the number of self-scanning periods included in the second period may increase.

[0016] In an exemplary embodiment of the present disclosure, each pixel arranged on an i-th (i is a natural number) horizontal line in the pixel may include: a light emitting element including a first electrode and a second electrode coupled to a second power supply; a first transistor including a first electrode coupled to a first node electrically connected to the first power supply and configured to control a driving current based on a voltage at the second node; a second transistor coupled between one of the data lines and the first node and configured to be turned on by a first scan signal supplied to an i-th first scan line in the first scan lines; a third transistor coupled between the second node and a third node coupled to the second electrode of the first transistor , and is configured to be turned on by a second scan signal supplied to an i-th second scan line among the second scan lines; a fourth transistor, coupled between the second node and the first initialization power supply, and is configured to be turned on by a second scan signal supplied to an i-1-th second scan line among the second scan lines; a fifth transistor, coupled between the first power supply and the first node, and is configured to be turned off by an emission control signal supplied to an i-th emission control line among the emission control lines; a sixth transistor, coupled to the third node and the first electrode of the light-emitting element, and is configured to be turned off by the emission control signal; and a storage capacitor, coupled between the first power supply and the second node.

[0017] In an exemplary embodiment of the present disclosure, each pixel disposed on the i-th horizontal line may further include a seventh transistor coupled between the first electrode of the light emitting element and the second initialization power supply, and the seventh transistor may be configured to be turned on by a first scan signal supplied to the i+1-th first scan line among the first scan lines. The voltage of the first initialization power supply may be different from the voltage of the second initialization power supply.

[0018] In an exemplary embodiment of the present disclosure, each pixel arranged on the i-th horizontal line may further include: a seventh transistor, coupled between the first electrode of the light emitting element and the first initialization power supply, and configured to be turned on by a first scan signal supplied to the i+1-th first scan line among the first scan lines; and an eighth transistor, coupled between the first node and the first initialization power supply, and configured to be turned on by a second scan signal supplied to the i-1-th second scan line.

[0019] In an exemplary embodiment of the present disclosure, each pixel arranged on the i-th horizontal line may further include: a seventh transistor, coupled between the first electrode of the light emitting element and the first initialization power supply, and configured to be turned on by a first scan signal supplied to the i+1th first scan line among the first scan lines; and an eighth transistor, coupled between the third node and the first initialization power supply, and configured to be turned on by a second scan signal supplied to the i-1th second scan line.

[0020] In an exemplary embodiment of the present disclosure, the first transistor, the second transistor, the fifth transistor, and the sixth transistor may be P-type transistors, and the third transistor and the fourth transistor may be N-type oxide semiconductor transistors.

[0021] In an exemplary embodiment of the present disclosure, each pixel disposed on the i-th horizontal line may further include a seventh transistor coupled between the first electrode of the light emitting element and the second initialization power supply, and the seventh transistor may be configured to be turned on by the second scan signal supplied to the i-th second scan line. The seventh transistor may be an N-type oxide semiconductor transistor. The voltage of the first initialization power supply may be different from the voltage of the second initialization power supply.

[0022] In an exemplary embodiment of the present disclosure, each pixel disposed on the i-th horizontal line may further include a seventh transistor coupled between the first electrode of the light emitting element and the second initialization power supply, and the seventh transistor may be configured to be turned on by an emission control signal supplied to the i-th emission control line. The seventh transistor may be an N-type oxide semiconductor transistor. The voltage of the first initialization power supply may be different from the voltage of the second initialization power supply.

[0023] In an exemplary embodiment of the present disclosure, each pixel arranged on the i-th (i is a natural number) horizontal line in the pixel may include: a light emitting element including a first electrode and a second electrode coupled to a second power supply; a first transistor including a first electrode coupled to a first node electrically connected to the first power supply and configured to control a driving current based on a voltage of the second node; a second transistor coupled between a data line in the data lines and the first node and configured to be turned on by a first scan signal supplied to the i-th first scan line in the first scan lines; a third transistor coupled between the second node and a third node coupled to the second electrode of the first transistor and configured to be turned on by a second scan signal supplied to the i-th second scan line in the second scan lines; a fourth transistor coupled between the second node and the first initialization power supply and configured to be turned on by a third scan signal supplied to the i-th third scan line; and a fifth transistor coupled between the first power supply and the first node and configured to be turned off by an emission control signal supplied to the i-th emission control line in the emission control lines.

[0024] In an exemplary embodiment of the present disclosure, the display device may further include a third scan driver configured to supply a third scan signal to each third scan line coupled to the pixel at a second frequency. The widths of the second scan signal and the third scan signal may be greater than the width of the first scan signal.

[0025] In an exemplary embodiment of the present disclosure, when the display device is driven at a driving frequency of a pixel, the second scan driver and the third scan driver may supply a second scan signal and a third scan signal, respectively, during a first period of a frame period. When the display device is driven at a driving frequency of a pixel, the second scan driver and the third scan driver may not supply the second scan signal and the third scan signal during a second period of a frame period.

[0026] In an exemplary embodiment of the present disclosure, during the first period, the second scan signal supplied to the i-th second scan line may not overlap with the third scan signal supplied to the i-th third scan line.

[0027] In an exemplary embodiment of the present disclosure, during a first period, a third scan signal supplied to the i-th third scan line may overlap with a first portion of a second scan signal supplied to the i-th second scan line, and a first scan signal supplied to the i-th first scan line may overlap with a second portion of a second scan signal supplied to the i-th second scan line.

[0028] An exemplary embodiment of the present disclosure may provide a display device, which includes: pixels coupled to a first scan line, a second scan line, an emission control line, and a data line; a first scan driver configured to supply a first scan signal to each first scan line at a first frequency; a second scan driver configured to supply a second scan signal to each second scan line at a second frequency, wherein the first frequency is greater than the second frequency; an emission driver configured to supply an emission control signal to each emission control line at the first frequency; a data driver configured to supply a data signal to each data line at the second frequency; and a timing controller configured to control the second scan driver to supply the second scan signal during a first period of a frame period and not to supply the second scan signal during a second period of the frame period. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a block diagram illustrating a display device according to an exemplary embodiment of the present disclosure.

[0030] Figure 2 is a diagram showing an exemplary embodiment of the present disclosure including Figure 1 A circuit diagram of a pixel in a display device.

[0031] Figure 3A is a diagram showing an exemplary embodiment of the present disclosure Figure 2 A timing diagram of the pixel operation.

[0032] Figure 3B is a diagram showing an exemplary embodiment of the present disclosure Figure 2 A timing diagram of the pixel operation.

[0033] Figure 4 FIG. 2 is a diagram showing a driving frequency when a display device is driven at a first driving frequency according to an exemplary embodiment of the present disclosure. Figure 1 A timing diagram of the method of the display device.

[0034] Figure 5 FIG. 2 is a diagram showing a driving frequency when the display device is driven at a second driving frequency according to an exemplary embodiment of the present disclosure. Figure 1 A timing diagram of the method of the display device.

[0035] Fig. 6A is a diagram showing that a driving frequency will be supplied to a Figure 1 A timing diagram of gate start pulses of an emission driver and a scan driver in a display device.

[0036] Figure 6B FIG. 1 is a diagram showing a driving frequency according to an exemplary embodiment of the present disclosure. Figure 1 Schematic diagram of a method for displaying a device.

[0037] Figure 7 is a diagram showing an exemplary embodiment of the present disclosure including Figure 1 A circuit diagram of a pixel in a display device.

[0038] Figure 8 is a diagram showing an exemplary embodiment of the present disclosure including Figure 1 A circuit diagram of a pixel in a display device.

[0039] Fig. 9 is a diagram showing an exemplary embodiment of the present disclosure including Figure 1 A circuit diagram of a pixel in a display device.

[0040] Fig. 10A is a diagram showing an exemplary embodiment of the present disclosure Fig. 9 A timing diagram of the pixel operation.

[0041] Fig. 10B is a diagram showing an exemplary embodiment of the present disclosure Fig. 9 A timing diagram of the pixel operation.

[0042] Fig.11 is a diagram showing an exemplary embodiment of the present disclosure including Figure 1 A circuit diagram of a pixel in a display device.

[0043] Fig.12 is a diagram showing an exemplary embodiment of the present disclosure Fig.11 A timing diagram of the pixel operation.

[0044] Fig.13 is a block diagram illustrating a display device according to an exemplary embodiment of the present disclosure.

[0045] Fig.14 is a diagram showing an exemplary embodiment of the present disclosure including Fig.13 A circuit diagram of a pixel in a display device.

[0046] Fig.15A , Fig. 15B and Fig. 15C is a diagram showing an exemplary embodiment of the present disclosure Fig.14 A timing diagram of the pixel operation.

[0047] Fig.16 is a diagram showing an exemplary embodiment of the present disclosure including Figure 1 A circuit diagram of a pixel in a display device.

[0048] Fig.17A and Fig. 17B is a diagram showing an exemplary embodiment of the present disclosure Fig.16 A timing diagram of the pixel operation.

[0049] Fig.18 is a diagram showing an exemplary embodiment of the present disclosure including Figure 1 A circuit diagram of a pixel in a display device.

[0050] Fig.19A and Fig.19B is a diagram showing an exemplary embodiment of the present disclosure Fig.18 A timing diagram of the pixel operation. DETAILED DESCRIPTION

[0051] Exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals used throughout the drawings may indicate the same components, and thus, repeated description of the same components may be omitted.

[0052] Figure 1 is a block diagram illustrating a display device 1000 according to an exemplary embodiment of the present disclosure.

[0053] refer to Figure 1 , the display device 1000 may include a pixel unit 100 , a first scan driver 200 , a second scan driver 300 , an emission driver 400 , a data driver 500 , and a timing controller 600 .

[0054] The display device 1000 may display an image using various driving frequencies according to driving conditions. In an exemplary embodiment of the present disclosure, the display device 1000 may adjust the output frequency of the second scan driver 300 and the output frequency of the data driver 500 corresponding to the output frequency of the first scan driver 200 and the second scan driver 300 according to the driving conditions. For example, the display device 1000 may display an image in response to various driving frequencies ranging from 1 Hz to 120 Hz.

[0055] The timing controller 600 may be supplied with input image data IRGB and timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a clock signal CLK from a host system such as an application processor (AP) through an interface.

[0056] The timing controller 600 may generate a data drive control signal DCS based on the input image data IRGB and timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a clock signal CLK. The data drive control signal DCS may be supplied to the data driver 500. The timing controller 600 may rearrange the input image data IRGB and supply the rearranged input image data IRGB to the data driver 500.

[0057] The timing controller 600 may supply the gate start pulses GSP1 and GSP2 and the clock signal CLK to the first and second scan drivers 200 and 300 based on the timing signal.

[0058] The timing controller 600 may supply the emission start pulse ESP and the clock signal CLK to the emission driver 400 based on the timing signal. The emission start pulse ESP may control the first timing of the emission control signal. The clock signal CLK provided to the emission driver 400 may be used to shift the emission start pulse ESP.

[0059] The first gate start pulse GSP1 may control a first timing of a scan signal to be supplied from the first scan driver 200. The clock signal CLK supplied to the first scan driver 200 may be used to shift the first gate start pulse GSP1.

[0060] The second gate start pulse GSP2 may control a first timing of a scan signal to be supplied from the second scan driver 300. The clock signal CLK supplied to the second scan driver 300 may be used to shift the second gate start pulse GSP2.

[0061] The data driver 500 may supply the data signal to the data line D in response to the data driving control signal DCS. The data signal supplied to the data line D may be supplied to the pixel PXL selected by the scan signal.

[0062] The data driver 500 may supply the data signal to the data line D during the frame period in response to the driving frequency. For example, when the display device 1000 is driven at the first driving frequency, the data driver 500 may supply the data signal to the data line D during the frame period. In this case, the data signal to be supplied to the data line D may be synchronized with the scan signal to be supplied to the first scan line S1 and the second scan line S2.

[0063] The data driver 500 may supply a data signal to the data line D during a first period in which a scan signal is supplied to the second scan line S2 during a single frame period, and may supply an arbitrary reference voltage to the data line D during a second period instead of the first period. For example, the reference voltage may be set to a specific voltage within the voltage range of the data signal. For example, the reference voltage may be set to a data voltage having a black grayscale. In addition, as a horizontal period elapses or a frame period elapses, the reference voltage may vary within the voltage range of the data signal.

[0064] In addition, the first period may be a period in which the scan signal is supplied to all of the first scan lines S1 and the second scan lines S2. The second period may be a period in which the scan signal is supplied to the first scan lines S1 but not to the second scan lines S2.

[0065] The first scan driver 200 may supply a scan signal to the first scan line S1 in response to the first gate start pulse GSP1. For example, the first scan driver 200 may sequentially supply the scan signal to the first scan line S1. In this case, the scan signal supplied from the first scan driver 200 may be set to a gate-on voltage so that a transistor included in the pixel PXL may be turned on.

[0066] The first scan driver 200 may supply a scan signal to the first scan line S1 at a constant first frequency regardless of a driving frequency (or frame frequency) of an image frame of the display device 1000. In this case, the first frequency may correspond to an output frequency of a first gate start pulse GSP1 to be supplied from the timing controller 600 to the first scan driver 200.

[0067] In addition, the first frequency at which the first scan driver 200 supplies the scan signal may be greater than the driving frequency. In an exemplary embodiment of the present disclosure, the driving frequency may be set to a divisor of the first frequency. For example, the first frequency may be set to approximately twice the maximum driving frequency of the display device 1000. In the case where the maximum driving frequency of the display device 1000 is approximately 120 Hz, the first frequency may be set to 240 Hz. Therefore, in each frame period, a plurality of scan operations of sequentially outputting scan signals to the first scan lines S1 may be repeated in a predetermined cycle. In other words, in each frame period, the scan signals to be supplied to each of the first scan lines S1 may be repeatedly supplied in each predetermined cycle.

[0068] For example, under all driving frequency conditions that can drive the display device 1000, the first scan driver 200 may perform a scan operation once during the first cycle, and perform at least one scan operation according to the driving frequency during the second cycle. In other words, during the first cycle, the scan signal is sequentially output to each first scan line S1 once. During the second cycle, the scan signal may be sequentially output to each first scan line S1 at least once. In other words, during the second cycle, the scan signal is sequentially output to each first scan line S1 twice or more.

[0069] In addition, if the driving frequency is reduced, the number of times the first scan driver 200 repeatedly performs supplying the scan signal to each of the first scan lines S1 during each frame period may increase.

[0070] The second scan driver 300 may supply a scan signal to the second scan line S2 in response to the second gate start pulse GSP2. For example, the second scan driver 300 may sequentially supply a scan signal to the second scan line S2. In this case, the scan signal supplied from the second scan driver 300 may be set to a gate-on voltage so that a transistor included in the pixel PXL may be turned on.

[0071] The second scan driver 300 may supply a scan signal to the second scan line S2 at a frequency (e.g., a second frequency) equal to a driving frequency corresponding to an image frame (or a frame frequency) of the display device 1000. In an exemplary embodiment of the present disclosure, the second frequency may correspond to an output frequency of a second gate start pulse GSP2 to be supplied from the timing controller 600 to the second scan driver 300.

[0072] The second frequency substantially the same as the driving frequency may be set to a submultiple of the first frequency.

[0073] The second scan driver 300 may supply a scan signal to the second scan line S2 during a first period of each frame. For example, the second scan driver 300 may supply at least one scan signal to each second scan line S2 during the first period. In this case, the scan signal to be supplied to the i-th first scan line S1i during the first period may overlap with the scan signal to be supplied to the i-th second scan line S2i.

[0074] The emission driver 400 may supply an emission control signal to the emission control line E in response to the emission start pulse ESP. For example, the emission driver 400 may sequentially supply the emission control signal to the emission control line E. If the emission control signal is sequentially supplied to the emission control line E, the pixel PXL may not emit on a horizontal line basis. In other words, the pixel PXL may not emit light. For this operation, the emission control signal may be set to a gate-off voltage so that the transistor included in the pixel PXL may be turned off. In an exemplary embodiment of the present disclosure, the emission driver 400 may supply the emission control signal to the i-th emission control line Ei so that the emission control signal overlaps with the scan signal supplied to the i-1th first scan line S1i-1 (and / or the i-1th second scan line S2i-1), the i-th first scan line S1i (and / or the i-th second scan line S2i), and the i+1th first scan line S1i+1 (and / or the i+1th second scan line S2i+1).

[0075] In an exemplary embodiment of the present disclosure, the emission driver 400 may supply the emission control signal to the emission control line E at the first frequency in the same manner as the first scan driver 200. Therefore, in each frame period, the emission control signal to be supplied to each emission control line E may be repeatedly supplied in each cycle period.

[0076] When the driving frequency decreases, the number of times the emission driver 400 repeatedly performs the operation of supplying the emission control signal to each emission control line E during each frame period may increase.

[0077] The pixel unit 100 may include a pixel PXL coupled to a data line D, first and second scan lines S1 and S2, and an emission control line E. Voltages of a first power source VDD, a second power source VSS, and an initialization power source Vint may be supplied to the pixel PXL from an external device.

[0078] When a scan signal is supplied to the first scan line S1 and the second scan line S2 coupled to the pixel PXL, and when a data signal is supplied to the data line D connected to the pixel PXL, each pixel PXL can be selected. In response to this, the pixel PXL supplied with the data signal can control the amount of current flowing from the first power supply VDD to the second power supply VSS via the light-emitting element. The light-emitting element can generate light with brightness in response to the amount of current. The light generated by the light-emitting element can be predetermined. The time when each pixel PXL emits light can be controlled by an emission control signal supplied from an emission control line E coupled to the pixel PXL.

[0079] In addition, depending on the structure of the pixel circuit, the pixel PXL may be coupled to one or more first scan lines S1, one or more second scan lines S2, and one or more emission control lines E. In other words, in an exemplary embodiment of the present disclosure, signal lines such as the first scan line S1 and the second scan line S2, the emission control line E, and the data line D to be coupled to the pixel PXL may be differently arranged depending on the circuit structure of the pixel PXL.

[0080] Figure 2 is a diagram showing a method of including a Figure 1 1000 is a circuit diagram of a pixel PXL in a display device 1000.

[0081] exist Figure 2 , for the purpose of description, the pixel PXL arranged on the i-th horizontal line and coupled to the m-th data line Dm is illustrated.

[0082] refer to Figure 2The pixel PXL may include a light emitting element LD, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7, and a storage capacitor Cst.

[0083] The light emitting element LD may include a first electrode (anode electrode or cathode electrode) coupled to the fourth node N4 and a second electrode (the other of the cathode electrode and the anode electrode) coupled to the second power supply VSS. The light emitting element LD may emit light having a predetermined brightness corresponding to the current supplied from the first transistor M1.

[0084] In an exemplary embodiment of the present disclosure, the light emitting element LD may be an organic light emitting diode including an organic light emitting layer. In an exemplary embodiment of the present disclosure, the light emitting element LD may be an inorganic light emitting element formed of an inorganic material. The light emitting element LD may have a shape in which a plurality of inorganic light emitting elements are coupled in parallel and / or in series between the second power supply VSS and the fourth node N4.

[0085] The first transistor (or driving transistor) M1 may include a first electrode coupled to the first node N1 and a second electrode coupled to the third node N3. The gate electrode of the first transistor M1 is coupled to the second node N2. The first transistor M1 may control the amount of current flowing from the first power supply VDD to the second power supply VSS via the light emitting element LD in response to the voltage of the second node N2. To achieve this, the first power supply VDD may be set to a voltage higher than the second power supply VSS.

[0086] The second transistor M2 may be coupled between the data line Dm and the first node N1. A gate electrode of the second transistor M2 may be coupled to the i-th first scan line S1i. When a scan signal is supplied to the i-th first scan line S1i, the second transistor M2 may be turned on to electrically couple the data line Dm to the first node N1.

[0087] The third transistor M3 may be coupled between the second electrode (e.g., the third node N3) of the first transistor M1 and the second node N2. The gate electrode of the third transistor M3 may be coupled to the i-th second scan line S2i. When the scan signal is supplied to the i-th second scan line S2i, the third transistor M3 may be turned on to electrically connect the second electrode of the first transistor M1 to the second node N2. Therefore, if the third transistor M3 is turned on, the first transistor M1 may be connected in the form of a diode.

[0088] The fourth transistor M4 is coupled between the second node N2 and the first initialization power source Vint1. The gate electrode of the fourth transistor M4 is coupled to the i-1th second scan line S2i-1. When the scan signal is supplied to the i-1th second scan line S2i-1, the fourth transistor M4 is turned on so that the voltage of the first initialization power source Vint1 can be supplied to the second node N2. The voltage of the first initialization power source Vint1 is set to be lower than the voltage of the data signal to be supplied to the data line Dm.

[0089] Therefore, when the fourth transistor M4 is turned on, the gate voltage of the first transistor M1 may be initialized to the voltage of the first initialization power supply Vint1, and the first transistor M1 may have an on bias state (eg, the first transistor M1 may be initialized to an on bias state).

[0090] The fifth transistor M5 is coupled between the first power supply VDD and the first node N1. A gate electrode of the fifth transistor M5 may be coupled to the i-th emission control line Ei. The fifth transistor M5 may be turned off when the emission control signal is supplied to the i-th emission control line Ei, and may be turned on in other cases.

[0091] The sixth transistor M6 may be coupled between the second electrode (e.g., the third node N3) of the first transistor M1 and the first electrode (e.g., the fourth node N4) of the light emitting element LD. The gate electrode of the sixth transistor M6 may be coupled to the i-th emission control line Ei. The sixth transistor M6 may be turned off when the emission control signal is supplied to the i-th emission control line Ei, and may be turned on in other cases.

[0092] The seventh transistor M7 may be coupled between the first electrode (e.g., the fourth node N4) of the light emitting element LD and the second initialization power source Vint2. The gate electrode of the seventh transistor M7 may be coupled to the i+1th first scan line S1i+1. When the scan signal is supplied to the i+1th first scan line S1i+1, the seventh transistor M7 is turned on so that the voltage of the second initialization power source Vint2 may be supplied to the first electrode of the light emitting element LD.

[0093] However, this configuration is for illustration purposes only, and the gate electrode of the seventh transistor M7 may be coupled to the (i-1)th first scan line S1i-1 or the i-th first scan line S1i.

[0094] If the voltage of the second initialization power supply Vint2 is supplied to the first electrode of the light emitting element LD, the parasitic capacitor of the light emitting element LD can be discharged. As the residual voltage charged in the parasitic capacitor is discharged (e.g., removed), undesired fine emission can be prevented. Therefore, the black performance of the pixel PXL can be enhanced.

[0095] The first initialization power source Vint1 and the second initialization power source Vint2 may generate different voltages. In other words, the voltage for initializing the second node N2 (eg, the first initialization power source Vint1) and the voltage for initializing the fourth node N4 (eg, the second initialization power source Vint2) may be set to different values.

[0096] In the low-frequency driving mode with a relatively long frame period, if the voltage of the first initialization power supply Vint1 supplied to the second node N2 is too low, the hysteresis of the first transistor M1 may vary excessively during the frame period. Such hysteresis may cause a flickering phenomenon in the low-frequency driving mode. Therefore, in the low-frequency driving mode of the display device 1000, the voltage of the first initialization power supply Vint1 may be higher than the voltage of the second power supply VSS.

[0097] However, if the voltage of the second initialization power Vint2 supplied to the fourth node N4 is higher than a predetermined reference value, the voltage of the parasitic capacitor of the light emitting element LD may be charged instead of discharged. Therefore, the voltage of the second initialization power Vint2 will be lower than the voltage of the second power supply VSS.

[0098] In various exemplary embodiments of the present disclosure, the pixel PXL included in the display device 1000 may be coupled to the first initialization power source Vint1 and the second initialization power source Vint2 providing different voltages. Therefore, since the voltage for initializing the first transistor M1 and the voltage for initializing the light emitting element LD are independently determined, a flicker phenomenon or an emission error may be prevented or mitigated.

[0099] The storage capacitor Cst may be coupled between the first power source VDD and the second node N2. The storage capacitor Cst may store a voltage applied to the second node N2.

[0100] The first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 can all be formed by polycrystalline silicon semiconductor transistors. For example, the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 can all include a polycrystalline silicon semiconductor layer formed by low temperature polycrystalline silicon (LTPS) treatment as an active layer (e.g., a channel). In addition, the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 can all be P-type transistors. Therefore, the gate-on voltage for turning on the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6 or the seventh transistor M7 can have a logic low level.

[0101] Since the polycrystalline silicon semiconductor transistor has a high response speed, the polycrystalline silicon semiconductor transistor can be applied to a switching element in which a high-speed switching operation is employed.

[0102] The third transistor M3 and the fourth transistor M4 may be formed of oxide semiconductor transistors. For example, the third transistor M3 and the fourth transistor M4 may be N-type oxide semiconductor transistors and include an oxide semiconductor layer as an active layer. Therefore, the gate-on voltage for turning on the third transistor M3 or the fourth transistor M4 may have a logic high level.

[0103] The oxide semiconductor transistor may be produced by a low temperature process and has a low charge mobility compared to that of a polysilicon semiconductor transistor. In other words, the oxide semiconductor transistor may have an excellent cut-off current characteristic. Therefore, if each of the third transistor M3 and the fourth transistor M4 is formed by an oxide semiconductor transistor, the leakage current from the second node N2 may be minimized. Therefore, the display quality of the display device 1000 may be improved.

[0104] Figure 3A is a diagram showing an exemplary embodiment of the present disclosure Figure 2 A timing diagram of the operation of the pixel PXL.

[0105] refer to Figure 2 and Figure 3A , a signal for displaying an image may be supplied to the pixel PXL during the first period. The first period may include a period in which a data signal DS substantially corresponding to an output image is input.

[0106] The gate-on voltage of the scan signal to be supplied to each of the second scan lines S2i and S2i-1 may have a logic high level, and the second scan lines S2i and S2i-1 are coupled to the third transistor M3 and the fourth transistor M4, both of which are N-type transistors. The gate-on voltage of the scan signal to be supplied to each of the first scan lines S1i and S1i+1 may have a logic low level, and the first scan lines S1i and S1i+1 are coupled to the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7, all of which are P-type transistors.

[0107] The emission control signal is supplied to the i-th emission control line Ei. If the emission control signal is supplied to the i-th emission control line Ei, the fifth transistor M5 and the sixth transistor M6 may be turned off. If the fifth transistor M5 and the sixth transistor M6 are turned off, the pixel PXL may be set to a non-emission state. In other words, the pixel PXL may not emit light when the fifth transistor M5 and the sixth transistor M6 are turned off.

[0108] Thereafter, the scan signal is supplied to the i-1th second scan line S2i-1. When the scan signal is supplied to the i-1th second scan line S2i-1, the fourth transistor M4 may be turned on. When the fourth transistor M4 is turned on, the voltage of the first initialization power source Vint1 is supplied to the second node N2.

[0109] Thereafter, the scan signal is supplied to the i-th first scan line S1i and the i-th second scan line S2i. When the scan signal is supplied to the i-th second scan line S2i, the third transistor M3 may be turned on. When the third transistor M3 is turned on, the first transistor M1 may be connected in a diode form, and the threshold voltage of the first transistor M1 may be compensated.

[0110] When the scan signal is supplied to the i-th first scan line S1i, the second transistor M2 may be turned on. When the second transistor M2 is turned on, the data signal DS may be supplied from the data line Dm to the first node N1. In this case, since the second node N2 has been initialized to a voltage lower than the first initialization power supply Vint1 of the data signal DS (e.g., the second node N2 has been initialized to a conduction bias state), the first transistor M1 may be turned on.

[0111] When the first transistor M1 is turned on, the data signal DS supplied to the first node N1 may be supplied to the second node N2 via the first transistor M1 connected in the form of a diode. Thereafter, a voltage corresponding to the data signal DS and a threshold voltage of the first transistor M1 may be applied to the second node N2. In this case, the storage capacitor Cst may store a voltage corresponding to the second node N2.

[0112] Thereafter, the scan signal is supplied to the i+1th first scan line S1i+1. When the scan signal is supplied to the i+1th first scan line S1i+1, the seventh transistor M7 may be turned on. When the seventh transistor M7 is turned on, the voltage of the second initialization power supply Vint2 may be supplied to the first electrode (e.g., the fourth node N4) of the light emitting element LD. Therefore, the residual voltage remaining in the parasitic capacitor of the light emitting element LD may be discharged.

[0113] Thereafter, the supply of the emission control signal to the i-th emission control line Ei may be suspended. The emission control signal may drop from a high level to a low level when it is suspended. When the supply of the emission control signal to the i-th emission control line Ei is suspended, the fifth transistor M5 and the sixth transistor M6 are turned on. In this case, the first transistor M1 may control the drive current flowing to the light emitting element LD in response to the voltage of the second node N2. The light emitting element LD may generate light having a brightness corresponding to the amount of current (e.g., the drive current).

[0114] Although for the sake of description Figure 3A The scanning signal is shown to be supplied to each of the first scanning line S1 and the second scanning line S2 during the first period, but the present disclosure is not limited thereto. For example, a plurality of scanning signals may be supplied to each of the first scanning line S1 and the second scanning line S2. In this case, the operation process is similar to Figure 3A The operation processes of are substantially the same, and thus, a detailed description thereof will be omitted. In the following description, it is assumed that a scan signal is supplied to each of the first scan line S1 and the second scan line S2.

[0115] The above-described operation in the first period may be implemented by the scan signal supplied to the second scan lines S2 i - 1 and S2 i , and may be synchronized with the frequency of the second scan driver 300 .

[0116] Figure 3B is a diagram showing an exemplary embodiment of the present disclosure Figure 2 A timing diagram of the operation of the pixel PXL.

[0117] refer to Figure 2 and Figure 3B In order to maintain the brightness of the image output during the first period, the pixel PXL may apply a predetermined reference voltage Vref to the first electrode (eg, the source electrode) of the first transistor M1 during the second period.

[0118] Figure 3B The timing diagram shows the cycle of operation during the second period.

[0119] For the sake of description, Figure 3B The driving period of the first transistor M1 is a self-scanning period for changing the characteristics of the first transistor M1. The second period may include at least one self-scanning period according to the driving frequency.

[0120] In an exemplary embodiment of the present disclosure, during the second period, the scan signal is neither supplied to the third transistor M3 nor to the fourth transistor M4. For example, during the second period, the scan signal to be supplied to the i-th second scan line S2i and the i+1-th second scan line S2i+1 may have a logic low level L.

[0121] Since the third transistor M3 and the fourth transistor M4 remain turned off, the gate voltage of the first transistor M1 (eg, the second node N2 ) may not be affected by the operation performed during the second period.

[0122] First, if Figure 3BAs shown in , the emission control signal is supplied to the i-th emission control line Ei. Here, the emission control signal changes from low to high. If the emission control signal is supplied to the i-th emission control line Ei, the fifth transistor M5 and the sixth transistor M6 are turned off. If the fifth transistor M5 and the sixth transistor M6 are turned off, the pixel PXL is set to a non-emission state.

[0123] Thereafter, the scan signal is supplied to the i-th first scan line S1i, and the second transistor M2 may be turned on. It can be seen that the second transistor M2 is turned on when the scan signal supplied to the i-th first scan line S1i becomes low. When the second transistor M2 is turned on, the reference voltage Vref is supplied to the first node N1 from the data line Dm. In this case, the reference voltage Vref may be set to a specific voltage within the voltage range of the data signal DS. Therefore, the voltage of the first node N1 changes from the voltage of the first power supply VDD to another voltage, and the characteristic curve of the first transistor M1 may be changed. Therefore, after the first period in which the data signal DS is supplied elapses, the brightness variation caused by the hysteresis of the first transistor M1 may be mitigated.

[0124] When the first frequency for driving the first scan line S1 and the emission control line E is set to 240 Hz and the driving frequency for displaying an actual image (for example, the frequency for driving the second scan line S2) is set to 80 Hz or lower, if the characteristics of the first transistor M1 are fixed to a specific state during each frame period, a flickering phenomenon may occur due to a hysteresis characteristic.

[0125] On the other hand, according to the present disclosure, if the reference voltage Vref is supplied to the first electrode (e.g., source electrode) of the first transistor M1 during the second period, the first transistor M1 enters a conduction bias state, and the characteristics of the first transistor M1 can be changed. Therefore, it is possible to prevent the characteristics of the first transistor M1 from being fixed in a specific state and thus deteriorating. In particular, in the case where the second period increases with a decrease in the driving frequency, the reference voltage Vref can be periodically supplied to the first electrode of the first transistor M1 by the first scan driver 200.

[0126] Thereafter, the scan signal is supplied to the i+1th first scan line S1i+1. When the scan signal is supplied to the i+1th first scan line S1i+1 at a low level, the seventh transistor M7 may be turned on. When the seventh transistor M7 is turned on, the voltage of the second initialization power supply Vint2 may be supplied to the first electrode (e.g., the fourth node N4) of the light emitting element LD. Thus, the residual voltage remaining in the parasitic capacitor of the light emitting element LD may be discharged.

[0127] Thereafter, the supply of the emission control signal to the i-th emission control line Ei may be suspended. If the supply of the emission control signal to the i-th emission control line Ei is suspended, the fifth transistor M5 and the sixth transistor M6 are turned on. In this case, the first transistor M1 may control the driving current flowing to the light emitting element LD in response to the voltage of the second node N2. The light emitting element LD may generate light having a brightness corresponding to the amount of the driving current.

[0128] The above-described operation in the second period may be implemented by the scan signals supplied to the first scan lines S1 i and S1 i+1, and may be synchronized with the frequency of the first scan driver 200 .

[0129] Figure 4 FIG. 2 is a diagram showing a driving frequency when the display device 1000 is driven at a first driving frequency according to an exemplary embodiment of the present disclosure. Figure 1 A timing diagram of the method of the display device 1000 is shown.

[0130] Here, the first driving frequency may be a maximum driving frequency that can be implemented by the display device 1000. For example, the first driving frequency may be set to a high frequency of 120 Hz or higher. The first driving frequency may be related to a cycle period in which the data signal DS is supplied to the data line D. Each frame period 1F may correspond to a supply cycle period of the data signal DS and the first driving frequency.

[0131] refer to Figure 1 and Figure 4 , when the display device 1000 is driven at the first driving frequency, each frame period 1F may include a first period P1 and a second period P2.

[0132] In an exemplary embodiment of the present disclosure, when the display device 1000 is driven at the first driving frequency, the length of the first period P1 may be substantially the same as the length of the second period P2.

[0133] In an exemplary embodiment of the present disclosure, the first scan driver 200 may sequentially supply scan signals to the first scan lines S11 to S1n at a first frequency. The emission driver 400 may sequentially supply emission control signals to the emission control lines E1 to En at a first frequency. In this case, the first frequency may be approximately twice the first driving frequency.

[0134] In an exemplary embodiment of the present disclosure, the second scan driver 300 may sequentially supply the scan signals to the second scan lines S21 to S2n at a second frequency equal to the first driving frequency.

[0135] During the first period P1, the scan signal is sequentially supplied to the first scan lines S11 to S1n and the second scan lines S21 to S2n. In this case, the scan signal supplied to the i-th first scan line S1i may overlap with the scan signal supplied to the i-th second scan line S2i. For example, the scan signal applied to the first scan line S11 may overlap with the scan signal applied to the second scan line S21.

[0136] In addition, during the first period P1, the emission control signal is sequentially supplied to the emission control lines E1 to En. In this case, the emission control signal supplied to the i-th emission control line Ei may overlap with the scan signal supplied to the i-1th first scan line S1i-1, the i-th first scan line S1i, and the i+1th first scan line S1i+1. The data signal DS is supplied to the data line D in synchronization with the scan signal. Therefore, during the first period P1, a voltage corresponding to the data signal DS is stored in each pixel PXL, and the pixel PXL may emit light based on the stored voltage.

[0137] During the second period P2, scan signals are supplied to the first scan lines S11 to S1n, respectively. In addition, during the second period P2, scan signals are not supplied to the second scan lines S21 to S2n. In addition, during the second period P2, emission control signals are supplied to the emission control lines E1 to En, respectively. In this case, the emission control signal supplied to the i-th emission control line Ei may overlap with the scan signals supplied to the i-1th first scan line S1i-1, the i-th first scan line S1i, and the i+1th first scan line S1i+1.

[0138] During the second period P2, the reference voltage Vref may be supplied to each data line D. In other words, the data signal DS is supplied to the data line D only during the first period P1, and thus power consumption may be reduced.

[0139] As reference Figure 3A As described, during the first period P1 , a voltage corresponding to the data signal DS is stored in each pixel PXL, and the pixel PXL may emit light based on the stored voltage.

[0140] As reference Figure 3B As described, during the second period P2, a predetermined on bias may be applied to the first transistor M1 by the scan signal supplied to each of the first scan lines S11 to S1n. Therefore, the hysteresis of the first transistor M1 in the first frame period 1F may be improved.

[0141] Since the first frequency as the output frequency of the first scan driver 200 and the emission driver 400 is set to a value greater than the driving frequency of the display device 1000, it is possible to support outputting images having various driving frequencies. For example, the driving frequency of the display device 1000 may correspond to a submultiple of the first frequency.

[0142] Figure 5 FIG. 2 is a diagram showing a driving frequency when the display device 1000 is driven at the second driving frequency according to an exemplary embodiment of the present disclosure. Figure 1 A timing diagram of the method of the display device 1000 is shown.

[0143] refer to Figure 1 , Figure 4 and Figure 5 , when the display device 1000 is driven at the second driving frequency, each frame period 1F may include a first period P1 and a second period P2'.

[0144] Figure 5 The first cycle P1 operates with reference to Figure 4 The operations in the described first period P1 are substantially the same; therefore, repeated description thereof will be omitted.

[0145] exist Figure 5 In the embodiment of the present disclosure, the first frequency may be set to approximately 240 Hz, and the second driving frequency may be set to a frequency less than 100 Hz. In addition, the second period P2' may be longer than the first period P1. In an exemplary embodiment of the present disclosure, the length of the second period P2' may correspond to an integer multiple of the length of the first period P1. For example, Figure 5 An example is shown where the second drive frequency is approximately 80 Hz.

[0146] In an exemplary embodiment of the present disclosure, the first scan driver 200 and the emission driver 400 may respectively drive the first scan lines S11 to S1n and the emission control lines E1 to En at a first frequency regardless of the driving frequency of the display device 1000. In this case, the first frequency may be kept constant. The second scan driver 300 may drive the second scan lines S21 to S2n at a second frequency substantially equal to the second driving frequency.

[0147] During the second period P2', a plurality of scan signals are supplied to each of the first scan lines S11 to S1n. In this case, the scan signal to be supplied to each of the first scan lines S11 to S1n may be supplied at a predetermined cycle period. For example, during the second period P2', the scan signal may be sequentially and repeatedly supplied to the first scan lines S11 to S1n a plurality of times. Figure 5In the embodiment, the scan signal is supplied twice to the first scan lines S11 to S1n, but the present disclosure is not limited thereto. For example, the scan signal may be supplied more than twice to the first scan lines S11 to S1n.

[0148] In addition, during the second period P2', a plurality of emission control signals are supplied to each of the emission control lines E1 to En. The emission control signals may be supplied at substantially the same cycle as the scan signals supplied to the first scan lines S11 to S1n. During the second period P2', a reference voltage Vref may be supplied to each data line D.

[0149] Therefore, during the second period P2', the on bias may be periodically (eg, at the first frequency) applied to the first transistor M1 of each pixel PXL. Therefore, the hysteresis of the first transistor M1 in the frame period 1F may be improved in response to various driving frequencies.

[0150] Fig. 6A is a diagram showing a driving frequency to be supplied to the Figure 1 1. A timing diagram of gate start pulses GSP1 and GSP2 of the emission driver 400 and the scan drivers 200 and 300 in the display device 1000. Figure 6B FIG. 1 is a diagram showing a driving frequency according to an exemplary embodiment of the present disclosure. Figure 1 1000 is a diagram of a method for displaying a display device 1000.

[0151] refer to Figure 1 , Figure 2 , Figure 4 , Figure 5 , Fig. 6A and Figure 6B , the output frequency of the second gate start pulse GSP2 may vary according to the driving frequency.

[0152] In an exemplary embodiment of the present disclosure, pulse widths of the first and second gate start pulses GSP1 and GSP2 may be substantially the same as each other. A pulse width of the emission start pulse ESP may be greater than that of the first and second gate start pulses GSP1 and GSP2.

[0153] In an exemplary embodiment of the present disclosure, the timing controller 600 may output the emission start pulse ESP and the first gate start pulse GSP1 at a constant frequency (e.g., a first frequency) regardless of the driving frequency. For example, the output frequency of the emission start pulse ESP and the first gate start pulse GSP1 may be set to twice the maximum driving frequency of the display device 1000.

[0154] The timing controller 600 may output the second gate start pulse GSP2 at the same frequency (eg, the second frequency) as the driving frequency. Each frame period of the display device 1000 may be determined by an output cycle period of the second gate start pulse GSP2.

[0155] In an exemplary embodiment of the present disclosure, Fig. 6A and Figure 6B The first period P1 may be a display scanning period T1, in which all emission start pulses ESP, first gate start pulses GSP1 and second gate start pulses GSP2 are output. For example, during the display scanning period T1, each pixel PXL may perform Figure 3A During the display scanning period T1, each pixel PXL may store a data signal DS corresponding to an image to be displayed.

[0156] In an exemplary embodiment of the present disclosure, Fig. 6A and Figure 6B The second period P2 or P2' may include at least one self-scanning period T2, in which the emission start pulse ESP and the first gate start pulse GSP1 are output. For example, during the self-scanning period T2, each pixel PXL may perform Figure 3B During the self-scan period T2, a predetermined reference voltage Vref may be applied to the first electrode of the first transistor M1 of each pixel PXL.

[0157] In an exemplary embodiment of the present disclosure, the length of the display scanning period T1 is substantially the same as the length of the self scanning period T2. However, the number of self scanning periods T2 included in the second period P2 or P2' of each frame period 1F may depend on the driving frequency.

[0158] like Fig. 6A and Figure 6B As shown in , in the case where the display device 1000 is driven at the first driving frequency of 120 Hz, the number of the second gate start pulses GSP2 to be supplied during each frame period 1F may be half the number of the first gate start pulses GSP1. Therefore, in the case where the display device 1000 is driven at the first driving frequency, each frame period 1F may include one display scanning period T1 and one self-scanning period T2.

[0159] The emission start pulse ESP may be supplied at the same frequency as the first gate start pulse GSP1. When the display device 1000 is driven at the first driving frequency of 120 Hz, each pixel PXL may alternately repeat emission (eg, display scanning) and non-emission (eg, self-scanning) twice during each frame period 1F.

[0160] In the case where the display device 1000 is driven at the second driving frequency of 80 Hz, the number of the second gate start pulses GSP2 to be supplied during each frame period 1F may be 1 / 3 of the number of the first gate start pulses GSP1. Therefore, in the case where the display device 1000 is driven at the second driving frequency, each frame period 1F may include one display scanning period T1 and two self-scanning periods T2. Here, each pixel PXL may alternately repeat emission and non-emission three times during each frame period 1F.

[0161] In the case where the display device 1000 is driven at the third driving frequency of 48 Hz, the number of the second gate start pulses GSP2 to be supplied during each frame period 1F may be 1 / 5 of the number of the first gate start pulses GSP1. Therefore, in the case where the display device 1000 is driven at the third driving frequency, each frame period 1F may include one display scanning period T1 and four self-scanning periods T2. Therefore, during the second period P2, the scanning signal may be supplied four times to each of the first scanning lines S11 to S1n. Here, each pixel PXL may alternately repeat emission and non-emission four times during each frame period 1F.

[0162] In a similar manner to the above, the display device 1000 can be driven at a driving frequency of 60 Hz, 30 Hz, 24 Hz, etc. by adjusting the number of self-scanning periods T2 included in the second period P2 or P2'. In other words, the display device 1000 can support various image frames at frequencies corresponding to submultiples of the first frequency.

[0163] In addition, since the driving frequency is reduced, the number of self-scanning periods T2 increases. Thus, a predetermined on-bias voltage may be periodically applied to the first transistor M1. Therefore, brightness reduction and high flicker visibility may not occur or may be mitigated in the low-frequency driving mode.

[0164] Figure 7 is a diagram showing an exemplary embodiment of the present disclosure including Figure 1 1000 is a circuit diagram of a pixel PXL in a display device 1000.

[0165] In the following Figure 7 In the description of Figure 2 The components are the same or similar components, and thus, repeated description thereof can be omitted.

[0166] refer to Figure 7 , the pixel PXL may include a light emitting element LD, first to seventh transistors M1 to M7, and a storage capacitor Cst. In an exemplary embodiment of the present disclosure, the pixel PXL may further include an eighth transistor M8.

[0167] The light emitting element LD may emit light having predetermined brightness corresponding to the current supplied from the first transistor M1.

[0168] In an exemplary embodiment of the present disclosure, according to Figure 3A and Figure 3B The driving method can be applied to Figure 7 Pixel PXL.

[0169] In an exemplary embodiment of the present disclosure, the fourth transistor M4 and the seventh transistor M7 may be coupled to the same initialization power source Vint.

[0170] In an exemplary embodiment of the present disclosure, the eighth transistor T8 may be coupled between the first node N1 and the initialization power supply Vint. The gate electrode of the eighth transistor M8 is coupled to the i-1th second scan line S2i-1. In other words, the gate electrode of the fourth transistor M4 and the gate electrode of the eighth transistor M8 are commonly coupled to the i-1th second scan line S2i-1.

[0171] When the scan signal is supplied to the (i-1)th second scan line S2i-1, the eighth transistor M8 is turned on so that the voltage of the initialization power source Vint can be supplied to the first node N1.

[0172] Therefore, during the first period P1 , the eighth transistor M8 may be controlled simultaneously with the fourth transistor M4 .

[0173] In an exemplary embodiment of the present disclosure, the eighth transistor M8 may remain turned off during the second period P2.

[0174] The voltage of the second node N2 can be initialized by turning on the fourth transistor M4 (for example, a conduction bias can be applied to the second node N2). The fourth transistor M4 can be turned on by the same signal used to turn on the eighth transistor M8. As described above, if an excessively high conduction bias is applied to the first transistor M1, the hysteresis variation of the first transistor M1 increases in the low-frequency drive mode including the relatively long second period P2. Therefore, in order to alleviate this hysteresis, the eighth transistor M8 can be added without removing the initialization power supply Vint.

[0175] The voltage of the initialization power supply Vint is simultaneously supplied to the first node N1 and the second node N2 by turning on the fourth transistor M4 and the eighth transistor M8. Thus, when the fourth transistor M4 and the eighth transistor M8 are turned on, the first transistor M1 has a relatively low gate-source voltage, and the magnitude of the bias voltage to be applied to the first transistor M1 is reduced. Therefore, the characteristic change of the first transistor M1 caused by the initialization of the gate voltage of the first transistor M1 can be minimized.

[0176] Therefore, the flicker phenomenon in the low frequency driving mode in which the length of the second period P2 increases in each frame period 1F can be alleviated. In addition, the initialization power Vint for the fourth transistor M4 and the seventh transistor M7 does not need to be divided into two parts, so the production cost can be reduced.

[0177] although Figure 7 It is shown that both the seventh transistor M7 and the eighth transistor M8 are P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the seventh transistor M7 and the eighth transistor M8 may be an N-type oxide semiconductor transistor.

[0178] Figure 8 is a diagram showing an exemplary embodiment of the present disclosure including Figure 1 1000 is a circuit diagram of a pixel PXL in a display device 1000.

[0179] In the following Figure 8 In the description of Figure 7 The components are the same or similar components, and thus, repeated description thereof can be omitted.

[0180] refer to Figure 8 , the pixel PXL may include a light emitting element LD, first to eighth transistors M1 to M8 , and a storage capacitor Cst.

[0181] In an exemplary embodiment of the present disclosure, the eighth transistor M8 may be coupled between the third node N3 and the initialization power supply Vint. The gate electrode of the eighth transistor M8 is coupled to the i-1 second scan line S2i-1. When the scan signal is supplied to the i-1 second scan line S2i-1, the eighth transistor M8 is turned on so that the voltage of the initialization power supply Vint can be supplied to the third node N3. Therefore, a voltage corresponding to the sum of the voltage of the initialization power supply Vint and the threshold voltage (Vint+Vth) can be supplied to the first node N1. In this case, the voltage of the initialization voltage Vint is supplied to the second node N2 by turning on the fourth transistor M4.

[0182] Therefore, when the first transistor M1 is initialized, a bias voltage variation of the first transistor M1 is reduced, and thus a characteristic variation of the first transistor M1 can be minimized.

[0183] Therefore, the flicker phenomenon in the low-frequency driving mode can be alleviated. In addition, there is no need to divide the initialization power Vint for the fourth transistor M4 and the seventh transistor M7 into two parts, thereby reducing the production cost.

[0184] although Figure 8It is shown that both the seventh transistor M7 and the eighth transistor M8 are P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the seventh transistor M7 and the eighth transistor M8 may be an N-type oxide semiconductor transistor.

[0185] Fig. 9 is a diagram showing a method of including a Figure 1 A circuit diagram of a pixel PXL in a display device 1000 is shown in FIG. Fig. 10A is a diagram showing an exemplary embodiment of the present disclosure Fig. 9 The timing diagram of the operation of the pixel PXL, and Fig. 10B is a diagram showing an exemplary embodiment of the present disclosure Fig. 9 A timing diagram of the operation of the pixel PXL.

[0186] In the following Fig. 9 In the description of Figure 2 The components are the same or similar components, and thus, repeated description thereof can be omitted.

[0187] refer to Fig. 9 , the pixel PXL may include a light emitting element LD, first to seventh transistors M1 to M7, and a storage capacitor Cst.

[0188] In an exemplary embodiment of the present disclosure, the third transistor M3 , the fourth transistor M4 , and the seventh transistor M7 are all N-type transistors. For example, the third transistor M3 , the fourth transistor M4 , and the seventh transistor M7 may be N-type oxide semiconductor transistors.

[0189] Since the seventh transistor M7 is an oxide semiconductor transistor, leakage current from the fourth node N4 may be minimized, and thus the display quality of the display device 1000 may be improved.

[0190] In an exemplary embodiment of the present disclosure, the gate electrode of the seventh transistor M7 may be coupled to the i-th second scan line S2i. Therefore, the third transistor M3 and the seventh transistor M7 may be turned on at the same time. Fig. 10A and Fig. 10B As shown in , the width of the emission control signal to be supplied to the i-th emission control line Ei can be reduced.

[0191] However, this is for illustration purposes only, and the gate electrode of the seventh transistor M7 may be coupled to the (i-1)th second scan line S2i-1 or the (i+1)th second scan line S2i+1.

[0192] Method and operation of operating pixel PXL Figure 2The method of the pixel PXL is basically the same. The main difference is that the gate electrode of the seventh transistor M7 is coupled to the i-th second scan line S2i and the time point at which the seventh transistor M7 is turned on is different from the time point at which the seventh transistor M7 is turned on. Figure 2 Therefore, repeated description thereof will be omitted.

[0193] Fig.11 It shows that the Figure 1 A circuit diagram of a pixel PXL in a display device 1000, and Fig.12 is a diagram showing an exemplary embodiment of the present disclosure Fig.11 A timing diagram of the operation of the pixel PXL.

[0194] In the following Fig.11 In the description of Figure 2 The components are the same or similar components, and thus, repeated description thereof can be omitted.

[0195] The pixel PXL may include a light emitting element LD, first to seventh transistors M1 to M7 , and a storage capacitor Cst.

[0196] The light emitting element LD may emit light having predetermined brightness corresponding to the current supplied from the first transistor M1.

[0197] In an exemplary embodiment of the present disclosure, the third transistor M3 , the fourth transistor M4 , and the seventh transistor M7 are all N-type transistors. For example, the third transistor M3 , the fourth transistor M4 , and the seventh transistor M7 may be N-type oxide semiconductor transistors.

[0198] The first transistor M1 , the second transistor M2 , the fifth transistor M5 , and the sixth transistor M6 are all P-type transistors. For example, the first transistor M1 , the second transistor M2 , the fifth transistor M5 , and the sixth transistor M6 may be P-type LTPS transistors.

[0199] The seventh transistor M7 is coupled between the second initialization power supply Vint2 and the fourth node N4. In an exemplary embodiment of the present disclosure, the gate electrode of the seventh transistor M7 may be coupled to the i-th emission control line Ei. The seventh transistor M7 may be turned on when the emission control signal is supplied to the i-th emission control line Ei, and may be turned off in other cases. In other words, the seventh transistor M7, which is an N-type transistor, may be turned on or off opposite to the fifth transistor M5 and the sixth transistor M6. For example, when the seventh transistor M7 is turned on, the fifth transistor M5 and the sixth transistor M6 are turned off.

[0200] When the emission control signal is supplied, the seventh transistor M7 is turned on so that the voltage of the second initialization power source Vint2 can be supplied to the first electrode of the light emitting element LD.

[0201] The signal to be supplied to the pixel PXL during the first period P1 (eg, the display scanning period T1) is connected to the reference Fig. 10A Signals of the described driving method are substantially the same; therefore, repeated description thereof will be omitted.

[0202] In an exemplary embodiment of the present disclosure, Fig.12 As shown in , during the second period P2 (e.g., the self-scanning period T2), only the emission control signal can be supplied to the pixel PXL through the i-th emission control line Ei. During the second period P2, the scan signal is neither supplied to the first scan line S1 nor to the second scan line S2. In other words, the gate-off voltage with a logic high level H can be supplied to the first scan line S1 (e.g., S1i). The gate-off voltage with a logic low level L can be supplied to the second scan line S2 (e.g., S2i-1 and S2i).

[0203] At the first time t1 at which all the second transistors M2 to the fourth transistor M4 are turned off, the emission control signal supplied to the i-th emission control line Ei is changed from a logic low level to a logic high level. Therefore, the fifth transistor M5 and the sixth transistor M6 are turned off. In this case, since the gate voltage of the fifth transistor M5 is increased, for example, by a parasitic capacitor between the gate electrode of the fifth transistor M5 and the first node N1, the voltage of the first node N1 is coupled to the increased gate voltage of the fifth transistor M5. Thus, the voltage of the first node N1 may increase. Therefore, the on bias may be applied to the first transistor M1 at each first time t1 of the second period P2.

[0204] Therefore, there is no need to turn on the second transistor M2 to apply the on bias during the second period P2, and the first scan driver 200 may not output the scan signal during the second period P2. Therefore, power consumption can be reduced.

[0205] Fig.13 is a block diagram illustrating a display device 1000 according to an exemplary embodiment of the present disclosure.

[0206] In the following Fig.13 In the description of Figure 1 The components are the same or similar components, and thus, repeated description thereof can be omitted.

[0207] refer to Fig.13, the display device 1000 may include a pixel unit 100, a first scan driver 200, a second scan driver 300, a third scan driver 350, an emission driver 400, a data driver 500, and a timing controller 600'.

[0208] The timing controller 600 ′ may supply gate start pulses GSP1 , GSP2 , GSP3 and a clock signal CLK to the first, second and third scan drivers 200 , 300 and 350 based on timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a clock signal CLK.

[0209] The first gate start pulse GSP1 may control a first timing of a scan signal to be supplied from the first scan driver 200. The second gate start pulse GSP2 may control a first timing of a scan signal to be supplied from the second scan driver 300.

[0210] The third gate start pulse GSP3 may control a first timing of a scan signal to be supplied from the third scan driver 350 .

[0211] In an exemplary embodiment of the present disclosure, the pulse widths of at least one of the first to third gate start pulses GSP1 to GSP3 may be different from each other, and therefore, the widths of their corresponding scan signals may also vary.

[0212] The data driver 500 may supply the data signal to the data line D in response to the data driving control signal DCS. The data signal supplied to the data line D may be supplied to the pixel PXL selected by the scan signal.

[0213] The first scan driver 200 may supply a scan signal to the first scan line S1 in response to the first gate start pulse GSP1. The first scan driver 200 may supply a scan signal to the first scan line S1 at a first frequency regardless of a driving frequency of the display device 1000. In other words, the first scan driver 200 may output a scan signal during the first period P1 and the second period P2. In particular, the first scan driver 200 may output a scan signal during each self-scan period T2.

[0214] The second scan driver 300 may supply a scan signal to the second scan line S2 in response to the second gate start pulse GSP2. The second scan driver 300 may supply a scan signal to the second scan line S2 at a second frequency corresponding to the driving frequency of the display device 1000. In other words, the second scan driver 300 may output a scan signal during the first period P1.

[0215] The third scan driver 350 may supply a scan signal to the third scan line S3 in response to the third gate start pulse GSP3. The third scan driver 350 may supply a scan signal to the third scan line S3 at a second frequency corresponding to the driving frequency of the display device 1000. In other words, the third scan driver 350 may output a scan signal during the first period P1. In an exemplary embodiment of the present disclosure, the width of the scan signal output from the third scan driver 350 may be different from the width of the scan signal output from the second scan driver 300.

[0216] In an exemplary embodiment of the present disclosure, the scan signal output from the first scan driver 200 may have a gate-on voltage with a logic low level to control the P-type transistor. Each of the scan signals output from the second scan driver 300 and the third scan driver 350 may have a gate-on voltage with a logic high level to control the N-type transistor.

[0217] The pixel PXL may be coupled to one or more first scan lines S1 , one or more second scan lines S2 , one or more third scan lines S3 , and one or more emission control lines E according to the structure of the pixel circuit.

[0218] Fig.14 is a diagram showing a method of including a Fig.13 A circuit diagram of a pixel PXL in a display device 1000, and FIG. 15A to FIG. 15C is a diagram showing an exemplary embodiment of the present disclosure Fig.14 A timing diagram of the operation of the pixel PXL.

[0219] exist Fig.14 , for the purpose of description, the pixel PXL disposed on the i-th horizontal line and coupled to the m-th data line Dm is illustrated.

[0220] In the following Fig.14 In the description of Fig.11 The components are the same or similar components, and thus, repeated description thereof can be omitted.

[0221] refer to Figures 14 to 15C , the pixel PXL may include a light emitting element LD, first to seventh transistors M1 to M7, and a storage capacitor Cst.

[0222] The light emitting element LD may emit light having predetermined brightness corresponding to the current supplied from the first transistor M1.

[0223] In an exemplary embodiment of the present disclosure, the third transistor M3 , the fourth transistor M4 , and the seventh transistor M7 are all N-type transistors. For example, the third transistor M3 , the fourth transistor M4 , and the seventh transistor M7 may be N-type oxide semiconductor transistors.

[0224] The first transistor M1, the second transistor M2, the fifth transistor M5 and the sixth transistor M6 are all P-type transistors. For example, the first transistor M1, the second transistor M2, the fifth transistor M5 and the sixth transistor M6 may be P-type LTPS transistors.

[0225] In an exemplary embodiment of the present disclosure, the gate electrode of the fourth transistor M4 may be coupled to the i-th third scan line S3i. Therefore, when the width of the scan signal supplied to the third scan line S3 is different from the width of the scan signal supplied to the second scan line S2, the turn-on time of the third transistor M3 and the turn-on time of the fourth transistor M4 may be different from each other.

[0226] First, the emission control signal is supplied to the i-th emission control line Ei. If the emission control signal is supplied to the i-th emission control line Ei, the fifth transistor M5 and the sixth transistor M6 are turned off, and the seventh transistor M7 is turned on. If the fifth transistor M5 and the sixth transistor M6 are turned off, the pixel PXL is set to a non-emission state. By turning on the seventh transistor M7, the second initialization power supply Vint2 is supplied to the fourth node N4.

[0227] In an exemplary embodiment of the present disclosure, Fig.15A and Fig. 15B As shown in , the scan signal supplied to the i-th third scan line S3i can be supplied earlier than the scan signal supplied to the i-th first scan line S1i or the scan signal supplied to the i-th second scan line S2i. Therefore, the fourth transistor M4 can be turned on by the scan signal supplied to the i-th third scan line S3i. If the fourth transistor M4 is turned on, the first initialization power supply Vint1 is supplied to the second node N2. In this case, the first transistor M1 has a conduction bias state.

[0228] Subsequently, the third transistor M3 may be turned on by the scan signal supplied to the i-th second scan line S2i. Therefore, the first transistor M1 may be coupled in the form of a diode.

[0229] like Fig.15A As shown in, in an exemplary embodiment of the present disclosure, the scan signal supplied to the i-th second scan line S2i may overlap with the scan signal supplied to the i-th first scan line S1i. In addition, the width of the scan signal supplied to the i-th second scan line S2i may be greater than the width of the scan signal supplied to the i-th first scan line S1i.

[0230] Thereafter, while the third transistor M3 is in the on state, the second transistor M2 is turned on by the scan signal supplied to the i-th first scan line S1i. If the second transistor M2 is turned on, the voltage of the data signal DS is supplied to the first transistor M1 through the first node N1, and the state of the first transistor M1 may be changed to a cut-off bias state in which the voltage of the second node N2 is lower than the voltage of the first node N1. In addition, through the first transistor M1 connected in the form of a diode, the data signal DS and a voltage corresponding to the threshold voltage of the first transistor M1 may be applied to the first node N1. In this case, the storage capacitor Cst may store a voltage corresponding to the second node N2.

[0231] Subsequently, the second transistor M2 and the third transistor M3 are sequentially turned off.

[0232] Thereafter, the supply of the emission control signal to the i-th emission control line Ei may be suspended. If the supply of the emission control signal to the i-th emission control line Ei is suspended, the fifth transistor M5 and the sixth transistor M6 are turned on, and the seventh transistor M7 is turned off. In this case, the first transistor M1 may control the driving current flowing to the light emitting element LD in response to the voltage of the second node N2. The light emitting element LD may generate light having a brightness corresponding to the amount of current supplied thereto.

[0233] In an exemplary embodiment of the present disclosure, each scan signal supplied to the i-th second scan line S2i and the i-th third scan line S3i may have a width corresponding to two or more horizontal periods (2H). Each of the second scan driver 300 and the third scan driver 350 may include a plurality of stages configured to shift and output the scan signals.

[0234] In the case where the scan signal to be supplied to the i-th second scan line S2i has a width corresponding to two or more horizontal periods (2H), the output of each stage included in the second scan driver 300 can share two or more consecutive second scan lines S2. In other words, the same scan signal can be supplied from the second scan driver 300 to the i-th horizontal line and the (i+1)-th horizontal line at the same time.

[0235] For example, in the case where each stage of the second scan driver 300 shares two second scan lines S2, the number of stages included in the second scan driver 300 can be reduced to half of the number of stages included in the first scan driver 200. Therefore, the production cost of the display device 1000 can be reduced.

[0236] In an exemplary embodiment of the present disclosure, Fig. 15BAs shown in , the scan signal supplied to the i-th second scan line S2i may overlap with the scan signal supplied to the i-th first scan line S1i and the scan signal to be supplied to the i-th third scan line S3i. In other words, the width of the scan signal supplied to the i-th second scan line S2i may be greater than the width of the scan signal supplied to the i-th first scan line S1i or the i-th third scan line S3i.

[0237] After the emission control signal has been supplied to the i-th emission control line Ei, the scan signal is supplied to the i-th second scan line S2i and the i-th third scan line S3i. Therefore, the third transistor M3 and the fourth transistor M4 are turned on. If the third transistor M3 and the fourth transistor M4 are turned on, the voltage of the first initialization power supply Vint1 is supplied to the second node N2 and the third node N3. In addition, if the third transistor M3 and the fourth transistor M4 are turned on, the first node N1 has a voltage corresponding to the sum (Vint+Vth) of the voltage of the first initialization power supply Vint1 and the threshold voltage of the first transistor M1 by means of the first transistor M1 connected in the form of a diode. Therefore, the first transistor M1 has a cut-off bias state.

[0238] Thereafter, the fourth transistor M4 is turned off, and the second transistor M2 is turned on by the scan signal supplied to the i-th first scan line S1i. Fig.15A The driving method is basically the same; therefore, further description thereof will be omitted.

[0239] like Fig. 15C As shown, the emission control signal is supplied to the i-th emission control line Ei during the self-scanning period T2 included in the second period P2. Therefore, the light emitting element LD is periodically initialized during the second period P2. In addition, the scan signal is supplied to the i-th first scan line S1i during the self-scanning period T2. Therefore, the predetermined voltage is periodically applied to the first electrode (e.g., source electrode) of the first transistor M1 during the second period P2.

[0240] Fig. 15C The driving method of the embodiment and the reference Figure 3B The driving method described in the examples is substantially the same; therefore, further description thereof will be omitted.

[0241] In reference Figures 14 to 15B In the described method of driving the pixel PXL, an off bias is applied to the first transistor M1 during the first period P1, and an on bias is periodically applied to the first transistor M1 during the second period P2. Therefore, the flicker phenomenon caused by the hysteresis of the first transistor M1 in the low-frequency driving mode can be minimized.

[0242] In substantially the same manner, reference FIG. 15A to FIG. 15C The driving method of the pixel PXL described is applied to the reference Figure 2 , Fig. 9 , Fig.11 The pixel PXL described by et al.

[0243] According to an exemplary embodiment of the present disclosure, Fig.16 It shows that the Figure 1 A circuit diagram of a pixel PXL in a display device 1000, and Fig.17A and Fig. 17B It shows Fig.16 A timing diagram of the operation of the pixel PXL.

[0244] In the following Figures 16 to 17B In the description of Figures 2 to 3B The components are the same or similar components, and thus, repeated description thereof can be omitted.

[0245] refer to Figures 16 to 17B , the pixel PXL may include a light emitting element LD, first to seventh transistors M1 to M7, and a storage capacitor Cst.

[0246] In an exemplary embodiment of the present disclosure, the first transistor M1 to the seventh transistor M7 are all polysilicon semiconductor transistors. For example, the first transistor M1 to the seventh transistor M7 may be a P-type LTPS transistor. Therefore, the scan signals to be supplied to the first transistor M1 to the seventh transistor M7 have a gate-on voltage with a logic low level.

[0247] Fig.17A The driving method shown in FIG. 1 is related to the operation of the pixel PXL during the first period P2 (eg, the display scanning period T1 ). Fig. 17B The driving method shown in FIG. 1 is related to the operation of the pixel PXL during the self-scanning period T2 of the second period P2. Fig.17A and Fig. 17B The driving method and Figure 3A and Figure 3B The driving method is basically the same; therefore, the repeated description thereof will be omitted. The main difference is: Fig.17A and Fig. 17B In the method, the scan signal has a gate-on voltage having a logic low level.

[0248] Fig.18 is a diagram showing a method of including a Figure 1 A circuit diagram of a pixel PXL in a display device 1000, and Fig.19A and Fig.19B is a diagram showing an exemplary embodiment of the present disclosure Fig.18 A timing diagram of the operation of the pixel PXL.

[0249] refer to Figures 18 to 19B , the pixel PXL may include a light emitting element LD, first to sixth transistors M1 ′ to M6 ′, and a storage capacitor Cst.

[0250] The first transistor M1 ′ to the sixth transistor M6 ′ may be oxide semiconductor transistors. For example, the first transistor M1 ′ to the sixth transistor M6 ′ may be N-type oxide semiconductor transistors.

[0251] The light emitting element LD may emit light having predetermined brightness corresponding to the current supplied from the first transistor M1 ′.

[0252] The first transistor M1' (or driving transistor) is connected between the first node N1 and the third node N3. The gate electrode of the first transistor M1' is coupled to the second node N2. The first transistor M1' can control the amount of current flowing from the first power source VDD to the second power source VSS via the light emitting element LD in response to the voltage of the second node N2.

[0253] The second transistor M2' may be coupled between the data line Dm and the fourth node N4. A gate electrode of the second transistor M2' may be coupled to the i-th first scan line S1i. When a scan signal is supplied to the i-th first scan line S1i, the second transistor M2' may be turned on to electrically couple the data line Dm to the fourth node N4.

[0254] The third transistor M3' is coupled between the first node N1 and the second node N2. A gate electrode of the third transistor M3' may be coupled to the i-th second scan line S2i.

[0255] The fourth transistor M4' is coupled between the first power supply VDD and the first node N1. A gate electrode of the fourth transistor M4' is coupled to the i-th emission control line Ei. The fourth transistor M4' may be turned off when the emission control signal is supplied to the i-th emission control line Ei, and may be turned on in other cases.

[0256] The fifth transistor M5' is coupled between the third node N3 and the fourth node N4. A gate electrode of the fifth transistor M5' may be coupled to the i-1th emission control line Ei-1. The fifth transistor M5' may be turned off when the emission control signal is supplied to the i-1th emission control line Ei-1, and may be turned on in other cases.

[0257] The sixth transistor M6' may be coupled between the third node N3 and the initialization power source Vint. A gate electrode of the sixth transistor M6' may be coupled to the i-th first scan line S1i.

[0258] The storage capacitor Cst may be coupled between the second node N2 and the fourth node N4. The storage capacitor Cst may store a voltage applied to the fourth node N4.

[0259] Fig.19A An example of a driving method during the first period P1 is shown.

[0260] First, the emission control signal is supplied to the i-1th emission control line Ei-1, and the fifth transistor M5' is turned off. In this case, since the sixth transistor M6' is in a turned-on state, the first power source VDD is supplied to the first node N1.

[0261] Thereafter, the scan signal is supplied to the first scan line S1i and the second scan line S2i, and the second transistor M2', the third transistor M3', and the sixth transistor M6' are turned on.

[0262] If the second transistor M2' is turned on, the data signal DS is supplied to the fourth node N4. If the third transistor M3' is turned on, the voltage of the first power supply VDD is supplied to the second node N2. Therefore, the first transistor M1' may have a cut-off bias state. If the sixth transistor M6' is turned on, the voltage of the initialization power supply Vint is supplied to the third node N3 (e.g., the first electrode of the light emitting element LD).

[0263] Subsequently, while the scan signal is supplied to the i-th first scan line S1i and the i-th second scan line S2i, the emission control signal is supplied to the i-th emission control line Ei. Therefore, while the second transistor M2', the third transistor M3' and the sixth transistor M6' remain turned on, the fourth transistor M4' is turned off.

[0264] If the fourth transistor M4' is turned off, the first transistor M1' enters a source follower state. Therefore, the first node N1 and the second node N2 may have a voltage corresponding to the sum (Vint+Vth) of the voltage of the initialization power supply Vint and the threshold voltage of the first transistor M1'. In other words, the threshold voltage of the first transistor M1' may be compensated.

[0265] Thereafter, supply of the scan signal to the i-th first scan line S1i and the i-th second scan line S2i is stopped, and the second transistor M2', the third transistor M3', and the sixth transistor M6' are turned off.

[0266] Subsequently, the supply of the emission control signal to the i-1th emission control line Ei-1 is stopped, and the fifth transistor M5' is turned on. If the fifth transistor M5' is turned on, the voltage of the initialization power supply Vint of the third node N3 is transmitted to the fourth node N4. The sum (DS+Vth) of the voltage corresponding to the data signal DS and the threshold voltage of the first transistor M1' is transmitted to the second node N2 by coupling. The voltage corresponding to Vth+DS-Vint is stored in the storage capacitor Cst.

[0267] Subsequently, supply of the emission control signal to the i-th emission control line Ei is stopped, and the fourth transistor M4' is turned on. Therefore, the pixel PXL may emit light based on a voltage corresponding to Vth+DS-Vint.

[0268] In the pixel PXL having the above configuration, the operation of compensating for the threshold voltage of the first transistor M1' and the data writing operation can be separated from each other. Therefore, the time required for the threshold voltage compensation can be reliably ensured.

[0269] Fig.19B An example of a driving method during the self-scan period T2 of the second period P2 is shown.

[0270] The scan signal is not supplied to the i-th second scan line S2i during the second period P2. Therefore, the third transistor M3' is not turned on during the second period P2.

[0271] During the second period P2, a predetermined reference voltage Vref may be supplied to the fourth node N4 by turning on the second transistor M2', and the light emitting element LD may be initialized by turning on the sixth transistor M6'.

[0272] The scan signal to be supplied to the i-th first scan line S1i and the emission control signal to be supplied to the emission control lines Ei-1 and Ei may be supplied at a first frequency regardless of the driving frequency. On the other hand, the scan signal to be supplied to the i-th second scan line S2i may be supplied to the i-th second scan line S2i at a second frequency corresponding to the driving frequency. In other words, when Fig.18 The pixel PXL is used for Figure 1 When the display device 1000 is configured to output images having various driving frequencies, the display device 1000 may support outputting images having various driving frequencies. For example, the driving frequency of the display device 1000 may correspond to a multiple of the first frequency.

[0273] In a display device according to an exemplary embodiment of the present disclosure, each frame period includes a display scanning period and at least one self-scanning period, thereby being able to support the output of images having various driving frequencies. In addition, as the driving frequency decreases, the number of self-scanning periods increases. Therefore, brightness reduction and high flicker visibility in a low-frequency driving mode may not occur or may be mitigated.

[0274] Furthermore, since a predetermined bias voltage is periodically applied to the first transistor (eg, the driving transistor), power consumption can be reduced, and a flicker phenomenon in a low-frequency driving mode can be mitigated.

[0275] Although the present disclosure has been described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as set forth herein.

Claims

1. A display device, wherein: The display device comprises: Pixels; a first scan line coupled to the second transistor of the pixel so as to supply a first scan signal to the pixel at a first frequency; a second scan line coupled to the third transistor of the pixel so as to supply a second scan signal to the pixel at a second frequency corresponding to the driving frequency of the pixel; an emission control line coupled to the pixel to supply an emission control signal to the pixel at the first frequency; and a data line coupled to the pixel so as to supply a data signal to the pixel based on the driving frequency, wherein the first frequency is greater than the second frequency, wherein the second frequency is equal to the driving frequency, and wherein the second frequency and the driving frequency correspond to submultiples of the first frequency.

2. The display device according to claim 1, wherein: The first scan line supplies the first scan signal to the pixel at the first frequency which is twice the maximum driving frequency of the display device.

3. The display device according to claim 2, wherein: The emission control line supplies the emission control signal to the pixel at the first frequency which is twice the maximum driving frequency of the display device.

4. The display device according to claim 2, wherein: The display device further comprises: a first scan driver configured to supply the first scan signal to the first scan line; a second scan driver configured to supply the second scan signal to the second scan line; an emission driver configured to supply the emission control signal to the emission control line; and The data driver is configured to supply the data signal to the data line.

5. The display device according to claim 4, in, When the display device is driven at the driving frequency of the pixel, the second scan driver supplies the second scan signal during a first period of a frame period, and Wherein, when the display device is driven at the driving frequency of the pixel, the second scan driver does not supply the second scan signal during a second period of the frame period.

6. The display device according to claim 5, wherein: When the display device is driven at the maximum driving frequency of the display device, the length of the first period is equal to the length of the second period.

7. The display device according to claim 5, in, The first period includes a display scanning period in which the first scanning driver and the second scanning driver supply the first scanning signal and the second scanning signal respectively to write the data signal to the pixel, and The second period includes a self-scan period in which a characteristic of a driving transistor included in each of the pixels is changed by supplying the first scan signal from the first scan driver.

8. The display device according to claim 7, wherein: When the driving frequency of the pixel decreases, the number of the self-scanning periods included in the second period increases.

9. A display device, wherein: The display device comprises: Pixels; a first scan line coupled to the pixel to supply a first scan signal to the pixel at a first frequency; a second scan line coupled to the pixel to supply a second scan signal to the pixel at a second frequency corresponding to the driving frequency of the pixel; an emission control line coupled to the pixel to supply an emission control signal to the pixel at the first frequency; and a data line coupled to the pixel so as to supply a data signal to the pixel based on the driving frequency, wherein the first frequency is greater than the second frequency, wherein the second frequency is equal to the drive frequency, and wherein the second frequency and the drive frequency correspond to submultiples of the first frequency, Among them, the pixels arranged on the i-th horizontal line include: A light emitting element including a first electrode and a second electrode coupled to a second power source; a first transistor including a first electrode coupled to a first node electrically connected to a first power source and configured to control a driving current based on a voltage of a second node; a second transistor coupled between one of the data lines and the first node and configured to be turned on by the first scan signal supplied to an i-th first scan line among the first scan lines; a third transistor coupled between the second node and a third node coupled to the second electrode of the first transistor and configured to be turned on by the second scan signal supplied to an i-th second scan line among the second scan lines; a fourth transistor coupled between the second node and a first initialization power source and configured to be turned on by the second scan signal supplied to an (i-1)th second scan line among the second scan lines; a fifth transistor coupled between the first power source and the first node and configured to be turned off by an emission control signal supplied to an i-th emission control line among the emission control lines; a sixth transistor coupled to the third node and the first electrode of the light emitting element and configured to be turned off by the emission control signal; and a storage capacitor coupled between the first power source and the second node, Wherein, i is a natural number.

10. The display device according to claim 9, in, The pixels arranged on the i-th horizontal line further include: a seventh transistor coupled between the first electrode of the light emitting element and a second initialization power source and configured to be turned on by the first scanning signal supplied to the (i+1)th first scanning line among the first scanning lines, and The voltage of the first initialization power source is different from the voltage of the second initialization power source.

11. The display device according to claim 9, wherein: The pixels arranged on the i-th horizontal line further include: a seventh transistor coupled between the first electrode of the light emitting element and the first initialization power source and configured to be turned on by the first scan signal supplied to the (i+1)th first scan line among the first scan lines; and An eighth transistor is coupled between the first node and the first initialization power source and is configured to be turned on by the second scan signal supplied to the (i-1)th second scan line.

12. The display device according to claim 9, wherein: The pixels arranged on the i-th horizontal line further include: a seventh transistor coupled between the first electrode of the light emitting element and the first initialization power source and configured to be turned on by the first scan signal supplied to the (i+1)th first scan line among the first scan lines; and An eighth transistor is coupled between the third node and the first initialization power source and is configured to be turned on by the second scan signal supplied to the (i-1)th second scan line.

13. The display device according to claim 9, in, The first transistor, the second transistor, the fifth transistor and the sixth transistor are all P-type transistors, and Wherein, the third transistor and the fourth transistor are both N-type oxide semiconductor transistors.

14. The display device according to claim 13, in, The pixels arranged on the i-th horizontal line further include: a seventh transistor, coupled between the first electrode of the light emitting element and a second initialization power source, and configured to be turned on by the second scanning signal supplied to the i-th second scanning line, Wherein, the seventh transistor is an N-type oxide semiconductor transistor, and The voltage of the first initialization power source is different from the voltage of the second initialization power source.

15. The display device according to claim 13, in, The pixels arranged on the i-th horizontal line further include: a seventh transistor coupled between the first electrode of the light emitting element and a second initialization power source and configured to be turned on by the emission control signal supplied to the i-th emission control line, Wherein, the seventh transistor is an N-type oxide semiconductor transistor, and The voltage of the first initialization power source is different from the voltage of the second initialization power source.

16. A display device, wherein: The display device comprises: Pixels; a first scan line coupled to the pixel to supply a first scan signal to the pixel at a first frequency; a second scan line coupled to the pixel to supply a second scan signal to the pixel at a second frequency corresponding to the driving frequency of the pixel; an emission control line coupled to the pixel to supply an emission control signal to the pixel at the first frequency; and a data line coupled to the pixel so as to supply a data signal to the pixel based on the driving frequency, wherein the first frequency is greater than the second frequency, wherein the second frequency is equal to the drive frequency, and wherein the second frequency and the drive frequency correspond to submultiples of the first frequency, Among them, the pixels arranged on the i-th horizontal line include: A light emitting element including a first electrode and a second electrode coupled to a second power source; a first transistor including a first electrode coupled to a first node electrically connected to a first power source and configured to control a driving current based on a voltage of a second node; a second transistor coupled between a first data line among the data lines and the first node and configured to be turned on by the first scan signal supplied to an i-th first scan line among the first scan lines; a third transistor coupled between the second node and a third node coupled to the second electrode of the first transistor and configured to be turned on by the second scan signal supplied to an i-th second scan line among the second scan lines; a fourth transistor coupled between the second node and a first initialization power source and configured to be turned on by a third scan signal supplied to an i-th third scan line; and a fifth transistor coupled between the first power source and the first node and configured to be turned off by the emission control signal supplied to the i-th emission control line among the emission control lines, Wherein, i is a natural number.

17. The display device according to claim 16, wherein: The display device further comprises: a first scan driver configured to supply the first scan signal to the first scan line; a second scan driver configured to supply the second scan signal to the second scan line; an emission driver configured to supply the emission control signal to the emission control line; a data driver configured to supply the data signal to the data line; and a third scan driver configured to supply the third scan signal to a third scan line coupled to the pixel at the second frequency, and Wherein, the width of the second scanning signal and the width of the third scanning signal are greater than the width of the first scanning signal.

18. The display device according to claim 17, in, When the display device is driven at the driving frequency of the pixel, the second scan driver and the third scan driver supply the second scan signal and the third scan signal, respectively, during a first period of a frame period, and Wherein, when the display device is driven at the driving frequency of the pixel, the second scan driver and the third scan driver do not supply the second scan signal and the third scan signal during a second period of the frame period.

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