Display device

Abstract

A display device includes: a substrate, the substrate including: a display area including thin film transistors having electrodes, a non-display area, and a pad area, the pad area including a lower conductive layer and an upper conductive layer facing each other, and an insulating layer between the lower conductive layer and the upper conductive layer. The lower conductive layer includes: a first conductive layer that defines an end surface of the display device; and a second conductive layer spaced apart from the first conductive layer to define a space between the first conductive layer and the second conductive layer, the insulating layer defining a first opening portion corresponding to the space, and the upper conductive layer is in the same layer as the electrode of the thin film transistor, and the upper conductive layer extends into the first opening portion corresponding to the space between the first conductive layer and the second conductive layer.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0070072, filed with the Korean Intellectual Property Office on Jun. 13, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] One or more embodiments relate to an electronic device, and more particularly, to a display device. Background Art

[0003] With the development of the information society, various demands for display devices for displaying images have increased. In the field of display devices, cathode ray tubes (“CRTs”) having a large volume have been replaced by flat panel display (“FPD”) devices, which are relatively thin and light and can have a large display area. The FPD devices may include liquid crystal display (“LCD”) devices, plasma display panel (“PDP”) devices, organic light emitting display (“OLED”) devices, electrophoretic display (“EPD”) devices, and the like.

[0004] After manufacturing such display devices, the operation of the display devices may be tested, for example, using test pads. Summary of the Invention

[0005] Test pads for testing the operation of a display device after manufacturing the display device may be disposed on a display substrate of the display device. Since the ineffective space of the display device has been reduced, the test pads may be disposed outside the display area of the display substrate. After testing the operation of the display device, the test pads may be separated from the rest of the display substrate by performing laser trimming or the like.

[0006] One or more embodiments provide a display device including a pad area having high reliability.

[0007] Additional features will be partly set forth in the description which follows, and partly will be obvious from the description, or may be learned by practice of the embodiments of the present disclosure.

[0008] According to one or more embodiments, a display device includes a substrate that includes a display area including thin film transistors having electrodes, a non-display area, and a pad area. The pad area includes a lower conductive layer and an upper conductive layer facing each other, and an insulating layer is between the lower conductive layer and the upper conductive layer. The lower conductive layer includes a first conductive layer defining an end surface of the display device; and a second conductive layer spaced apart from the first conductive layer to define a space between the first conductive layer and the second conductive layer. The insulating layer defines a first opening portion corresponding to the space, and the upper conductive layer is in the same layer as the electrode of the thin film transistor and extends into the first opening portion.

[0009] The upper conductive layer may be connected to the first conductive layer at a first contact hole and connected to the second conductive layer at a second contact hole.

[0010] The insulating layer may include a first insulating layer and a second insulating layer.

[0011] The first opening portion may include a first insulating opening portion of the first insulating layer and a second insulating opening portion of the second insulating layer, and the first insulating opening portion and the second insulating opening portion may be connected to each other.

[0012] The display area may further include: a gate electrode facing the electrode, both a gate insulating layer and an interlayer insulating layer being between the gate electrode and the electrode; and a semiconductor layer facing the gate insulating layer, the gate electrode being between the semiconductor layer and the gate insulating layer. The insulating layer may include: a first insulating layer in the same layer as the gate insulating layer; and a second insulating layer in the same layer as the interlayer insulating layer.

[0013] The display device may further include a lower insulating layer between the first conductive layer and the substrate.

[0014] The display device may further include a protective layer disposed on the upper conductive layer to at least partially overlap the upper conductive layer and including an organic material.

[0015] The first conductive layer and the second conductive layer may be disposed in different layers from each other.

[0016] The display area may further include: a gate electrode facing the electrode, both a gate insulating layer and an interlayer insulating layer being between the gate electrode and the electrode; and a semiconductor layer facing the gate insulating layer, the gate electrode being between the semiconductor layer and the gate insulating layer. The insulating layer may include: a first insulating layer in the same layer as the gate insulating layer; and a second insulating layer in the same layer as the interlayer insulating layer, the first insulating layer being disposed between the substrate and the second conductive layer, and the second insulating layer facing the first insulating layer, the second conductive layer being between the second insulating layer and the first insulating layer.

[0017] The display device may further include a lower insulating layer and a buffer layer between the first insulating layer and the substrate. The buffer layer may define a buffer opening portion corresponding to the space, the lower insulating layer may define a lower opening portion corresponding to the space, the buffer opening portion and the lower opening portion may be connected to each other, and the upper conductive layer may be disposed at the buffer opening portion and the lower opening portion by surrounding the upper surfaces and side surfaces of the first conductive layer and the second conductive layer.

[0018] The display device may further include a third conductive layer disposed below the second conductive layer. The third conductive layer is disposed closer to the display area than the second conductive layer.

[0019] The display device may further include a lower insulating layer between the first conductive layer and the substrate.

[0020] According to one or more embodiments, a display device includes a substrate including a display area, a non-display area, and a pad area in the non-display area, and including a lower conductive layer, an insulating layer, and an upper conductive layer. The lower conductive layer includes: a first conductive layer including a side surface in the same plane as the side surface of the insulating layer; and a second conductive layer separated from the first conductive layer. The insulating layer includes: an external insulating layer on the first conductive layer; and an internal insulating layer on the second conductive layer, and the upper conductive layer is on the external insulating layer and the internal insulating layer and is integrally disposed along the side surfaces of the external insulating layer and the internal insulating layer.

[0021] The external insulating layer may define a first contact hole exposing the first conductive layer, the internal insulating layer may define a second contact hole exposing the second conductive layer, and the upper conductive layer may be connected to the first conductive layer at the first contact hole and may be connected to the second conductive layer at the second contact hole.

[0022] The external insulating layer may include a first external insulating layer and a second external insulating layer, and the internal insulating layer may include a first internal insulating layer and a second internal insulating layer.

[0023] The display device may further include a planarization layer disposed on the upper conductive layer to at least partially overlap the upper conductive layer.

[0024] The display device may further include a lower insulating layer between the first conductive layer and the substrate, and the upper conductive layer and the lower insulating layer may at least partially contact each other.

[0025] The display device may further include a first conductive layer and a second conductive layer in different layers, and an insulating layer is between the first conductive layer and the second conductive layer.

[0026] The display device may further include: a first lower insulating layer between the first conductive layer and the substrate; and a second lower insulating layer between the second conductive layer and the first lower insulating layer.

[0027] The display device may further include: an external lower layer between the first conductive layer and the substrate; and an internal lower layer between the second conductive layer and the substrate. The upper conductive layer may be connected to the first conductive layer and the second conductive layer, and may be disposed along side surfaces of the external lower layer and the internal lower layer.

[0028] The display device may further include a third conductive layer between the display region and the second conductive layer. The third conductive layer may be in the same layer as the first conductive layer, and the third conductive layer may be connected to the upper conductive layer at a third contact hole of the insulating layer.

[0029] The lower insulating layer may be between the third conductive layer and the substrate, and the third conductive layer and the lower insulating layer may be in contact with each other.

[0030] According to one or more embodiments, a display device includes: a substrate including a display region including thin film transistors having electrodes, a non-display region adjacent to the display region, and a pad region in the non-display region, the pad region including a lower conductive layer facing the upper conductive layer, an insulating layer between the upper conductive layer and the lower conductive layer, the lower conductive layer including: a first conductive layer defining an end surface of the display device; and a second conductive layer that is in a different layer from the first conductive layer and is spaced apart from the first conductive layer along the substrate to define a space between the first conductive layer and the second conductive layer, both a lower insulating layer and a buffer layer being between the substrate and the first conductive layer, the buffer layer defining a buffer opening portion corresponding to the space between the first conductive layer and the second conductive layer, the lower insulating layer defining a lower opening portion corresponding to the space between the first conductive layer and the second conductive layer. The buffer opening portion and the lower opening portion are connected to each other, and the upper conductive layer is in the same layer as the electrodes of the thin film transistors and extends into both the buffer opening portion and the lower opening portion.

[0031] The upper conductive layer may be connected to the first conductive layer and the second conductive layer.

[0032] An insulating layer may be provided between the lower insulating layer and the second conductive layer, the insulating layer including an internal insulating layer and an external insulating layer spaced apart from each other along the substrate, the internal insulating layer being closer to the display region than the external insulating layer, inner surfaces of the external insulating layer and the internal insulating layer corresponding to both the buffer opening portion and the lower opening portion and facing each other, and the upper conductive layer extending from the buffer opening portion and the lower opening portion to be disposed along the inner surfaces of the external insulating layer and the internal insulating layer.

[0033] The display device may further include a protective layer disposed on the upper conductive layer to at least partially overlap with the upper conductive layer and including an organic material. Description of the Drawings

[0034] The above and other features and advantages of the embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0035] Figure 1 is a schematic top view of an embodiment of a display device;

[0036] Figure 2 is a schematic top view of an embodiment of a preliminary display device on which a reliability test is performed;

[0037] Figure 3 is a top view of an embodiment of a display device provided from the preliminary display device;

[0038] Figure 4A is along Figure 1 the I-I' line of Figure 3 and Figure 4B is Figure 4A a magnified cross-sectional view of part B in

[0039] FIG. 5 shows a comparative example of a display device;

[0040] Figure 6A is a cross-sectional view of another embodiment of the pad area of the display device;

[0041] Figure 6B is a cross-sectional view of yet another embodiment of the pad area of the display device; and

[0042] Figure 7 is a cross-sectional view of still another embodiment of the pad area of the display device. Detailed Description of the Embodiments

[0043] Reference will now be made in detail to the embodiments, examples of which are illustrated in the accompanying drawings, wherein the same reference numerals refer to the same elements throughout. In this regard, the embodiments may have different forms and should not be construed as limited to the description set forth herein. Accordingly, the embodiments are described below only by referring to the drawings to explain the features of the present specification.

[0044] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. For example, unless the context clearly indicates otherwise, "an element" has the same meaning as "at least one element". Expressions such as "at least one", when preceding a list of elements, modify the entire list of elements and not individual elements of the list. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0045] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In this description, like reference numerals refer to like elements, and the same description will not be repeated.

[0046] It will be understood that terms such as "first", "second", etc. may be used herein to describe various components, and these components should not be limited by these terms. These components are only used to distinguish one component from another.

[0047] It will be further understood that the terms "comprising" and / or "including" as used herein specify the presence of the stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0048] It will be understood that when a layer, region or component is referred to as being related to another element, such as "on" another layer, region or component, it can be formed directly or indirectly on the other layer, region or component. That is, for example, there may be intermediate layers, regions or components. In contrast, when a layer, region or component is referred to as being related to another element, such as "directly on" another layer, region or component, there are no intermediate layers, regions or components.

[0049] For ease of illustration, the dimensions of the elements in the drawings may be exaggerated. In other words, since the dimensions and thicknesses of the components in the drawings are arbitrarily shown for ease of illustration, the following embodiments are not limited thereto.

[0050] When an embodiment can be implemented differently, a particular processing order may be executed differently from the described order. For example, two consecutively described processes may be executed substantially simultaneously or in an order opposite to the described order.

[0051] In the following embodiments, it will be understood that when an element, region or layer is referred to as being related to another element, such as "connected to" another element, region or layer, the element, region or layer can be physically and / or mechanically in contact with the other element, region or layer, or electrically connected to the other element, region or layer.

[0052] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is flipped, an element described as on the "lower" side of another element will be oriented on the "upper" side of that other element. Thus, depending on the particular orientation of the figure, the exemplary term "lower" can encompass both the "lower" and "upper" orientations. Similarly, if the device in one of the figures is flipped, an element described as "below" or "beneath" another element will be oriented as "above" that other element. Thus, the exemplary term "below" or "beneath" can encompass both the upper and lower orientations.

[0053] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0054] Exemplary embodiments are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments. As such, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, the embodiments described herein should not be construed as limited to the particular shapes of regions shown herein but should include, for example, shape deviations resulting from manufacturing. For example, regions shown or described as flat may typically have rough and / or non-linear features. Additionally, the sharp angles shown may be rounded. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to show the exact shape of the regions and are also not intended to limit the scope of the claims.

[0055] Figure 1 is a schematic top view of an embodiment of the display device 1.

[0056] Reference Figure 1 , the display device 1 may include a display area DA ( Figure 1 the dashed line in) on which an image is generated and / or displayed, and a non-display area NDA on which no image is displayed. The display device 1 can provide an image by using light emitted from pixels P (e.g., a plurality of pixels P) arranged in the display area DA.

[0057] Each pixel in pixel P may include a display element, such as an organic light-emitting diode (“OLED”). Each pixel P may generate and / or emit light from the organic light-emitting diode (“OLED”), for example, light of red, green, blue, and / or white. In this specification, as described above, pixel P may be a pixel P that emits any one of red light, green light, blue light, and white light.

[0058] Each pixel in pixel P may be electrically connected to an external circuit disposed in the non-display area NDA. The external circuit may include, but is not limited to, a first scan driving circuit 121, a second scan driving circuit 122, a pad area PDA, a data driving circuit 150, a first power supply line 160, and a second power supply line 170 disposed in the non-display area NDA.

[0059] The first scan driving circuit 121 outside the display area DA may provide a scan signal to each pixel P inside the display area DA through scan lines SL extending to be provided in each of the display area DA and the non-display area NDA. Similarly, the first scan driving circuit 121 may provide an emission control signal to each pixel P through an emission control line EL. The second scan driving circuit 122 may be disposed in parallel with the first scan driving circuit 121, and the display area DA is between the first scan driving circuit 121 and the second scan driving circuit 122. Some of the pixels P disposed in the display area DA may be electrically connected to the first scan driving circuit 121, and other pixels in pixel P may be electrically connected to the second scan driving circuit 122. According to another embodiment, the second scan driving circuit 122 may be omitted.

[0060] One or more of the foregoing components may define a display panel 10 of the display device 1. The display panel 10 and / or its components may include a display area DA and a non-display area NDA corresponding to the above-described display area DA and non-display area NDA. An electrical signal may be provided from the outside of the display panel 10 to the display area DA (e.g., pixel P) for displaying an image, generating and / or emitting light, etc.

[0061] The display device 1, the display panel 10, and / or its components may be arranged along a plane defined by an x direction and a y direction that intersect each other. The thickness of the display device 1, the display panel 10, and / or its components may be defined along the z direction. The x direction, the y direction, and the z direction may differently represent the first to third directions that intersect each other.

[0062] The pad region PDA may be disposed on one side of the substrate 110. Pads PAD (e.g., a plurality of pads PAD) arranged as a plurality may be provided in the pad region PDA. Each pad in the pads PAD of the pad region PDA may not be covered by an insulating layer (e.g., may be exposed to the outside of the substrate 110) and may be electrically connected to the printed circuit board PCB. Electrical signals may be provided to various components of the display panel 10 from the outside of the substrate 110 and / or the display panel 10 through the pads PAD.

[0063] The terminals PCB-P (or terminal pads PCB-P) of the printed circuit board PCB may be electrically connected to the pads PAD of the display panel 10. Electrical signals such as drive signals, control signals, power supply signals, data signals, etc. may be provided to the display panel 10 from a controller (not shown). The printed circuit board PCB may be connected between the controller and the display panel 10, but is not limited thereto. Control signals generated in the controller may be transmitted to each of the first scan driving circuit 121 and the second scan driving circuit 122 through the printed circuit board PCB. In one embodiment, the controller may supply a first power supply voltage and a second power supply voltage to the first power supply line 160 and the second power supply line 170 through a first connection line 161 (e.g., a first connection wiring 161) and a second connection line 171 (e.g., a second connection line 171), respectively. The first power supply voltage may be provided to each pixel P through a driving voltage line PL connected to the first power supply line 160, and the second power supply voltage may be provided to each pixel P connected to the second power supply line 170.

[0064] The data driving circuit 150 may be electrically connected to the data line DL. The data signal of the data driving circuit 150 may be provided to each pixel P through a connection line 151 (e.g., a third connection line 151 or a third connection wiring 151) connected to the pad region PDA and through the data line DL connected to the connection line 151. Figure 1 It is shown that the data driving circuit 150 is disposed in the printed circuit board PCB. However, according to another embodiment, the data driving circuit 150 may be disposed on the substrate 110. In one embodiment, for example, the data driving circuit 150 may be disposed between the pad region PDA and the first power supply line 160.

[0065] The first power supply line 160 may include a first sub-line 162 and a second sub-line 163 that extend parallel to each other in the x direction, and the display region DA is between the first sub-line 162 and the second sub-line 163. The second power supply line 170 may have an annular shape with an open side and may partially surround the display region DA. Refer Figure 1 , the second power supply line 170 is open on the side of the display panel 10 where the printed circuit board PCB can be attached to the display panel 10.

[0066] To improve the reliability of the above-described display device 1, a substrate test of the display device 1 can be performed, and a light emission test of the display device 1 can be performed by using a plurality of test pads TPAD (e.g., a plurality of test pads TPAD) that are provided. The test pads TPAD can be deleted from the display device 1 and / or the display panel 10 that have been tested, but are not limited thereto. Hereinafter, a description will be given in detail with reference to Figure 2 for reference.

[0067] Figure 2 is a schematic top view of an embodiment of a preliminary display device 1' (hereinafter the display device 1') on which a reliability test process is performed.

[0068] Refer to Figure 2 , the display device 1' can include a display area DA and a non-display area NDA corresponding to the display area DA and the non-display area NDA of the display device 1. The non-display area NDA can include a pad area PDA and a test area TA that are arranged with respect to a cutting line CL along which a part of the display device 1' can be separated from the rest of it. The cutting line CL can correspond to an end or an edge of the display panel 10 and / or its components (e.g., the substrate 110), but is not limited thereto.

[0069] Within the display device 1', a first end of a first signal line SL1 is connected to a pixel P. A pad PAD connected to a second end of the first signal line SL1 opposite to its first end, and a part of a second signal line SL2 that is connected to the pad PAD and extends into the test area TA can be arranged in the pad area PDA. One or more of the foregoing elements, such as the first signal line SL1, the pad PAD, and the second signal line SL2, can be arranged in the pad area PDA.

[0070] The first signal line SL1 can include a first connection line 161 and a second connection line 171 (refer to Figure 1 ) and a connection line 151 (refer to Figure 1 ).

[0071] A part of the second signal line SL2 connected to the pad PAD and a test pad TPAD connected to the second signal line SL2 can be arranged in the test area TA.

[0072] The second signal lines SL2 can be connected to each other via connection lines LSL. In one embodiment, for example, the connection lines LSL can connect the second signal lines SL2 of the first group to each other, and the second signal lines SL2 of the first group are connected to pixels P that emit the same color. Therefore, it is possible to test whether the pixels P emit light by using a test signal applied to the test pad TPAD, and the test pad TPAD is connected to the pixels P through one or more second signal lines SL2.

[0073] The cutting line CL can be arranged to cross the second signal lines SL2. It is possible to test whether the display device 1' is operating by using the test pad TPAD, and the test pad TPAD can be separated from the rest of the display device 1' alone or together with other layers of the display device 1' along the cutting line CL. The rest of the display device 1' can define the display panel 10, and the test pad TPAD is separated from the rest of the display device 1' alone or together with other layers of the display device 1'. That is, Figure 1 the display panel 10 of the display device 1 in

[0074] Figure 3 is a top view of the display device 1 provided from the display device 1'. Figure 4A is along Figure 1 line I-I' of Figure 3 and a cross-sectional view taken along line A-A' of Figure 4B is Figure 4A an enlarged cross-sectional view of part B in

[0075] Refer to Figure 3 , in the rest of the display device 1' (for example, the display panel 10 of the display device 1), a part of the first signal line SL1, the pad PAD, and a part of the second signal line SL2 can be arranged in the pad area PDA. The part of the second signal line SL2 can be retained in the pad area PDA of the display panel 10, where the end of the part of the second signal line SL2 is aligned with the end of the substrate 110 corresponding to the cutting line CL. That is, the end of the part of the second signal line SL2 can define the end of the display panel 10 and / or the display device 1.

[0076] Refer to Figure 4A and Figure 4B , the pad PAD of the display device 1 can include parts of the substrate 110, the buffer layer 111 (for example, the first lower insulating layer), the lower layer 112 (for example, the lower insulating layer 112 or the second lower insulating layer), the lower conductive layer M, the first insulating layer 114, the second insulating layer 116, the upper conductive layer UM, and the protective layer 118.

[0077] The substrate 110 may include glass or a polymer resin. The polymer resin may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose acetate propionate, etc. The substrate 110 including the polymer resin may be flexible, rollable, or bendable. The substrate 110 may have a multilayer structure, which includes: a layer containing one or more of the above polymer resins, and an inorganic layer (not shown).

[0078] The buffer layer 111 may be located on the substrate 110, may reduce or prevent the penetration of foreign substances, moisture, or foreign objects from below (e.g., outside) the substrate 110, and may provide a planarized surface on the substrate 110. The buffer layer 111 may include an inorganic material such as an oxide or a nitride, an organic material, or both an organic material and an inorganic material, and may have a single-layer structure or a multilayer structure including the inorganic material and / or the organic material. A barrier layer (not shown) that reduces or prevents the penetration of foreign objects may be further included between the substrate 110 and the buffer layer 111. In some embodiments, the buffer layer 111 may include silicon oxide (SiO2) or silicon nitride (SiN x ).

[0079] The lower layer 112 may be provided to cover the buffer layer 111. The lower layer 112 (e.g., the lower insulating layer 112) may include an inorganic insulating material such as SiO2, SiN x , silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), etc. The lower layer 112 may include a single layer or multiple layers containing the above inorganic insulating materials.

[0080] The lower conductive layer M may be disposed on the upper surface of the lower layer 112, and the lower conductive layer M includes a first conductive layer M1 and a second conductive layer M2.

[0081] According to an embodiment, the first conductive layer M1 and the second conductive layer M2 may be disposed in the same layer along the substrate 110, and a space SPC is between the first conductive layer M1 and the second conductive layer M2. Since they are in the "same layer", components may be provided or formed by the same material layer, e.g., to be part of the same material layer on the substrate 110. These parts in the same layer may be disposed at the same distance from the substrate 110.

[0082] The side surface of the first conductive layer M1 may include a first cutting surface CA1 (e.g., a first cutting side surface CA1). Moreover, the first conductive layer M1 may include a first cutting surface CA1 that is in the same plane (e.g., coplanar with) the second cutting surface CA2 (e.g., a second cutting side surface CA2) of the first insulating layer 114 and / or the third cutting surface CA3 (e.g., a third cutting side surface CA3) of the second insulating layer 116, which will be described below. Such cutting surfaces may be exposed to the outside of the display panel 10 to define the end surfaces of the substrate 110, the display panel 10, and / or the display device 1, but are not limited thereto.

[0083] The second conductive layer M2 may be arranged to be separated from the first conductive layer M1 along the substrate 110 and may be arranged closer to the display area DA than the first conductive layer M1. Different from the first conductive layer M1, the second conductive layer M2 may not include the first cutting surface CA1. Moreover, a space SPC may be between the first conductive layer M1 and the second conductive layer M2. The first conductive layer M1 and the second conductive layer M2 may include Mo, Al, Cu, Ti, etc., and may include a single layer or multiple layers. In one embodiment, for example, the first conductive layer M1 and the second conductive layer M2 may include a single Mo layer.

[0084] The first conductive layer M1 and the second conductive layer M2 may include the same material as the gate electrode G, which will be described below.

[0085] The first insulating layer 114 may cover the first conductive layer M1 and the second conductive layer M2. The first insulating layer 114 may have a first insulating layer opening portion OP1 (e.g., a first opening OP1) corresponding to the space SPC between the first conductive layer M1 and the second conductive layer M2.

[0086] The first insulating layer 114 may have a first portion 114a covering or corresponding to the first conductive layer M1 and a second portion 114b covering or corresponding to the second conductive layer M2.

[0087] One side of the first portion 114a for connecting its upper surface and lower surface to each other may include or define the second cutting surface CA2. As described above, the second cutting surface CA2 may coincide with or be in the same plane as the first cutting surface CA1.

[0088] The first portion 114a may be arranged to cover the side surface of the first conductive layer M1. In one embodiment, for example, the side surface of the first conductive layer M1 may include a first cut surface CA1 and a second side surface that is opposite to the first cut surface CA1 and closer to the display area DA than the first cut surface CA1. The second side surface of the first conductive layer M1 may contact the first portion 114a. The first portion 114a may cover the second side surface of the first conductive layer M1 and may be arranged at the space SPC. The first portion 114a may include or define a first portion contact hole CNT1 (e.g., the first contact hole CNT1) that exposes the first conductive layer M1. The upper conductive layer UM and the first conductive layer M1, which will be described below, may be connected to each other at the first portion contact hole CNT1.

[0089] The second portion 114b may be arranged to cover the upper surface and the side surface of the second conductive layer M2. The second portion 114b may cover one or more side surfaces of the second conductive layer M2 and may be arranged at a part of the space SPC. Similarly to the first portion 114a, the second portion 114b may include a second portion contact hole CNT2 (e.g., the second contact hole CNT2) that exposes the second conductive layer M2. The upper conductive layer UM and the second conductive layer M2, which will be described below, may be connected to each other at the second portion contact hole CNT2.

[0090] The first insulating layer 114 including the first portion 114a and the second portion 114b may include an inorganic insulating material such as SiO x , SiN x , SiON, Al2O3, TiO2, Ta2O5, HfO2, ZnO2, etc. The first insulating layer 114 may include a single layer or multiple layers including the above inorganic insulating materials. The first insulating layer 114 may include the same material as the second gate insulating layer 115 that will be described below. The first insulating layer 114 may be provided or formed simultaneously with the second gate insulating layer 115 so as to be provided in the same layer as the second gate insulating layer 115, as will be described below.

[0091] The first insulating layer opening portion OP1 may be disposed in the first insulating layer 114 to correspond to the space SPC. The size of the first insulating layer opening portion OP1 (e.g., the distance intercepted between the sidewalls of the first insulating layer 114 along the substrate 110 at the space SPC) may be smaller than the size of the space SPC (e.g., the distance intercepted between the sidewalls of the lower conductive layer M along the substrate 110). In one embodiment, for example, the center of the first insulating layer opening portion OP1 may correspond to the center of the space SPC. The distance between the center of the first insulating layer opening portion OP1 and the end of the first insulating layer opening portion OP1 (e.g., at the sidewall of the first insulating layer 114) may be smaller than the distance between the center of the space SPC and the side surface of the first conductive layer M1 which is the sidewall of the lower conductive layer M. As another example, the distance between the center of the first insulating layer opening portion OP1 and the end of the first insulating layer opening portion OP1 may be smaller than the distance between the central axis of the space SPC and the side surface of the second conductive layer M2 which is the sidewall of the lower conductive layer M.

[0092] The first insulating layer opening portion OP1 may not overlap with the first conductive layer M1 or the second conductive layer M2, that is, it may be spaced apart from the first conductive layer M1 or the second conductive layer M2 along the substrate 110. The upper conductive layer UM to be described below may be disposed on the first insulating layer opening portion OP1 and extend into the first insulating layer opening portion OP1. Thus, the first conductive layer M1 and the second conductive layer M2 may be spaced apart from the upper conductive layer UM and shielded by the upper conductive layer UM.

[0093] The second insulating layer 116 may cover the first insulating layer 114. Moreover, similar to the first insulating layer 114, the second insulating layer 116 may include a first insulating portion 116a and a second insulating portion 116b. The second insulating layer 116 may have a second insulating layer opening portion OP1' (e.g., the second opening OP1') to correspond to the first insulating layer opening portion OP1.

[0094] The first insulating portion 116a may be disposed on the first portion 114a. One side of the first insulating portion 116a may include a third cutting surface CA3. As described above, the third cutting surface CA3 may be disposed in the same plane as the first cutting surface CA1. The first cutting surface CA1, the second cutting surface CA2, and the third cutting surface CA3 may form a single side surface CA in a single plane, but is not limited thereto.

[0095] In one embodiment, for example, the side surface of the first insulating portion 116a may include a third cutting surface CA3 and a second side surface opposite to the third cutting surface CA3, the second side surface being closer to the display area DA than the third cutting surface CA3 and being disposed at the space SPC. Similarly to the first portion 114a, the first insulating portion 116a may include a first insulating portion contact hole CNT1' (e.g., a third contact hole CNT1'). The first insulating portion contact hole CNT1' may be connected to the first portion contact hole CNT1, for example, to form a single contact hole. Additionally, an upper conductive layer UM and a first conductive layer M1, which will be described below, may be connected to each other at the first insulating portion contact hole CNT1'.

[0096] The second insulating portion 116b may be disposed on the second portion 114b and may partially overlap with the space SPC. Similarly to the second portion 114b, the second insulating portion 116b may include a second insulating portion contact hole CNT2' (e.g., a fourth contact hole CNT2'). The second insulating portion contact hole CNT2' may be connected to the second portion contact hole CNT2, for example, to form a single contact hole. Additionally, an upper conductive layer UM and a second conductive layer M2, which will be described below, may be connected to each other at the second insulating portion contact hole CNT2'.

[0097] However, the embodiments are not limited thereto. There may be at least one of each of the second portion contact hole CNT2 and the second insulating portion contact hole CNT2'. Accordingly, there may be two single contact holes, each provided by a second insulating portion contact hole CNT2' connected to the second portion contact hole CNT2 and each exposing the second conductive layer M2. The two single contact holes may be spaced apart from each other along the substrate 110. Thus, various modifications may be made.

[0098] The second insulating layer 116 including the first insulating portion 116a and the second insulating portion 116b may include SiO2, SiN x , SiON, Al2O3, TiO2, TA2O5, HfO2, or ZnO2. The second insulating layer 116 may include the same material as the interlayer insulating layer 117, which will be described below. The second insulating layer 116 may be provided or formed simultaneously with the interlayer insulating layer 117 to be disposed in the same layer as the interlayer insulating layer 117.

[0099] The second insulating layer opening portion OP1' may be disposed in the second insulating layer 116 to correspond to the space SPC. The second insulating layer opening portion OP1' may be connected to the first insulating layer opening portion OP1 to form a single opening portion. Similarly to the first insulating layer opening portion OP1, an upper conductive layer UM, which will be described below, may be disposed on the second insulating layer opening portion OP1' and extend into the second insulating layer opening portion OP1'.

[0100] The upper conductive layer UM may be disposed on the second insulating layer 116 and may also be disposed in each of the first partial contact hole CNT1, the first insulating partial contact hole CNT1', the second partial contact hole CNT2, the second insulating partial contact hole CNT2', the first insulating layer opening portion OP1, and the second insulating layer opening portion OP1'. In one embodiment, for example, the upper conductive layer UM may be integrally or commonly disposed along the side surface of the first portion 114a, the side surface of the first insulating portion 116a, the side surface of the second portion 114b, and the side surface of the second insulating portion 116b at the space SPC.

[0101] The upper conductive layer UM may be electrically connected to the first conductive layer M1 and the second conductive layer M2. The upper conductive layer UM may be connected to the first conductive layer M1 at the first partial contact hole CNT1 and the first insulating partial contact hole CNT1'. Moreover, the upper conductive layer UM may be connected to the second conductive layer M2 at the second partial contact hole CNT2 and the second insulating partial contact hole CNT2'. When performing a reliability test of the display device 1, the upper conductive layer UM may be electrically connected to the first conductive layer M1 to transmit a test signal from the test pad TPAD to the pad PAD. The upper conductive layer UM may include or define a line through which the test signal is transmitted from the pad PAD to the display area DA.

[0102] The upper conductive layer UM may be disposed at the space SPC to shield the first conductive layer M1 and the second conductive layer M2. According to one embodiment, the upper conductive layer UM may form a valley portion or a concave portion to correspond to the space SPC. In one embodiment, for example, the upper conductive layer UM may contact the lower layer 112 or the buffer layer 111 at the space SPC.

[0103] The upper conductive layer UM may include a conductive material containing Mo, Al, Cu, Ti, etc., and may include a multi-layer or a single layer containing one or more of the above conductive materials. According to an embodiment, the upper conductive layer UM may include: a first layer UM1 containing titanium (e.g., the first titanium layer UM1), a second layer UM2 containing aluminum (e.g., the aluminum layer UM2) on the first titanium layer UM1, and a third layer UM3 containing titanium (e.g., the second titanium layer UM3) on the aluminum layer UM2. The upper conductive layer UM may be provided or formed simultaneously with the source electrode S and the drain electrode D to be disposed in the same layer as the source electrode S and the drain electrode D, as will be described below.

[0104] The protective layer 118 may be disposed on the upper conductive layer UM and may at least partially overlap the upper conductive layer UM. The protective layer 118 may expose the upper conductive layer UM of the pad PAD to the outside of the protective layer 118, and the pad PAD of the display panel 10 may be electrically connected to components of the display device 1, such as a printed circuit board PCB, etc.

[0105] The protective layer 118 may be disposed on the upper conductive layer tip UMT of the upper conductive layer UM, and the upper conductive layer tip UMT is the end of the upper conductive layer UM that is farthest from the display area DA (e.g., the end or edge closest to the display panel 10 where components can be attached to the display panel 10). The protective layer 118 may be disposed on the upper conductive layer tip UMT to protect the upper conductive layer tip UMT. The protective layer 118 may extend further in the direction away from the display area DA than the upper conductive layer tip UMT, and may extend in the direction towards the display area DA to terminate at a position corresponding to the space SPC or at a position outside the space SPC.

[0106] The protective layer 118 may include a single layer or multiple layers containing an organic material or an inorganic material. The protective layer 118 may include benzocyclobutene, polyimide, hexamethyldisiloxane, polymethyl methacrylate, or a general polymer, such as polystyrene, a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluoropolymer, a parylene polymer, a polyvinyl alcohol polymer, and mixtures thereof. The protective layer 118 may be provided or formed simultaneously with the planarization layer 119 on the display area DA to be disposed in the same layer as the planarization layer 119, as will be described below.

[0107] Hereinafter, reference will be made to Figure 4A and Figure 4B to describe in detail the stacked structure of the display area DA of the display device 1.

[0108] The buffer layer 111 described above may be disposed on the substrate 110, and the thin film transistor T may be disposed on the buffer layer 111. The thin film transistor T may include a semiconductor layer A, a gate electrode G, a source electrode S, and a drain electrode D.

[0109] Hereinafter, an example in which the thin film transistor T includes a top-gate thin film transistor T is shown. However, the embodiments are not limited thereto, and various types of thin film transistors including bottom-gate thin film transistors may be implemented.

[0110] In addition, hereinafter, an example in which there is one thin film transistor T is shown. However, the embodiments are not limited thereto. According to an embodiment, the display device 1 may include two or more thin film transistors T with respect to one pixel P. Various modifications may be made. In an embodiment, for example, in some embodiments, six to seven thin film transistors T may be included with respect to one pixel P.

[0111] The semiconductor layer A may include amorphous silicon or polycrystalline silicon. According to another embodiment, the semiconductor layer A may include an oxide of at least one material selected from In, Ga, Sn, Zr, V, Hf, Cd, Ge, Cr, Ti, and Zn. The semiconductor layer A may include a channel region, and a source region and a drain region each having a carrier concentration relatively higher than that of the channel region.

[0112] The gate electrode G may be disposed on the semiconductor layer A, and a first gate insulating layer 113 is between the gate electrode G and the semiconductor layer A. The gate electrode G may include Mo, Al, Cu, Ti, etc., and may include a single layer or multiple layers. In one embodiment, for example, the gate electrode G may include a single Mo layer.

[0113] The first gate insulating layer 113 may insulate the semiconductor layer A from the gate electrode G, and may include SiO2, SiN x , SiON, Al2O3, TiO2, TA2O5, HfO2, or ZnO2.

[0114] The lower conductive layer M may be provided or formed simultaneously with the gate electrode G, for example, to be disposed in the same layer as the gate electrode G. In addition, the lower layer 112 may be provided or formed simultaneously with the first gate insulating layer 113, for example, to be disposed in the same layer as the first gate insulating layer 113.

[0115] The first electrode CE1 of the storage capacitor Cst can be provided or formed, for example, in the same layer as the gate electrode G by including the same material as the gate electrode G, being provided or formed by the same material layer, etc. The second electrode CE2 of the storage capacitor Cst can overlap with the first electrode CE1, and the second gate insulating layer 115 is between the second electrode CE2 and the first electrode CE1. As described above, the first insulating layer 114 can be formed simultaneously with the second gate insulating layer 115, and thus be provided in the same layer as the second gate insulating layer 115.

[0116] Figure 4A It is shown that the storage capacitor Cst does not overlap with the thin film transistor T. However, the embodiment is not limited thereto. In one embodiment, for example, the storage capacitor Cst can overlap with the thin film transistor T. In some embodiments, the first electrode CE1 of the storage capacitor Cst can be integrated with the gate electrode G (for example, one of the first electrode CE1 and the gate electrode G extends to define a part of it as the other of the first electrode CE1 and the gate electrode G). That is, the gate electrode G of the thin film transistor T can be used as the first electrode CE1 of the storage capacitor Cst.

[0117] The interlayer insulating layer 117 can cover the second electrode CE2. The interlayer insulating layer 117 can include SiO2, SiN x , SiON, Al2O3, TiO2, Ta2O5, HfO2 or ZnO2. As described above, the interlayer insulating layer 117 can be provided or formed simultaneously with the second insulating layer 116, and thus be provided in the same layer as the second insulating layer 116.

[0118] The source electrode S and the drain electrode D (for example, electrodes) can be arranged on the interlayer insulating layer 117. The source electrode S and the drain electrode D can include a conductive material containing Mo, Al, Cu, Ti, etc., and can include a multi-layer or a single layer containing the above materials. In one embodiment, for example, the source electrode S and the drain electrode D can include a multi-layer structure containing Ti / Al / Ti. The upper conductive layer UM can be provided or formed simultaneously with the source electrode S or the drain electrode D, and thus be provided in the same layer as the source electrode S or the drain electrode D.

[0119] The planarization layer 119 may be located on the source electrode S and the drain electrode D, and the display device 300 (e.g., the display element 300) may be located on the planarization layer 119. The planarization layer 119 may include a single layer or multiple layers containing an organic material. The organic material may include general polymers such as polymethyl methacrylate or polystyrene, polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluoropolymers, parylene polymers, vinyl alcohol polymers, and mixtures thereof. Moreover, the planarization layer 119 may include a stacked structure of an inorganic insulating layer and an organic insulating layer. The protective layer 118 may be provided or formed simultaneously with the planarization layer 119 and may include the same material as the planarization layer 119 or may be provided in the same layer as the planarization layer 119.

[0120] Figure 4A It is shown that the planarization layer 119 is disposed between the thin film transistor T and the display device 300. However, the embodiments are not limited thereto, and various modifications can be made. In one embodiment, for example, the lower planarization layer and the upper planarization layer may be arranged as an aggregate of the planarization layer 119 between the thin film transistor T and the display device 300.

[0121] The display device 300 may be located on the planarization layer 119 in the display area DA of the substrate 110. The display device 300 includes a pixel electrode 310, a counter electrode 330, and an emission layer 320 between the pixel electrode 310 and the counter electrode 330 and including an emission region (e.g., a light-emitting region). The pixel electrode 310 may be electrically connected to the thin film transistor T at the opening portion in the planarization layer 119. One or more of the display device 300, the pixel electrode 310, the counter electrode 330, and the emission layer 320 may be provided in multiple numbers within the display area DA, but are not limited thereto.

[0122] The pixel electrode 310 may be a reflective electrode. In one embodiment, for example, the pixel electrode 310 may include a reflective layer containing Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and combinations thereof, and a transparent or semi-transparent electrode layer on the reflective layer. The transparent or semi-transparent electrode layer may include at least one selected from indium tin oxide (“ITO”), indium zinc oxide (“IZO”), zinc oxide (“ZnO”), indium oxide (In2O3), indium gallium oxide (“IGO”), or aluminum zinc oxide (“AZO”).

[0123] The pixel defining layer 200 may be disposed on the planarization layer 119. The pixel defining layer 200 may have or define openings corresponding to sub-pixels and / or pixels P. The openings in the pixel defining layer 200 expose a part of the pixel electrode 310 to define the light emitting region of the pixel P and / or pixel P. Moreover, the pixel defining layer 200 may increase the distance in the thickness direction between the edge of the pixel electrode 310 and the counter electrode 330 located on the pixel electrode 310 to reduce or prevent the occurrence of arcs or the like at the edge of the pixel electrode 310. The pixel defining layer 200 may include an organic material such as polyimide or hexamethyldisiloxane.

[0124] The emission layer 320 of the display device 300 may include a relatively low molecular weight material or a relatively high molecular weight material. When the emission layer 320 includes a relatively low molecular weight material, the emission layer 320 may have a structure in which each of a hole injection layer (“HIL”), a hole transport layer (“HTL”), an emission layer (“EML”), an electron transport layer (“ETL”), and an electron injection layer (“EIL”) is stacked as a single layer, or each of HIL, HTL, EML, ETL, and EIL is stacked as multiple layers, and may include various organic materials such as copper phthalocyanine (CuPc), N,N'-bis(naphthalen-1-yl)-N,N'-diphenylbenzidine (NPB), tris(8-hydroxyquinoline) aluminum (Alq3), etc. These layers may be provided or formed by using a vapor deposition method.

[0125] When the emission layer 320 includes a relatively high molecular weight material, the emission layer 320 may have a structure including, for example, an HTL and an EML. Here, the HTL may include poly(3,4-ethylenedioxythiophene), and the EML may include polymer materials such as polyphenylene vinylene-based polymer materials and polyfluorene-based polymer materials. The emission layer 320 may be provided or formed by using a screen printing method, an inkjet printing method, a laser-induced thermal imaging (“LITI”) method, etc.

[0126] The structure of the emission layer 320 is not necessarily limited thereto, and the emission layer 320 may have various structures. In addition, the emission layer 320 may include an overall layer with respect to a plurality of pixel electrodes 310, where a single emission layer 320 is commonly provided to the plurality of pixel electrodes 310, or may include layers that are separately patterned to correspond to the plurality of pixel electrodes 310, where a separate one of the layers in the emission layer 320 corresponds to the pixel electrode 310.

[0127] The counter electrode 330 may be disposed on the display area DA and may be disposed to cover the display area DA, as Figure 4AAs shown. That is, the counter electrode 330 can be an overall layer (e.g., a single layer) with respect to the plurality of display devices 300, and can correspond to each of the plurality of pixel electrodes 310.

[0128] The counter electrode 330 can include a transmissive electrode. In one embodiment, for example, the counter electrode 330 can include a transparent or semi-transparent electrode, and can include a metal thin film having a relatively low work function, such as Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, and combinations thereof.

[0129] When the pixel electrode 310 includes a reflective electrode and the counter electrode 330 includes a transmissive electrode, the light emitted from the emission layer 320 can be front-emission type light emitted toward the counter electrode 330. However, the embodiment is not limited thereto, and the light emitted from the emission layer 320 can be back-emission type light emitted toward the substrate 110. In this case, the pixel electrode 310 can include a transparent or semi-transparent electrode, and the counter electrode 330 can include a reflective electrode. Additionally, the display device 1 can be a dual-emission type display device for emitting light in both the front and back directions.

[0130] The thin film encapsulation layer 400 can cover the display area DA and a part of the non-display area NDA to reduce or prevent external moisture and oxygen from penetrating into the elements of the display device 300. The thin film encapsulation layer 400 can include at least one organic encapsulation layer and at least one inorganic encapsulation layer. Figure 4A An example is shown in which the thin film encapsulation layer 400 includes two inorganic encapsulation layers, such as a first inorganic encapsulation layer 410 and a second inorganic encapsulation layer 430, and one organic encapsulation layer 420. However, the stacking order and the number of layers are not limited to Figure 4A the embodiment shown.

[0131] The first inorganic encapsulation layer 410 can cover the counter electrode 330, and can include SiO x , SiN x and / or SiON. However, other layers such as a cover layer can be disposed between the first inorganic encapsulation layer 410 and the counter electrode 330. The first inorganic encapsulation layer 410 can be provided or formed along the structure below it (e.g., to have a profile corresponding to the profile of the stacked structure below the first inorganic encapsulation layer 410), and thus, can have an uneven upper surface, as Figure 4A shown.

[0132] The organic encapsulation layer 420 may cover the first inorganic encapsulation layer 410. Different from the first inorganic encapsulation layer 410, the organic encapsulation layer 420 may approximately have a flat upper surface. Specifically, the organic encapsulation layer 420 may approximately have a flat upper surface at a portion corresponding to the display area DA. The organic encapsulation layer 420 may include at least one material selected from polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, and hexamethyldisiloxane.

[0133] The second inorganic encapsulation layer 430 may cover the organic encapsulation layer 420 and may include SiO2, SiN x and / or SiON.

[0134] The thin film encapsulation layer 400 defines an assembly member including the first inorganic encapsulation layer 410, the organic encapsulation layer 420, and the second inorganic encapsulation layer 430. Therefore, even when cracks occur in the thin film encapsulation layer 400, due to the multi-layer structure of the thin film encapsulation layer 400 as described above, the cracks will not connect between the first inorganic encapsulation layer 410 and the organic encapsulation layer 420 or between the organic encapsulation layer 420 and the second inorganic encapsulation layer 430. Therefore, the generation of paths through which external moisture or oxygen in the thin film encapsulation layer 400 penetrates into the display area DA and the non-display area can be prevented or minimized. The second inorganic encapsulation layer 430 may contact the first inorganic encapsulation layer 410 at an edge or an end of the second inorganic encapsulation layer 430 that is located outside the display area DA. Therefore, the organic encapsulation layer 420 may not be exposed to the outside of the thin film encapsulation layer 400 and / or the display panel 10.

[0135] According to one or more embodiments, the upper conductive layer UM may be arranged to extend along the space SPC and overlap with the space SPC. The profile or shape of the upper conductive layer UM (e.g., a valley-like structure along the thickness direction) may increase the reliability of the display device 1.

[0136] After testing whether the display device 1' is operating (refer to Figure 3 ), laser trimming or the like may be performed to set or form the first cutting surface CA1 of the first conductive layer M1. Therefore, the side surface of the first conductive layer M1 may be exposed to the outside of the display device 1' via the first cutting surface CA1. The first conductive layer M1 may include a relatively highly corrosive material (e.g., Mo), and thus may be prone to corrosion. In one embodiment, for example, when the first conductive layer M1 includes Mo, due to the oxidation of Mo, the first conductive layer M1 may be peeled off from the underlying element within the stacked structure of the display device 1'. When the first conductive layer M1 is corroded and peeled off, the first portion 114a may also be peeled off from the underlying element within the stacked structure of the display device 1'.

[0137] In the comparative embodiment shown in FIG. 5, when the upper conductive layer UM does not form a valley-like structure corresponding to the space SPC, the upper conductive layer UM may not shield the first conductive layer M1 and the second conductive layer M2. When the first conductive layer M1 is etched and peeled off, the first insulating layer 114 may be peeled off. When the first insulating layer 114 is peeled off, the etching may spread to the second conductive layer M2 of the pad PAD. Therefore, the second conductive layer M2 may also be etched.

[0138] To minimize this phenomenon, according to one or more embodiments, the first insulating layer opening portion OP1 and the second insulating layer opening portion OP1' may be provided. Moreover, the upper conductive layer UM that shields the first conductive layer M1 and the second conductive layer M2 may be disposed at the space SPC. Since the upper conductive layer UM forms a valley-like structure at the first insulating layer opening portion OP1 and the second insulating layer opening portion OP1' and at the space SPC, the second conductive layer M2 may not be etched even when the first conductive layer M1 is etched. Therefore, the display device 1 including the pad region PDA containing a conductive material can have increased reliability, and the display device 1 is provided from the display device 1' including the test pad TPAD.

[0139] Figure 6A is a cross-sectional view of another embodiment of the pad region PDA of the display device 1. In Figure 6A in, reference numerals identical to those in Figure 4A and Figure 4B denote components identical to those in Figure 4A and Figure 4B and thus, the description thereof will not be repeated.

[0140] Referring to Figure 6A , the pad PAD of the display device 1 may include a first conductive layer M1 and a second conductive layer M2 spaced apart from the first conductive layer M1 in the thickness direction. Moreover, the first insulating layer opening portion OP1 and the second insulating layer opening portion OP1' may be provided corresponding to the space SPC between the first conductive layer M1 and the second conductive layer M2. The upper conductive layer UM that shields the first conductive layer M1 and the second conductive layer M2 may be disposed at the space SPC between the first conductive layer M1 and the second conductive layer M2.

[0141] According to one or more embodiments, in a single material layer disposed on a substrate 110, a first conductive layer M1 and a second conductive layer M2 may be disposed in different layers from each other. In one embodiment, for example, the first conductive layer M1 may be disposed between the lower layer 112 and the first insulating layer 114. The second conductive layer M2 may be disposed between the first insulating layer 114 and the second insulating layer 116. However, it is not limited thereto. In another embodiment, for example, the first conductive layer M1 may be disposed between the first insulating layer 114 and the second insulating layer 116, and the second conductive layer M2 may be disposed between the lower layer 112 and the first insulating layer 114. As another example, the first conductive layer M1 and the second portion 114b may be disposed on the same layer.

[0142] The second insulating portion 116b may include a second insulating portion contact hole CNT2' within the pad PAD. The second conductive layer M2 may be connected to the upper conductive layer UM at the second insulating portion contact hole CNT2'.

[0143] Since the first conductive layer M1 and the second conductive layer M2 are disposed in different layers from each other, even when the first conductive layer M1 is exposed to the outside and oxidized, the oxide does not diffuse to the second conductive layer M2. In one embodiment, for example, even when the first portion 114a or the first insulating portion 116a above the first conductive layer M1 is peeled off, the second conductive layer M2 is not affected.

[0144] Figure 6B is a cross-sectional view of still another embodiment of the pad region PDA of the display device 1.

[0145] In Figure 6B the same reference numerals as those in Figure 4A and Figure 4B denote components identical to those in Figure 4A and Figure 4B and thus, the description thereof will not be repeated.

[0146] Referring to Figure 6B , the pad PAD of the display device 1 may include a first conductive layer M1 and a second conductive layer M2 spaced apart from the first conductive layer M1. Moreover, a first insulating layer opening portion OP1 and a second insulating layer opening portion OP1' may be provided at a space SPC between the first conductive layer M1 and the second conductive layer M2, and an upper conductive layer UM layer that shields the first conductive layer M1 and the second conductive layer M2 may be disposed at the space SPC and extend into the space SPC between the first conductive layer M1 and the second conductive layer M2.

[0147] The buffer layer 111 may include a first buffer layer portion 111a and a second buffer layer portion 111b. The first buffer layer portion 111a may be disposed between the substrate 110 and the first conductive layer M1. The second buffer layer portion 111b may be disposed between the substrate 110 and the second conductive layer M2. The second buffer layer portion 111b may be arranged closer to the display area DA than the first buffer layer portion 111a.

[0148] The lower layer 112 may include a first lower layer portion 112a and a second lower layer portion 112b. The first lower layer portion 112a may be disposed between the first buffer layer portion 111a and the first conductive layer M1. The second lower layer portion 112b may be disposed between the second buffer layer portion 111b and the second conductive layer M2. The second lower layer portion 112b may be arranged closer to the display area DA than the first lower layer portion 112a.

[0149] The buffer layer 111 may include a buffer opening portion BOP corresponding to the space SPC. The buffer opening portion BOP (e.g., the buffer layer opening BOP) may be disposed between the first buffer layer portion 111a and the second buffer layer portion 111b. The lower layer 112 may include a lower opening portion UOP (e.g., the lower layer opening UOP) corresponding to the space SPC. The lower opening portion UOP may be disposed between the first lower layer portion 112a and the second lower layer portion 112b.

[0150] The buffer opening portion BOP and the lower opening portion UOP may be connected to each other. The lower opening portion UOP may be connected to the first insulating layer opening portion OP1. Thus, the buffer opening portion BOP, the lower opening portion UOP, and the first insulating layer opening portion OP1 may form a single and continuous opening portion.

[0151] The width of the first insulating layer opening portion OP1 may be greater than the width of the lower opening portion UOP. The width of the second insulating layer opening portion OP1' may be greater than the width of the first insulating layer opening portion OP1. The width of the second insulating layer opening portion OP1′ may be greater than the size (e.g., width) of the space SPC. These widths may be intercepted in the direction along the substrate 110 (e.g., Figure 6B the horizontal in

[0152] The upper conductive layer UM may be disposed at the buffer opening portion BOP and the lower opening portion UOP. Thus, the upper conductive layer UM may contact the substrate 110 at the buffer opening portion BOP and shield the first conductive layer M1 and the second conductive layer M2.

[0153] The upper conductive layer UM may be an integral layer disposed or formed to extend along the side surfaces of the first buffer layer portion 111a, the second buffer layer portion 111b, the first lower layer portion 112a, and the second lower layer portion 112b at the space SPC. Further, the upper conductive layer UM may be disposed along the side surface of the second portion 114b at the space SPC.

[0154] The upper conductive layer UM may be connected to each of the first conductive layer M1 and the second conductive layer M2. The upper conductive layer UM may be disposed on the upper surface of the first conductive layer M1 and extend to be disposed along the side surface of the first conductive layer M1. Further, the upper conductive layer UM may be disposed on the upper surface of the second conductive layer M2 and extend to be disposed along the side surface of the second conductive layer M2 at the space SPC.

[0155] After testing whether the display device 1' is operating, laser trimming or the like may be performed to set or form the first cutting surface CA1 of the display device 1. Even when the first conductive layer M1 is corroded due to the exposure of the first conductive layer M1 through the first cutting surface CA1, the corrosion does not spread to the second conductive layer M2.

[0156] Figure 7 is a cross-sectional view of another embodiment of the pad region PDA of the display device 1. In Figure 7 , reference numerals identical to those in Figure 4A and Figure 4B represent components identical to those in Figure 4A and Figure 4B , and thus, the description thereof will not be repeated.

[0157] Referring to Figure 7 , the pad PAD of the display device 1 may include a first conductive layer M1 and a second conductive layer M2 spaced apart from the first conductive layer M1. Further, a first insulating layer opening portion OP1 and a second insulating layer opening portion OP1' may be provided at the space SPC between the first conductive layer M1 and the second conductive layer M2, and an upper conductive layer UM that shields the first conductive layer M1 and the second conductive layer M2 may be disposed at the space SPC between the first conductive layer M1 and the second conductive layer M2.

[0158] According to one or more of the embodiments, a third conductive layer M3 may be disposed below the second conductive layer M2. In one embodiment, for example, the third conductive layer M3 may be disposed in the same layer as the first conductive layer M1 and may be disposed closer to the display area DA than the second conductive layer M2. As another example, the third conductive layer M3 may be in contact with the lower layer 112, but is not limited thereto. In another embodiment, the third conductive layer M3 may be disposed between the buffer layer 111 and the lower layer 112. Thus, various modifications may be made.

[0159] The third part contact hole CNT3 of the first insulating layer 114 and the third insulating part contact hole CNT3' of the second insulating layer 116 may be arranged corresponding to the third conductive layer M3. The third part contact hole CNT3 and the third insulating part contact hole CNT3' may be connected to each other. The third conductive layer M3 may be connected to the upper conductive layer UM at the third part contact hole CNT3 and the third insulating part contact hole CNT3'.

[0160] The above arrangement of the first conductive layer M1, the second conductive layer M2, and the third conductive layer M3 may reduce the height difference of the pad PAD. Additionally, even when the first cutting surface CA1 of the first conductive layer M1 is exposed and corroded, the corrosion of the first conductive layer M1 does not spread to the second conductive layer M2 or the third conductive layer M3.

[0161] The display device 1 according to one or more embodiments has been described by using terms such as the first buffer layer part 111a, the second buffer layer part 111b, the first lower layer part 112a, the second lower layer part 112b, the first part 114a, the second part 114b, the first insulating part 116a, the second insulating part 116b, etc. However, the embodiments are not limited thereto. In one embodiment, for example, the first part 114a may be understood as the first external insulating layer, the second part 114b may be understood as the first internal insulating layer, the first insulating part 116a may be understood as the second external insulating layer, the second insulating part 116b may be understood as the second internal insulating layer, the first buffer layer part 111a and the first lower layer part 112a may be understood as the external lower layer, and the second buffer layer part 111b and the second lower layer part 112b may be understood as the internal lower layer. The parts described as "internal" may be closer to the display area DA than the parts described as "external".

[0162] In one embodiment, for example, with reference to Figure 4A, the insulating layers (114 and 116) include: outer insulating layer portions (114a and 116a) corresponding to the first conductive layer M1; and inner insulating layer portions (114b and 116b) corresponding to the second conductive layer M2, and the inner insulating layer portions (114b and 116b) are spaced apart from the outer insulating layers (114a and 116a) along the substrate 110. The outer side surfaces of the first conductive layer M1 and the outer insulating layers (114a and 116a) are defined at the ends of the display device 1 (e.g., at the side surface CA), and are coplanar with each other. The inner side surfaces of the outer insulating layers (114a and 116a) are opposite to their outer side surfaces, and the inner side surfaces of the inner insulating layers (114b and 116b) face the inner side surfaces of the outer insulating layers (114a and 116a) at the space SPC. The upper conductive layer UM extends from the upper surfaces of each of the outer insulating layer and the inner insulating layer and along their inner side surfaces facing each other.

[0163] In one embodiment, for example, referring to Figure 6B , the insulating layers (114 and 116) include inner insulating layers (114b and 116b) and outer insulating layers (114a and 116a) spaced apart from each other along the substrate 110. The inner insulating layers (114b and 116b) are closer to the display area DA than the outer insulating layers (114a and 116a). The inner surfaces of the outer insulating layers (114a and 116a) and the inner insulating layers (114b and 116b) correspond to both the buffer opening portion BOP and the lower opening portion UOP, and face each other (e.g., at the space SPC), and the upper conductive layer UM extends from the buffer opening portion BOP and the lower opening portion UOP to be disposed along the inner surfaces of the outer insulating layers (114a and 114b) and the inner insulating layers (114b and 116b).

[0164] The display device 1 according to one or more embodiments may include a pad region PDA, and the pad region PDA includes an insulating layer opening structure and an upper conductive layer UM covering the insulating layer opening structure. Therefore, the display device 1 including the pad region PDA containing a conductive material at the upper conductive layer UM may have improved reliability such as corrosion resistance and peeling resistance.

[0165] However, the described effects are examples, and the scope of the present disclosure is not limited thereto.

[0166] As described above, the first end of the first signal line SL1 is connected to the pixel P, and the pad PAD is connected to the second end of the first signal line SL1. In one embodiment, the upper conductive layer UM, the second conductive layer M2, and / or the third conductive layer M3 may correspond to the first signal line SL1 ( Figure 2) The electrical signal is supplied from the pad region PDA to the display region DA through the first signal line SL1. In one embodiment, the upper conductive layer UM may extend from the pad region PDA to the display region DA to be connected to the pixel P (e.g., at the thin film transistor T), but is not limited thereto. As described above, a part of the second signal line SL2 is connected to the pad PAD and extends to the test region TA. In one embodiment, the first conductive layer M1 may correspond to the part of the second signal line SL2 ( Figure 2 ) through which the electrical signal is supplied from the test region TA to the pad region PDA, but is not limited thereto.

[0167] It should be understood that the embodiments described herein should be considered only in a descriptive sense and not for purposes of limitation. The description of the features in each embodiment should generally be considered applicable to other similar features in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

Claims

1. A display device, comprising: a substrate, comprising: a display area including thin film transistors including electrodes; a non-display area adjacent to the display area; and a pad area in the non-display area and including a lower conductive layer and an upper conductive layer facing each other, with an insulating layer between the lower conductive layer and the upper conductive layer, wherein, the lower conductive layer includes: a first conductive layer defining an end surface of the display device, and a second conductive layer closest to the first conductive layer along the substrate and spaced apart from the first conductive layer along the substrate to define a space between the first conductive layer and the second conductive layer, the insulating layer defines a first opening corresponding to the space between the first conductive layer and the second conductive layer, and the upper conductive layer in the pad area and the electrode of the thin film transistor in the display area are in the same layer, and the upper conductive layer extends into the first opening.

2. The display device according to claim 1, wherein, Within the pad area, the insulating layer defines a first contact hole and a second contact hole spaced apart from each other along the substrate, and the upper conductive layer is connected to the first conductive layer at the first contact hole and connected to the second conductive layer at the second contact hole.

3. The display device according to claim 1, wherein, within the pad area, the insulating layer includes a first insulating layer and a second insulating layer arranged along the thickness direction of the substrate.

4. The display device according to claim 3, wherein, Within the pad area, the first opening includes: a first insulating opening defined in the first insulating layer; and a second insulating opening defined in the second insulating layer, and the first insulating opening and the second insulating opening are connected to each other at the space.

5. The display device according to claim 1, wherein, the display area further includes within the thin film transistor: a gate electrode facing the electrode, with both a gate insulating layer and an interlayer insulating layer between the gate electrode and the electrode, and a semiconductor layer facing the gate insulating layer, the gate electrode being between the semiconductor layer and the gate insulating layer, and in the pad area, the insulating layer includes: a first insulating layer in the same layer as the gate insulating layer, and a second insulating layer in the same layer as the interlayer insulating layer.

6. The display device according to claim 1, further comprising: a lower insulating layer between the first conductive layer and the substrate.

7. The display device according to claim 1, wherein, within the pad area, the end of the upper conductive layer is the farthest from the display area, a protective layer is further included in the pad area, the protective layer includes an organic material and faces the insulating layer, the upper conductive layer is between the protective layer and the insulating layer, and the protective layer covers the end of the upper conductive layer.

8. The display device according to claim 1, wherein, the first conductive layer and the second conductive layer are in different layers from each other.

9. The display device according to claim 8, wherein, The display region further includes, within the thin film transistor: a gate electrode facing the electrode, with both a gate insulating layer and an interlayer insulating layer therebetween between the gate electrode and the electrode, and a semiconductor layer facing the gate insulating layer, with the gate electrode therebetween between the semiconductor layer and the gate insulating layer, and in the pad region, the insulating layer includes: a first insulating layer in the same layer as the gate insulating layer, the first insulating layer being disposed between the substrate and the second conductive layer; and a second insulating layer in the same layer as the interlayer insulating layer, the second insulating layer facing the first insulating layer, with the second conductive layer therebetween between the second insulating layer and the first insulating layer.

10. The display device according to claim 9, further including, in the pad region: a lower insulating layer and a buffer layer, both between the first insulating layer and the substrate, wherein, the buffer layer defines a buffer opening portion corresponding to the space between the first conductive layer and the second conductive layer, the lower insulating layer defines a lower opening portion corresponding to the space between the first conductive layer and the second conductive layer, the buffer opening portion and the lower opening portion are connected to each other, and at the space, the upper conductive layer extends from the upper surfaces of each of the first conductive layer and the second conductive layer and along the side surfaces of each of the first conductive layer and the second conductive layer to be disposed in the buffer opening portion and the lower opening portion that are connected to each other.

11. The display device according to claim 8, wherein, the lower conductive layer further includes a third conductive layer spaced apart from the first conductive layer along the substrate, with the second conductive layer therebetween between the third conductive layer and the first conductive layer, the third conductive layer being closer to the display region than the second conductive layer, and the upper conductive layer is commonly connected to each of the first conductive layer, the second conductive layer, and the third conductive layer.

12. A display device, including: a substrate including: a display region including a thin film transistor including an electrode; a non-display region adjacent to the display region; and a pad region in the non-display region, the pad region including: a lower conductive layer facing an upper conductive layer, with an insulating layer therebetween between the lower conductive layer and the upper conductive layer, the lower conductive layer including: a first conductive layer defining an end surface of the display device; and a second conductive layer in a different layer from the first conductive layer and spaced apart from the first conductive layer along the substrate to define a space between the first conductive layer and the second conductive layer; and a lower insulating layer and a buffer layer, both between the substrate and the first conductive layer, the buffer layer defines a buffer opening portion corresponding to the space between the first conductive layer and the second conductive layer, and The lower insulating layer defines a lower opening portion corresponding to the space between the first conductive layer and the second conductive layer. Wherein, the buffer opening portion and the lower opening portion are connected to each other, and the upper conductive layer is in the same layer as the electrode of the thin film transistor and extends into both the buffer opening portion and the lower opening portion.

13. The display device according to claim 12, wherein, within the pad region, the upper conductive layer is commonly connected to the first conductive layer and the second conductive layer.

14. The display device according to claim 13, wherein, Within the pad region, the insulating layer is disposed between the lower insulating layer and the second conductive layer, the insulating layer includes an inner insulating layer and an outer insulating layer spaced apart from each other along the substrate, and the inner insulating layer is closer to the display region than the outer insulating layer, the inner surfaces of the outer insulating layer and the inner insulating layer correspond to both the buffer opening portion and the lower opening portion and face each other, and the upper conductive layer extends from the buffer opening portion and the lower opening portion to be disposed along the inner surfaces of the outer insulating layer and the inner insulating layer.

15. The display device according to claim 12, wherein, within the pad region, the end of the upper conductive layer is the farthest from the display region, a protective layer is further included in the pad region, the protective layer includes an organic material and faces the insulating layer, the upper conductive layer is between the protective layer and the insulating layer, and the protective layer covers the end of the upper conductive layer.

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