Semiconductor device and method of manufacturing semiconductor device

Abstract

Semiconductor device and method of manufacturing the same. A semiconductor device comprising: a first electronic device, the first electronic device comprising a first surface and a second surface opposite the first surface; and a barrier, the barrier coupled to the second surface of the first electronic device and comprising: a first film, the first film comprising: a first barrier; and first barrier strands, the first barrier strands being bounded by the first barrier and defining first perforations, wherein at least one first perforation has a first dimension between a pair of adjacent first barrier strands; and a reduction structure, the reduction structure coupled to the first film to reduce the first dimension. Other examples and related methods are also disclosed herein.

Description

Technical Field

[0001] The present disclosure relates generally to electronic devices, and more particularly to semiconductor devices and methods for manufacturing semiconductor devices. Background Art

[0002] Existing semiconductor packages and methods for forming semiconductor packages have deficiencies such as excessive cost, reduced reliability, relatively low performance, or package size that is too large. Additional limitations and disadvantages of conventional and traditional methods will become apparent to those skilled in the art by comparing such methods with the present disclosure and referring to the accompanying drawings. Summary of the invention

[0003] In an example disclosed herein, a semiconductor device includes: a first electronic device, the first electronic device including a first surface and a second surface opposite to the first surface; and a blocking member, the blocking member coupled to the second surface of the first electronic device and including: a first film, the first film including: a first blocking body; and a first blocking strand, the first blocking strand being defined by the first blocking body and defining a first perforation, wherein at least one first perforation has a first dimension between a pair of adjacent first blocking strands; and a reducing structure, the reducing structure coupled to the first film to reduce the first dimension.

[0004] In the semiconductor device of the example, the first electronic device includes a cavity extending partially inward from the second surface to provide a membrane adjacent to the first surface; and the barrier extends across the cavity.

[0005] The semiconductor device in the example further includes: a packaging structure, the packaging structure including: a base substrate, the base substrate including a dielectric structure, a conductive structure and a via, the via extending through a portion of the base substrate, wherein the first electronic device is coupled to the base substrate so that the diaphragm is connected to the via.

[0006] In the semiconductor device in the example, the base substrate further includes a groove disposed around the perimeter of the via; the blocking member further includes a protrusion pattern having a plurality of protrusions separated by a plurality of concave portions; and the protrusion pattern is coupled to the base substrate within the groove.

[0007] In the semiconductor device of the example, the package structure further includes a cover structure coupled to the base substrate; the cover structure includes a second conductive structure; and the first electronic device is electrically coupled to the second conductive structure.

[0008] In the semiconductor device in the example, the blocking member further includes: a protrusion pattern having a plurality of protrusions separated by a plurality of concave portions.

[0009] In the semiconductor device in the examples disclosed herein, the barrier further includes a reinforcement member disposed adjacent to the first barrier; and the protrusion pattern is integrated with the reinforcement member.

[0010] In the semiconductor device in the example, the barrier further includes a reinforcement member disposed adjacent to the first barrier; and the protrusion pattern is a separate layer on the reinforcement member.

[0011] In the semiconductor device of the example, the reduction structure includes: one or more conformal film layers disposed on the first barrier strand.

[0012] In the semiconductor device of the example, the one or more conformal film layers are further disposed over the first barrier.

[0013] In the semiconductor device of the example, a side surface of each of the first barrier strands is exposed from the one or more conformal film layers.

[0014] In the semiconductor device in the example, the reduction structure includes a second film, the second film having a second blocking strand, the second blocking strand being disposed on the first blocking strand and at least partially overlapping the first blocking strand; the second blocking strand defining a second perforation; and the second perforation being laterally offset relative to the first perforation.

[0015] In the semiconductor device in the example, the second film further includes a second barrier disposed on the first barrier; and the barrier further includes a reinforcing member disposed on the second barrier.

[0016] In the semiconductor device of the example, the first electronic device includes a micro-electromechanical system (MEMS) sensor; and the barrier includes one or more dielectric materials.

[0017] In another example disclosed herein, an electronic device includes: a first electronic device, the first electronic device including a first surface and a second surface opposite to the first surface and a cavity, the cavity partially extending inward from the second surface to provide a membrane adjacent to the first surface; and a barrier, the barrier coupled to the second surface of the first electronic device, wherein the barrier extends across the cavity and includes: a first film, the first film comprising: a first barrier body; and a first barrier strand, the first barrier strand being defined by the first barrier body and defining a first perforation; and one or more of the following: a protruding pattern, the protruding pattern having an outer surface including a non-planar shape; one or more conformal film layers, the one or more conformal film layers being disposed on the first barrier strand; or a second barrier strand, the second barrier strand being located on the first barrier strand and defining a second perforation laterally offset from the first perforation.

[0018] In the electronic device in the other example, the electronic device includes the protruding pattern; the blocking member further includes a reinforcing member disposed on the first blocking body; the protruding pattern includes a plurality of protruding portions separated by a plurality of concave portions; and the protruding pattern is connected to the reinforcing member.

[0019] In the electronic device in the other example, the electronic device includes the one or more conformal film layers, and the one or more conformal film layers include: a first conformal film layer, the first conformal film layer having a first electrical polarity; and a second conformal film layer, the second conformal film layer is disposed on the first conformal film layer and has a second electrical polarity opposite to the first electrical polarity.

[0020] In the electronic device in the other example, the electronic device includes the second blocking strand; the blocking member further includes: a second blocking body, the second blocking body is disposed on the first blocking body; and a reinforcing member, the reinforcing member is disposed on the second blocking body.

[0021] In another example disclosed herein, a method of forming an electronic device includes: providing a first electronic device, the first electronic device including a first surface and a second surface opposite to the first surface and a cavity, the cavity extending partially inward from the second surface to provide a membrane adjacent to the first surface; and providing a barrier, the barrier coupled to the second surface of the first electronic device, the barrier including: a film, the film containing: a first barrier body; and a first barrier strand, the first barrier strand defining a first perforation; and one or more of the following: a protruding pattern, the protruding pattern having an outer surface including a non-planar shape; one or more conformal film layers, the one or more conformal film layers being disposed on the first barrier strand; or a second barrier strand, the second barrier strand being located on the first barrier strand and defining a second perforation laterally offset relative to the first perforation.

[0022] In the method in the further example, providing the blocking member includes: disposing the first electronic device among a plurality of electronic devices in the form of a portion of a semiconductor wafer, the first electronic device including the cavity extending partially inward from the second surface; providing a first material layer adjacent to the second surface to enclose the cavity; forming the first through-hole in the first material layer to establish the first blocking body and the first blocking line strand; attaching the semiconductor wafer to a carrier substrate; and singulating the semiconductor wafer to provide the first electronic device, wherein the singulating step includes singulating through the first material layer.

[0023] In yet another example, an electronic device includes a semiconductor sensor device having a cavity that extends partially inward from one surface to provide a diaphragm adjacent to an opposing surface. A barrier is disposed adjacent to the one surface and extends across the cavity, the barrier having a membrane having a barrier body and a first barrier strand bounded by the barrier body to define a first perforation. The electronic device further includes one or more of: a protruding pattern disposed adjacent to the barrier structure, the protruding pattern may include a plurality of protruding portions separated by a plurality of recessed portions; one or more conformal film layers disposed on the first barrier strand; or a second barrier strand disposed on the first barrier strand and at least partially overlapping the first barrier strand. The second barrier strand defines a second perforation laterally offset from the first perforation. Other examples and related methods are also disclosed herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A cross-sectional view of an example semiconductor device is shown.

[0025] Figure 2 A cross-sectional view of an example semiconductor device is shown.

[0026] Figure 3 A cross-sectional view of an example semiconductor device is shown.

[0027] Figure 4A , 4B , 4C, 4D, 4E, 4F, and 4G illustrate cross-sectional views of an example method for fabricating an example semiconductor device.

[0028] Figure 5 A cross-sectional view of an example method for fabricating an example semiconductor device is shown.

[0029] Figure 6 A cross-sectional view of an example method for fabricating an example semiconductor device is shown.

[0030] Figure 7 A cross-sectional view of an example semiconductor device is shown.

[0031] Fig. 8A is an enlarged cross-sectional view of an example barrier.

[0032] Figure 8B yes Fig. 8A Bottom view of an example barrier.

[0033] Fig. 9 A cross-sectional view of an example semiconductor device is shown.

[0034] Fig.10 A cross-sectional view of an example semiconductor device is shown.

[0035] Fig.11A , 11B , 11C, 11D, 11E, 11F, 11G, 11H, and 11I illustrate cross-sectional views and top views of an example method for making an example barrier.

[0036] Fig. 12A , 12B , 12C, 12D, and 12E illustrate cross-sectional and top views of an example method for making an example barrier.

[0037] Fig.13A and 13B A cross-sectional view of an example method for making an example barrier is shown.

[0038] Fig.14A , 14B , 14C, 14D, 14E and 14F illustrate cross-sectional and top views of an example method for making an example barrier.

[0039] Fig.15 is an enlarged cross-sectional view of an example barrier. DETAILED DESCRIPTION

[0040] The following discussion provides various examples of semiconductor devices and methods of manufacturing semiconductor devices. Such examples are non-limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "example" and "for example" are non-limiting.

[0041] The accompanying drawings illustrate general construction methods, and descriptions and details of known features and techniques may be omitted to avoid unnecessarily obscuring the present disclosure. In addition, the elements in the accompanying drawings are not necessarily drawn to scale. For example, the size of some of the elements in the accompanying drawings may be enlarged relative to other elements to help improve the understanding of the examples discussed in the present disclosure. The same reference numerals in different drawings represent the same elements.

[0042] The term “and / or” includes any single item or any combination of items in the list connected by “and / or.” As used in the present disclosure, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise.

[0043] The terms “comprises,” “comprising,” “includes,” and / or “including” are “open” terms and specify the presence of stated features, but do not preclude the presence or addition of one or more other features.

[0044] The terms "first", "second", etc. may be used herein to describe various elements, and these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present disclosure, the first element discussed in the present disclosure may be referred to as the second element.

[0045] Unless otherwise indicated, the term "coupled" may be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly connected through one or more other elements. For example, if element A is coupled to element B, element A may directly contact element B or be indirectly connected to element B through an intermediate element C. Similarly, the terms "above" or "on" may be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly connected through one or more other elements. It should be further understood that the examples appropriately shown and described below may have examples and / or may be practiced in the absence of any element not specifically disclosed herein.

[0046] The present specification includes packaged electronic device structures and associated methods and other features including a barrier disposed adjacent to a surface of an electronic device. In some instances, the electronic device is a sensor device having a cavity and a diaphragm, and the barrier extends across the cavity. In some instances, the barrier includes a film having a barrier body and a first barrier strand, the first barrier strand being bounded by the barrier body and defining a first perforation. In some instances, a conformal film layer may be added to the first barrier strand to reduce the size of the first perforation. In other embodiments, a second barrier strand may be added to the first barrier strand and the second barrier strand at least partially overlaps the first barrier strand. The second barrier strand defines a second perforation that is laterally offset from the first perforation.

[0047] In some instances, a protruding pattern is disposed in the form of a portion of the barrier, and the protruding pattern can be configured to reduce the contact area of ​​the barrier with a contact film used during manufacturing. This advantageously increases the ease with which an electronic die can be removed from the contact film during, for example, a pick-and-place process. In other instances, a blocking structure can be formed when the electronic device is in the form of a portion of a semiconductor wafer or in the form of a wafer among a plurality of electronic devices to improve the manufacturability of the electronic device. In other instances, the barrier includes a reinforcing structure for increasing the rigidity of the membrane. The barrier is configured to prevent or reduce the likelihood that contaminants such as particles will reach, contact or interfere with the diaphragm, etc. of the electronic device, thereby improving the reliability of the device.

[0048] More specifically, in one example, a semiconductor device includes a first electronic device, the first electronic device including a first surface and a second surface opposite the first surface. A barrier is disposed adjacent to the second surface of the first electronic device and the barrier includes a first film, the first film having a first barrier body and a first barrier strand, the first barrier strand being bounded by the first barrier body and defining a first perforation, wherein at least one first perforation has a first dimension between a pair of adjacent first barrier strands. The structure includes a reduction structure, the reduction structure being coupled to the first film to reduce the first dimension. In other examples, the reduction structure may include one or more conformal film layers on the first barrier strand. In other examples, the reduction structure may include a second barrier strand, the second barrier strand being located on the first barrier strand and defining a second perforation. The second perforation is laterally offset from the first perforation. In other examples, the barrier includes a protrusion pattern, the protrusion pattern having an outer surface including a non-planar shape.

[0049] In other examples, an electronic device includes a first electronic device having a first surface and a second surface opposite the first surface and a cavity, the cavity partially extending inward from the second surface to provide a diaphragm adjacent to the first surface. A barrier is disposed adjacent to the second surface of the first electronic device, wherein the barrier extends across the cavity. The barrier includes a first film, the first film including a first barrier body and a first barrier strand, the first barrier strand being bounded by the first barrier body and defining a first perforation. The barrier further includes one or more of the following: a protruding pattern having an outer surface including a non-planar shape; one or more conformal film layers, the one or more conformal film layers being disposed on the first barrier strand; or a second barrier strand, the second barrier strand being located on the first barrier strand and defining a second perforation laterally offset from the first perforation. In some examples, the protruding pattern includes a plurality of protruding portions separated by a plurality of concave portions.

[0050] In another example, a method of forming an electronic device includes providing a first electronic device having a first surface and a second surface opposite the first surface and a cavity extending partially inward from the second surface to provide a membrane adjacent to the first surface. The method includes providing a barrier coupled to the second surface of the first electronic device, the barrier including a film including a first barrier body and a first barrier strand defining a first perforation; and one or more of: a raised pattern having an outer surface including a non-planar shape; one or more conformal film layers disposed on the first barrier strand; or a second barrier strand located on the first barrier strand and defining a second perforation laterally offset relative to the first perforation.

[0051] The present disclosure includes other examples. Such examples may be found in the drawings, claims, and / or description of the present disclosure.

[0052] Figure 1 A cross-sectional view of an example packaged electronic device 100 (eg, semiconductor device 100) is shown. Figure 1 In the example shown, the semiconductor device 100 may include electronic devices 110 and 180 , an interconnect 130 , a base substrate 140 , a barrier 190 , and a cap structure 160 .

[0053] The electronic device 110 may include an interconnect 115, a cavity 117, and a diaphragm 119. The electronic device 180 may include a corresponding device interconnect 125. The base substrate 140 may include a dielectric structure 141, a conductive structure 142 (such as a base interconnect 1421, a trace 1422, a through hole 1423, or an external interconnect 1424), and a passage 143. The barrier or barrier structure 190 may include: a barrier perforation 121; a barrier film 120, a barrier strand or a barrier strand structure 122; and a barrier body 123. In some examples, the barrier strand structure 122 defines a plurality of perforations or perforated portions 121. The cover structure 160 may include a cover wall 161 and a side wall 162. In some examples, an adhesive 170 may be interposed between the electronic device 110 and the base substrate 140, and / or an adhesive 170 may be interposed between the electronic device 180 and the base substrate 140. The base substrate 140 and / or the cap structure 160 may be commonly applied to the example semiconductor devices disclosed in the present disclosure.

[0054] The base substrate 140, the barrier 190, and the cap structure 160 may define or be referred to as a semiconductor package for the semiconductor device 100, and such a package may provide protection for the electronic devices 110 and 180 and the interconnect 130 from external elements and / or environmental exposure. In addition, such a semiconductor package may provide electrical coupling between an external electrical component (not shown) and the external interconnect 1424.

[0055] Figure 2 A cross-sectional view of an example packaged electronic device 200 (eg, semiconductor device 200) is shown. Figure 2 In the example shown, the semiconductor device 200 may include electronic devices 110 and 180 , an interconnect 130 , a base substrate 240 , a barrier 190 , and a cap structure 260 .

[0056] Base substrate 240 may be similar to base substrate 140 and may include dielectric structure 241 and conductive structure 2415 (with base interconnect 1421, trace 1422, through hole 1423) and via 143. Cap structure 260 may include cap wall 261 and sidewall 262. Cap wall 261 may include conductive structure 2615 with trace 1422, through hole 1423 and external interconnect 1424. Sidewall 262 may include vertical paths 2625 and 2626. In some examples, vertical paths 2625 and 2626 may electrically connect and / or be interposed between trace 1422 of conductive structure 2415 of base substrate 240 and trace 1422 of conductive structure 2615 of cap wall 261. Base substrate 240 and / or cap structure 260 may be commonly applied to example semiconductor devices disclosed in the present disclosure.

[0057] Figure 3A cross-sectional view of an example packaged electronic device 300, such as a semiconductor device 300, is shown. Figure 3 In the example shown, the semiconductor device 300 may include the electronic devices 110 and 180 , the interconnect 130 , a base substrate 340 , a barrier 190 , and a cap structure 360 ​​.

[0058] The base substrate 340 may include a bottom wall 341 and a side wall 342 as a single integral piece. In some examples, the bottom wall 341 may be similar to the base substrate 140 and / or 240, and the side wall 342 may be similar to the side wall 262. The base substrate includes a conductive structure 3415 having a base interconnect 1421, a trace 1422, and a vertical path 2625, and a via 143. The cap structure 360 ​​may include or be similar to the cap wall 261, having a conductive structure 2615 with a trace 1422, a through hole 1423, and an external interconnect 1424. The vertical path 2625 of the side wall 342 may be interposed between the trace 1422 of the base substrate 340 and the trace 1422 of the cap wall 261. The base substrate 340 and / or the cap structure 360 ​​may be commonly applied to the example semiconductor devices disclosed in the present disclosure.

[0059] Figures 4A to 4G A cross-sectional view of an example method for manufacturing a packaged electronic device, such as a packaged semiconductor device, is shown. Figures 4A-4G Some of the described elements or steps may be compatible with or applicable to the fabrication of other semiconductor devices described in the present disclosure. Figure 4A A cross-sectional view is shown at an early stage in the manufacturing method.

[0060] exist Figure 4A In the example shown, the electronic device 110 may include a MEMS (micro-electromechanical system) sensor. In some examples, the MEMS sensor 110 may be referred to as or may include an acoustic sensor (e.g., a microphone), an environmental sensor (e.g., a pressure sensor or a gas sensor), or a motion sensor (e.g., an accelerometer or a gyroscope sensor). In some examples, the MEMS sensor 110 may include silicon, polymers, metals, and / or ceramics, and may be part of a circular or rectangular wafer containing multiple sensors. For example, the MEMS sensor 110 may include a semiconductor die. In Figure 4A , three MEMS sensors 110 are shown side by side, but the present disclosure does not limit the number of MEMS sensors 110 to three (3). In other examples, one MEMS sensor 110 or four or more MEMS sensors 110 may be provided. In some examples, the MEMS sensor 110 is provided in the form of a portion of a semiconductor substrate such as a silicon wafer.

[0061] Example processes for forming the MEMS sensor 110 may include: semiconductor manufacturing processes; deposition processes, such as physical deposition or chemical deposition; photolithography processes, such as photolithography, electron beam lithography, ion beam lithography, or X-ray lithography; patterning processes, such as diamond patterning; and / or etching processes. The thickness and width of the MEMS sensor 110 may be in the range of about 50 microns (micron or micrometer) to about 200 microns. In some instances, the MEMS sensor 110 may sense external sound, environment, or motion and convert it into an electrical signal to output the electrical signal to an external device and / or the electronic device 180.

[0062] In some examples, the MEMS sensor 110 may include a device interconnect 115 formed on a first surface. The device interconnect 115 may be referred to as or may include a pad, a solder ring, or a bump. In some examples, the MEMS sensor 110 may include a cavity 117 formed on a second surface opposite to the first surface or extending inwardly from the second surface. The depth of the cavity 117 may be less than the thickness of the MEMS sensor 110. An example process for forming the cavity 117 may include anisotropic etching and / or isotropic etching. In some examples, the MEMS sensor 110 may include a thin diaphragm 119 left due to the formation of the cavity 117. In some examples, the diaphragm 119 may be deformed or bent due to external sound, environment, or movement, and the output voltage and / or resistance value based on the diaphragm 119 may change and may be monitored by an internal or external circuit system. As will be described later, the electronic device 180 may monitor and control the MEMS sensor 110.

[0063] Figure 4B A cross-sectional view is shown at a later stage in the manufacturing method. Figure 4B In the example shown, a material layer such as a dielectric film 120A may be laminated on or near the surface of the MEMS sensor 110, and the cavity 117 may be closed by the dielectric film 120A. In some examples, the dielectric film 120A may be referred to as or may include a polyimide (PI) film, a polyethylene (PE) film, a polypropylene (PP) film, a benzocyclobutene (BCB) film, a polybenzoxazole (PBO) film, a bismaleimide triazine (BT) film, an epoxy resin film, a phenol resin film, a silicone resin film, or an acrylate polymer film. The thickness of the dielectric film 120A may be in the range of about 1 micrometer to about 10 micrometers.

[0064] Figure 4C A cross-sectional view is shown at a later stage in the manufacturing method. Figure 4CIn the example shown, a plurality of openings such as blocking perforations 121 are formed in the thin dielectric film 120A, thereby defining a blocking member 190. In some examples, the blocking member 190 may be referred to as or may include a membrane 120, a film, or a selective blocking member. In some examples, the membrane 120 may include a blocking perforation 121, a blocking strand structure 122, and a blocking body 123. The blocking strand structure is disposed in the blocking perforation 121 to subdivide the blocking perforation 121 into a plurality of openings. This reduces the amount of open area in the blocking perforation 121. The blocking body 123 of the membrane 120 may be attached to the MEMS sensor 110. In some examples, the cavity 117 and the diaphragm 119 of the MEMS sensor 110 may be connected to the external environment through the plurality of blocking perforations 121 formed in the membrane 120. In some examples, the diaphragm 119 of the MEMS sensor 110 may be deformed or bent due to an external force (e.g., air pressure) acting on the plurality of blocking perforations 121 formed in the membrane 120. However, the size of the barrier perforations 121 is limited so that the barrier strand structure 122 will prevent foreign material from reaching the septum 119 or cavity 117. The diameter, width and / or spacing of the barrier perforations 121 and / or barrier strand structure 122 may be in the range of about 1 micron to about 10 microns.

[0065] Figure 4D A cross-sectional view is shown at a later stage in the manufacturing method. Figure 4D In the example shown, the MEMS sensor 110 and the stopper 190 may be singulated together while being attached to a carrier substrate (e.g., a mounting film 901 attached to a frame), thereby defining independent MEMS sensors 110 each having a corresponding stopper 190. In some examples, the device interconnects 115 and the diaphragm 119 of the MEMS sensor 110 may be directly attached to the mounting film 901.

[0066] Figure 4E A cross-sectional view is shown at a later stage in the manufacturing method. Figure 4E In the example shown, the MEMS sensor 110 with the barrier 190 can be attached to the base substrate 140. In some examples, the MEMS sensor 110 can be attached to the base substrate 140 by the adhesive 170. In some examples, the electronic device 180 can be attached to the base substrate 140 before or after the MEMS sensor 110 is attached. In some examples, the electronic device 180 can be attached to the base substrate 140 by the adhesive 170.

[0067] In some examples, the electronic device 180 may be referred to as or may include a controller device, a logic die, a memory, a digital signal processor, a network processor, a power management unit, an audio processor, an RF circuit, a wireless baseband system-on-chip processor, or an application-specific integrated circuit (ASIC). The controller device 180 may include a device interconnect 125 formed on its surface. The device interconnect 125 may be referred to as or may include a pad, a solder ring, or a bump. The thickness of the controller device 180 may be in the range of about 50 microns to about 200 microns. The controller device 180 may process the electrical signal input from the MEMS sensor 110 and output the result from such processing to an external device.

[0068] In some examples, the MEMS sensor 110 having the blocking member 190 may be attached to a peripheral portion of an area corresponding to the via 143 of the base substrate 140. In some examples, the blocking member 190 may be adhered to the base substrate 140 by the adhesive 170. In some examples, the blocking body 123 of the blocking member 190 may be adhered to a predetermined area of ​​the base substrate 140 disposed outside the via 143 by the adhesive 170.

[0069] The base substrate 140 may be formed as a substantially planar panel having a passage 143. In some instances, the diameter of the passage 143 may be in the range of about 1 micron to about 50 microns. External force or pressure may be transmitted to the MEMS sensor 110 through the passage 143 disposed in the base substrate 140. The base substrate 140 may be referred to as or may include a laminate substrate, a circuit board, or a wiring board. The base substrate 140 may include a dielectric structure 141 and a conductive structure 142. In some instances, the dielectric structure 141 may be referred to as or may include Si3N4, SiO2, SiON, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), epoxy resin, phenol resin, silicone resin, or acrylate polymer. The thickness of the dielectric structure 141 may be in the range of about 50 microns to about 1000 microns. The dielectric structure 141 may support the MEMS sensor 110, the controller device 180, and the conductive structure 142 and may prevent electrical short circuits from occurring. Conductive structure 142 may be referred to as or may include a circuit pattern or a wiring pattern. Conductive structure 142 may include a substrate interconnect 1421 and a trace 1422 formed on a first surface of dielectric structure 141. In addition, substrate interconnect 1421 may be referred to as or may include a pad, a solder ring, or an under-bump metallization layer (UBM). In addition, conductive structure 142 may further include an external interconnect 1424 formed on a second surface opposite to the first surface. External interconnect 1424 may be referred to as or may include a pad, a solder ring, or a bump. In addition, conductive structure 142 may further include at least one through hole 1423 and / or at least one trace 1422. As an example, at least one through hole 1423 may connect trace 1422 and external interconnect 1424 to each other. Through hole 1423 and / or trace 1422 may be formed inside dielectric structure 141. In some examples, conductive structure 142 may include titanium, tungsten, titanium / tungsten, copper, gold, silver, palladium, and / or nickel. Additionally, the thickness and width of conductive structure 142 may be in a range of about 2 microns to about 20 microns. Conductive structure 142 may electrically connect MEMS sensor 110 and controller device 180 to an external device including, for example, a next level assembly such as a printed circuit board or another electronic device.

[0070] Figure 4F A cross-sectional view is shown at a later stage in the manufacturing method. Figure 4FIn the example shown, the device interconnect 115 of the MEMS sensor 110 and the base interconnect 1421 of the base substrate 140 may be connected to each other through the interconnect 130. The interconnect 130 may be referred to as or may include wire bonding. In addition, the device interconnect 125 of the controller device 180 and the base interconnect 1421 of the base substrate 140 may be electrically connected to each other through the interconnect 130. In some examples, the interconnect 130 may electrically connect the device interconnect 115 of the MEMS sensor 110 and the interconnect 125 of the controller device 180 directly to each other.

[0071] In some examples, interconnect 130 may be referred to as or may include a gold wire, a silver wire, a copper wire, or an aluminum wire. The diameter of interconnect 130 may be in a range of about 1 micron to about 20 microns.

[0072] In some examples, the controller device 180 can be attached to the base substrate 140 in a flip chip configuration. In the flip chip example, the controller device 180 can be electrically connected to the base interconnect 1421 through an interconnect, such as a bump, a pillar, a stud (not shown), or other connection structures known to those of ordinary skill in the art.

[0073] Figure 4G A cross-sectional view at a later stage of the manufacturing method is shown. A semiconductor device 100 may be defined at this stage, the semiconductor device having a cover structure 160 attached to the base substrate 140 while covering the MEMS sensor 110 and the controller device 180. The cover structure 160 may include a top wall 161 and a side wall 162 attached to the surface of the base substrate 140. In some instances, the side wall 162 may be attached to the surface of the base substrate 140 by an adhesive. In some instances, the cover structure 160 may be referred to as or may include a cover, a lid, a seal, or a protector. In addition, in some instances, the cover structure 160 may be referred to as or may include polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), epoxy resin, phenolic resin, silicone resin, acrylate polymer, metal, or ceramic. The thickness of the cover structure 160 may be in the range of about 50 microns to about 1000 microns. Additionally, the height of the cap structure 160 may be in a range of about 500 microns to about 5000 microns. The cap structure 160 may protect the MEMS sensor 110, the controller device 180, and the interconnect 130 from external elements and / or environmental exposure.

[0074] Figure 5 2 shows a cross-sectional view of an example method for manufacturing an example semiconductor device 200. In some examples, before reaching Figure 5 Prior to the stage depicted, the method may include one or more of the steps described above with respect to Figures 4A-4FThe stages described are similar to the stages described in Figure 5 In the example shown, cover wall 261 can be attached to sidewall 262, and sidewall 262 can be attached to base substrate 240. In some examples, sidewall 262 can be attached to base substrate 240, and cover wall 261 can be attached to sidewall 262. In some examples, cover wall 261 and sidewall 262 can be referred to as cover structure 260.

[0075] In some instances, each of the cover wall 261 and / or the side wall 262 may be referred to as or may include a laminate substrate, a circuit board or a wiring board. The cover wall 261 and / or the side wall 262 may include features similar to the features described above with respect to the base substrate 140 and 240. For example, the dielectric material covering the wall 261 and / or the side wall 262 may include Si3N4, SiO2, SiON, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), epoxy resin, phenol resin, silicone resin or acrylate polymer. The thickness of each of the cover wall 261 and / or the side wall 262 may be in the range of about 50 microns to about 1000 microns. The cover wall 261 may include a trace 1422 formed on a first surface, an external interconnect 1424 formed on a second surface opposite to the first surface, and at least one through hole 1423 and / or trace 1422 connecting the trace 1422 and the external interconnect 1424 to each other. The external interconnect 1424 may be referred to as or may include a pad, a solder ring, or a bump. The through hole 1423 and / or the trace 1422 may be formed on the inner side of the cover wall 261. In some examples, the trace 1422, the external interconnect 1424, and the through hole 1423 may include titanium, tungsten, titanium / tungsten, copper, gold, silver, palladium, and / or nickel. In addition, the thickness and width of the trace 1422, the external interconnect 1424, and the through hole 1423 may be in the range of about 2 microns to about 20 microns.

[0076] Sidewall 262 may include a vertical path 2625 formed on one surface thereof. Vertical path 2625 may be referred to as or may include a sidewall surface path or trace. In addition, sidewall 262 may include a vertical path 2626 passing therethrough. Vertical path 2626 may be referred to as or may include a sidewall embedded path or trace. The height of sidewall 262 may be in the range of about 500 microns to about 5000 microns.

[0077] In some examples, vertical paths 2625 and 2626 can be electrically connected to traces 1422 disposed in cover wall 261 directly or through a conductive adhesive. In some examples, vertical paths 2625 and 2626 can be electrically connected to traces 1422 disposed in base substrate 240 directly or through a conductive adhesive. In some examples, the conductive adhesive can be referred to as or can include conductive paste, solder paste, silver-filled epoxy, or anisotropic conductive film.

[0078] Figure 6 3 shows a cross-sectional view of an example method for manufacturing an example semiconductor device 300. In some examples, before reaching Figure 6 Prior to the stage depicted, the method may include one or more of the steps described above with respect to Figures 4A-4F The stages described are similar to the stages described in Figure 6 In the example shown, the cap structure 360 ​​can be attached to the sidewall 342 of the base substrate 340. In some examples, the traces 1422 of the cap structure 360 ​​can be electrically connected to the vertical paths 2625 disposed in the sidewall 342, either directly or through a conductive adhesive.

[0079] Figure 7 4 is a cross-sectional view of an example semiconductor device 400. Corresponding features or elements of the semiconductor device 400 may be similar to the features or elements described above with respect to the semiconductor devices 100, 200, and / or 300. Figure 7 In the example shown, the semiconductor device 400 may include electronic devices 110 and 180 , an interconnect 130 , a base substrate 140 , a barrier 490 , and a cap structure 160 .

[0080] The barrier 490 may be similar to the barrier 190 and may include a membrane 420 and a reinforcement 430. The membrane 420 may include perforations 421, blocking strands 422, and a blocking body 423. In addition, the reinforcement 430 may include perforations 434. The perforations 421 and blocking strands 422 disposed in the membrane 420 and the perforations 434 disposed in the reinforcement 430 may be aligned with the vias 143 disposed in the dielectric structure 141. In addition, the barrier 490 may be interposed between the MEMS sensor 110 and the base substrate 140. In some embodiments, the adhesive 170 may be interposed between the barrier 490 and the base substrate 140.

[0081] Fig. 8A is an enlarged cross-sectional view of an example blocking member 490, and Figure 8B is a bottom view of an example blocking member 490. Fig. 8A and 8BIn the example shown, the barrier 490 may include a film 420 and a reinforcement 430. As described above, the barrier 490 may also include perforations 421, barrier strands 422, and a barrier body 423, and the reinforcement 430 may include one or more protrusion patterns 431 and perforations 434. In some examples, the film 420 including the perforations 421, barrier strands 422, and barrier body 423 may be similar to the film 120 in terms of configuration, material, and / or thickness.

[0082] In some examples, the barrier 423 of the film 420 may be coupled to a first surface of the reinforcement 430, and the protrusion pattern 431 may be disposed on a second surface opposite to the first surface. Fig. 8A As shown, the protruding pattern 431 includes an outer surface or an outwardly facing surface having a non-planar shape. In some examples, the protruding pattern 431 may include a recess or concave portion 432 and a convex portion or convex portion 433. In some examples, when viewed from a planar angle, the recess 432 and the convex portion 433 may be formed as a substantially checkered pattern. In some examples, the protruding pattern 431 may be generally formed at the four corners or four sides of the reinforcement 430. In some examples, one or more protruding patterns 431 may be formed along the entire outer perimeter (e.g., four corners and four sides) of the perforation 434. The protruding pattern 431 is an example in which the protruding pattern is integrated with the reinforcement.

[0083] During the manufacture of the blocking member 490, the adhesion between the reinforcement member 430 and the mounting film 901 can be reduced by forming a protruding pattern 431 on the bottom surface of the reinforcement member 430 to reduce the bottom surface area available for adhesion with the mounting film 901, which better promotes the separation of the blocking member 490 from the mounting film 901. In some examples, the mounting film 901 may include a semi-rigid adhesive or an adhesive with high viscosity. In addition, when the blocking member 410 is later attached to the base substrate 140 using the adhesive 170, the adhesive 170 may be absorbed into the increased adhesion area defined by the concave portion 431 and the convex portion 433 of the protruding pattern 431 formed on the reinforcement member 430, thereby increasing the adhesion between the blocking member 410 and the base substrate 140. In some examples, the adhesive 170 may include a liquid adhesive or an adhesive with low viscosity.

[0084] Fig. 9 1 shows a cross-sectional view of an example semiconductor device 500 that may be similar to semiconductor device 100. Fig. 9 In the example shown, semiconductor device 500 may include a trench 510 or a recessed area 510 formed in base substrate 140. In some examples, trench 510 may be formed at an area around the perimeter of via 143. In some examples, the diameter of trench 510 may be greater than the diameter of via 143.

[0085] The trench 510 may have a bottom 511 and a sidewall 512. The barrier 490 may be adhered to the bottom 511 of the trench 510 by an adhesive 540. In some examples, the barrier 490 may contact and / or may be adhered to the sidewall 512 of the trench 510. In some examples, the depth of the trench 510 may be less than or greater than the thickness of the barrier 490. In some examples, the depth of the trench 510 may be less than or greater than the thickness of the reinforcement 430. In some examples, the depth of the trench 510 may be less than the sum of the thickness of the barrier 490 and the thickness of the MEMS sensor 110. The trench 510 formed in the base substrate 140 and the barrier 490 adhered to the trench 510 may be commonly applied to the example semiconductor device disclosed in the present disclosure.

[0086] Fig.10 A cross-sectional view of an example semiconductor device 600 is shown, which may be similar to semiconductor device 100. Fig.10 In the example shown, the semiconductor device 600 may include a MEMS sensor 110 attached laterally from a via 143 formed in a base substrate 140. In some examples, the MEMS sensor 110 may be attached to a plane region that does not correspond to the via 143 by an adhesive 640. Therefore, pressure passing through the via 143 may be indirectly applied to the MEMS sensor 110. In some examples, the stopper 490 may provide a buffer space to the MEMS sensor 110. The MEMS sensor 110 connected to the plane region of the base substrate 140 that does not correspond to the via 143 may be commonly applied to the example semiconductor devices disclosed in the present disclosure.

[0087] Figures 11A to 11I A cross-sectional view is shown of an example method for manufacturing an example barrier 490. In some examples, the disclosed barrier 490 can be applied to one or more of the semiconductor devices and / or MEMS devices described in the present disclosure.

[0088] Fig.11A A cross-sectional view of a blocking member 490 is shown in an early stage of manufacture. Fig.11AIn the example shown, dielectric structure 420A can be formed on planar substrate 902. In some examples, planar substrate 902 can be referred to as or can include glass, ceramic, metal or low-grade wafer. In some examples, dielectric structure 420A can be referred to as or can include Si3N4, SiO2, SiON, polyimide (PI), polypropylene (PP), polyethylene (PE), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), epoxy resin, phenol resin, silicone resin or acrylate polymer. In some examples, dielectric structure 420A can be formed by any process in various processes including PVD, CVD, MOCVD, ALD, LPCVD, PECVD, printing, spin coating, spray coating, sintering or thermal oxidation. In some examples, the thickness of dielectric structure 420A can be in the range of about 1 micron to about 10 microns.

[0089] Fig. 11B A cross-sectional view and a top view of the blocking member 490 are shown at a later stage of manufacture. Fig. 11B In the example shown, a patterning process can be performed on the dielectric structure 420A to form a film 420 including perforations 421, blocking strands 422, and blocking bodies 423. In some examples, the film 420 can be formed from the dielectric structure 420A by, for example: a deposition process, such as physical deposition or chemical deposition of a photoresist; a photolithography process performed on the photoresist, such as photolithography, electron beam lithography, ion beam lithography, or X-ray lithography; a patterning process, such as diamond patterning; and / or an etching process performed on the dielectric structure 420A. The diameter and / or spacing of the perforations 421 can be in the range of about 1 micron to about 10 microns. The spacing can vary within a particular structure. In addition, the width and / or spacing of the blocking strands 422 can be in the range of about 1 micron to about 10 microns.

[0090] Fig. 11C A cross-sectional view of the blocking member 490 is shown at a later stage of manufacture. Fig. 11C In the example shown, the film 490 can be covered by a dielectric structure 430A. In some examples, the dielectric structure 430A can cover the perforations 421 , the blocking strands 422 , and the blocking bodies 423 of the film 420 .

[0091] In some examples, dielectric structure 430A may be referred to as or may include Si3N4, SiO2, SiON, polyimide (PI), polypropylene (PP), polyethylene (PE), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), epoxy resin, phenolic resin, silicone resin, or acrylate polymer. In some examples, dielectric structure 430A may be formed by any of a variety of processes including PVD, CVD, MOCVD, ALD, LPCVD, PECVD, printing, spin coating, spray coating, sintering, or thermal oxidation. In some examples, dielectric structure 430A may be in a range of about 10 microns to about 50 microns thick from the surface of film 420.

[0092] Fig.11D A cross-sectional view and a top view of the blocking member 490 are shown at a later stage of manufacture. Fig.11D In the example shown, a patterning process may be performed on the dielectric structure 430A to form a stiffener 430 having a through hole 434, such as Fig.11D . In some examples, the stiffener 430 can be formed from the dielectric structure 430A by, for example: a deposition process, such as physical deposition or chemical deposition of a photoresist; a lithography process performed on the photoresist, such as photolithography, electron beam lithography, ion beam lithography, or X-ray lithography; a patterning process, such as diamond patterning; and / or an etching process performed on the dielectric structure 430A. The diameter of the through-hole 434 can be in the range of about 500 microns to about 900 microns. As described above, a through-hole 434 can be formed at the center of the dielectric structure 430A to complete the stiffener 430.

[0093] Fig.11E A cross-sectional view of the blocking member 490 is shown at a later stage of manufacture. Fig.11E In the example shown, the barrier 490 including the membrane 420 and the stiffener 430 may be covered by a dielectric structure 430B. In some examples, the dielectric structure 430B may be referred to as or may include Si3N4, SiO2, SiON, polyimide (PI), polypropylene (PP), polyethylene (PE), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), epoxy resin, phenolic resin, silicone resin, or acrylate polymer. In some examples, the dielectric structure 430B may be formed by any of a variety of processes including PVD, CVD, MOCVD, ALD, LPCVD, PECVD, printing, spin coating, spray coating, sintering, or thermal oxidation. In some examples, the thickness of the dielectric structure 430B from the surface of the stiffener 430 may be in the range of about 1 micron to about 10 microns.

[0094] Fig.11FA cross-sectional view and a top view of the blocking member 490 are shown at a later stage of manufacture. Fig.11F In the example shown, a patterning process may be performed on the reinforcement member 430 to form one or more protruding patterns 431 on the outer regions of the through holes 434 formed in the reinforcement member 430. In some examples, the protruding patterns 431 may be formed on regions corresponding to the four corners of the reinforcement member 430 or on regions corresponding to the four sides of the reinforcement member 430, such as Fig.11F In some examples, the protruding pattern 431 may be formed on the entire outer surface around the perimeter of the perforation 434, such as Fig.11F As shown in the top view on the right side of the figure. In some examples, the protruding pattern 431 can be formed on the reinforcing member 430 by, for example, a deposition process, such as physical deposition or chemical deposition of a photoresist; a photolithography process performed on the photoresist, such as photolithography, electron beam lithography, ion beam lithography, or X-ray lithography; a patterning process, such as diamond patterning; and / or an etching process performed on the reinforcing member 430. The spacing, width, depth, and / or thickness of the recesses 432 and protrusions 433 constituting the protruding pattern 431 can be in the range of about 3 microns to about 30 microns. Although the protrusions 433 of the protruding pattern 431 are shown as being arranged in the form of a column matrix in this example, in some examples, the protrusions 433 of the protruding pattern 431 can be shaped or arranged in different ways. For example, the protrusion 433 can be alternatively shaped as one or more adjacent lines or walls defining one or more recesses 432 therebetween. In some examples, the protrusion 433 can be patterned into a shape other than a matrix pattern. In some examples, if attachment to a MEMS device, such as MEMS device 110 , is desired, barrier 490 may be separated from planar substrate 902 at this time. Fig.11F is an example where the relief pattern is provided in the form of a separate layer on top of the reinforcement structure.

[0095] Fig.11G A cross-sectional view of the blocking member 490 is shown at a later stage of manufacture. Fig.11G In the example shown, the mounting film 901 may be attached to the protruding pattern 431 of the reinforcement member 430. In some examples, when the area of ​​the recessed portion 432 of the protruding pattern 431 increases, the adhesion between the reinforcement member 430 and the mounting film 901 may decrease or weaken. Therefore, the adhesion between the reinforcement member 430 and the mounting film 901 may be controlled by appropriately adjusting the recessed area of ​​the protruding pattern 431.

[0096] Fig.11H A cross-sectional view of the blocking member 490 is shown at a later stage of manufacture. Fig.11HIn the example shown, the planar substrate 902 can be separated from the film 420. In some examples, the planar substrate 902 can be separated from the blocking member 490 by applying heat, light having a specific wavelength (e.g., UV light), or physical force to the film 420 and the planar substrate 902. The blocking member 490 can remain mounted on the mounting film 901. In some examples, the protruding pattern 431 of the reinforcement member 430 can be mounted on the mounting film 901. Since the reinforcement member 430 can include the protruding pattern 431 and the mounting film 901 can include a semi-rigid adhesive or an adhesive with high viscosity, the bonding area between the reinforcement member 430 and the mounting film 901 can be relatively small, and the adhesion force between the reinforcement member 430 and the mounting film 901 can be reduced.

[0097] Fig.11I A cross-sectional view of the blocking member 490 is shown at a later stage of manufacture. Fig.11I In the example shown, the blocking member 490 may be picked up by a pick-and-place device 904 and placed, for example, on the base substrate 140. In some examples, the bottom surface of the mounting film 901 corresponding to the blocking member 490 may be raised by a needle 905. Thus, the adhesion between the blocking member 490 and the mounting film 901 may be further weakened. The pick-and-place device 904 may be coupled to the top surface of the blocking member 490 to transfer and place the blocking member 490 on, for example, the base substrate 140. In some examples, the pick-and-place device 904 may contact the blocking body 423 of the film 420 to pick up the blocking member 490.

[0098] In some examples, features of this method for making a blocking member 490 may be commonly applied to example methods for making a blocking member disclosed in the present disclosure.

[0099] Figures 12A to 12E A cross-sectional view and a top view of an example method for manufacturing an example blocking member 790 are shown. In some examples, the blocking member 790 can be applied to one or more of the semiconductor devices and / or MEMS devices described in the present disclosure. The blocking member 790 can include several features or elements similar to corresponding features or elements of other blocking members described in the present disclosure.

[0100] Fig. 12A 790 is shown in a cross-sectional view and a top view of a barrier or barrier structure 790 in a manufacturing stage. In some examples, this manufacturing stage can be performed by performing the same steps as described above with respect to Figures 11A-11D The described stages are similar to one or more stages to achieve. Fig. 12AIn the example shown, the film 720 can include elements such as perforations 721, barrier strands 722, and barrier bodies 723. The film 720 and its elements can be similar to other films and corresponding elements described in the present disclosure. In addition, a reinforcement 730 having perforations 734 can be attached to the barrier body 723. Here, the diameter of a perforation 721 can be defined as a first diameter. In addition, the thickness or cross-section of each barrier strand in the barrier strand 722 can be defined as a first thickness.

[0101] Fig. 12B A cross-sectional view and a top view of the blocking member 790 are shown at a later stage of manufacture. Fig. 12B In the example shown, the film 720 may be immersed in a dielectric solution, or a dielectric material or a dielectric solution may be sprayed or spin-coated on the film 720, thereby forming conformal film layers 722A and 723A on the surface of the film 720. In some examples, the conformal film layer 722A may be formed on the barrier strand 722, and the conformal film layer 723A may be formed on the barrier body 723. In some examples, the conformal film layers 722A and 723A may be parts of the same conformal layer.

[0102] In some examples, conformal film layers 722A and 723A may be formed using any of a variety of processes including PVD, CVD, MOCVD, ALD, LPCVD, PECVD, printing, sintering, or thermal oxidation. In some examples, conformal film layers 722A and 723A may be formed using a single mask. In addition, in some examples, one electrical polarity (e.g., positive (+) polarity) may be supplied to film 720, and another electrical polarity (e.g., negative (-) polarity) may be supplied to the dielectric material or dielectric solution. Therefore, the time required to form conformal film layers 722A and 723A may be shortened, and product quality may be improved. In some instances, the dielectric material or dielectric solution used for conformal film layers 722A and 723A may be referred to as or may include Si3N4, SiO2, SiON, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), epoxy resin, phenol resin, silicone resin, or acrylate polymer.

[0103] By adding conformal film layers 722A and 723A, a second diameter of the through hole 721A of the conformal film layer 722A can be formed, which is smaller than Fig. 12A The first diameter of the perforation 721 is shown. In addition, a second thickness or cross-section of the barrier strand 722A may be formed that is greater than Fig. 12A The first thickness of the barrier strand 722 is shown. Such changes or variations in perforation diameter and / or barrier strand thickness may be in the range of, for example, about 100 nanometers (nm) to about 10 microns.

[0104] Fig. 12C A cross-sectional view and a top view of the blocking member 790 are shown at a later stage of manufacture. Fig. 12C In the example shown, you can use Fig. 12B The same materials as those shown are Fig. 12B The film 720 is processed in the same manner as shown to form additional conformal film layers 722B and 723B.

[0105] By adding conformal film layers 722A and 723A, a third diameter of the through hole 721B of the conformal film layer 722B can be formed, which is smaller than Fig. 12B The second diameter of the perforation 721A is shown. In addition, the third thickness or cross-section of the barrier strand 722B can be greater than Fig. 12B The second thickness of the barrier strand 722A shown. Such changes or variations in the perforation diameter and / or barrier strand thickness can be, for example, in the range of about 100 nm to about 10 microns. In some examples, additional conformal film layers can be formed by treating the film 720 a desired number of times in a similar manner. In some examples, the protrusion pattern 431 described above can be formed on the reinforcement member 730, if desired.

[0106] Fig.12D A cross-sectional view of the blocking member 790 is shown at a later stage of manufacture. Fig.12D In the example shown, mounting membrane 901 may be attached to reinforcement member 730 .

[0107] Fig.12E A cross-sectional view of the blocking member 790 is shown at a later stage of manufacture. Fig.12E In the example shown, the planar substrate 902 can be separated from the film 720. In some examples, the planar substrate 902 can be separated from the film 720 by applying heat, light having a specific wavelength, or physical force to the film 720 and the planar substrate 902. The barrier 790 can remain mounted on the mounting film 901.

[0108] By following the process described above, the diameter of the perforations 721 formed on the film 720 and / or the thickness of the barrier line strand film 722 can be controlled by a layer-by-layer (LBL) process by iteratively or sequentially adding subsequent conformal layers such as 722A, 722B, 723A, 723B, etc. Such processing can produce an enhanced fine pitch of the barrier 790, and in some examples, can allow a single or the same mask to be used for each subsequent conformal layer. This allows for a predetermined adjustment of the barrier 790 according to the expected use environment of the MEMS sensor 110.

[0109] Fig.13A and 13BA cross-sectional view of an example method for making an example barrier is shown. Figures 13A-13B The different stages shown in can correspond to Figures 12A to 12E The relevant stages of the method are described. Fig.13A and 13B In the example shown, the diameter of the through-hole 721 of the film 720 and / or the width of the barrier film 722 (including the conformal film layers 722A, 722B) can be controlled by the LBL process described above.

[0110] In some examples, as the number of LBL processes performed increases, the diameter of the perforation 721 (or the perforations 721A, 721B) may gradually decrease, and the thickness or cross-section of the barrier strand 722 may gradually increase. In addition, when the LBL process is performed, opposite electrical polarities may be supplied to the preformed dielectric material and the added dielectric material, respectively, thereby allowing the preformed dielectric material and the added dielectric material to adhere to each other quickly and firmly.

[0111] Figures 14A to 14F A cross-sectional view of an example method for manufacturing an example blocking member 890 is shown. In some examples, the blocking member 890 can be applied to one or more of the semiconductor devices described in the present disclosure. The blocking member 890 can include several features or elements similar to corresponding features or elements of other blocking members described in the present disclosure.

[0112] Fig.14A 890 is shown in a cross-sectional view and a top view of a blocking member 890 at a later stage of manufacture. In some examples, this stage of manufacture can be performed by performing the same steps as described above with respect to Figures 11A-11B The described stages are similar to one or more stages to achieve. Fig.14A In the example shown, film 820 may include elements that may be covered by dielectric structure 820A, such as blocking perforations 821, blocking strands 822, and substrate 823. Film 820 and its elements may be similar to other films and corresponding elements described in the present disclosure. In some instances, dielectric structure 820A may be referred to as or may include Si3N4, SiO2, SiON, polyimide (PI), polypropylene (PP), polyethylene (PE), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), epoxy resin, phenol resin, silicone resin, or acrylate polymer. In some instances, dielectric structure 820A may be formed by any process in various processes including PVD, CVD, MOCVD, ALD, LPCVD, PECVD, printing, spin coating, spray coating, sintering, or thermal oxidation. In some instances, the thickness of dielectric structure 820A from film 820 may be in the range of about 1 micron to about 10 microns.

[0113] Fig. 14B A cross-sectional view of the blocking member 890 is shown at a later stage of manufacture. Fig. 14B In the example shown, a stacked film 820Z may be formed on the film 820. The stacked film 820Z may include or define stacked blocking perforations 821Z and stacked blocking strands 822Z and may be formed from the dielectric structure 820A by, for example: a deposition process, such as physical deposition or chemical deposition of a photoresist; a lithography process performed on the photoresist, such as photolithography, electron beam lithography, ion beam lithography, or X-ray lithography; a patterning process, such as diamond patterning; and / or an etching process performed on the dielectric structure 820A. In some examples, the spacing of the stacked blocking perforations 821Z and / or the stacked blocking strands 822Z may be similar to the spacing of the blocking perforations 821 and / or the blocking strands 822, respectively, but in other examples, such spacing need not be similar. In some examples, the vertical / horizontal positions of the stacked blocking perforations 821Z and the stacked blocking strands 822Z may be offset from the vertical / horizontal positions of the blocking perforations 821 and the blocking strands 822, respectively. Therefore, an overlapping spacing based on the overlapping of the blocking perforations 821 and the stacked blocking perforations 821Z can be formed, and the overlapping spacing is further reduced compared to the corresponding spacing of the blocking perforations 821. Similarly, an overlapping spacing based on the overlapping of the blocking strands 822 and the stacked blocking strands 822Z can be formed, and the overlapping spacing is further reduced compared to the corresponding spacing of the blocking strands 822.

[0114] Fig. 14C A cross-sectional view of the blocking member 890 is shown at a later stage of manufacture. Fig. 14C In the example shown, the film 820 can be covered by a dielectric structure 830A. In some examples, the dielectric structure 830A can cover the film 820 and the stacked film 820A. Here, the dielectric structure 830A can be similar to the dielectric structure 820A, such as in terms of manufacturing methods, materials and / or dimensions.

[0115] Fig.14D A cross-sectional view and a top view of the blocking member 890 are shown at a later stage of manufacture. Fig.14D In the example shown, a patterning process can be performed on the dielectric structure 830A to form the through-hole 834 and define the stiffener 830. Here, the stiffener 830 can be similar to the stiffener 430 described above, such as in terms of manufacturing methods, materials, and / or dimensions. The barrier 890 can be picked up by a pick-and-place device and subsequently attached and / or attached to the MEMS device 110 as part of one of the different semiconductor devices described herein. In some examples, if it is desired to attach to a MEMS device such as the MEMS device 110, the barrier 890 can be separated from the planar substrate 902 at this time.

[0116] Fig.14EA cross-sectional view of the blocking member 890 is shown at a later stage of manufacture. Fig.14E In the example shown, the mounting film 901 may be attached to the reinforcement member 830. In some examples, if necessary, a protrusion pattern 431 may be further formed on the surface of the reinforcement member 830 as described above.

[0117] Fig.14F A cross-sectional view of the blocking member 890 is shown at a later stage of manufacture. Fig.14F In the example shown, the planar substrate 902 may be separated from the membrane 820. The separation process may be performed as previously described with respect to the planar substrate 902. The stopper 890 may be picked up by a pick-and-place device and subsequently attached as part of one of the different semiconductor devices described herein and / or attached to the MEMS device 110.

[0118] Fig.15 is an enlarged cross-sectional view of an example blocking member 890. Fig.15 In the example shown, the spacing of blocking perforations 821 and / or blocking strands 822 can be defined as a first spacing, as shown in coarse spacing 825. In addition, the spacing of stacked perforations 821Z and / or stacked blocking strands 822Z can be defined as a second spacing, as shown in coarse spacing 825Z. In some instances, the horizontal / vertical position of blocking perforations 821 or blocking strands 822 can be offset from the horizontal / vertical position of stacked perforations 821Z or stacked blocking strands 822Z. Therefore, the third spacing represented by fine spacing 825X and defined by the offset overlap of blocking perforations 821 and stacked perforations 821Z and / or by the offset overlap of blocking strands 822 and stacked blocking strands 822Z can be less than any one of coarse spacing 825 and / or 825Z. In some instances, fine spacing 825X can be in the range of about 0.001 micron to about 2 microns. The barrier 890 having such a fine pitch 825X may enable prevention of smaller foreign particles 888 from being induced into the cavity 117 of the MEMS sensor 110 .

[0119] In summary, an electronic device structure and associated methods have been described that include a barrier configured to reduce the effects of contaminants on an electronic device. In some instances, the barrier includes a film having a barrier body and a first barrier strand, the first barrier strand being bounded by the barrier body and defining a first perforation. In some instances, a conformal film layer may be added to the first barrier strand to reduce the size of the first perforation. In other embodiments, a second barrier strand may be added to the first barrier strand and the second barrier strand at least partially overlaps the first barrier strand. The second barrier strand defines a second perforation that is laterally offset from the first perforation. In some instances, a protruding pattern is disposed in the form of a portion of the barrier, and the protruding pattern may be configured to reduce the contact area of ​​the barrier with a contact film used during manufacturing. This advantageously increases the ease with which an electronic die can be removed from the contact film during, for example, a pick-and-place process. In other instances, a barrier structure may be formed when the electronic device is in the form of a portion of a semiconductor wafer among a plurality of electronic devices to improve manufacturability. The structures and methods described herein improve the reliability and manufacturability of electronic devices.

[0120] The present disclosure includes references to certain examples, however, it will be appreciated by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present disclosure. In addition, the disclosed examples may be modified without departing from the scope of the present disclosure. Therefore, it is intended that the present disclosure is not limited to the disclosed examples, and the present disclosure will include all examples falling within the scope of the appended claims.

Claims

1. A semiconductor device comprising: a first electronic device, the first electronic device comprising a first surface and a second surface opposite to the first surface; as well as a barrier coupled to the second surface of the first electronic device and comprising: A first film, the first film comprising: a first barrier; and first barrier strands bounded by the first barrier body and defining first perforations, wherein at least one first perforation has a first dimension between a pair of adjacent first barrier strands; and A second film, the second film comprising: a second barrier strand disposed on and at least partially overlapping the first barrier strand; The second barrier strand defines a second perforation; and The second aperture is laterally offset relative to the first aperture.

2. The semiconductor device according to claim 1, wherein: The first electronic device includes a cavity extending partially inwardly from the second surface to provide a membrane adjacent to the first surface; and The barrier extends across the cavity.

3. The semiconductor device according to claim 2, further comprising: A packaging structure, the packaging structure comprising: A base substrate includes a dielectric structure, a conductive structure, and a via extending through a portion of the base substrate, wherein the first electronic device is coupled to the base substrate such that the diaphragm is in communication with the via.

4. The semiconductor device according to claim 3, wherein: The base substrate further includes a groove disposed around a perimeter of the via; The blocking member further includes a convex pattern having a plurality of convex portions separated by a plurality of concave portions; and The protrusion pattern is coupled to the base substrate within the trench.

5. The semiconductor device according to claim 3, wherein: The package structure further includes a cover structure coupled to the base substrate; The cap structure includes a second conductive structure; and The first electronic device is electrically coupled to the second conductive structure.

6. The semiconductor device according to claim 1, wherein the blocking member further comprises: A convex pattern having a plurality of convex portions separated by a plurality of concave portions.

7. The semiconductor device according to claim 6, wherein: The barrier further includes a reinforcement member disposed adjacent to the first barrier body; and The raised pattern is integral with the reinforcement.

8. The semiconductor device according to claim 6, wherein: The barrier further includes a reinforcement member disposed adjacent to the first barrier body; and The raised pattern is a separate layer on the reinforcement.

9. The semiconductor device according to claim 1, wherein: The second film further includes a second barrier disposed on the first barrier; and The blocking member further includes a reinforcement member disposed on the second blocking body.

10. The semiconductor device according to claim 1, wherein: The first electronic device comprises a micro-electromechanical system sensor; and The barrier includes one or more dielectric materials.

11. An electronic device comprising: a first electronic device including a first surface and a second surface opposite the first surface and a cavity extending partially inwardly from the second surface to provide a membrane adjacent to the first surface; as well as a barrier coupled to the second surface of the first electronic device, wherein the barrier extends across the cavity and comprises: A first film, the first film comprising: a first barrier; and a first barrier strand bounded by the first barrier body and defining a first perforation; a second blocking body, the second blocking body being disposed on the first blocking body; and A reinforcement member is arranged on the second blocking body.

12. The electronic device according to claim 11, further comprising: A convex pattern comprising a plurality of convex portions separated by a plurality of concave portions, wherein: The protruding pattern is connected to the reinforcement member.

13. The electronic device according to claim 11, further comprising: A package structure comprising a base substrate, the base substrate comprising a dielectric structure, a conductive structure, and a via extending through a portion of the base substrate, wherein: The first electronic device is coupled to the base substrate such that the diaphragm is in communication with the via.

14. The electronic device according to claim 13, wherein: The package structure further includes a cover structure coupled to the base substrate; The cap structure includes a second conductive structure; and The first electronic device is electrically coupled to the second conductive structure.

15. A method of forming an electronic device, the method comprising: providing a first electronic device, the first electronic device comprising a first surface and a second surface opposite the first surface, and a cavity extending partially inwardly from the second surface to provide a membrane adjacent to the first surface; as well as Providing a blocking member, the blocking member coupled to the second surface of the first electronic device, the blocking member comprising: A first film, the first film comprising: a first barrier; and a first barrier strand defining a first perforation; and A second film, the second film comprising: a second barrier strand disposed on and at least partially overlapping the first barrier strand; The second barrier strand defines a second perforation; and The second aperture is laterally offset relative to the first aperture.

16. The method of claim 15, wherein providing the barrier comprises: Disposing the first electronic device among a plurality of electronic devices in the form of a portion of a semiconductor wafer, the first electronic device including the cavity extending partially inwardly from the second surface; providing a first material layer adjacent to the second surface to enclose the cavity; forming the first perforations in the first material layer to establish the first barrier body and the first barrier strand; attaching the semiconductor wafer to a carrier substrate; as well as The semiconductor wafer is singulated to provide the first electronic devices, wherein the singulation step includes singulating through the first material layer.

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