semiconductor packages

Abstract

A semiconductor package includes a substrate; a semiconductor chip disposed on a first surface of the substrate; solder bumps disposed between the first surface of the semiconductor chip and the substrate; and a redistribution layer disposed on a second surface of the semiconductor chip opposite the first surface. The substrate includes a substrate pattern, and the substrate pattern covers the second surface of the substrate. The substrate pattern covers 60% to 100% of the total area of the second surface of the substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0074185 filed on June 21, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Exemplary embodiments of the inventive concept relate to a semiconductor package, and more particularly, to a semiconductor package having an electromagnetic shielding function and an antenna function. Background Art

[0004] Increasing packaging density can improve speed and miniaturize electronic devices. However, electromagnetic waves emitted from electronic devices can degrade their performance. For example, electromagnetic waves can cause malfunctions in communication devices, potentially creating serious safety issues. Therefore, electromagnetic shielding technologies are being developed to minimize electromagnetic interference.

[0005] In addition, during the development of mobile communication technology in 5G communication technology, various technologies (such as large capacity, high speed, and small antenna technology) have been developed. Summary of the Invention

[0006] According to an exemplary embodiment of the present inventive concept, a semiconductor package includes: a substrate; a semiconductor chip disposed on a first surface of the substrate; solder bumps disposed between the first surface of the semiconductor chip and the substrate; and a redistribution layer disposed on a second surface of the semiconductor chip opposite the first surface. The substrate includes a substrate pattern, and the substrate pattern covers the second surface of the substrate. The substrate pattern covers 60% to 100% of the total area of the second surface of the substrate.

[0007] According to an exemplary embodiment of the present invention, a semiconductor package includes: a substrate; a semiconductor chip mounted on a first surface of the substrate; a solder bump disposed between the first surface of the semiconductor chip and the first surface of the substrate; a shielding layer disposed between the semiconductor chip and the solder bump; and a redistribution layer disposed on a second surface of the semiconductor chip opposite to the first surface, wherein the substrate includes a substrate pattern and an antenna pattern, and wherein the substrate pattern covers the second surface of the substrate.

[0008] According to an exemplary embodiment of the present invention, a semiconductor package includes: a substrate; a semiconductor chip mounted on a first surface of the substrate; a solder bump disposed between the first surface of the semiconductor chip and the substrate; a solder mask disposed on the first surface of the substrate; a shielding layer disposed between the semiconductor chip and the solder bump; a redistribution layer disposed on a second surface of the semiconductor chip opposite to the first surface; a mold layer covering the sidewalls of the semiconductor chip and disposed between the substrate and the redistribution layer; and a via passing through the substrate and the mold layer. The substrate includes a substrate pattern and an antenna pattern, and the substrate pattern covers the second surface of the substrate. The solder bump is disposed in an area formed by the solder mask, and the via includes a ground via, a signal via, and a power via. The redistribution layer is electrically connected to the semiconductor chip, and the shielding layer includes an adhesive layer, a shielding metal layer, and a protective layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other features of the present inventive concept will become more apparent by describing in detail exemplary embodiments of the present inventive concept with reference to the accompanying drawings, in which:

[0010] Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 1D 、 Figure 1E and Figure 1F is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an exemplary embodiment of the present inventive concept;

[0011] Figure 2 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment of the present inventive concept;

[0012] Figure 3 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment of the present inventive concept;

[0013] Figure 4 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment of the present inventive concept; and

[0014] Figure 5 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0015] Throughout the specification and drawings, like reference numerals or like reference numerals may refer to like elements or components. Hereinafter, a semiconductor package and a method of manufacturing the same according to exemplary embodiments of the present inventive concept will be described.

[0016] Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 1D 、 Figure 1E and Figure 1F is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an exemplary embodiment of the inventive concept.

[0017] Reference Figure 1A , a substrate 100 may be prepared. The substrate 100 may be a printed circuit board (PCB). For example, the substrate 100 may be a metal sheet including an insulating layer. The substrate 100 may have a first surface 100a and a second surface 100b. A substrate 100 having a substrate pattern 112 disposed therein may be prepared. The substrate pattern 112 may vertically pass through the substrate 100 and may be exposed on the top surface (e.g., the first surface 100a) of the substrate 100. For example, the substrate pattern 112 may be provided on the second surface 100b and may pass through the substrate 100 to be exposed on the first surface 100a of the substrate 100. At least one of the substrate patterns 112 may include a first portion 112a and a second portion 112b. A solder mask 121 may be formed on the first surface 100a of the substrate 100. The solder mask 121 may be provided on the first surface 100a to provide an area A in which the solder bumps 122 will be disposed. Then, solder bumps 122 may be formed in region A.

[0018] Reference Figure 1B , a semiconductor chip 200 can be prepared. The semiconductor chip 200 may have one surface 200a (e.g., a first surface) and another surface 200b (e.g., a second surface) opposite to the one surface 200a. The semiconductor chip 200 may be provided with one or more bonding patterns 204 and one or more contact pads 202 bonded to the surface of the semiconductor chip 200. For example, the bonding pattern 204 may be provided on the first surface 200a of the semiconductor chip 200, and the contact pad 202 may be provided on the second surface 200b of the semiconductor chip 200. The semiconductor chip 200 may be provided on the first surface 100a of the substrate 100 in such a manner that the bonding pattern 204 contacts the solder bumps 122 formed on the solder mask 121.

[0019] A reflow process may be performed after the semiconductor chip 200 is disposed on the substrate 100. The reflow process may include a process of applying heat to the solder bumps 122. After the reflow process, the semiconductor chip 200 may be fixed on the substrate 100 and may be aligned with a predetermined position. For example, the solder bumps 122 melted by the reflow process may be in a liquid state, and therefore, the surface tension of the solder bumps 122 may increase. Therefore, even if the semiconductor chip 200 is misaligned with the predetermined position on the substrate 100, the semiconductor chip 200 can be self-aligned on the substrate 100 by surface tension. Since the semiconductor chip 200 is self-aligned, the process yield for manufacturing semiconductor packages with fine pitches can be improved.

[0020] Reference Figure 1C After the semiconductor chip 200 is fixed on the first surface 100a of the substrate 100, a mold layer 130 may be formed on the substrate 100 and the second surface 200b of the semiconductor chip 200. The mold layer 130 may cover the substrate 100, the solder bumps 122, the semiconductor chip 200, and the contact pads 202. The mold layer 130 may cover the second surface 200b of the semiconductor chip 200 and the top surface and sidewalls of the contact pads 202.

[0021] Reference Figure 1D , the top surface 130a of the mold layer 130 may be polished. For example, the polishing process may be a chemical mechanical polishing (CMP) process. The top surface 130a of the mold layer 130 may be polished to be parallel to the substrate 100. Therefore, the top surface of the contact pad 202 covered by the mold layer 130 may be exposed.

[0022] Reference Figure 1E A redistribution layer 150 may be formed on the second surface 200b of the semiconductor chip 200. The redistribution layer 150 may include an insulating layer 152, a redistribution pattern 154, and connection pads 156. For example, the redistribution pattern 154 and the connection pads 156 are formed in the insulating layer 152, and the connection pads 156 are exposed at the first surface of the insulating layer 152.

[0023] Reference Figure 1F , solder balls 160 may be formed on the connection pads 156, respectively. The semiconductor package including the substrate 100, the semiconductor chip 200, and the redistribution layer 150 may be turned over after forming the solder balls 160. The semiconductor package may be connected to an external device through the solder balls 160 in a state in which the semiconductor package is turned over.

[0024] Figure 2 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment of the inventive concept.

[0025] Reference Figure 2 , a semiconductor package 10 according to an exemplary embodiment of the present inventive concept may include a substrate 100, solder bumps 122, a solder mask 121, a bonding pattern 204, a molding layer 130, a semiconductor chip 200, a contact pad 202, a redistribution layer 150, and solder balls 160. Figures 1A to 1F The described method manufactures the semiconductor package 10 .

[0026] A substrate 100 may be provided. Substrate patterns 112 may be exposed on the first surface 100a and the second surface 100b of the substrate 100. At least one of the substrate patterns 112 may include a first portion 112a and a second portion 112b. The first portion 112a may vertically pass through the substrate 100. The second portion 112b may be provided on the second surface 100b of the substrate 100. The second portion 112b may be connected to the first portion 112a and may extend to the sidewall 100c of the substrate 100 in a direction parallel to the first surface 100a of the substrate 100. The substrate patterns 112 may be connected to each other via conductive lines. The substrate patterns 112 may include a conductive material. For example, the substrate patterns 112 may include copper (Cu), nickel (Ni), cobalt (Co), aluminum (Al), and / or gold (Au). When viewed in a plan view, the substrate patterns 112 may cover portions of the first surface 100a and / or the second surface 100b of the substrate 100, thereby suppressing or preventing electromagnetic waves generated in the semiconductor chip 200 from being transmitted to the outside. The substrate pattern 112 can shield or block external electromagnetic waves directed toward the semiconductor chip 200 and / or absorb a portion of these electromagnetic waves. As a result, the semiconductor chip 200 can be protected from external electromagnetic waves, thereby reducing or minimizing malfunctions of the semiconductor package 10 due to electromagnetic interference and improving the operational reliability of the semiconductor package 10. When viewed in plan, the area of the second surface 100b of the substrate 100 covered by the substrate pattern 112 can range from approximately 60% to 100% of the total area of the substrate 100. When the area of the second surface 100b of the substrate 100 covered by the substrate pattern 112 ranges from approximately 60% to 100% of the total area of the substrate 100, the substrate pattern 112 can exhibit or perform an electromagnetic shielding function. If this area is less than 60% of the total area, the substrate pattern 112 may not effectively shield the semiconductor chip 200 from electromagnetic waves. Furthermore, the substrate pattern 112 can dissipate or release heat generated by the semiconductor chip 200 to the outside. The width W1 of the substrate pattern 112 present in the substrate 100 may be substantially equal to the maximum width of the region A in which the solder bump 122, which will be described in detail later, is provided. For example, the width W1 of the first portion 112a passing through the substrate 100 is substantially equal to the maximum width of the region A. Therefore, a heat dissipation path can be effectively ensured to smoothly dissipate or release heat to the outside. The substrate pattern 112 can be connected to another semiconductor chip stacked on the semiconductor chip 200 in a package-on-package (PoP) or system-in-package (SiP) structure. However, the shape of the substrate pattern 112 is not limited to Figure 2 The term 'connect' used herein may mean 'physically connected' or 'electrically connected'. In addition, the term 'electrically connected' may mean 'directly or indirectly connected'.

[0027] Solder bumps 122 may be provided on the first surface 100a of the substrate 100. For example, the solder bumps 122 may be provided in the region A formed by the solder mask 121. Thus, the substrate pattern 112 may be aligned with the solder bumps 122, respectively. The solder bumps 122 may include a metal with a relatively low melting point for the reflow process. For example, the solder bumps 122 may include lead (Pb), tin (Sn), and / or gold (Au). Alternatively, the solder bumps 122 may be replaced by a metal layer.

[0028] The solder mask 121 may be disposed between the solder bump 122 and the substrate pattern 112. The solder mask 121 may be disposed on the first surface 100a of the substrate 100 to form a region A in which the solder bump 122 is disposed. For example, the solder mask 121 may include a polymer material. For example, the solder mask 121 may be formed from epoxy-based insulating ink. The region A may have the same planar shape as the bonding pattern 204, which will be described in detail later, thereby increasing or maximizing the self-alignment effect.

[0029] The semiconductor chip 200 may be disposed on the first surface 100a of the substrate 100. For example, the semiconductor chip 200 may be an application processor (AP) chip, a memory chip, a radio frequency (RF) chip, a logic chip, or a graphics chip. The semiconductor chip 200 may include semiconductor devices therein. The semiconductor devices in the semiconductor chip 200 may be disposed adjacent to the second surface 200b of the semiconductor chip 200. The second surface 200b of the semiconductor chip 200 may be an active surface.

[0030] Contact pads 202 may be provided on the second surface 200 b of the semiconductor chip 200. The contact pads 202 may include a conductive material. For example, the contact pads 202 may include copper (Cu), nickel (Ni), cobalt (Co), titanium (Ti), and / or aluminum (Al). The contact pads 202 may be electrically connected to the semiconductor devices in the semiconductor chip 200.

[0031] The bonding pattern 204 may be disposed on the first surface 200a of the semiconductor chip 200. The width W2 of the bonding pattern 204 may be substantially equal to the maximum width of the region A in which the solder bumps 122 are disposed. Therefore, the heat generated by the semiconductor chip 200 can be smoothly dissipated. The bonding pattern 204 may improve the interface characteristics between the semiconductor chip 200 and the solder bumps 122. For example, the bonding pattern 204 may improve the bonding strength between the semiconductor chip 200 and the solder bumps 122. To achieve this, the bonding pattern 204 may include a metal material. For example, each of the bonding patterns 204 may have a double-layer structure of titanium (Ti) and copper (Cu), where titanium (Ti) has excellent interface characteristics with respect to silicon (Si) of the semiconductor chip 200, and copper (Cu) has excellent interface characteristics with respect to the solder bumps 122. The bonding pattern 204 may be bonded to the first surface 200a of the semiconductor chip 200 to help the semiconductor chip 200 be fixed to the substrate 100 via the solder bumps 122. The bonding pattern 204 may not be electrically connected to the semiconductor devices in the semiconductor chip 200 .

[0032] The mold layer 130 may be disposed on the first surface 100a of the substrate 100. The mold layer 130 may cover the substrate 100, the solder bumps 122, the semiconductor chip 200, and the contact pads 202. The mold layer 130 may cover the second surface 200b of the semiconductor chip 200 and the sidewalls of the contact pads 202. For example, the first surface (e.g., the lower surface) of the contact pads 202 may be exposed through the mold layer 130. In an exemplary embodiment of the present inventive concept, the mold layer 130 may at least partially cover the top surface of the contact pads 202. The width of the mold layer 130 may be substantially equal to the width of the substrate 100. The sidewalls 130c of the mold layer 130 may be aligned with the sidewalls 100c of the substrate 100. The sidewalls 100c of the substrate 100 may not be covered by the mold layer 130 but may be exposed to the outside. The mold layer 130 may protect the semiconductor chip 200 from impact and insulate the semiconductor chip 200 from the outside. For example, the mold layer 130 may include a polymer material. For example, the mold layer 130 may include epoxy resin.

[0033] The redistribution layer 150 may be disposed on the second surface 200b of the semiconductor chip 200. The redistribution layer 150 may include an insulating layer 152, a redistribution pattern 154, and connection pads 156. The insulating layer 152 may include multiple layers. The redistribution pattern 154 may include multiple conductive layers and multiple conductive vias and may be electrically connected to the semiconductor devices in the semiconductor chip 200. The conductive layers may be disposed between the multiple insulating layers 152. The conductive vias may pass through at least a portion of the insulating layer 152 to connect to the conductive layers. The connection pads 156 may be disposed in the upper portion and / or lower portion of the redistribution layer 150. For example, the connection pads 156 may be exposed through the redistribution layer 150 at the lower portion of the redistribution layer 150. The connection pads 156 may be laterally spaced apart from each other. The redistribution pattern 154 and the connection pads 156 may include conductive material. For example, the redistribution pattern 154 and the connection pad 156 may each include copper (Cu), nickel (Ni), cobalt (Co), aluminum (Al), and / or titanium (Ti). The insulating layer 152 may include an insulating material. For example, the insulating layer 152 may include silicon oxide and / or silicon nitride.

[0034] Solder balls 160 may be respectively disposed on the connection pads 156. The solder balls 160 may include a conductive material.

[0035] The semiconductor package 10 can be connected to an external device via the solder balls 160. For example, the electrical signals generated by the semiconductor devices in the semiconductor chip 200 can be output to the outside (e.g., an external device) via the contact pads 202, the redistribution pattern 154, the connection pads 156, and the solder balls 160. The heat generated by the semiconductor chip 200 can be dissipated to the outside via the substrate pattern 112. For example, the heat generated by the operation of the semiconductor devices in the semiconductor chip 200 can be dissipated to the outside via the bonding pattern 204, the solder bumps 122, and the substrate pattern 112. The bonding pattern 204, the solder bumps 122, and the substrate pattern 112 may include a material having a relatively high heat transfer coefficient, so that the heat can be easily dissipated or released. At least one of the substrate patterns 112 may include a second portion 112b. For example, the second portion 112b may be connected to the first portion 112a and may also extend along the second surface 100b of the substrate 100, so that at least a portion of the second surface 100b of the substrate 100 is covered. Therefore, the area of substrate pattern 112 for heat dissipation can be increased to improve heat dissipation efficiency. Since heat is easily dissipated, malfunctions of semiconductor package 10 can be reduced or minimized, and the operational reliability of semiconductor package 10 can be improved. The direction in which the electrical signals generated by the semiconductor devices in semiconductor chip 200 are output to the outside through solder balls 160 can be parallel to the direction in which the heat generated by semiconductor chip 200 is dissipated to the outside through substrate pattern 112. For example, the heat generated by semiconductor chip 200 can be dissipated in a direction toward substrate 100, and an electrical signal can be generated from semiconductor chip 200 in a direction toward redistribution layer 150.

[0036] Figure 3 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment of the inventive concept.

[0037] Reference Figure 3 , a semiconductor package 20 according to an exemplary embodiment of the present inventive concept may include a substrate 100, solder bumps 122, a solder mask 121, a bonding pattern 204, a mold layer 130, ground vias 141, power vias 142, signal vias 143, a semiconductor chip 200, a contact pad 202, a redistribution layer 150, and solder balls 160. The substrate 100, the solder bumps 122, the mold layer 130, the solder mask 121, the bonding pattern 204, the semiconductor chip 200, the contact pad 202, the redistribution layer 150, and the solder balls 160 may be the same as those described above with reference to FIG. Figures 1A to 1F and Figure 2 Hereinafter, for the purpose of ease and convenience of explanation, descriptions of the same features as those described in the above embodiments will be omitted.

[0038] The substrate 100 may include an antenna pattern 114. The antenna pattern 114 may be disposed in the substrate 100. For example, the antenna pattern 114 may have a curved conductive line shape. The antenna pattern 114 may include a conductive material, such as copper (Cu), nickel (Ni), cobalt (Co), aluminum (Al), and / or gold (Au). The antenna pattern 114 may be connected to a ground via 141. The ground via 141 may pass through the substrate 100 and the mold layer 130 to connect the antenna pattern 114 and the redistribution pattern 154. The ground via 141 may be connected to the substrate pattern 112. For example, the antenna pattern 114 may be grounded through the ground via 141, the redistribution pattern 154, the connection pad 156, and the solder ball 160. The antenna pattern 114 may be connected to a power via 142. The power via 142 may pass through the substrate 100 and the mold layer 130 to connect the antenna pattern 114 and the redistribution pattern 154 to each other. For example, the antenna pattern 114 can be electrically connected to an external power source through the solder balls 160, the redistribution pattern 154, and the power vias 142. Thus, a potential difference can be generated in the antenna pattern 114, and current can flow through the antenna pattern 114. The antenna pattern 114 can be connected to the signal vias 143. The signal vias 143 can pass through the substrate 100 and the mold layer 130 to connect the antenna pattern 114 and the redistribution pattern 154 to each other. For example, current can flow into the antenna pattern 114 through the solder balls 160, the connection pads 156, the redistribution pattern 154, and the signal vias 143. This current can be an electrical signal input to the antenna pattern 114. The ground vias 141, the power vias 142, and the signal vias 143 may include conductive materials. For example, the ground vias 141, the power vias 142, and the signal vias 143 may include copper (Cu), nickel (Ni), cobalt (Co), aluminum (Al), and / or gold (Au). The positions and numbers of the ground vias 141, the power vias 142 and the signal vias 143 are not limited to Figure 3 , but can be changed differently. When an electrical signal is input to the antenna pattern 114, the semiconductor package 20 can perform a communication function without an additional antenna structure. Therefore, a small and thin semiconductor package 20 with a communication function can be realized.

[0039] The substrate pattern 112 may be connected to the ground via 141 and thus may be grounded. However, the substrate pattern 112 may not be electrically connected to the power via 142 and the signal via 143 .

[0040] Substrate pattern 112 and antenna pattern 114 may be disposed on first surface 200a of semiconductor chip 200 to cover semiconductor chip 200. Thus, substrate pattern 112 and antenna pattern 114 may block external electromagnetic waves to protect semiconductor chip 200, and / or may suppress or prevent electromagnetic waves generated in semiconductor chip 200 from being transmitted to the outside. As a result, substrate 100 may perform both electromagnetic shielding and antenna functions, thereby enabling the manufacture or implementation of a small and thin semiconductor package 20. Furthermore, when current is applied to substrate pattern 112, substrate pattern 112 may better absorb electromagnetic waves, thereby improving the efficiency of the electromagnetic shielding function.

[0041] Figure 4 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment of the inventive concept.

[0042] Reference Figure 4 , a semiconductor package 30 according to an exemplary embodiment of the present inventive concept may include a substrate 100, solder bumps 122, a solder mask 121, a mold layer 130, ground vias 141, power vias 142, signal vias 143, a semiconductor chip 200, a shielding layer 210, contact pads 202, a redistribution layer 150, and solder balls 160. The substrate 100, solder bumps 122, the mold layer 130, the solder mask 121, the semiconductor chip 200, the contact pads 202, the redistribution layer 150, and the solder balls 160 may be the same as those described above with reference to FIG. Figures 1A to 1F and Figure 2 The ground via 141, power via 142 and signal via 143 can be the same as those described in the reference. Figure 3 Hereinafter, for the purpose of simplicity and ease of explanation, descriptions of features identical to those described in the above embodiments will be omitted.

[0043] The shielding layer 210 may be disposed on the first surface 200a of the semiconductor chip 200. The shielding layer 210 may include an adhesive layer 211, a shielding metal layer 212, and a protective layer 213. The adhesive layer 211 may be disposed on the first surface 200a of the semiconductor chip 200. The adhesive layer 211 may cover the first surface 200a of the semiconductor chip 200. For example, the adhesive layer 211 may completely cover the first surface 200a of the semiconductor chip 200. The adhesive layer 211 may include a metal having excellent adhesion properties to the silicon (Si) of the semiconductor chip 200. For example, the adhesive layer 211 may include titanium (Ti). Therefore, the adhesive layer 211 may be disposed between the semiconductor chip 200 and the shielding metal layer 212 to secure the shielding metal layer 212 to the semiconductor chip 200.

[0044] The shielding metal layer 212 may be disposed on the top surface of the adhesive layer 211. The shielding metal layer 212 may cover the top surface of the adhesive layer 211. For example, the shielding metal layer 212 may completely cover the top surface of the adhesive layer 211. The shielding metal layer 212 may include a metal material. For example, the shielding metal layer 212 may include copper (Cu). The shielding metal layer 212 may be disposed on the first surface 200a of the semiconductor chip 200 to shield external electromagnetic waves, thereby protecting the semiconductor chip 200. In addition, the shielding metal layer 212 may prevent the electromagnetic waves generated by the semiconductor chip 200 from being transmitted to the outside. Therefore, the performance degradation of the semiconductor package 30 caused by external electromagnetic waves can be prevented.

[0045] A protective layer 213 may be disposed on the top surface of the shielding metal layer 212. The protective layer 213 may cover at least a portion of the top surface of the shielding metal layer 212. For example, the protective layer 213 may cover portions of the top surface of the shielding metal layer 212 that do not contact the solder bumps 122. The protective layer 213 may include an insulating polymer. For example, the protective layer 213 may include polyimide (PI). The protective layer 213 may prevent the shielding metal layer 212 from oxidation. The protective layer 213 may protect the shielding metal layer 212 from external impacts. The electromagnetic shielding function of the semiconductor package 30 may be enhanced by including the shielding layer 210 in direct contact with the first surface 200a of the semiconductor chip 200.

[0046] Figure 5 is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment of the inventive concept.

[0047] Reference Figure 5 , a semiconductor package 40 according to an exemplary embodiment of the present inventive concept may include a substrate 100, solder bumps 122, a solder mask 121, a mold layer 130, ground vias 141, power vias 142, signal vias 143, a semiconductor chip 200, a shielding layer 210, contact pads 202, a redistribution layer 150, and solder balls 160. The solder bumps 122, the mold layer 130, the solder mask 121, the semiconductor chip 200, the contact pads 202, the redistribution layer 150, and the solder balls 160 may be the same as those described above with reference to FIG. Figures 1A to 1F and Figure 2 The ground via 141, power via 142 and signal via 143 can be the same as those described in the reference. Figure 3 Hereinafter, for the purpose of simplicity and ease of explanation, descriptions of features identical to those described in the above embodiments will be omitted.

[0048] The substrate 100 may include an antenna pattern 114'. The antenna pattern 114' may be provided in the substrate 100. When the antenna pattern 114' is formed as multiple layers in the substrate 100, the process cost may increase. Therefore, the antenna pattern 114' may be formed by patterning a single layer. As a result, the production efficiency of the antenna pattern 114' may be improved. The antenna pattern 114' may have a curved or curved shape. The antenna pattern 114' may include a conductive material, for example, copper (Cu), nickel (Ni), cobalt (Co), aluminum (Al), and / or gold (Au).

[0049] The shielding layer 210 may be disposed on the first surface 200a of the semiconductor chip 200. The shielding layer 210 may include an adhesive layer 211, a shielding metal layer 212', and a protective layer 213'. The adhesive layer 211 may be provided with a reference Figure 4 The shielding metal layer 212' and the protective layer 213' can be the same as those described in reference Figure 4 Those described are basically the same. However, the upper portion of the shielding metal layer 212' may include a pattern portion 212'a and a contact portion 212'b. For example, a portion of the upper portion of the shielding metal layer 212' may be etched to form a recess. The pattern portion 212'a may be formed between the recesses. The recess may be filled with a protective layer 213'. The width W3 of the contact portion 212'b may be substantially equal to the maximum width of the area A in which the solder bump 122 is disposed. For example, the contact portion 212'b may contact the solder bump 122 and may have a width greater than the width of the pattern portion 212'a. For example, the pattern portion 212'a may have a curved or curved shape. The pattern portion 212'a may serve as an antenna for the semiconductor package 40. For example, a current may flow through the pattern portion 212'a, and the current may be an electrical signal input to the pattern portion 212'a. For example, current can flow from the outside into pattern portion 212'a through solder balls 160, redistribution patterns 154, contact pads 202, and the internal interconnects and vias of semiconductor chip 200. When current flows through pattern portion 212'a, pattern portion 212'a can function as an antenna for semiconductor package 40, thereby enabling communication functionality in semiconductor package 40 without an additional antenna structure. When antenna pattern 114' is formed by patterning a single layer, pattern portion 212'a can be additionally provided on first surface 200a of semiconductor chip 200. Consequently, the antenna performance of semiconductor package 40 can be enhanced.

[0050] In the semiconductor packages 10, 20, 30, and 40 according to exemplary embodiments of the present inventive concept, the sidewalls 100c of the substrate 100 and the sidewalls 130c of the mold layer 130 may be exposed to the outside. Therefore, moisture generated in the semiconductor packages 10, 20, 30, and 40 may be smoothly discharged or released to prevent moisture from causing chip damage, such as cracks (e.g., popcorn cracks) in the semiconductor chip 200.

[0051] The semiconductor package according to the exemplary embodiment of the present inventive concept may include a substrate pattern and / or an antenna pattern in a substrate. Therefore, the performance of the semiconductor package may be enhanced, and a small and thin semiconductor package may be realized.

[0052] While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined in the appended claims.

Claims

1. A semiconductor package, comprising: substrate; a semiconductor chip disposed on the first surface of the substrate; a solder bump disposed between the first surface of the semiconductor chip and the substrate; as well as a redistribution layer disposed on a second surface of the semiconductor chip opposite to the first surface, wherein the substrate includes a substrate pattern, wherein the substrate pattern covers the second surface of the substrate, and wherein the substrate pattern covers 60% to 100% of the total area of the second surface of the substrate, Each of the substrate patterns has a first portion vertically passing through the substrate and a second portion connected to the first portion, wherein a width of the first portion is substantially equal to a maximum width of each of the regions in which the solder bumps are disposed.

2. The semiconductor package according to claim 1, further comprising: a molding layer disposed between the substrate and the redistribution layer; as well as a via hole passing through the substrate and the molding layer, Wherein, the substrate further includes an antenna pattern, and The vias include ground vias, power vias and signal vias.

3. The semiconductor package according to claim 2, wherein The redistribution layer includes a redistribution pattern, and wherein the signal via is connected to at least one of the antenna pattern and the redistribution pattern.

4. The semiconductor package according to claim 2, wherein The redistribution layer includes a redistribution pattern, and wherein the ground via is connected to at least one of the antenna pattern and the redistribution pattern.

5. The semiconductor package according to claim 2, further comprising: A bonding pattern is provided between the semiconductor chip and the solder bump. The semiconductor package according to claim 5 , wherein: The redistribution layer includes connection pads, The solder balls are respectively arranged on the connection pads, and The semiconductor chip includes a semiconductor device electrically connected to the solder balls.

7. The semiconductor package according to claim 6, further comprising: a solder mask disposed on the first surface of the substrate, The solder mask forms a region in which the solder bumps are disposed.

8. The semiconductor package according to claim 7, wherein The shape of the region in which the solder bump is provided corresponds to the shape of the bonding pattern.

9. A semiconductor package comprising: substrate; a semiconductor chip mounted on the first surface of the substrate; a solder bump disposed between the first surface of the semiconductor chip and the first surface of the substrate; a shielding layer disposed between the semiconductor chip and the solder bump; as well as a redistribution layer disposed on a second surface of the semiconductor chip opposite to the first surface, Wherein, the substrate includes a substrate pattern and an antenna pattern, and Wherein, the substrate pattern covers the second surface of the substrate, Each of the substrate patterns has a first portion vertically passing through the substrate and a second portion connected to the first portion, wherein a width of the first portion is substantially equal to a maximum width of each of the regions in which the solder bumps are disposed.

10. The semiconductor package according to claim 9, wherein The substrate pattern covers 60% to 100% of the total area of the second surface of the substrate.

11. The semiconductor package according to claim 9, further comprising: a molding layer disposed between the substrate and the redistribution layer; as well as a via hole passing through the substrate and the molding layer, The vias include ground vias, power vias and signal vias.

12. The semiconductor package according to claim 11, wherein The redistribution layer includes a redistribution pattern, and The ground via is connected to at least one of the substrate patterns and at least one of the redistribution patterns.

13. The semiconductor package according to claim 12, wherein The shielding layer includes an adhesive layer, a shielding metal layer, and a protection layer stacked on the semiconductor chip.

14. The semiconductor package according to claim 13, wherein The adhesive layer covers the first surface of the semiconductor chip, and Wherein, the shielding metal layer covers the first surface of the adhesive layer.

15. The semiconductor package according to claim 13, wherein The barrier metal layer includes a contact portion and a pattern portion in an upper portion of the barrier metal layer.

16. The semiconductor package according to claim 15, wherein The shielding metal layer is connected to one of the ground via and the substrate pattern.

17. The semiconductor package according to claim 11, further comprising: a solder mask disposed on the first surface of the substrate, The solder mask forms a region in which the solder bumps are disposed.

18. A semiconductor package, comprising: substrate; a semiconductor chip mounted on the first surface of the substrate; a solder bump disposed between the first surface of the semiconductor chip and the substrate; a solder mask disposed on the first surface of the substrate; a shielding layer disposed between the semiconductor chip and the solder bump; a redistribution layer disposed on a second surface of the semiconductor chip opposite to the first surface; a molding layer covering a sidewall of the semiconductor chip and disposed between the substrate and the redistribution layer; as well as a via hole passing through the substrate and the molding layer, Wherein, the substrate includes a substrate pattern and an antenna pattern, Wherein, the substrate pattern covers the second surface of the substrate, wherein the solder bump is provided in an area formed by the solder mask, Wherein, the vias include ground vias, signal vias and power vias, wherein the redistribution layer is electrically connected to the semiconductor chip, and Wherein, the shielding layer includes an adhesive layer, a shielding metal layer and a protective layer, Each of the substrate patterns has a first portion vertically passing through the substrate and a second portion connected to the first portion, wherein a width of the first portion is substantially equal to a maximum width of each of the regions in which the solder bumps are disposed.

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