Display devices

Abstract

A display device is provided, the display device comprising: a substrate having an island and a plurality of connecting portions extending from the ends of the island in different directions and connected to different islands; a display area disposed on the island and including a display element connected to a common electrode; a common voltage power line disposed on the island and disposed on at least one first connecting portion of the plurality of connecting portions extending from the island; and at least one contact portion disposed on at least one first connecting portion, wherein the at least one contact portion is connected to the common electrode and the common voltage power line.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2019-0081523, filed on July 5, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] One or more embodiments relate to display devices, and more specifically, to stretchable display devices. Background Technology

[0003] Flat panel displays are electronic viewing technologies used to enable people to view content such as still and moving images, text, etc. Flat panel displays are much lighter, thinner, and use less power than traditional cathode ray tube televisions and video displays. Flat panel displays can include liquid crystal displays, light-emitting diode displays, organic light-emitting diode displays, plasma displays, electroluminescent panels, and quantum dot light-emitting diode displays.

[0004] However, flat panel displays are typically rigid and can be damaged if bent. Flexible displays can be folded or rolled up without being damaged. Stretchable displays can also be transformed into various shapes without damage. Summary of the Invention

[0005] At least one exemplary embodiment disclosed provides a display device having a stretchable or deformable shape.

[0006] According to an exemplary embodiment of the inventive concept, a display device is provided, the display device comprising: a substrate having an island and a plurality of connecting portions extending from the ends of the island in different directions and connected to different islands; a display area disposed on the island and including a display element connected to a common electrode; a common voltage power line disposed on the island and disposed on at least one first connecting portion of the plurality of connecting portions extending from the island; and at least one contact portion disposed on at least one first connecting portion, wherein the at least one contact portion is connected to the common electrode and the common voltage power line.

[0007] In one embodiment, the display device further includes a driving voltage power line disposed on at least one of the islands, wherein the driving voltage power line is disposed on a different layer from the layer on which the common voltage power line is disposed.

[0008] In one embodiment, a drive voltage power supply line is disposed on at least one first connection portion and is arranged to overlap with a common voltage power supply line.

[0009] In this embodiment, the width of the common voltage power supply line is larger than the width of the drive voltage power supply line.

[0010] In one embodiment, the display device further includes: a thin-film transistor disposed on the island and connected to the display element; and an inorganic protective layer disposed between the thin-film transistor and the display element, wherein the inorganic protective layer directly contacts the common electrode in the inorganic contact area, and the inorganic contact area is configured to surround the display area.

[0011] In one embodiment, at least one contact portion is disposed outside the inorganic contact area.

[0012] In an embodiment, the display device further includes: an encapsulation layer having an organic encapsulation layer, a first inorganic encapsulation layer disposed below the organic encapsulation layer, and a second inorganic encapsulation layer disposed on the organic encapsulation layer, wherein the organic encapsulation layer is stacked with the display area, and the first inorganic encapsulation layer and the second inorganic encapsulation layer are in contact with each other in the inorganic contact area.

[0013] In an embodiment, a first inorganic encapsulation layer and a second inorganic encapsulation layer are formed on a substrate, and the first inorganic encapsulation layer and the second inorganic encapsulation layer are in contact with each other at a plurality of connection portions.

[0014] In one embodiment, the substrate includes a plurality of through-holes penetrating the substrate around the island, and a first inorganic encapsulation layer and a second inorganic encapsulation layer are at least partially disposed on the side surfaces of the plurality of through-holes.

[0015] In an embodiment, the display device further includes at least one inorganic insulating layer disposed below the display element, wherein the at least one inorganic insulating layer includes an opening region corresponding to at least a portion of each of the plurality of connecting portions, and the opening region is filled with at least one organic material layer.

[0016] In one embodiment, the contact portion is disposed on at least one inorganic insulating layer.

[0017] In one embodiment, the display device further includes a drive voltage power line disposed on at least one of the island and the plurality of connecting portions, wherein the drive voltage power line is disposed on the same layer as the layer on which the common voltage power line is disposed.

[0018] In this embodiment, the width of the common voltage power supply line is larger than the width of the drive voltage power supply line.

[0019] In an embodiment, the display device further includes: a driving voltage power line disposed on an island and on at least one second connection portion among a plurality of connection portions, the at least one second connection portion extending in a direction different from the direction along which the at least one first connection portion extends, wherein the common voltage power line intersects the driving voltage power line in the display area.

[0020] In an embodiment, the display device further includes: an upper scan line disposed on at least one second connecting portion among a plurality of connecting portions, the at least one second connecting portion extending in a direction different from the direction along which the at least one first connecting portion extends; and a lower scan line disposed on an island, wherein the upper scan line and the lower scan line are disposed in different layers from each other and are connected to each other via a contact hole disposed in the at least one second connecting portion.

[0021] In one embodiment, the display device further includes a plurality of data lines disposed on at least one first connection portion, wherein the plurality of data lines and the upper scan line are disposed on the same layer.

[0022] According to an exemplary embodiment of the inventive concept, a display device is provided, the display device comprising: a substrate having a plurality of islands spaced apart from each other, a plurality of connecting portions connecting the plurality of islands, and a plurality of through holes penetrating the substrate between the plurality of connecting portions; a plurality of display areas respectively disposed on the plurality of islands, each display area including: an organic light-emitting diode; and an encapsulation layer hermetically sealing each of the plurality of display areas, wherein one of the plurality of connecting portions includes a common voltage power line and a contact portion, the contact portion being connected to the common electrode and the common voltage power line of an organic light-emitting diode of one of the plurality of display areas in one of the plurality of islands.

[0023] In one embodiment, the display device further includes a contact electrode disposed in a contact portion between the common electrode and the common voltage power line, wherein the contact electrode comprises the same material as the pixel electrode of the organic light-emitting diode.

[0024] In one embodiment, the display device further includes drive voltage power lines disposed on a portion of an island and multiple connections, wherein the drive voltage power lines are disposed on a different layer than the layer on which common voltage power lines are disposed.

[0025] In one embodiment, the drive voltage power supply line is configured to overlap with at least a portion of the common voltage power supply line.

[0026] In one embodiment, a display area further includes: a thin-film transistor connected to an organic light-emitting diode; and an inorganic protective layer disposed between the thin-film transistor and the organic light-emitting diode, wherein the inorganic protective layer directly contacts the common electrode in an inorganic contact area, and the inorganic contact area surrounds a display area.

[0027] In this embodiment, the encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer, wherein the first inorganic encapsulation layer and the second inorganic encapsulation layer are in direct contact with each other in the inorganic contact area.

[0028] According to an exemplary embodiment of the inventive concept, a display device is provided, the display device comprising: a substrate including a first pair of islands spaced apart from each other in a first direction and a second pair of islands spaced apart from each other in a first direction, the first pair and the second pair being spaced apart in a second direction different from the first direction, wherein each island includes: a display area including at least one display element; a plurality of connecting portions including a first connecting portion connecting the first pair of islands, a second connecting portion connecting the second pair of islands, a third connecting portion connecting the first islands of each pair, and a fourth connecting portion connecting the second islands of each pair; and an inorganic layer completely surrounding each of the display areas.

[0029] In an exemplary embodiment, the display device includes: a first power line for transmitting a first power supply voltage to one of a plurality of display areas of one of a plurality of islands, the first power line being disposed on a connection portion connected to one end of an island and an additional connection portion connected to the other end of an island; and a second power line for transmitting a second power supply voltage different from the first power supply voltage to a display area, the second power line being disposed on a connection portion and an additional connection portion.

[0030] In an exemplary embodiment, the display device includes: a first power line for transmitting a first power supply voltage to one of a plurality of display areas of one of a plurality of islands, the first power line being disposed on a connection portion connected to a first end of an island and on a first additional connection portion connected to a second end of an island opposite to the first end; and a second power line for transmitting a second power supply voltage different from the first power supply voltage to a display area, the second power line being disposed on a second additional connection portion connected to a third end of an island and on a third additional connection portion connected to a fourth end of an island opposite to the third end. Attached Figure Description

[0031] The above disclosure will become clearer from the following description taken in conjunction with the accompanying drawings, in which:

[0032] Figure 1 This is a schematic plan view of a display device according to the disclosed exemplary embodiments;

[0033] Figure 2 yes Figure 1 A schematic plan view of an example of area A;

[0034] Figure 3A and 3B It is an equivalent circuit diagram of any pixel of a display device according to the disclosed exemplary embodiments;

[0035] Figure 4 This is a schematic plan view of the basic unit of the substrate of a display device according to the disclosed exemplary embodiments;

[0036] Figure 5 It is along Figure 4 A schematic cross-sectional view taken from line II′;

[0037] Figure 6 This is a schematic cross-sectional view of a display device according to the disclosed exemplary embodiments;

[0038] Figure 7 This is a schematic cross-sectional view of a display device according to the disclosed exemplary embodiments;

[0039] Figure 8 This is a schematic cross-sectional view of a display device according to the disclosed exemplary embodiments;

[0040] Figure 9 A schematic plan view of a display device according to the disclosed exemplary embodiments; and

[0041] Figure 10 This is a schematic plan view of the signal lines applicable to the disclosed embodiments. Detailed Implementation

[0042] Reference will now be made in detail to the disclosed exemplary embodiments, examples of which are illustrated in the accompanying drawings, wherein the same reference numerals always denote the same elements. In this respect, the embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, the embodiments described below are explained only by reference to the accompanying drawings to clarify various aspects of this description. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0043] In the following description, expressions used in the singular include expressions used in the plural, unless they have a distinctly different meaning in the context.

[0044] In the following description, it will be understood that when a component such as a layer, film, region, or plate is referred to as being “on” another component, the component may be directly on the other component, or there may be an intermediate component on the other component.

[0045] When an embodiment can be implemented differently, the specific process sequence can be performed differently than the described sequence. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of the described sequence.

[0046] In the following description, it will be understood that when a layer, region, or component is referred to as being "connected to" another layer, region, or component, the layer, region, or component may be directly connected to the other layer, region, or component, or indirectly connected to the other layer, region, or component via an intermediate layer, region, or component. For example, in this specification, when a layer, region, or component is referred to as being electrically connected to another layer, region, or component, the layer, region, or component may be directly electrically connected to the other layer, region, or component, or indirectly electrically connected to the other layer, region, or component via an intermediate layer, region, or component.

[0047] Figure 1 This is a schematic plan view of a display device 10 according to the disclosed exemplary embodiments. Figure 2 yes Figure 1 A schematic plan view of an example of region A.

[0048] Reference Figure 1 The display device 10 according to the disclosed exemplary embodiments includes a substrate 100 and a plurality of display units 200 (e.g., display areas) disposed on the substrate 100.

[0049] The substrate 100 may include various materials. For example, the substrate 100 may include glass, metal or other organic materials.

[0050] In optional embodiments, substrate 100 may include a flexible material. For example, substrate 100 may include a bendable, foldable, or rollable material. The flexible material used to form substrate 100 may be ultrathin glass, metal, or plastic. When substrate 100 includes plastic, substrate 100 may include polyimide (PI). In another example, substrate 100 may include another type of plastic material.

[0051] The substrate 100 includes a plurality of islands 101 separated from each other, a plurality of connecting portions 102 connecting the islands 101 to each other, and a plurality of through holes V (bubbles, voids, spaces, etc.) penetrating the substrate 100 between the connecting portions 102.

[0052] The islands 101 are arranged to be separated from each other. For example, the islands 101 are repeatedly arranged in a first direction X and a second direction Y, which is different from the first direction X, to form a flat grid pattern. In one example, the first direction X and the second direction Y are perpendicular to each other. In another example, the first direction X and the second direction Y form an obtuse angle or an acute angle.

[0053] The display unit 200 is arranged on the island 101. The display unit 200 may include at least one display element to provide visible light or an image.

[0054] Connecting portions 102 connect islands 101 to each other. In an exemplary embodiment, each island 101 is connected to four connecting portions 102. In an exemplary embodiment, the four connecting portions 102 of island 101 extend in different directions around an island 101. For example, a first connecting portion of the four connecting portions 102 may be connected to a first end of an island 101, a second connecting portion of the four connecting portions 102 may be connected to a second end of the island 101 opposite to the first end, a third connecting portion of the four connecting portions 102 may be connected to a third end of the island 101, and a fourth connecting portion of the four connecting portions 102 may be connected to a fourth end of the island 101 opposite to the third end. For example, the four connecting portions 102 may form spokes. At least a portion of the island 101 and the connecting portions 102 may be formed continuously from the same material. The island 101 may be integrally formed with the connecting portions 102.

[0055] The through-hole V is formed by penetrating the substrate 100. The through-hole V provides a separation area between the islands 101, thereby reducing the weight of the substrate 100 and enhancing its flexibility. Furthermore, when the substrate 100 is bent, folded, or rolled, the shape of the through-hole V changes, thus easily reducing stress generation during deformation of the substrate 100. Therefore, abnormal deformation of the substrate 100 can be prevented, and its durability can be improved. Thus, user convenience can be improved during use of the display device 10; specifically, the display device 10 can be easily applied to wearable devices such as smartwatches.

[0056] The via V can be formed by removing a region of the substrate 100 using methods such as etching. In another example, the via V can be formed during the fabrication of the substrate 100. The via V can be formed in the substrate 100 using various methods.

[0057] In the following description, the basic unit U is defined as the basic unit used to form the substrate 100, and the structure of the substrate 100 is described in detail by using the basic unit U.

[0058] The basic unit U can be repeatedly arranged in the first direction X and the second direction Y. In other words, the base 100 can be interpreted as being formed by combining the basic units U repeatedly arranged in the first direction X and the second direction Y. The basic unit U may include an island 101 and at least one connecting portion 102 connected to the island 101. For example, four connecting portions 102 may be connected to an island 101.

[0059] In an exemplary embodiment, the islands 101 of two adjacent basic units U are separated or partitioned from each other, and the connecting portions 102 of the two adjacent basic units U can be connected to each other. The connecting portion 102 included in the basic unit U can refer to a portion of the connecting portion 102 located within the region of the basic unit U, or the entire connecting portion 102 connecting the two adjacent islands 101. In an exemplary embodiment, the two adjacent islands 101 are separated from each other, but connected to each other via the connecting portion 102.

[0060] Four adjacent basic units U within a basic unit U form a closed loop CL, which can define a through-hole V as an empty space. The through-hole V, formed by removing a portion of the substrate 100, can improve the flexibility of the substrate 100 and reduce the stress generated when the substrate 100 deforms. In an exemplary embodiment, the connecting portion 102 has a width smaller than the width of the island 101, so the through-hole V can contact the island 101 of the four basic units U. For example, the width of the connecting portion 102 in the second direction Y can be smaller than the width of the island 101.

[0061] Two adjacent basic units U in a basic unit U can be symmetrical to each other. In an exemplary embodiment, such as Figure 1 As shown, a basic unit U is symmetrical with respect to an axis of symmetry parallel to a first direction X and another basic unit U is arranged to be adjacent to the first basic unit U in a second direction Y. At the same time, the first basic unit U is symmetrical with respect to an axis of symmetry parallel to the second direction Y and yet another basic unit U is arranged to be adjacent to the first basic unit U in the first direction X.

[0062] Furthermore, the angle θ formed by the direction along which the connecting portion 102 extends and the side surface of the island 101 to which the connecting portion 102 connects can be an acute angle. For example, when the island 101 has a rectangular shape, and the corner portions of the rectangle are arranged to face the first direction X and the second direction Y, the connecting portion 102 can connect to the island 101 in the region adjacent to the corner portion, and can extend in a direction parallel to the second direction Y or the first direction X. In other words, the connecting portion 102 connected to the corner portion located in the first direction X can extend in the second direction Y or -second direction-Y, and the connecting portion 102 connected to the corner portion located in the second direction Y can extend in the first direction X or -first direction-X. For example, -first direction-X can be in a direction opposite to the first direction X, and -second direction-Y can be in a direction opposite to the second direction Y. Therefore, the side surfaces of two adjacent islands 101 connected to a connecting portion 102 can form an acute angle with the direction along which the connecting portion 102 extends. Therefore, islands 101 can be densely arranged, the length of connecting portion 102 can be reduced, and the size of through hole V can be increased. Additionally, as... Figure 2 As shown, the substrate 100 can be configured to be stretchable.

[0063] Figure 2 The shape of the substrate 100 when stretched in the first direction X and the second direction Y is shown. (Refer to...) Figure 2 When an external force is applied to the substrate 100, the angle θ' between the side surface of the connecting portion 102 of the island 101 and the connecting portion 102 increases (θ < θ'), thus the size of the through hole V can be increased. Therefore, as the spacing between the islands 101 increases, the substrate 100 can be stretched in the first direction X and the second direction Y, thus the shape of the substrate 100 can be changed in two or three dimensions.

[0064] Because the connecting portion 102 has a width smaller than that of the island 101, when an external force is applied to the base 100, the shape change for the increased angle θ mainly occurs in the connecting portion 102, and the shape of the island 101 remains unchanged even when the base 100 is stretched. Therefore, the display unit 200 disposed on the island 101 can be stably maintained even when the base 100 is stretched. Therefore, the display device 10 can be easily applied to display devices that require flexibility, such as curved (e.g., bendable) display devices, flexible display devices, or stretchable display devices.

[0065] When the base 100 is stretched, stress concentrates on the contact portion of the connector 102 that connects to the side surface of the corresponding island 101. Therefore, in order to prevent the connector 102 from tearing due to stress concentration, the contact portion of the connector 102 may include a curved surface.

[0066] The display unit 200 is provided with pixels PX having display elements to provide a certain image. Each pixel PX can emit, for example, red light, green light, blue light, or white light. For example, each pixel PX may include an organic light-emitting diode. In addition, each pixel PX may also include devices such as thin-film transistors (TFTs) or capacitors.

[0067] In an exemplary embodiment, pixel PX represents a sub-pixel that emits any one of the following: red light, green light, blue light, and white light as described above.

[0068] Although an organic light-emitting display device has been described above as an example of display device 10, the disclosed display device 10 is not limited thereto. For example, display device 10 may be a liquid crystal display, an electrophoretic display, an organic light-emitting display, an inorganic electroluminescent (EL) display, a field emission display, a surface conduction electron emitter display, a plasma display, or a cathode ray display.

[0069] Figure 3A and Figure 3B This is an equivalent circuit diagram of any pixel PX of the display device 10 according to the disclosed exemplary embodiments.

[0070] Reference Figure 3A Each pixel PX includes a pixel circuit PC connected to a scan line SL (e.g., a gate line) and a data line DL, and an organic light-emitting diode (OLED) connected to the pixel circuit PC.

[0071] The pixel circuit PC may include a driving thin-film transistor T1, a switching thin-film transistor T2, and a storage capacitor Cst. The switching thin-film transistor T2 may be connected to the scan line SL and the data line DL, and in response to the scan signal Sn input through the scan line SL, transmits the data signal Dm input through the data line DL to the driving thin-film transistor T1.

[0072] The storage capacitor Cst can be connected to the switching thin-film transistor T2 and the first power supply line PL1, and can store the voltage corresponding to the difference between the voltage received from the switching thin-film transistor T2 and the first power supply voltage (ELVDD or drive voltage) supplied to the first power supply line PL1.

[0073] The driving thin-film transistor T1 can be connected to the first power line PL1 and the storage capacitor Cst, and in response to the voltage value stored in the storage capacitor Cst, the driving current flowing from the first power line PL1 through the organic light-emitting diode (OLED) can be controlled. The OLED can emit light with a certain brightness according to the driving current.

[0074] although Figure 3AThe illustration shows a scenario where the pixel circuit PC includes two thin-film transistors and a storage capacitor, but the disclosure is not limited thereto. For example, the pixel circuit PC may include additional thin-film transistors.

[0075] Reference Figure 3B The pixel circuit PC includes a driving thin-film transistor T1, a switching thin-film transistor T2, a compensation thin-film transistor T3, a first initialization thin-film transistor T4, an operation control thin-film transistor T5, an emission control thin-film transistor T6, and a second initialization thin-film transistor T7.

[0076] although Figure 3B The illustration shows a configuration where signal lines SLn, SLn-1, EL, and DL, an initialization voltage line VL, and a first power line PL1 are provided for each pixel PX, but the disclosure is not limited thereto. In another embodiment, at least one of the signal lines SLn, SLn-1, EL, and DL and / or the initialization voltage line VL may be shared by adjacent pixels PX.

[0077] The drain electrode of the driving thin-film transistor T1 is electrically connected to the organic light-emitting diode (OLED) via the emitter control thin-film transistor T6. The driving thin-film transistor T1 receives the data signal Dm in response to the switching operation of the switching thin-film transistor T2 and supplies driving current to the OLED.

[0078] The gate electrode of the switching thin-film transistor T2 is connected to the scan line (e.g., SLn), and the source electrode of the switching thin-film transistor T2 is connected to the data line DL. The drain electrode of the switching thin-film transistor T2 is connected to the source electrode of the driving thin-film transistor T1, and is connected to the first power supply line PL1 via the operation control thin-film transistor T5.

[0079] The switching thin-film transistor T2 can be turned on in response to the scan signal Sn received through the scan line SLn and can perform a switching operation to transmit the data signal Dm through the data line DL to the source electrode of the driving thin-film transistor T1.

[0080] The gate electrode of the compensation thin-film transistor T3 is connected to the scan line SLn. The source electrode of the compensation thin-film transistor T3 is connected to the drain electrode of the driving thin-film transistor T1, and is connected to the pixel electrode of the organic light-emitting diode (OLED) via the emission control thin-film transistor T6. The drain electrode of the compensation thin-film transistor T3 is connected to the first electrode of the storage capacitor Cst, the source electrode of the first initialization thin-film transistor T4, and the gate electrode of the driving thin-film transistor T1. The compensation thin-film transistor T3 can be turned on in response to the scan signal Sn received via the scan line SLn, and the driving thin-film transistor T1 can be diode-connected by connecting the gate electrode and the drain electrode of the driving thin-film transistor T1 to each other.

[0081] The gate electrode of the first initialization thin-film transistor T4 is connected to the previous scan line SLn-1. The drain electrode of the first initialization thin-film transistor T4 is connected to the initialization voltage line VL. The source electrode of the first initialization thin-film transistor T4 is connected to the first electrode of the storage capacitor Cst, the drain electrode of the compensation thin-film transistor T3, and the gate electrode of the driving thin-film transistor T1. The first initialization thin-film transistor T4 can be turned on in response to the previous scan signal Sn-1 received through the previous scan line SLn-1, and transmit the initialization voltage VINT to the gate electrode of the driving thin-film transistor T1, thereby performing an initialization operation to initialize the voltage of the gate electrode of the driving thin-film transistor T1.

[0082] The gate electrode of the operation control thin-film transistor T5 is connected to the emitter control line EL. The source electrode of the operation control thin-film transistor T5 is connected to the first power supply line PL1. The drain electrode of the operation control thin-film transistor T5 is connected to the source electrode of the driving thin-film transistor T1 and the drain electrode of the switching thin-film transistor T2.

[0083] The gate electrode of the emission control thin-film transistor T6 is connected to the emission control line EL. The source electrode of the emission control thin-film transistor T6 is connected to the drain electrode of the driving thin-film transistor T1 and the source electrode of the compensation thin-film transistor T3. The drain electrode of the emission control thin-film transistor T6 can be electrically connected to the pixel electrode of the organic light-emitting diode (OLED). The operation control thin-film transistor T5 and the emission control thin-film transistor T6 can be simultaneously turned on in response to the emission control signal EM received through the emission control line EL, and can transmit the first power supply voltage ELVDD to the OLED, thus driving current flows in the OLED.

[0084] The gate electrode of the second initialization thin-film transistor T7 is connected to the previous scan line (e.g., SLn-1). The source electrode of the second initialization thin-film transistor T7 is connected to the pixel electrode of the organic light-emitting diode (OLED). The drain electrode of the second initialization thin-film transistor T7 is connected to the initialization voltage line VL. The second initialization thin-film transistor T7 can be turned on in response to the previous scan signal Sn-1 received through the previous scan line SLn-1, and can initialize the pixel electrode of the organic light-emitting diode (OLED).

[0085] although Figure 3B The illustration shows a case where the first initialization thin-film transistor T4 and the second initialization thin-film transistor T7 are connected to the previous scan line SLn-1, but the disclosure is not limited thereto. In another embodiment, the first initialization thin-film transistor T4 may be connected to the previous scan line SLn-1 and may be driven by the previous scan signal Sn-1, and the second initialization thin-film transistor T7 may be connected to a separate signal line (e.g., the next scan line) and may be driven by a signal transmitted to the corresponding scan line.

[0086] The second electrode of the storage capacitor Cst is connected to the first power supply line PL1. The first electrode of the storage capacitor Cst is connected to the gate electrode of the driving thin-film transistor T1, the drain electrode of the compensation thin-film transistor T3, and the source electrode of the first initialization thin-film transistor T4.

[0087] The common electrode (e.g., cathode) of the organic light-emitting diode (OLED) is connected to a second power supply line PL2 and receives a second power supply voltage (ELVSS or common power supply voltage). The OLED emits light by receiving a drive current from the driving thin-film transistor T1. The second power supply voltage ELVSS can be ground. The second power supply voltage ELVSS can be lower than the first power supply voltage ELVDD.

[0088] Because the quantity and circuit design can be varied, the pixel circuit PC is not limited to the reference. Figure 3A and Figure 3B The number of thin-film transistors and storage capacitors described, as well as the circuit design.

[0089] Figure 4 It is a schematic plan view of the basic unit U according to the disclosed exemplary embodiments. Figure 5 It is along Figure 4 A schematic cross-sectional view taken from line I-I'.

[0090] Reference Figure 4 and Figure 5 The display unit 200 (e.g., display area) and the inorganic contact area ICA surrounding the display unit 200 may be located on the island 101 of the basic unit U. The connecting portion 102 may include a pair of first connecting portions 102a and a pair of second connecting portions 102b. The pair of first connecting portions 102a are located on opposite sides of the island 101 and extend in a direction parallel to the first direction X. The pair of second connecting portions 102b are located on opposite sides of the island 101 and extend in a direction parallel to the second direction Y.

[0091] Display unit 200 is located on island 101. At least one organic light-emitting diode (OLED) emitting, for example, red, blue, green, or white light may be located within display unit 200. In an embodiment, the OLED is electrically connected to a thin-film transistor (TFT). In this embodiment, the OLED is described as a display element. However, since display unit 200 may include various types of display elements (such as inorganic EL devices, quantum dot light-emitting devices, or liquid crystal devices), the disclosed embodiments are not limited thereto.

[0092] Each display unit 200 may include multiple OLEDs for different colors of light. For example, such as Figure 4As shown, a display unit 200 may include an OLED for emitting red R light, an OLED for emitting green G light, and an OLED for emitting blue B light.

[0093] However, the disclosed embodiments are not limited thereto. In another example, each of the display units 200 may include only one organic light-emitting diode (OLED) for emitting red, blue, green, or white light, such that each of the display units 200 may form a sub-pixel.

[0094] In addition, the organic light-emitting diodes (OLEDs) in the display unit 200 can be arranged in various ways, such as RGB, pentile structure or honeycomb structure, depending on the efficiency of the organic light-emitting layer material.

[0095] In an exemplary embodiment, the display unit 200 on island 101 is completely surrounded by an inorganic contact area (ICA). For example, one or more inorganic layers may surround each display unit 200. In this respect, Figure 4 The diagram shows a red R OLED, a green G OLED, and a blue B OLED completely surrounded on a flat surface by an inorganic contact area (ICA).

[0096] In an exemplary embodiment, the inorganic contact area ICA is a region formed by at least two layers comprising inorganic materials in direct contact with each other. The inorganic contact area ICA can prevent external moisture from penetrating into the display element disposed in each pixel PX. The inorganic contact area ICA can extend along the edge of island 101, and the pixel PX can be disposed inside the inorganic contact area ICA.

[0097] In an exemplary embodiment, the connection portion 102 is disposed outside the inorganic contact area ICA, and the wire connected to the display unit 200 is disposed on the connection portion 102. In an exemplary embodiment, all or part of the wire passes through the connection portion 102. For example, a power cord may pass through the connection portion 102 such that the connection portion 102 completely surrounds the power cord.

[0098] For example, used to convert the first power supply voltage ELVDD (see Figure 3A and Figure 3B The first power supply line PL1 (or drive voltage power supply line) is transmitted to the display unit 200, and the second power supply voltage ELVSS (see...) is used to transmit the second power supply voltage to the display unit 200. Figure 3A and Figure 3B The second power line PL2 (or common voltage power line) that transmits power to the display unit 200 can be connected to the display unit 200 via the connection part 102.

[0099] In an exemplary embodiment, such as Figure 4As shown, a first power line PL1 and a second power line PL2 are disposed in a first connecting portion 102a extending along a first direction X and passing through the display unit 200. For example, portions of the first power line PL1 and the second power line PL2 may overlap with the display unit 200. In another embodiment, the first power line PL1 and the second power line PL2 are disposed in a second connecting portion 102b extending along a second direction Y and passing through the display unit 200. In another embodiment, the first power line PL1 is disposed in the first connecting portion 102a, and the second power line PL2 is disposed in the second connecting portion 102b. For example, the first connecting portion 102a may completely surround the first power line PL1, and the second connecting portion 102b may completely surround the second power line PL2.

[0100] like Figure 4 As shown, the first power line PL1 and the second power line PL2 can be disposed in different layers so that they cross each other inside island 101. However, the disclosed embodiments are not limited to this. In an exemplary embodiment, the first power line PL1 and the second power line PL2 do not cross each other in a plane, and the first power line PL1 and the second power line PL2 can be disposed in the same layer. Although Figure 4 The second power line PL2 is shown to be thicker than the first power line PL1, but the disclosed embodiments are not limited thereto. For example, power lines PL1 and PL2 may have the same or substantially the same thickness, or the first power line PL1 may be thicker than the second power line PL2.

[0101] The connection portion 102 may be provided with a common electrode contact portion CCNT (hereinafter referred to as the contact portion) for applying a certain voltage to the common electrode of each display element. Since the common electrode of the display element and the second power line PL2 are connected to each other through the contact portion CCNT, the second driving voltage (ELVSS) can be transmitted to the common electrode. The contact portion CCNT may be provided outside the inorganic contact area ICA.

[0102] The contact portion CCNT can be disposed in the first connecting portion 102a of the connecting portion 102. The contact portion CCNT can be disposed in either or both of the first connecting portions 102a. However, the disclosed embodiments are not limited thereto. The contact portion CCNT can be varied according to the arrangement position of the second power line PL2. For example, the contact portion CCNT can be disposed in the second connecting portion 102b.

[0103] In one embodiment, a contact portion CCNT may be provided for each basic unit U. In another embodiment, the contact portion CCNT may be provided periodically for each basic unit U, rather than for each individual basic unit U.

[0104] Despite Figure 4Although not shown, various signal lines (e.g., data lines DL and scan lines SL) can be provided in the connection section 102 and the display unit 200.

[0105] The following reference Figure 5 The stacking structure of the display device 10 according to the disclosed exemplary embodiments is described. First, the display units 200 disposed on the island 101 are described in stacking order.

[0106] A buffer layer 201 is formed on island 101. The buffer layer 201 prevents impurities from entering the semiconductor layer Act of the thin-film transistor (TFT). The buffer layer 201 may include materials such as silicon oxide (SiO2). x or silicon nitride (SiN) x The inorganic insulating material may include a single layer or multiple layers containing the aforementioned inorganic insulating material.

[0107] A pixel circuit PC is disposed on a buffer layer 201. The pixel circuit PC includes a thin-film transistor (TFT) and a storage capacitor Cst. The TFT includes a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE. Although this embodiment shows a top-gate type in which the gate electrode GE is disposed on the semiconductor layer Act and a gate insulating layer 203 is between the gate electrode GE and the semiconductor layer Act, according to another embodiment, the TFT may be a bottom-gate type.

[0108] The semiconductor layer Act may include polycrystalline silicon. Alternatively, the semiconductor layer Act may include amorphous silicon, oxide semiconductor, or organic semiconductor. The gate electrode GE may include a low-resistance metallic material. The gate electrode GE may include a conductive material comprising aluminum (Al), copper (Cu), or titanium (Ti), and may comprise a multilayer or a single layer comprising the aforementioned materials.

[0109] The gate insulating layer 203 between the semiconductor layer Act and the gate electrode GE may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, or hafnium oxide. The gate insulating layer 203 may include a single layer or multiple layers containing the above-mentioned materials.

[0110] The source electrode SE and drain electrode DE can include materials exhibiting excellent conductivity. The source electrode SE and drain electrode DE can include conductive materials comprising molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and can comprise multilayers or single layers containing the aforementioned materials. In an embodiment, the source electrode SE and drain electrode DE can comprise a Ti / Al / Ti multilayer.

[0111] The storage capacitor Cst includes a lower electrode CE1 and an upper electrode CE2, which are stacked on top of each other, and a first interlayer insulating layer 205 is provided between the lower electrode CE1 and the upper electrode CE2. The storage capacitor Cst can be stacked with a thin-film transistor (TFT). In this respect, Figure 5 The diagram shows that the gate electrode GE of the thin-film transistor TFT is the lower electrode CE1 of the storage capacitor Cst. In another embodiment, the storage capacitor Cst is not stacked with the thin-film transistor TFT. The storage capacitor Cst is covered by a second interlayer insulating layer 207.

[0112] The source electrode SE and drain electrode DE, the data line DL, and the first power line PL1 are disposed on the second interlayer insulating layer 207. The source electrode SE and drain electrode DE can be connected to the semiconductor layer Act via vias that penetrate the second interlayer insulating layer 207, the first interlayer insulating layer 205, and the gate insulating layer 203.

[0113] The first interlayer insulation layer 205 and the second interlayer insulation layer 207 may comprise inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, or hafnium oxide. Both the first interlayer insulation layer 205 and the second interlayer insulation layer 207 may comprise a single layer or multiple layers containing the aforementioned materials.

[0114] An inorganic protective layer PVX is disposed on the thin-film transistor TFT, the data line DL, and the first power line PL1. The inorganic protective layer PVX covers and protects the source electrode SE and drain electrode DE of the thin-film transistor TFT, the data line DL, and the first power line PL1. A line (not shown) formed in the same process as the source electrode SE is exposed in a portion of the substrate 100. The exposed portion of the line is damaged by the patterned etchant used for the pixel electrode 221. Figure 5 In the embodiment shown, since the inorganic protective layer PVX covers at least a portion of the lines, the lines can be prevented from being damaged during the patterning process of the pixel electrode 221.

[0115] The inorganic protective layer PVX may include silicon nitride (SiN). x ) and silicon dioxide (SiO) x () Single or multiple layers.

[0116] The lower planarization layer 208 may be disposed on the inorganic protective layer PVX. The lower planarization layer 208 may include an organic insulating material such as a general-purpose polymer. The general-purpose polymer may include polymethyl methacrylate (PMMA) or polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0117] In an exemplary embodiment, a connection metal CM connecting the pixel electrode 221 to the thin-film transistor TFT is disposed on the lower planarization layer 208. In an exemplary embodiment, the second power line PL2 is disposed on the same layer as the connection metal CM. The connection metal CM and the second power line PL2 may comprise a conductive material containing molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may comprise multiple layers or a single layer containing the aforementioned materials. The second power line PL2 may be partially superimposed on the first power line PL1 or the data line DL. Because the lower planarization layer 208 is disposed, lines can be disposed on the upper surface of the lower planarization layer 208, thereby improving the density of the display unit 200.

[0118] In an exemplary embodiment, a planarization layer 209 is disposed on the lower planarization layer 208 to cover the second power line PL2. The planarization layer 209 may include an organic insulating material such as a general-purpose polymer. General-purpose polymers may include polymethyl methacrylate (PMMA) or polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof. In an embodiment, the planarization layer 209 comprises polyimide.

[0119] In an exemplary embodiment, the planarization layer 209 has an approximately flat or completely flat upper surface. In an exemplary embodiment, a pixel electrode 221 is formed on the planarization layer 209. The pixel electrode 221 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or zinc aluminum oxide (AZO). In another embodiment, the pixel electrode 221 may include a reflective layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or mixtures thereof. In another embodiment, the pixel electrode 221 may also include a layer comprising ITO, IZO, ZnO, or In2O3 on or below the aforementioned reflective layer.

[0120] In an exemplary embodiment, a pixel defining layer 211 is formed on the pixel electrode 221. The pixel defining layer 211 may include an opening 211OP exposing the upper surface of the pixel electrode 221 while covering the edge of the pixel electrode 221. Therefore, the pixel defining layer 211 can define the light-emitting region of the pixel PX. The pixel defining layer 211 may include an organic insulating material.

[0121] In an exemplary embodiment, an intermediate layer 222 is disposed in the opening 211OP to cover the exposed portion of the pixel electrode 221. The intermediate layer 222 of the organic light-emitting diode (OLED) may comprise a low molecular weight material or a polymer material. When comprising a low molecular weight material, the intermediate layer 222 may have a stacked structure and may comprise various organic materials such as copper phthalocyanine (CuPc), N,N'-di(naphthyl-1-yl)-N,N'-diphenylbenzidine (NPB), or aluminum tri-8-hydroxyquinoline (Alq3), the stacked structure having a single-layer or composite structure of a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). These layers may be formed by vacuum deposition.

[0122] When the interlayer 222 comprises a polymer material, it can typically have a structure including an HTL and an EML. In this state, the HTL can include PEDOT, and the EML can include polyphenylenevinyl chloride (PPV) and polyfluorene polymer materials. The interlayer 222 can be formed by screen printing, inkjet printing, or laser-induced thermal imaging (LITI).

[0123] Intermediate layer 222 is not limited to this and may have various structures. Intermediate layer 222 may include an integrated layer covering a plurality of pixel electrodes 221 and may include a layer patterned to correspond to each of the pixel electrodes 221.

[0124] The common electrode 223 comprises a conductive material. The conductive material may have a low work function. For example, the common electrode 223 may comprise a (semi-)transparent layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or alloys thereof. Optionally, the common electrode 223 may also comprise a layer such as ITO, IZO, ZnO, or In2O3 situated on the (semi-)transparent layer comprising the aforementioned material. The common electrode 223 may be formed not only in the display area (e.g., display unit 200) but also in the non-display area. The non-display area may surround the display area. The intermediate layer 222 and the common electrode 223 may be formed by thermal deposition. The common electrode 223 may be formed on the entire surface of the substrate 100 and partially on the side surface of the via V.

[0125] A capping layer (not shown) for protecting the common electrode 223 may also be disposed on the common electrode 223. The capping layer may include lithium fluoride (LiF), other inorganic materials and / or organic materials.

[0126] The lower planarization layer 208, planarization layer 209, and pixel definition layer 211 may include inorganic contact holes ICH of the inorganic protective layer PVX at the edge of the exposed island 101. The inorganic contact region ICA may be defined by the area of ​​the inorganic protective layer PVX exposed by the inorganic contact holes ICH.

[0127] The inorganic contact hole ICH can be formed by a first hole 208H of the lower planarization layer 208, a second hole 209H of the planarization layer 209, and a third hole 211H of the pixel defining layer 211, which are connected to each other. Therefore, a step can be formed on the inner surface of the inorganic contact hole ICH.

[0128] Since the common electrode 223 is disposed in the inorganic contact hole ICH, the inorganic protective layer PVX, which includes inorganic material, and the common electrode 223 can directly contact each other. In an exemplary embodiment, the end of the inorganic protective layer PVX directly contacts the common electrode 223. Because portions of the lower planarization layer 208, planarization layer 209, and pixel defining layer 211, which include organic material, are removed, the inorganic contact hole ICH is formed. Therefore, the inorganic contact region ICA can prevent moisture from penetrating into the organic light-emitting diode (OLED) through the organic material.

[0129] Next, the stacking structure provided in one of the first connecting parts 102a will be described below.

[0130] The buffer layer 201, gate insulating layer 203, first interlayer insulating layer 205, and second interlayer insulating layer 207 disposed in island 101 can extend to the first connection portion 102a of substrate 100 to be disposed in the first connection portion 102a of substrate 100. The buffer layer 201, gate insulating layer 203, first interlayer insulating layer 205, and second interlayer insulating layer 207, which may be referred to as inorganic insulating layer 215, may comprise inorganic materials. Inorganic insulating layer 215 may comprise an opening region OA corresponding to a portion of the first connection portion 102a. In other words, the buffer layer 201, gate insulating layer 203, first interlayer insulating layer 205, and second interlayer insulating layer 207 may all have openings corresponding to portions of the first connection portion 102a. Although the openings are shown in the figures as having matching inner surfaces, the disclosed embodiments are not limited thereto. For example, the side surface of the inorganic insulating layer 215 forming the opening region OA may have a step.

[0131] The display device 10 according to the disclosed exemplary embodiment includes an organic material layer 202 that fills the opening region OA of the inorganic insulating layer 215. Since the first connection portion 102a of the substrate 100 has a width smaller than the width of the island 101, the first connection portion 102a can be weaker than the stress generated when the display device 10 deforms.

[0132] In the disclosed exemplary embodiment, in the first connection portion 102a, the opening region OA is formed by removing a portion of the inorganic insulating layer 215 that has a high probability of crack generation, and the organic material layer 202 is disposed in the opening region OA, so that even when the display device 10 is deformed, the generation of cracks can be prevented or reduced.

[0133] In an exemplary embodiment, the width of the opening region OA is smaller than the length of the first connection portion 102a. In other words, a portion of the inorganic insulating layer 215 may extend into the first connection portion 102a to be disposed therein. The end portion EG of the inorganic insulating layer 215 is disposed on the first connection portion 102a. In other words, the end portions EG of the buffer layer 201, the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207 may be disposed on the first connection portion 102a.

[0134] The organic material layer 202 can be configured to cover the end EG of the inorganic insulating layer 215. Optionally, the organic material layer 202 can be understood as filling the opening region OA and extending to the upper surface of the inorganic insulating layer 215 to be disposed on the upper surface of the inorganic insulating layer 215. Lines PL1, PL2, and WL for transmitting voltage or signals to the display unit 200 are disposed on the organic material layer 202. The organic material layer 202 can reduce the height difference when lines PL1, PL2, and WL extend to the island 101, and simultaneously absorb the stress applied to lines PL1, PL2, and WL.

[0135] The organic material layer 202 may include organic insulating materials such as polyimide, polyamide, acrylic resin, benzocyclobutene, hexamethyldisiloxane (HMDSO), and phenolic resin. The organic material layer 202 may have a single-layer or multi-layer structure of the organic insulating material as described above.

[0136] The line WL and the first power line PL1 disposed on the organic material layer 202 may comprise the same material as the source electrode SE or drain electrode DE of the thin-film transistor TFT disposed on island 101. Optionally, the line WL disposed on the organic material layer 202 may comprise the same material as the gate electrode GE of the thin-film transistor TFT. The line WL may be a line for transmitting signals to the pixel circuit PC. For example, the line WL may be a data line for transmitting data signals (e.g., Dm) to the pixel circuit PC. Optionally, the line WL may be a scan line for transmitting scan signals (e.g., Sn) to the pixel circuit PC. The line WL and the first power line PL1 may be covered by the lower planarization layer 208.

[0137] The second power line PL2 can be disposed on the lower planarization layer 208. In this embodiment, the second power line PL2 can be disposed on a different layer than the layer on which the first power line PL1 and line WL are disposed. Therefore, the second power line PL2 is formed to be stacked with various lines WL and PL1, thereby improving density.

[0138] Although a first power line PL1 and a line WL are shown in the accompanying drawings, the disclosed embodiments are not limited thereto. The first power line PL1 and the line WL disposed on a first connection portion 102a may each include multiple first power lines PL1 and multiple lines WL.

[0139] The second power line PL2 is covered by a planarization layer 209, which may include a contact portion CCNT exposing a portion (e.g., the upper surface) of the second power line PL2. A contact electrode COE may be disposed in the contact portion CCNT. The contact electrode COE may include the same material as the pixel electrode 221. The contact electrode COE may be introduced to prevent the second power line PL2 from being damaged during the manufacturing process. The contact electrode COE may be disposed between the second power line PL2 and the common electrode 223.

[0140] In an exemplary embodiment, the common electrode 223 is formed entirely above the island 101 and the first connection portion 102a, and is connected to the second power line PL2 via the contact portion CCNT. In one embodiment, the common electrode 223 is connected to the second power line PL2 via a contact electrode COE disposed in the contact portion CCNT. In another embodiment, the common electrode 223 directly contacts the second power line PL2. For example, the contact electrode COE may be omitted.

[0141] In this embodiment, the contact portion CCNT is disposed on an inorganic insulating layer 215, such as a buffer layer 201, extending from the island 101. In other words, the contact portion CCNT can be disposed on the first connection portion 102a to be stacked with the buffer layer 201, the gate insulating layer 203, the first interlayer insulating layer 205, and / or the second interlayer insulating layer 207. In this case, the height difference between the contact portion CCNT and the region of the island 101 is relatively small when the contact portion CCNT is formed, which can be advantageous in the manufacturing process.

[0142] However, the disclosed embodiments are not limited thereto. Various modifications can be made to the contact portion CCNT such that the contact portion CCNT is formed in the opening region OA, which is the area where the inorganic insulating layer 215 is removed.

[0143] Figure 6 This is a schematic cross-sectional view of a display device 10 according to a disclosed exemplary embodiment. Figure 6 In the attached figures, the reference numerals and... Figure 5 The accompanying figures are labeled the same, and their redundant descriptions are omitted.

[0144] Reference Figure 6 The display device 10 includes a substrate 100 having an island 101 and a first connecting portion 102a. A display element is disposed on the island 101, and a contact portion CCNT to which the common electrode 223 of the display element and the second power line PL2 are connected is disposed on the first connecting portion 102a. In addition, the first power line PL1 and the second power line PL2 are disposed in the first connecting portion 102a on different layers from each other.

[0145] although Figure 5 The first power line PL1 and the second power line PL2 are shown not overlapping each other at the first connection portion 102a, but the disclosed embodiment is not limited thereto. Figure 6 As shown, the second power line PL2 is stacked on top of the first power line PL1. Since the second power line PL2 is located on a different layer than the layer where the first power line PL1 is located, the width W2 of the second power line PL2 can be larger than the width W1 of the first power line PL1. Therefore, the voltage drop phenomenon in the second power supply voltage ELVSS can be significantly reduced.

[0146] Figure 7 This is a schematic cross-sectional view of a display device 10 according to an exemplary embodiment of the inventive concept. Figure 7 In the attached figures, the reference numerals and... Figure 5 The accompanying figures are labeled the same, and their redundant descriptions are omitted.

[0147] Reference Figure 7 The display device 10 includes an encapsulation layer 300 that seals the display unit 200. The encapsulation layer 300 can block external oxygen and moisture, and can include a single layer or multiple layers. The encapsulation layer 300 can include at least one of organic encapsulation layers and inorganic encapsulation layers.

[0148] although Figure 7 The illustration shows an encapsulation layer 300 comprising a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 disposed between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330; however, the disclosed embodiments are not limited thereto. In other embodiments, the number of organic encapsulation layers, the number of inorganic encapsulation layers, and their stacking order may be varied.

[0149] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may comprise at least one inorganic insulating material such as alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, or silicon oxynitride, and may be formed by chemical vapor deposition (CVD). The organic encapsulation layer 320 may comprise a polymeric material. Polymeric materials may include acrylic resins, epoxy resins, polyimides, and polyethylene.

[0150] Since the first inorganic encapsulation layer 310 is formed according to the underlying structure, therefore, Figure 7 As shown, the upper surface of the first inorganic encapsulation layer 310 is not flat. An organic encapsulation layer 320 covers the first inorganic encapsulation layer 310 to have an approximately flat upper surface different from that of the first inorganic encapsulation layer 310. In an exemplary embodiment, the organic encapsulation layer 320 has an approximately flat upper surface in the portion corresponding to the organic light-emitting diode (OLED) as a display element. Furthermore, the organic encapsulation layer 320 can reduce the stress generated in the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330.

[0151] The organic encapsulation layer 320 may include polymethyl methacrylate (PMMA), polycarbonate (PC), polystyrene (PS), acrylic resin, epoxy resin, polyimide, polyethylene, polyethylene sulfonate, polyoxymethylene, polyarylate, or hexamethyldisiloxane.

[0152] In an exemplary embodiment, the organic encapsulation layer 320 includes a plurality of unit organic encapsulation layers 320u, each corresponding to a display unit 200. In other words, each unit organic encapsulation layer 320u can be disposed on the island 101 of the substrate 100, rather than in the connecting portion 102. Therefore, since the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 are in contact with each other at the edge of the unit organic encapsulation layer 320u, each of the display units 200 can be individually encapsulated.

[0153] Since the encapsulation layer 300 may include a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330, even if cracks appear in the encapsulation layer 300, the multilayer structure prevents the cracks from connecting between the first inorganic encapsulation layer 310 and the organic encapsulation layer 320, or between the organic encapsulation layer 320 and the second inorganic encapsulation layer 330. Therefore, the formation of pathways for external moisture or oxygen to enter the display unit 200 can be prevented or reduced. Furthermore, since the second inorganic encapsulation layer 330 contacts the first inorganic encapsulation layer 310 at its edge located outside the unit's organic encapsulation layer 320u, the unit's organic encapsulation layer 320u is prevented from being exposed to the outside.

[0154] In an exemplary embodiment, the unit organic encapsulation layer 320u is not disposed in the inorganic contact region ICA. Since the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 are in direct contact with each other in the inorganic contact region ICA, the inorganic protective layer PVX, the common electrode 223, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330, which are inorganic material layers, are sequentially stacked in the inorganic contact region ICA.

[0155] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 can be formed on the entire surface of the substrate 100 using chemical vapor deposition (CVD) such that the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 cover the side surface of the via V.

[0156] The organic encapsulation layer 320 is not disposed on the first connecting portion 102a. Therefore, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 can be in direct contact with each other on the first connecting portion 102a.

[0157] In the disclosed exemplary embodiments, the encapsulation layer 300 hermetically seals each of the display units 200. Therefore, even when the shape of the display device 10 is deformed, the change in the sealing properties of the encapsulation layer 300 can be reduced.

[0158] Figure 8 This is a schematic cross-sectional view of a display device 10 according to a disclosed exemplary embodiment. Figure 8 In the attached figures, the reference numerals and... Figure 5 The accompanying figures are labeled the same, and their redundant descriptions are omitted.

[0159] Reference Figure 8 The display device 10 includes a base 100 having an island 101 and a first connecting portion 102a. A display element is disposed on the island 101, and a contact portion CCNT to which the common electrode 223 and the second power line PL2 of the display element are connected is disposed on the first connecting portion 102a.

[0160] exist Figure 8 In the embodiment shown, the first power line PL1, the second power line PL2, and the line WL on the first connection portion 102a are disposed on the same layer. For example, the first power line PL1, the second power line PL2, and the line WL can be disposed on the organic material layer 202. In this case, the first power line PL1, the second power line PL2, and the line WL can include the same material as the source electrode SE. Since the first power line PL1, the second power line PL2, and the line WL are disposed on the same layer, the lower planarization layer 208 is omitted in this embodiment. In this embodiment, the width W2 of the second power line PL2 can be larger than the width W1 of the first power line PL1.

[0161] Figure 9 This is a schematic plan view of a display device 10 according to a disclosed exemplary embodiment. Figure 9 In the attached figures, the reference numerals and... Figure 4 The accompanying figures are labeled the same, and their redundant descriptions are omitted.

[0162] Reference Figure 9The inorganic contact area ICA surrounding the display unit 200 can be located on the island 101 of the basic unit U. The connecting part 102 can include a first connecting part 102a and a second connecting part 102b. The first connecting part 102a is located on the opposite side of the island 101 and extends in a direction parallel to the first direction X. The second connecting part 102b is located on the opposite side of the island 101 and extends in a direction parallel to the second direction Y.

[0163] In this embodiment, one of the first power line PL1 and the second power line PL2 is disposed in the first connecting part 102a, and the other is disposed in the second connecting part 102b.

[0164] For example, such as Figure 9 As shown, the first power line PL1 can be disposed on the second connecting portion 102b extending along the second direction Y, and the second power line PL2 can be disposed on the first connecting portion 102a extending along the first direction X. Optionally, the second power line PL2 can be disposed on the second connecting portion 102b extending along the second direction Y, and the first power line PL1 can be disposed on the first connecting portion 102a extending along the first direction X. Therefore, the first power line PL1 and the second power line PL2 intersect each other in the display unit 200. In this case, the first power line PL1 and the second power line PL2 can be disposed on different layers. The first power line PL1 may include multiple first power lines.

[0165] Figure 10 This is a schematic plan view of the signal lines applicable to the disclosed embodiments. Figure 10 In the attached figures, the reference numerals and... Figure 4 The accompanying figures are labeled the same, and their redundant descriptions are omitted.

[0166] Reference Figure 10 The inorganic contact area ICA surrounding the display unit 200 and the display unit 200 are located in the island 101 of the basic unit U. The connecting part 102 includes a first connecting part 102a and a second connecting part 102b. The first connecting part 102a is located on the opposite side of the island 101 and extends in a direction parallel to the first direction X. The second connecting part 102b is located on the opposite side of the island 101 and extends in a direction parallel to the second direction Y.

[0167] Multiple pixel circuits PC1, PC2, and PC3 are disposed in island 101. The first pixel circuit PC1 is connected to the blue BOLED, the second pixel circuit PC2 is connected to the red ROLED, and the third pixel circuit PC3 is connected to the green GOLED, thereby driving the respective OLEDs.

[0168] In an exemplary embodiment, a scan line SL extends from a second connection portion 102b on one side and passes through a first pixel circuit PC1, a second pixel circuit PC2, and a third pixel circuit PC3 via the second connection portion 102b on the other side to reach an adjacent island. The scan line SL includes an upper scan line SL1 and a lower scan line SLb disposed on different layers. The upper scan line SL1 may be disposed on the second connection portion 102b and connected to the lower scan line SLb via a contact hole SCNT. The upper scan line SL1 may be disposed on the organic material layer 202 (see...). Figure 5 The lower scan line SLb can be disposed on island 101 and can be disposed on gate insulating layer 203 (see Figure 5 ) or first interlayer insulation layer 205 (see Figure 5 On the previous scan line SLn-1 and the emission control line EL (see...) Figure 3B It can be set parallel to the scan line SL.

[0169] The data line DL may include a first data line DL1, a second data line DL2, and a third data line DL3. The first data line DL1 can be connected to a first pixel circuit PC1, the second data line DL2 can be connected to a second pixel circuit PC2, and the third data line DL3 can be connected to a third pixel circuit PC3. A first power line PL1 can be arranged parallel to the data lines DL. The data lines DL can be... Figures 5 to 8 The lines WL correspond to each other. The data lines DL and SL can cross each other in the display unit 200.

[0170] According to at least one of the above embodiments, a display device with a deformable or stretchable shape and high brightness uniformity can be provided. However, the scope of the disclosed exemplary embodiments is not limited to the effects described above.

[0171] Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept.

Claims

1. A display device, the display device comprising: The base includes an island and a plurality of connecting portions extending from the ends of the island in different directions and connected to different islands; A display area is disposed on the island and includes a display element connected to a common electrode; A common voltage power supply line is provided on the island and on at least one first connection of the plurality of connection portions extending from the island; At least one contact portion is disposed on the at least one first connecting portion, wherein the at least one contact portion is connected to the common electrode and the common voltage power supply line; and A contact electrode is disposed in at least one contact portion between the common electrode and the common voltage power line, and is completely covered by the common electrode. The common electrode is continuously disposed on the at least one contact portion, and The contact electrode is a layer separate from the common electrode and the common voltage power line.

2. The display device according to claim 1, further comprising: A drive voltage power supply line is provided on at least one of the islands. The driving voltage power supply line is located on a different layer than the layer where the common voltage power supply line is located.

3. The display device according to claim 2, wherein, The driving voltage power line is disposed on the at least one first connection portion and is arranged to overlap with the common voltage power line.

4. The display device according to claim 2, wherein, The width of the common voltage power supply line is larger than the width of the drive voltage power supply line.

5. The display device according to claim 1, further comprising: A thin-film transistor is disposed on the island and connected to the display element; as well as An inorganic protective layer is disposed between the thin-film transistor and the display element. The inorganic protective layer directly contacts the common electrode in the inorganic contact area, and the inorganic contact area is configured to surround the display area.

6. The display device according to claim 5, wherein, The at least one contact portion is disposed outside the inorganic contact area.

7. The display device according to claim 5, further comprising: The encapsulation layer includes an organic encapsulation layer, a first inorganic encapsulation layer disposed below the organic encapsulation layer, and a second inorganic encapsulation layer disposed on the organic encapsulation layer. The organic encapsulation layer is stacked on top of the display area, and the first inorganic encapsulation layer and the second inorganic encapsulation layer are in contact with each other in the inorganic contact area.

8. The display device according to claim 7, wherein, The substrate includes a plurality of through-holes penetrating the substrate around the island, and the first inorganic encapsulation layer and the second inorganic encapsulation layer are at least partially disposed on the side surfaces of the plurality of through-holes.

9. The display device according to claim 1, further comprising: At least one inorganic insulating layer is disposed beneath the display element. The at least one inorganic insulating layer includes an opening region corresponding to at least a portion of each of the plurality of connecting portions, and the opening region is filled with at least one organic material layer. The at least one contact portion is disposed on the at least one inorganic insulating layer.

10. The display device according to claim 1, further comprising: A drive voltage power supply line is provided on at least one of the island and the plurality of connecting parts. The driving voltage power supply line is disposed on the same layer as the layer on which the common voltage power supply line is disposed.

11. The display device according to claim 10, wherein, The width of the common voltage power supply line is larger than the width of the drive voltage power supply line.

12. The display device according to claim 1, further comprising: A drive voltage power line is disposed on the island and on at least one second connection among the plurality of connection portions, the at least one second connection portion extending in a direction different from the direction along which the at least one first connection portion extends. The common voltage power supply line intersects with the driving voltage power supply line in the display area.

13. The display device according to claim 1, further comprising: An upper scan line is disposed on at least one second connecting portion among the plurality of connecting portions, wherein the at least one second connecting portion extends in a direction different from the direction along which the at least one first connecting portion extends; as well as The lower scan line is set on the island. The upper scan line and the lower scan line are disposed in different layers and are connected to each other via contact holes disposed in the at least one second connection portion.

14. The display device according to claim 13, further comprising: Multiple data lines are provided on at least one first connecting part. The multiple data lines and the upper scan line are arranged on the same layer.

15. The display device according to claim 1, wherein, The contact electrode is made of the same material as the pixel electrode of an organic light-emitting diode.

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