System on Chip

Abstract

A system on chip is provided. The system on chip includes: a system bus; a plurality of IP units connected to the system bus; a processor unit including a plurality of cores, the processor unit being configured to control the plurality of IP units via the system bus; a monitoring unit configured to monitor the state of the processor unit; and an error detection unit configured to serve as a master device of the plurality of IP units and to monitor a register in each of the plurality of IP units storing error information indicating whether an error has occurred.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2019-0087527 filed on July 19, 2019 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Methods and apparatus consistent with example embodiments relate to a system on chip and a method of operating the system on chip. Background Art

[0004] A system on chip is a semiconductor device that includes various intellectual property (IP) units and a processor unit including a core that performs main operations. The system on chip is used as a main component of autonomous vehicles and various electronic devices including computer devices, and its application range is expanding. Summary of the invention

[0005] One or more example embodiments provide a system on chip and a method of operating the system on chip, in which a register storing error information indicating whether an error has occurred in each of a plurality of IP units is actively monitored to quickly detect whether an error has occurred and the generated error can be stably processed.

[0006] According to one aspect of an example embodiment, a system on chip includes: a system bus; a plurality of IP units connected to the system bus; a processor unit including a plurality of cores, the processor unit being configured to control the plurality of IP units via the system bus; a monitoring unit configured to monitor a state of the processor unit; and an error detection unit configured to serve as a master device for the plurality of IP units and to monitor a register in each of the plurality of IP units storing error information indicating whether an error has occurred.

[0007] According to one aspect of an example embodiment, a system on chip includes: a system bus; a processor unit having multiple cores; a plurality of IP units configured to operate based on a control command received from the processor unit via the system bus, each of the plurality of IP units including a register configured to store error information indicating whether an error has occurred; and an error detection unit configured to: monitor the register in each of the plurality of IP units, identify whether the error has occurred in the IP unit based on the error information stored in the register of each of the plurality of IP units, and transmit the error information indicating that the error has occurred to the processor unit based on the error information indicating that the error has occurred not being initialized within a predetermined time period after identifying that the error has occurred.

[0008] According to one aspect of the exemplary embodiment, a system on chip includes: a processor unit having a plurality of cores; an interrupt controller configured to transmit an interrupt to the processor unit; a plurality of IP units, each of the plurality of IP units having a register storing error information indicating whether an error has occurred; and an error detection unit configured to: monitor the register in each of the plurality of IP units to identify whether an error has occurred in the IP unit, and send information of an IP unit in which an error has occurred among the plurality of IP units to the processor unit through the interrupt controller. The error detection unit is further configured to reset the IP unit in which the error has occurred based on the error information in the register of the IP unit in which the error has occurred being not initialized after the information of the IP unit is sent to the processor unit through the interrupt controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1A , Figure 1B and Figure 2 is a diagram schematically illustrating a device in which a system on a chip according to an example embodiment may be installed;

[0011] Figure 3 and Figure 4 is a schematic diagram illustrating a system on a chip according to an example embodiment;

[0012] Figure 5 is a diagram schematically illustrating a processor unit included in a system on chip according to an example embodiment;

[0013] Figures 6 to 8is a flowchart illustrating a method of operating a system on chip according to an example embodiment;

[0014] Fig. 9 and Fig.10 is a diagram illustrating a method of operating a system on chip according to an example embodiment;

[0015] Fig.11 and Fig.12 is a timing diagram illustrating a method of operating a system on chip according to an example embodiment;

[0016] Fig.13 is a diagram schematically illustrating a system on chip according to an example embodiment;

[0017] Fig.14 is a flowchart illustrating a method of operating a system on chip according to an example embodiment;

[0018] Fig.15 and Fig.16 is a diagram illustrating a method of operating a system on chip according to an example embodiment;

[0019] Fig.17 and Fig.18 is a timing diagram illustrating a method of operating a system on chip according to an example embodiment; and

[0020] Fig.19 is a flowchart illustrating a method of operating a system on chip according to example embodiments. DETAILED DESCRIPTION

[0021] Hereinafter, example embodiments will be described with reference to the accompanying drawings. When a statement such as "at least one of..." follows a list of elements, it modifies the entire list of elements, rather than the individual elements in the list. For example, the statement "at least one of a, b, and c" should be understood to include only a, only b, only c, including a and b, including a and c, including b and c, or including all of a, b, and c.

[0022] Figure 1A , Figure 1B and Figure 2 is a diagram schematically illustrating a device in which a system on chip according to example embodiments may be mounted.

[0023] First, refer to Figure 1A and Figure 1B , a device on which the system on chip according to the example embodiment is installed may be the electronic device 1. Figure 1A and Figure 1B , the electronic device 1 is shown as a smart phone, but in addition, the system on chip according to the example embodiment may be installed in various devices such as a desktop computer, a laptop computer, a tablet PC, etc.

[0024] Reference Figure 1A , the electronic device 1 according to the exemplary embodiment may include a housing 2, a display 5 disposed on the front surface of the housing 2, front cameras 6 and 7, etc. The display 5 is disposed on the front surface of the housing 2 and may substantially cover the entire front surface of the housing 2. For example, most of the front surface of the housing 2 may be allocated to the display area of ​​the display 5.

[0025] The front cameras 6 and 7 may have different viewing angles, pixel counts, and aperture values, and the user may capture various types of images using the front cameras 6 and 7. For example, at least one of the plurality of front cameras 6 and 7 may be used to obtain biometric information by recognizing the user's face, iris, etc.

[0026] Next, refer to Figure 1B The electronic device 1 may include a housing 2, a rear camera 8, etc. Figure 1B Unlike the exemplary embodiment shown, the rear camera 8 may include multiple cameras. In the case where the rear camera 8 includes multiple cameras, the multiple cameras may have different pixel counts, viewing angles, aperture values, and the like.

[0027] Inside the housing 2 of the electronic device 1, various components may be Figure 1B The components are components for realizing various functions of the electronic device 1, and examples of the components may include semiconductor devices, circuit boards, batteries, circuit devices, etc. For example, the circuit board 10 may be installed inside the housing 2 of the electronic device 1, and the circuit devices and various semiconductor devices including the system on chip 20 may be installed on the circuit board 10. The system on chip 20 may exchange data and / or power with other semiconductor devices, circuit devices, batteries, etc. through the circuit board 10.

[0028] In an example, the system on chip 20 may be an application processor, and in addition to a processor unit having a core that performs calculation and control operations, may also include a graphics processing unit (GPU) that processes graphics, a memory controller that controls a dynamic random access memory (DRAM) and / or a flash memory, and an IP unit such as an input / output interface connected to other semiconductor devices, etc. The processor unit and various IP units included in the system on chip 20 may exchange data with each other through a system bus inside the system on chip 20.

[0029] The system on chip 20 according to an example embodiment may include an error detection unit that actively detects errors that may occur in a plurality of IP units included in the system on chip 20. The error detection unit may operate in a master-slave manner with the IP units inside the system on chip 20. For example, the error detection unit may function as a master device of the IP units, and the IP units may function as slave devices.

[0030] Each of the plurality of IP units may include a register storing error information. The error detection unit may monitor the register in each IP unit regardless of the operating state of the IP unit. Therefore, the error detection unit may actively detect error information indicating the occurrence of an error in each IP unit, and may quickly resolve the error of the IP unit by quickly sending the error information to a processor unit, etc.

[0031] Next, refer to Figure 2 , the system on chip 31 according to the example embodiment may be installed on the vehicle 30. The vehicle 30 on which the system on chip 31 according to the example embodiment is installed may be an autonomous driving vehicle capable of autonomous driving without the manipulation of a driver. Figure 2 , the system on chip 31 is shown as being mounted at the rear of the vehicle 30 , but example embodiments thereof are not necessarily limited thereto.

[0032] The vehicle 30 may include various devices required for autonomous driving. For example, the vehicle 30 may include: a front camera 32 and a rear camera 33 for capturing external images; a front sensor 34 and a rear sensor 35 for detecting objects around the vehicle; a global positioning system (GPS) sensor 36 for detecting the position of the vehicle 30, etc. In addition, a body control module (BCM) 37, a brake device 38, a driving recorder 39, etc. that controls the overall travel of the vehicle 30 may be installed in the vehicle 30.

[0033] Devices 32 to 39 installed in the vehicle 30 may be controlled by the system on chip 31. The system on chip 31 may control the travel of the vehicle 30 based on surrounding information and location information collected by the front camera 32 and the rear camera 33, the front sensor 34 and the rear sensor 35, the GPS sensor 36, and the like. For example, the camera (e.g., the front camera 32 and the rear camera 33) may be implemented as a general image sensor or a time-of-flight (ToF) sensor, and the sensor (e.g., the front sensor 34 and the rear sensor 35) may include a radar device. The arrangement and number of the cameras 32 and 33 and the sensors 34 and 35 may be variously modified according to the exemplary embodiment.

[0034] In the vehicle 30 with an autonomous driving function, an error occurring in the system on chip 31 may cause a major accident. For example, if an error occurring in a part of the IP units included in the system on chip 31 cannot be quickly resolved, a traffic accident or the like may occur. In the exemplary embodiment, unlike the related art method in which each IP unit outputs error information by itself and notifies the processor unit or the like through an interrupt signal, a separate error detection unit installed in the system on chip 31 can actively detect the error information of the IP unit. Therefore, an interrupt signal is generated by the IP unit in which an error has occurred, and therefore, it is possible to determine whether an error has occurred more quickly than in the related art method in which the processor unit identifies whether an error has occurred, thereby improving the stability and reliability of the system on chip 31.

[0035] Figure 3 and Figure 4 is a schematic diagram illustrating a system on chip according to example embodiments.

[0036] Reference Figure 3 , the system on chip 100 according to the example embodiment may be installed in the electronic device 40 together with other peripheral devices 200. The electronic device 40 may correspond to various devices such as home appliances, servers, and autonomous driving vehicles in addition to computer devices such as smart phones, tablet PCs, and desktops. The peripheral device 200 may include a camera 210, a sensor module 220, a communication terminal 230, a body control module 240, and the like. The number and type of the peripheral devices 200 may vary according to the type of the electronic device 40.

[0037] The system on chip 100 may include a processor unit 110, a monitoring unit 120, an error detection unit 130, and other various IP units 101 to 108. The number and type of the IP units 101 to 108 may vary according to the functions provided by the system on chip 100. For example, one or more additional IP units different from the IP units 101 to 108 may be added to the system on chip 100, or at least one of the IP units 101 to 108 may be removed from the system on chip 100. Figure 3 In the example embodiment shown, the IP unit (101 to 108) may include an internal memory 101, an audio processing unit 102, a graphics processing unit 103, an input / output interface 104, an image processing system (IPS) 105, a power management unit (PMU) 106, a memory controller 107, a security unit 108, and the like.

[0038] The processor unit 110 may include one or more cores that perform operations and generate and process instructions. The processor unit 110 may control the overall operation of the system on chip 100. The processor unit 110 may be connected to a monitoring unit 120 including a watchdog timer circuit and the like.

[0039] The processor unit 110 may periodically reset the watchdog timer included in the monitoring unit 120. When the watchdog timer is not reset at a predetermined period, the monitoring unit 120 may determine that an error has occurred in the processor unit 110. In an example, the monitoring unit 120 may be implemented as a programmable unit. When it is determined that an error has occurred in the processor unit 110, the monitoring unit 120 may perform a process such as resetting the processor unit 110, re-powering after disconnection, or activating a safe mode.

[0040] The error detection unit 130 may monitor a register storing error information in each of the plurality of IP units 101 to 108. Each of the plurality of IP units 101 to 108 may have a register storing error information indicating whether an error has occurred. The error detection unit 130 may function as a master device of the plurality of IP units 101 to 108, and may detect whether an error has occurred by monitoring a register of each of the plurality of IP units 101 to 108 functioning as a slave device.

[0041] Typically, when an error has occurred, each of the plurality of IP units 101 to 108 changes the value of error information stored in a register and reports the error occurrence to the processor unit 110 or a separate error handling unit using an interrupt signal, etc. Therefore, it may take additional time before the error occurrence is sent to the processor unit 110, the error handling unit, etc.

[0042] The plurality of IP units 101 to 108 may notify the processor unit 110 that an error has occurred through an interrupt controller connected to the processor unit 110, or may notify the processor unit 110 and / or the error handling unit that an error has occurred via the system bus. Therefore, in the event that an error also occurs in the interrupt controller or the system bus, the error occurrence is generally not notified to the processor unit 110 and / or the error handling unit.

[0043] Therefore, in an example embodiment, the error detection unit 130 may actively monitor the register storing error information in each of the plurality of IP units 101 to 108. The error detection unit 130 acts as a master device for the plurality of IP units 101 to 108, and may monitor the register storing error information regardless of whether the plurality of IP units 101 to 108 are actually operating. For example, the error detection unit 130 may monitor the register even if the plurality of IP units 101 to 108 are in an idle state. In an example embodiment, an idle IP unit in an idle state among the plurality of IP units 101 to 108 may be configured to recognize error information based on an input clock signal.

[0044] Therefore, in the system on chip 100 according to the example embodiment, the occurrence of an error in each of the plurality of IP units 101 to 108 can be quickly detected and processed. The error detection unit 130 can notify the processor unit 110 and / or the error handling unit of information of the IP unit determined to have an error among the plurality of IP units 101 to 108. In the example embodiment, the error detection unit 130 can notify the information of the IP unit in which the error has occurred through the interrupt controller or the system bus. In addition, when it is determined that an error has also occurred in the interrupt controller or the system bus, the error detection unit 130 can directly notify the processor unit 110 and / or the error handling unit of the information of the IP unit in which the error has occurred.

[0045] Next, refer to Figure 4 The system on chip 300 according to an example embodiment may include a system bus 305, a processor unit 310, an interrupt controller 320, an error detection unit 330, a monitoring unit 340, and other various IP units 350 to 390. Figure 4 In the example embodiment shown, the IP unit (350 to 590) may include a memory controller 350, an internal memory 360, an input / output interface 370, a graphics processing unit 380, a power management unit 390, and the like.

[0046] The processor unit 310 may exchange data with the IP units 350 to 390 through the system bus 305. The interrupt controller 320 may generate an interrupt signal by receiving requests from the processor unit 310 and the IP units 350 to 390. The error detection unit 330 may determine whether an error has occurred in each IP unit 350 to 390 by monitoring a register in which error information is stored in each IP unit 350 to 390.

[0047] The monitoring unit 340 may include a watchdog timer circuit, etc. The monitoring unit 340 may communicate directly with the processor unit 310 without passing through the system bus 305, and may determine that an error has occurred in the processor unit 310 when the processor unit 310 does not reset the watchdog timer within a predetermined period or predetermined timing.

[0048] In an example embodiment, the error detection unit 330 may monitor the register even when the IP units 350 to 390 are in an idle state. For example, when error information is detected as an error state in the registers of the IP units 350 to 390 in an idle state (i.e., the error information indicates that an error has occurred), the error detection unit 330 may notify the processor unit 310 of the error information. In detail, before the IP units 350 to 390 are switched from the idle state to the active mode, the processor unit 310 may process the error, and the IP units 350 to 390 are activated and may operate normally. Therefore, the reliability of the system on chip 300 may be improved.

[0049] The error detection unit 330 may also detect whether an error has occurred in the system bus 305 and the interrupt controller 320. As an example, when an error is detected in at least one of the IP units 350 to 390, the error detection unit 330 may request the interrupt controller 320 to generate an interrupt based on the error information of the register of the at least one of the IP units 350 to 390. When the interrupt controller 320 receives the request of the error detection unit 330, the interrupt controller 320 may send the information of the IP unit in which the error has occurred to the processor unit 310, and the processor unit 310 may process the error occurred in the IP unit and may initialize the error information stored in the register. For example, when the interrupt controller 320 does not work properly and does not generate an interrupt despite the request, the error information stored in the register of the IP unit 350 to 390 in which the error has occurred will not be initialized.

[0050] In this case, in an exemplary embodiment, after the error detection unit 330 detects error information as an error state from the register of at least one of the IP units 350 to 390 and sends an interrupt generation request to the interrupt controller 320, if the error information of the register is not initialized within a predetermined period of time, it can be determined that an error has occurred in the interrupt controller 320. In this case, the error detection unit 330 can directly notify the processor unit 310 of the abnormal state of the IP units 350 to 390 in which the error information is detected as an error state, without passing through the interrupt controller 320. The processor unit 310 can perform a process of restarting the interrupt controller 320 by controlling the power management unit 390 to resolve the abnormal state of the interrupt controller 320.

[0051] In addition, for example, when an error occurs in the system bus 305, the error information may not be initialized within a predetermined period of time after the error detection unit 330 detects the error information as an error state and requests the interrupt controller 320 to generate an interrupt. In this case, the error detection unit 330 may notify the processor unit 310 of the abnormality of the system bus 305. The processor unit 310 may apply a process such as restarting the system bus 305 through the power management unit 390 to resolve the abnormal state of the system bus 305.

[0052] In an example embodiment, the error detection unit 330 may operate based on a code expressed in a hardware form, which may be obtained at a register transfer level (RTL) or a gate level implementing a gate that performs this function. Therefore, the error detection unit 330 may monitor registers storing error information in the IP units 350 to 390 without increasing the resources of the system on chip 300.

[0053] Figure 5 is a diagram schematically illustrating a processor unit included in a system on chip according to example embodiments.

[0054] Reference Figure 5 , the processor unit 400 according to the example embodiment may include a plurality of cores 410 to 440. The plurality of cores 410 to 440 may include a first core 410, a second core 420, a third core 430, and a fourth core 440. The plurality of cores 410 to 440 may perform functions such as executing an operation or generating and processing instructions. The number of cores 410 to 440 included in the processor unit 400 may be changed according to the example embodiment, and the cores 410 to 440 may have the same or different architectures.

[0055] The plurality of cores 410 to 440 may include cache memories 415 to 445, respectively. The first core 410 may include a first cache memory 415, the second core 420 may include a second cache memory 425, the third core 430 may include a third cache memory 435, and the fourth core 440 may include a fourth cache memory 445. The processor unit 400 may include a common cache memory 450 shared by the plurality of cores 410 to 440. The cache memories 415 to 445 and the common cache memory 450 may be implemented by the same or different types of memory. In an example, the cache memories 415 to 445 and the common cache memory 450 may all be implemented as dynamic random access memory (DRAM); or the cache memories 415 to 445 may be implemented as static random access memory (SRAM) and the common cache memory 450 may be implemented by dynamic random access memory (DRAM). The storage capacity of the common cache memory 450 may be greater than the storage capacity of each of the cache memories 415 to 445. The common cache memory 450 and the cache memories 415 to 445 may be used to increase the speed of exchanging data with a main memory outside the system on chip.

[0056] Figures 6 to 8 is a flowchart illustrating a method of operating a system on chip according to example embodiments.

[0057] First, refer to Figure 6 , the method of operating a system on chip according to an example embodiment includes an error detection unit monitoring a register storing error information in each of a plurality of IP units (S10). Each IP unit may update the register storing error information when an error has occurred. The error detection unit may determine whether error information indicating the occurrence of an error is retrieved from the register of each IP unit (S11).

[0058] When an error has occurred in at least one IP unit, the IP unit may update the register so that the error information indicates that the error has occurred, and the processor unit may be notified that the error has occurred through an interrupt controller, etc. When the processor unit is normally notified that an error has occurred, the processor unit may process the error of the IP unit and restore the error information stored in the register to an initial state.

[0059] The error detection unit may retrieve the error information and may determine whether the error information stored in the register is initialized after a predetermined time has passed (S12). When the processor unit is normally notified of the error information of the IP unit and the error is resolved, in operation S12, the error detection unit may confirm that the error information has been initialized. On the other hand, when the error of the IP unit cannot be resolved due to a problem with an interrupt controller, a system bus, or other components, in operation S12, the error detection unit may confirm that the error information is not initialized.

[0060] When it is determined in operation S12 that the error information has not been initialized after the predetermined time has passed, the error detection unit may send information of the IP unit in which the error information has been detected (i.e., the IP unit in which the error information has been detected) to the processor unit (S13). For example, in operation S13, the error detection unit may directly send information of the IP unit in which the error information has been detected to the processor unit without the intervention of the interrupt controller. Alternatively, the error detection unit may request a power management unit or the like to perform an operation such as resetting the IP unit in which the error information has been detected.

[0061] Next, refer to Figure 7 , the method of operating a system on chip according to an example embodiment may include an error detection unit monitoring a register storing error information in each of a plurality of IP units (S20). The monitoring operation of operation S20 may be applied not only to an activated IP unit exchanging data with a processor unit or the like through a system bus, but also to an IP unit in an idle state that is not activated.

[0062] In detail, the exemplary embodiment adopts an operation mode in which the error detection unit is used as a master device of the IP unit to actively monitor the register storing error information, rather than the IP unit itself determining whether an error has occurred and changing the error information stored in the register, and then outputting the information when an error has occurred. Therefore, it is possible to quickly determine whether an error has occurred, and in the case where an error occurs in the IP unit in an idle state, the error can be actively processed before activating the IP unit, thereby preventing the on-chip system from failing in advance.

[0063] The error detection unit may determine whether error information stored in a register of at least one IP unit indicates the occurrence of an error during the monitoring operation (S21). When the determination result of operation S21 is that error information indicating the occurrence of an error is not detected, the monitoring operation may continue. When error information indicating the occurrence of an error is detected in operation S21, the error detection unit may transmit information of the IP unit in which the error information indicating the occurrence of an error has been detected to the processor unit through the interrupt controller (S22).

[0064] As an example, in operation S22, the error detection unit may request the interrupt controller to generate an interrupt to notify the information of the IP unit that has detected the error information indicating the occurrence of the error. The processor unit that receives the interrupt from the interrupt controller may process the error that occurred in the IP unit and may initialize the error information stored in the register. The error detection unit may determine whether the error information is initialized in the register of the IP unit that has detected the error information indicating the occurrence of the error (S23).

[0065] When the error information is initialized in operation S23, the error detection unit can end the error handling operation without any additional operation. On the other hand, when the error information is not initialized in operation S23, the error detection unit can determine that an error has occurred in the interrupt controller. Therefore, the error detection unit can directly send information of the IP unit that has detected the error information to the processor unit without the intervention of the interrupt controller (S24).

[0066] Next, refer to Figure 8 , the method of operating a system on chip according to an example embodiment may include an error detection unit monitoring a register storing error information in each of a plurality of IP units (S30). Similar to reference Figure 7 As described, the monitoring operation of operation S20 may be applied to the inactive IP unit in the idle state as well as the activated IP unit.

[0067] During the monitoring operation, the error detection unit may determine whether error information stored in a register of at least one IP unit indicates an error occurrence (S31). When the determination result of operation S31 is that error information indicating the occurrence of an error is not detected, the monitoring operation may continue. When error information indicating the occurrence of an error is detected in operation S31, the error detection unit may transmit information of the IP unit in which the error information has been detected to the processor unit through the interrupt controller (S32).

[0068] When the interrupt controller receives the request of the error detection unit and sends the information of the IP unit where the error has occurred to the processor unit, the processor unit can process the error occurred in the IP unit and can initialize the error information stored in the register. The error detection unit can determine whether the error information is initialized in the register of the IP unit where the error has occurred (S33).

[0069] When the error information is initialized in operation S33, the error detection unit can end the error handling operation without any additional operation. On the other hand, when the error information is not initialized in operation S33, the error detection unit can force the IP unit that has detected the error information to be reset (S34). As an example, the error detection unit can perform the reset operation of operation S34 by forcibly restarting the IP unit in which an error has occurred through a power management unit installed on the system on chip.

[0070] According to reference Figures 6 to 8 The operations of the described example embodiments may be combined with each other. Figure 8 The reset operation of operation S34 described above can be found in reference to Figure 6 Operation S13 described and / or in reference to Figure 7 The operation S24 described above is performed after that. Figure 7 In the illustrated example embodiment, the error detection unit may determine whether the error information is initialized by monitoring the register of the IP unit in which the error has occurred after performing the operation of operation S24. When the error information is not initialized, the error detection unit may determine that an abnormality has occurred in the system bus, etc., and may perform a reset operation of operation S34 in which the IP unit in which the error has occurred is forcibly reset.

[0071] Fig. 9 and Fig.10 is a diagram illustrating a method of operating a system on chip according to example embodiments. Fig.11 and Fig.12 is a timing diagram illustrating a method of operating a system on chip according to example embodiments.

[0072] according to Fig. 9 and Fig.10 The system on chip 500 of the illustrated example embodiment may include a system bus 505 , a processor unit 510 , an interrupt controller 520 , an error detection unit 530 , a monitoring unit 540 , and a plurality of IP units 550 to 590 .

[0073] First refer to Fig. 9, the error detection unit 530 may monitor the register storing the error information in each of the IP units 550 to 590. The IP units 550 to 590 may include a memory controller 550, an internal memory 560, an input / output interface 570, a graphics processing unit 580, and a power management unit 590. When error information indicating the occurrence of an error is detected in the register of at least one of the IP units 550 to 590, the error detection unit 530 may request the interrupt controller 520 to generate an interrupt. When the interrupt is normally generated and transferred to the processor unit 510, the processor unit 510 may process the error of the IP units 550 to 590 for which the error information has been detected, for example, the error of the memory controller 550, the input / output interface 570, the graphics processing unit 580, etc., and may initialize the error information.

[0074] Fig.11 It is shown Fig. 9 The timing diagram of the operation of the system on chip 500 is shown in FIG. Fig.11 , showing the state of a register storing error information in each of the memory controller 550, the input / output interface 570, and the graphics processing unit 580 together with the internal clock signal CLK of the system on chip 500.

[0075] For example, when an error occurs in the memory controller 550, the input / output interface 570, and the graphics processing unit 580, each of the memory controller 550, the input / output interface 570, and the graphics processing unit 580 may change the error information stored in the register from the initial state (INIT.) to the error state (ERROR). The error detection unit 530 may detect that the error information has been changed to the error state ERROR, and may request the interrupt controller 520 to generate an interrupt.

[0076] Upon receiving an interrupt generation request, the interrupt controller 520 may output an interrupt to the processor unit 510 at a first time point t1. Upon receiving an interrupt, the processor unit 510 may process errors occurring in the memory controller 550, the input / output interface 570, and the graphics processing unit 580, and may initialize the error information of the register to an initial state (INIT.). When the error information is restored to the initial state (INIT.), the interrupt output of the interrupt controller 520 may also be initialized at a second time point t2.

[0077] Next, in Fig.10In the illustrated example embodiment, when error information indicating an error occurrence is detected in a register of at least one of IP units 550 to 590 , error detection unit 530 may directly send the error information to processor unit 510 without passing through interrupt controller 520 . Fig.10 The illustrated example embodiment may correspond to a case where an error occurs in the interrupt controller 520 and an interrupt is not output to the processor unit 510 even if there is a request of the error detection unit 530 .

[0078] As an example, the error detection unit 530 may transmit information of units (e.g., information of the memory controller 550, the input / output interface 570, and the graphics processing unit) among the IP units 550 to 590, which have detected error information indicating an error occurrence, directly to the processor unit 510. The processor unit 510 may process errors of the memory controller 550, the input / output interface 570, and the graphics processing unit 580, and initialize the error information of the register.

[0079] Fig.12 It is shown Fig.10 The timing diagram of the operation of the system on chip 500 is shown in FIG. Fig.12 , showing the state of a register storing error information in each of the memory controller 550, the input / output interface 570, and the graphics processing unit 580 together with the internal clock signal CLK of the system on chip 500.

[0080] exist Fig.12 In the illustrated example embodiment, the error detection unit 530 detects error information from the memory controller 550, the input / output interface 570, and the graphics processing unit 580, and may request the interrupt controller 520 to generate an interrupt. However, as in the above example case, since an exception occurs in the interrupt controller 520, an interrupt is not sent from the interrupt controller 520 to the processor unit 510.

[0081] After the error detection unit 530 requests the interrupt controller 520 to generate an interrupt, the error detection unit 530 may monitor the register storing the error information in each of the memory controller 550, the input / output interface 570, and the memory controller 550. When the error information stored in the register still maintains the error state (ERROR) after the interrupt generation is requested and a predetermined time has passed, the error detection unit 530 may directly notify the processor unit 510 of the occurrence of the error without going through the interrupt controller 520.

[0082] Alternatively, the error detection unit 530 may request the interrupt controller 520 to generate an interrupt, and may monitor the output of the interrupt controller 520. When the interrupt is not output from the interrupt controller 520 after the request to generate an interrupt and a predetermined time has passed, the error detection unit 530 directly notifies the processor unit 510 that an error has occurred without passing through the interrupt controller 520. The processor unit 510 notified of the error occurrence may process the error of the IP units 550, 570, and 580 in which the error has occurred, and may restore the error information stored in the register to the initial state (INIT.).

[0083] Alternatively, the error detection unit 530 can identify whether an error has occurred in the interrupt controller 520 when sending information about an IP unit with an error to the processor unit 510, and send error information indicating that there are errors in the interrupt controller 520 and the IP unit to the processor unit 510 based on the identification of the error in the interrupt controller 520.

[0084] Fig.13 is a diagram schematically illustrating a system on chip according to example embodiments.

[0085] Reference Fig.13 The system on chip 600 according to an example embodiment may include a system bus 605, a processor unit 610, an interrupt controller 620, an error detection unit 630, an error handling unit 635, a monitoring unit 640, and other various IP units 650 to 690. Fig.13 In the example embodiment shown, the IP unit (650 to 690) may include a memory controller 650, an internal memory 660, an input / output interface 670, a graphics processing unit 680, a power management unit 690, and the like.

[0086] according to Fig.13 The system on chip 600 of the illustrated example embodiment may include an error handling unit 635 that operates with an operating system different from that of the processor unit 610. The core included in the processor unit 610 and the core included in the error handling unit 635 may have different architectures. Therefore, even in the case where an abnormality occurs in the processor unit 610, the error handling unit 635 may operate normally.

[0087] The error processing unit 635 may process an error occurring in each of the IP units 650 to 690. The error processing unit 635 may process an error in the IP units 650 to 690 in which an error has occurred, or may restart the IP units 650 to 690 in which an error has occurred. The error processing unit 635 may have control authority of the power management unit 690 to restart the IP units 650 to 690 in which an error has occurred.

[0088] Fig.14 is a flowchart illustrating a method of operating a system on chip according to example embodiments.

[0089] Reference Fig.14 , the method of operating a system on chip according to an example embodiment may include an error detection unit monitoring a register storing error information in each of a plurality of IP units (S40). The monitoring operation of operation S40 may be applied to an IP unit in an idle state that is not activated, and an activated IP unit that exchanges data with a processor unit or the like through a system bus. Therefore, in an example embodiment, when an error occurs in an IP unit in an idle state, a malfunction of the system on chip may be prevented by pre-processing the error before activating the IP unit.

[0090] During the monitoring operation, the error detection unit may determine whether the error information stored in the register of at least one IP unit indicates an error occurrence (S41). When the determination result of operation S41 is that the error information indicating the occurrence of an error is not detected, the monitoring operation may continue. On the other hand, when the error information indicating the occurrence of an error is detected in operation S41, the error detection unit may transmit information of the IP unit in which an error has occurred to the error handling unit through the interrupt controller (S42).

[0091] As an example, in operation S42, the error detection unit may directly transmit information of the IP unit in which an error has occurred to the error handling unit without passing through the system bus. In this case, even when an error occurs in the system bus, the error handling unit may quickly handle the error of the IP unit. The error detection unit may determine whether the error information is initialized in the register of the IP unit in which an error has occurred (S43).

[0092] When the error information is initialized in operation S43, the error detection unit can end the error handling operation without additional operation. On the other hand, when the error information is not initialized in operation S43, the error detection unit can determine that an error has occurred in the interrupt controller or the system bus. In this case, the error detection unit can transmit information of the IP unit in which an error has occurred to the processor unit or the processing unit through the interrupt controller (S44).

[0093] Fig.15 and Fig.16 is a diagram illustrating a method of operating a system on chip according to example embodiments. Fig.17 and Fig.18 is a timing diagram illustrating a method of operating a system on chip according to example embodiments.

[0094] according to Fig.15 and Fig.16The system on chip 700 of the illustrated example embodiment may include a system bus 705, a processor unit 710, an interrupt controller 720, an error detection unit 730, an error handling unit 735, a monitoring unit 740, and a plurality of IP units 750 to 790. For example, the plurality of IP units may include a memory controller 750, an internal memory 760, an input / output interface 770, a graphics processing unit 780, and a power management unit 790. The error handling unit 735 may operate based on an operating system different from that of the processor unit 710.

[0095] First refer to Fig.15 , the error detection unit 730 may monitor the register storing the error information in each of the IP units 750 to 790. When the error information is detected in the register of at least one of the IP units 750 to 790 to be in an error state, the error detection unit 730 may notify the error handling unit 735 that an error has occurred. In an example, the error detection unit 730 may notify the error handling unit 735 of the information of the IP unit in which the error has occurred. The error handling unit 735 may process the error of the IP unit (e.g., the memory controller 750, the input / output interface 770, the graphics processing unit 780) in which the error has occurred, and may initialize the error information.

[0096] Fig.17 Is used to describe Fig.15 The timing diagram of the operation of the system on chip 700 is shown. Fig.17 , showing the state of a register storing error information in each of the memory controller 750, the input / output interface 770, and the graphics processing unit 780 together with the internal clock signal CLK of the system on chip 700.

[0097] For example, when an error occurs in the memory controller 750, the input / output interface 770, and the graphics processing unit 780, the error information stored in the register of each of the memory controller 750, the input / output interface 770, and the graphics processing unit 780 may be changed from the initial state (INIT.) to the error state (ERROR). When the error detection unit 730 detects that the error information is changed to the error state ERROR, the error detection unit 730 may notify the error processing unit 735 that an error has occurred in the memory controller 750, the input / output interface 770, and the graphics processing unit 780.

[0098] The error processing unit 735 notified that an error has occurred may process errors of the memory controller 750, the input / output interface 770, and the graphics processing unit 780. When the error is processed, error information stored in registers of the memory controller 750, the input / output interface 770, and the graphics processing unit 780 may be initialized to an initial state (INIT.).

[0099] Next, in Fig.16 In the illustrated example embodiment, when error information is detected in an error state in a register of at least one of the IP units 750 to 790, the error detection unit 730 may notify the error handling unit 735 of information of the IP unit in which an error has occurred. Fig.16 The illustrated example embodiment may correspond to a case where an error occurs in the error processing unit 735 and the error processing unit 735 cannot process the error even if there is a request of the error detection unit 730 .

[0100] The error detection unit 730 notifies the error processing unit 735 that an error has occurred, and then can continuously monitor the registers of the memory controller 750, the input / output interface 770, and the graphics processing unit 780 where the error has occurred. The error processing unit 735 is notified that an error has occurred, and after a predetermined time has passed, when the error information of the register is not initialized to the initial state (INIT.), the error detection unit 730 can request the interrupt controller 720 to generate an interrupt. Fig.18 In the illustrated example embodiment, the error detection unit 730 may send the generated interrupt to the interrupt controller 720 at a first time point t1 .

[0101] The interrupt controller 720 may output an interrupt for notifying the processor unit 710 that an error has occurred in the memory controller 750, the input / output interface 770, and the graphics processing unit 780 in response to a request from the error detection unit 730. The processor unit 710 may process the errors of the memory controller 750, the input / output interface 770, and the graphics processing unit 780 in response to the interrupt, and may restore the error information of the register to the initial state (INIT.).

[0102] Fig.19 is a flowchart illustrating a method of operating a system on chip according to example embodiments.

[0103] Reference Fig.19, the method of operating a system on chip according to an example embodiment may include an error detection unit monitoring whether the IP unit is in an idle state (S50). In the example, the idle state of the IP unit may be defined as a state in which the IP unit does not operate by actually inputting / outputting or processing data. The error detection unit may determine whether the IP unit is in an idle state by monitoring the operation (S51).

[0104] When the determination result of operation S51 is that the IP unit is in an idle state, the error detection unit may request to perform a diagnostic process on the IP unit in the idle state (S52). After receiving the request from the error detection unit, the IP unit may perform a diagnostic process to determine whether there is a problem (S53).

[0105] When the result of the determination of operation S53 is that there is a problem, in detail, it is determined that an error has occurred, and the IP unit can update the error information of the register to indicate the occurrence of the error. In addition, information about the IP unit that has detected the error information can be sent through the interrupt controller (S54). Operation S54 can be performed by the IP unit, or can be performed by the error detection unit.

[0106] The error detection unit may monitor the register storing the error information of the IP unit, and may determine whether the error information is initialized (S55). In an example, the error information may be initialized when the IP unit or the error detection unit successfully transmits the error information to the processor unit via the interrupt controller. Therefore, when the error information is not initialized, the error detection unit may determine that a problem has occurred in the interrupt controller, the system bus, etc., so that the error of the IP unit is not handled normally.

[0107] When the error information is not initialized in operation S55, the error detection unit may directly send information of the IP unit that has detected the error information to the processor unit without the intervention of the interrupt controller (S56). Alternatively, the error detection unit may transmit information of the IP unit that has detected the error information to a separate error processing unit, or may reset the IP unit that has detected the error information by controlling the power management unit. In detail, the error detection unit notifies the processor unit of information of the IP unit that has detected the error information, and even after a predetermined time has passed, when the error information of the IP unit has not been initialized, the error detection unit may perform processing for processing the error of the IP unit through various paths.

[0108] The system on chip according to the various embodiments described above can be applied to an autonomous vehicle. When the error detection unit of the system on chip applied to the autonomous vehicle detects an error from at least one IP unit, the error handling unit or the processor unit can handle the error. However, when the error is not handled within a predetermined time period, the system on chip can force the autonomous vehicle to stop and enter a safe mode to diagnose the system.

[0109] The method of handling an error occurring in the IP unit may include: restarting the IP unit where an error has occurred, forcibly shutting down the IP unit where an error has occurred by controlling the power management unit, etc. On the other hand, in the case where the above operation is performed during the operation of the autonomous driving vehicle, a safety accident may occur, and therefore, the system on chip may first stop the vehicle and then perform the above operation.

[0110] As described above, according to the example embodiment, an error detection unit used as a master device of multiple IP units is included in the system on chip, and the error detection unit can monitor the register storing error information of each of the multiple IP units. When error information is detected, the error detection unit can pass the error information to the processor unit and / or a separate error handling unit directly or via an interrupter. By implementing the error detection unit used as a master device of multiple IP units in hardware within the system on chip, errors can be handled quickly and stably without increasing the resources of the system on chip.

[0111] According to an exemplary embodiment, Figure 1A , Figure 1B , Figures 2 to 5 , Fig. 9 , Fig.10 , Fig.13 , Fig.15 and Fig.16At least one of the components, elements, modules or units represented by the boxes in the figure may be embodied as various numbers of hardware, software and / or firmware structures that perform the above-mentioned functions. For example, at least one of these components, elements, modules or units may use a direct circuit structure, such as a memory, a processor, a logic circuit, a lookup table, etc., and the direct circuit structure may perform respective functions by controlling one or more microprocessors or other control devices. Moreover, at least one of these components, elements, modules or units may be specifically embodied by a part of a module, a program or a code containing one or more executable instructions for performing a specified logical function, and may be performed by one or more microprocessors or other control devices. Moreover, at least one of these components, elements, modules or units may also include a processor, a microprocessor, etc. such as a central processing unit (CPU) that performs respective functions, or may be implemented by a processor, a microprocessor, etc. such as a central processing unit (CPU) that performs respective functions. Two or more of these components, elements, modules or units may be combined into a single component, element, module or unit that performs all operations or functions of the two or more components, elements, modules or units combined. Moreover, at least a portion of the functions of at least one of these components, elements, modules or units can be performed by another of these components, elements, modules or units. In addition, although the bus is not shown in the above block diagram, the communication between the components, elements, modules or units can be performed by the bus. The functional aspects of the above exemplary embodiments can be realized with an algorithm executed on one or more processors. In addition, the components, elements, modules or units represented by the frame or processing steps can adopt any number of related technologies for electronic configuration, signal processing and / or control, data processing, etc.

[0112] While example embodiments have been illustrated and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A system on chip, comprising: System bus; a plurality of IP units connected to the system bus, each of the plurality of IP units comprising a register storing error information indicating whether an error has occurred in the IP unit; a processor unit including a plurality of cores, the processor unit being configured to control the plurality of IP units via the system bus; a monitoring unit configured to monitor a status of the processor unit; as well as The error detection unit is configured to serve as a master device of the plurality of IP units and monitor the register storing the error information of an idle IP unit in an idle state among the plurality of IP units. 2 . The system on chip according to claim 1 , further comprising an error handling unit configured to operate with an operating system different from an operating system of the processor unit.

3. The system on chip according to claim 2, wherein: The error detection unit is further configured to send, to the error handling unit, information of an IP unit among the plurality of IP units in which the error information indicating that an error has occurred is detected from a register thereof.

4. The system on chip according to claim 3, wherein: The error detection unit is further configured to directly send the information of the IP unit detecting that the error information indicates that an error has occurred to the error handling unit without intervention of the processor unit.

5. The system on chip according to claim 3, wherein: The error processing unit is further configured to process an error of the IP unit for which the error information indicates that the error has occurred, and initialize the error information stored in the register corresponding to the IP unit.

6. The system on chip according to claim 3, wherein: The error detection unit is also configured to monitor whether the error information corresponding to the IP unit has been initialized, and based on the fact that the error information stored in the register has not been initialized within a predetermined time period after the information of the IP unit is sent to the error handling unit, the error detection unit sends the information of the IP unit to the processor unit.

7. The system on chip according to claim 1, further comprising an interrupt controller configured to generate an interrupt, in, The error detection unit is further configured to request the interrupt controller to generate an interrupt corresponding to at least one IP unit among the plurality of IP units for which the error information indicating that an error has occurred is detected from a register thereof.

8. The system on chip according to claim 7, wherein: The processor unit is further configured to: based on the interrupt corresponding to the at least one IP unit being received, process an error of the at least one IP unit and initialize the error information in the register of the at least one IP unit.

9. The system on chip according to claim 7, wherein: The error detection unit is further configured to request the interrupt controller to generate an interrupt corresponding to the at least one IP unit when the error information in the register of the at least one IP unit is not initialized within a predetermined period of time after the error detection unit detects the error information.

10. The system on chip according to claim 1, further comprising a power management unit configured to supply power to the processor unit, the plurality of IP units, the system bus, the error detection unit, and the monitoring unit, in, The error detection unit is also configured to control the power management unit to reset the at least one IP unit among the multiple IP units based on detecting from the register of at least one IP unit among the multiple IP units that the error information indicates that an error has occurred, and the error information is not initialized within a predetermined time period after the error information is detected from the register.

11. The system on chip according to claim 1, wherein: The error detection unit is configured to operate based on code represented in a hardware form obtained at a register transfer level and a gate level.

12. A system on chip, comprising: System bus; a processor unit with multiple cores; a plurality of IP units configured to operate based on a control command received from the processor unit via the system bus, each of the plurality of IP units including a register configured to store error information indicating whether an error has occurred; as well as an error detection unit configured to: monitor the register in each of the multiple IP units, identify whether an error has occurred in the IP unit based on the error information stored in the register of each of the multiple IP units, and transmit the error information indicating that an error has occurred to the processor unit based on the error information indicating that an error has occurred not being initialized within a predetermined time period after identifying that an error has occurred.

13. The system on chip according to claim 12, wherein: The error detection unit is configured to function as a master device for the plurality of IP units.

14. The system on chip according to claim 13, wherein: The error detection unit is configured to monitor the register in each of the plurality of IP units regardless of whether the plurality of IP units are operating.

15. The system on chip according to claim 13, wherein: An idle IP unit in an idle state among the plurality of IP units is configured to recognize the error information based on an input clock signal.

16. The system on chip according to claim 12, wherein: The error detection unit is further configured to reset the IP unit storing the error information indicating that an error has occurred in its register based on the error information indicating that an error has occurred not being initialized within a predetermined time period after the error information indicating that an error has occurred is transmitted to the processor unit.

17. A system on chip, comprising: a processor unit with multiple cores; an interrupt controller configured to transmit an interrupt to the processor unit; a plurality of IP units, each of the plurality of IP units having a register storing error information indicating whether an error has occurred; as well as an error detection unit configured to: monitor the register in each of the plurality of IP units to identify whether an error has occurred in the IP unit, and send information of the IP unit in which an error has occurred among the plurality of IP units to the processor unit through the interrupt controller, The error detection unit is further configured to reset the IP unit where an error has occurred based on the fact that the error information in the register of the IP unit where an error has occurred is not initialized after the information of the IP unit is sent to the processor unit through the interrupt controller.

18. The system on chip according to claim 17, wherein: The error detection unit is further configured to reset the IP unit in which an error has occurred by controlling a power management unit that supplies power to the plurality of IP units.

19. The system on chip according to claim 17, wherein: The error detection unit is also configured to identify whether an error has occurred in the interrupt controller when sending the information that the IP unit has an error, and send error information indicating that the interrupt controller and the IP unit have errors to the processor unit based on identifying the error in the interrupt controller.

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