Round-based determination of completion of barrier termination commands

Abstract

The present disclosure relates to round-based determination of completion of a barrier termination command. An apparatus includes: transaction processing circuitry for issuing memory access transactions, each memory access transaction specifying a round identifier indicating the current round in which the memory access transaction was issued; transaction tracking circuitry for tracking, for each of at least two rounds, the number of outstanding memory access transactions issued in that round; barrier termination circuitry for signaling completion of a barrier termination command when the transaction tracking circuitry indicates that no outstanding memory access transactions issued in one or more rounds prior to a barrier point remain; and round change circuitry for changing the current round to a next round in response to a barrier point signal indicating the barrier point. This helps reduce circuit area overhead for tracking completion of memory access transactions prior to a barrier point.

Description

Technical Field

[0001] The present technology relates to the field of data processing. Background Art

[0002] A data processing system can issue memory access transactions to be serviced by a memory system. A barrier termination command can be defined that, when executed, requests the system to signal completion of the barrier termination command when it has determined that any memory access transactions issued before a barrier point have completed. Such barriers are useful for constraining out-of-order execution of operations or for handling situations where updates to certain control information are made and it is desirable to force subsequently executed operations to observe the updated control information. Tracking whether memory access transactions before a barrier point have completed can incur significant circuit overhead. Summary of the Invention

[0003] At least some examples provide an apparatus comprising: transaction processing circuitry for issuing memory access transactions, each memory access transaction specifying a round identifier indicating a current round in which the memory access transaction is issued; transaction tracking circuitry for tracking, for each of at least two rounds, a number of outstanding memory access transactions issued in that round; barrier termination circuitry for signaling completion of a barrier termination command when the transaction tracking circuitry indicates that no outstanding memory access transactions issued in one or more rounds prior to a barrier point remain; and round change circuitry for changing a current round to a next round in response to a barrier point signal indicating the barrier point.

[0004] At least some examples provide an apparatus comprising: means for issuing memory access transactions, each memory access transaction specifying a round identifier indicating a current round in which the memory access transaction is issued; means for tracking, for each of at least two rounds, a number of outstanding memory access transactions issued in that round; means for signaling completion of a barrier termination command when the means for tracking indicates that no outstanding memory access transactions issued in one or more rounds prior to a barrier point remain; and means for changing the current round to a next round in response to a barrier point signal indicating the barrier point.

[0005] At least some examples provide a method comprising: issuing memory access transactions, each memory access transaction specifying a round identifier indicating a current round in which the memory access transaction is issued; tracking, for each of at least two rounds, a number of outstanding memory access transactions issued in that round; changing the current round to a next round in response to a barrier point signal indicating a barrier point; and signaling completion of a barrier termination command when the tracking indicates that no outstanding memory access transactions issued in one or more rounds prior to the barrier point remain. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Further aspects, features, and advantages of the present technology will be apparent from the following description of examples, which is to be read in conjunction with the accompanying drawings, in which:

[0007] Figure 1 An example of an apparatus that supports round-based tracking of memory access transactions and barrier-terminating command completions is schematically illustrated;

[0008] Figures 2 to 5 is a flow chart illustrating a method of responding to a memory access transaction, a transaction response, a barrier point signal, and a barrier termination command, respectively;

[0009] Figure 6 and Figure 7 A specific embodiment is shown in greater detail, wherein the barrier abort command is an invalidation synchronization command for detecting completion of a transaction issued prior to invalidation of conversion data in the conversion lookaside buffer;

[0010] Figure 8 shows how round-based transaction tracking can be performed for the read channel and the write channel separately; and

[0011] Figures 9 to 13 Five options are shown for implementing tracking of completion of invalid synchronization commands based on the round in which the transaction was issued. DETAILED DESCRIPTION

[0012] A data processing system may support a barrier abort command that requests the system to signal completion of the command when it has determined that a memory access transaction prior to a barrier point has completed. However, challenges may exist in meeting competing demands for high system performance and circuit area efficiency, as well as power consumed by the device.

[0013] One approach could be that upon receiving a barrier abort command, the system could simply stop issuing memory access transactions and wait for all previous transactions to complete before signaling the completion of the barrier abort command and then resuming issuing memory access transactions. While this technique is simple to implement in terms of circuit area and power budget, it has a high performance impact by preventing all memory access transactions from being issued during the period between the receipt of the barrier abort command and its completion.

[0014] An alternative technique would be to maintain a complete tracking structure that tracks the identifier of each issued transaction and mark a given transaction as completed when a corresponding response to the transaction is received. When a barrier terminate command is received, all outstanding (incomplete) memory access transactions can be marked as "need to be checked", and once it is detected that there are no longer any outstanding transactions marked as "need to be checked", the completion of the barrier terminate command can be signaled. This approach provides much better performance, but requires significantly more circuit area for the transaction tracker. In practice, this approach does not scale well with increasing numbers of outstanding transactions because, in addition to the storage circuitry required for each entry in the transaction tracker, it will be necessary to provide comparison logic for comparing the transaction identifier of each transaction response with each entry in the transaction tracker to detect when a given transaction is completed. This approach limits the scalability of the transaction tracker and therefore limits the maximum number of outstanding transactions that can be supported.

[0015] To address these concerns, the inventors propose a different approach. Transaction processing circuitry issues memory access transactions that specify a round identifier indicating the current round in which the memory access transaction was issued. Transaction tracking circuitry can track, for each of at least two rounds, the number of outstanding memory access transactions issued in that round. When the transaction tracking circuitry indicates that there are no remaining outstanding memory access transactions issued in one or more rounds prior to a barrier point, barrier termination circuitry can signal completion of a barrier termination command. Round change circuitry can change the current round to a next round in response to a barrier point signal indicating a barrier point.

[0016] The method provides a better balance between performance and circuit area overhead by providing a function for dividing memory access transactions into rounds, changing the rounds assigned to transactions in response to a barrier point signal indicating a barrier point, and using transaction tracking circuitry to track the number of outstanding memory access transactions issued in a particular round. This means that it is possible to detect when a barrier termination command can be signaled as completed without stopping the issuance of memory access transactions, but utilizing transaction tracking circuitry with a lower circuit area cost than when individual transactions are tracked based on their transaction identifiers.

[0017] Each round is a certain period of time during which memory access transactions are issued. It will be appreciated that the duration of a particular round need not be fixed, and in practice the duration of one round may vary compared to the next depending on the relative timing of receiving the barrier point signal.

[0018] In some embodiments, the barrier point signal may include the barrier termination command itself. In this case, the same command triggers the change from the current round to the next round and causes the barrier termination circuitry to begin tracking whether it can signal the completion of the barrier termination command. In the case where the barrier point signal includes the barrier termination command itself, the relevant round to be checked by the barrier termination circuitry may be the round that was the current round at the time the barrier termination command was received (before the current round was changed to the next round in response to the barrier termination command). Thus, for this example, upon receiving the barrier termination command, the barrier termination circuitry waits for the transaction tracking circuitry to indicate that there are no remaining uncompleted memory access transactions issued in the current round (the current round at the time the barrier termination command was received). It then signals the completion of the barrier termination command. Furthermore, by changing the current round to the next round in response to the barrier termination command, any memory access transactions issued after the barrier termination command is received will specify the next round.

[0019] In other embodiments, the barrier point signal may include a barrier point identification signal distinct from the barrier termination command. Using this approach, a separate command can be defined that allows the barrier point to be defined at a different point in time than when the barrier termination command is received. This can be useful in certain scenarios because it allows for more accurate identification of barrier points, potentially meaning that the completion of the barrier termination command need not be delayed while awaiting completion of any memory access transactions issued between the receipt of the barrier point identification signal and the receipt of the barrier termination command. In certain circumstances, this can benefit performance by allowing the completion of the barrier termination command to be signaled earlier, enabling subsequent operations that would otherwise have waited for the completion of the barrier termination command to commence earlier. In the case where the barrier point signal is a barrier point identification signal distinct from the barrier termination command, the one or more rounds examined by the barrier termination circuitry may be earlier rounds than the round that was the current round at the time the barrier termination command was received. With this approach, it may be useful for the transaction tracking circuitry to support round tracking for at least three or more different rounds, because it may be possible for multiple barrier point identification signals to be received in succession before a barrier termination command is received, and thus being able to support a larger number of rounds may enable more accurate pinpointing of the latest barrier point before a given barrier termination command is received, which may enable a faster response to a barrier termination command than would be possible if the rounds could not be defined as accurately.

[0020] The techniques discussed above can be used to handle any type of barrier termination where it is necessary to check whether memory access transactions preceding the barrier point have completed before completion of the barrier termination command can be signaled. However, for some types of barrier termination commands, it may be necessary for other reasons to provide a full transaction tracker anyway in order to check transaction responses individually against the transaction identifiers of individual transactions in the transaction tracker, and if such a full transaction tracker structure is already provided, it may be more efficient to handle those types of barriers using the alternative technique discussed above in which the full transaction tracker compares transaction identifiers, thus eliminating the need to use the round-based approach discussed above.

[0021] However, a round-based approach may be particularly useful for processing a particular form of barrier termination command, namely an invalidation synchronization command used after invalidation of page table information from a translation lookaside buffer. A translation lookaside buffer is a cache of page table information from a page table in a memory system that provides address translation data used to control memory address translation and / or memory permission data used to specify whether memory access transactions to specific regions of the address space are permitted. Thus, transaction processing circuitry may initiate a lookup in a translation lookaside buffer (TLB) to check for page table information corresponding to an address specified by a memory access transaction to be issued. An invalidation command may be provided, in response to which the TLB invalidates page table information that satisfies a certain invalidation condition. Often, when the underlying page table structures in a memory system have been updated by software, the TLB may be required to invalidate the page table information to ensure that subsequently issued memory access transactions cannot look up outdated page table information. Therefore, an invalidation synchronization command may be defined that requests the barrier termination circuitry to signal completion when the invalidation of the TLB has completed and at least any memory access transaction that was looked up in the TLB prior to receiving the invalidation command has also completed. Some TLBs may be located in components that do not have a full transaction tracker that supports comparing individual transaction identifiers with each entry of the tracker because the full transaction tracker may not be needed for other purposes. For such a TLB, introducing a full transaction tracker for the sole purpose of tracking the completion of invalidate synchronization commands would introduce a significant amount of additional circuit area cost. Therefore, for handling this type of barrier termination, the round-based approach discussed above may be particularly useful because it enables the need for a full transaction tracker to be avoided, thereby reducing circuit area, without incurring the performance cost of freezing issued transactions when an invalidate synchronization command is received. Therefore, the barrier termination command discussed above may be useful if it is an invalidate synchronization command that is used to synchronize operations after the TLB is invalidated.

[0022] In some embodiments, the invalidate command and the invalidate synchronization command may actually be the same command. That is, the processor architecture may define a single command that serves as both an invalidate command requesting invalidation of page table information and an invalidate synchronization command requesting confirmation that the memory access transaction prior to invalidation has completed. Therefore, in this case, the single command that serves as both the invalidate command and the invalidate synchronization command also serves as both the barrier point signal and the barrier termination command mentioned above.

[0023] On the other hand, in other architectures, the invalidate command can be a different command from the invalidate synchronization command. In this case, although the invalidate synchronization command serves as the barrier termination command, the barrier point signal can be either the invalidate command or the invalidate synchronization command. Defining the invalidate synchronization command as a barrier point signal may have the advantage of potentially requiring fewer rounds to support, while defining the invalidate command as a barrier point signal may have the advantage of enabling faster response to synchronization operations because the barrier point is at an earlier execution point than the invalidate synchronization command, allowing operations that must wait for the barrier termination command to complete to begin earlier.

[0024] In the case where the barrier point signal is an invalidate command, note that while the round may generally be changed in response to an invalidate command, the exact time at which the round is actually changed may be varied flexibly relative to the receipt of the invalidate command, as long as the receipt of the invalidate command ultimately does result in the round being changed. If the TLB lookup is allowed to proceed while the invalidate operation is in progress, then the trigger for updating the current round to the next round may be the completion of the invalidate operation performed for the given invalidate command (rather than just the receipt of the invalidate command) - this may ensure that any transactions that accessed the TLB at a time when the TLB may have been only partially invalidated are granted the current round identifier, rather than the next round identifier, to ensure that they will need to complete before the barrier termination based on the current round can be signaled as complete, as there is a risk that they may hit against old translation data.

[0025] In other embodiments, the TLB may be arranged to prevent further TLB lookup requests during a period in which entries of the TLB are being traversed due to a TLB invalidation operation. Thus, in such cases, the exact timing of updating the current-round identifier relative to the start and end of the TLB invalidation operation may not be important, as long as transactions that are looked up in the TLB before the start of the TLB invalidation operation are assigned the current-round identifier and transactions that are looked up after the end of the TLB invalidation operation are assigned the next-round identifier.

[0026] Alternatively, another design, when sequentially traversing each TLB entry to check whether it matches the invalidation condition, can record the progress identifier of the latest TLB entry reached in the invalidation traversal, and TLB lookups may still continue during the invalidation traversal. In this case, transactions that hit entries earlier in the traversal sequence than the entry indicated by the progress identifier can be assigned the next-round identifier (because they will hit entries that have not been invalidated and are therefore still correct), and transactions that hit entries later in the traversal sequence than the entry indicated by the progress identifier are assigned the current-round identifier (because there is a risk that they may still contain outdated translation data, so transactions that have already been issued should be tracked because they are before the barrier point), until the invalidation sequence is completed and then the current round is fully updated to the next-round identifier to be used for subsequent transactions.

[0027] Another implementation option might be that because it might be common to receive several invalidation commands in close succession (e.g., specifying different addresses to be invalidated), some TLB implementations might choose to perform TLB invalidations lazily, thereby storing tracking information (which collects information about a series of received TLB invalidation commands) to allow a single pass through the entries of the TLB to implement multiple different sets of invalidation criteria, where each entry is checked against the invalidation criteria of all received TLB invalidation commands tracked in the tracking information. Therefore, for such an implementation, it might be preferable to defer the actual changes for the current pass relative to the receipt of the invalidation command until the moment when the invalidation of the requested TLB entry is actually performed.

[0028] It will therefore be appreciated that a number of options are available for implementing TLB invalidation, so while the turn may generally be changed in response to receiving an invalidate command, there is some flexibility in how this is achieved.

[0029] The transaction tracking circuitry may include two or more transaction counters, each configured to count the number of outstanding memory access transactions issued in a corresponding round. In response to a memory access transaction to be issued by the transaction processing circuitry, the transaction tracking circuitry may increment the transaction counter corresponding to the current round. A transaction response received by the transaction processing circuitry may specify the same round identifier that was specified by the corresponding memory access transaction being responded to by the transaction response. Therefore, upon receiving a transaction response, the transaction tracking circuitry may decrement the transaction counter corresponding to the round indicated by the round identifier specified by the transaction response. In this manner, the number of outstanding transactions may be tracked, and when the counter reaches zero, it may be determined that no memory access transactions remain to be issued in a particular round.

[0030] Typically, when a given transaction counter is reset, it may be reset to a specific reset value. When a counter has a reset value, this indicates that there are no outstanding transactions of the type counted by that counter that were issued in the round corresponding to that counter. While the reset value may most commonly be zero, this is not required, and other reset values ​​may also be used. The terms "increment" and "decrement" refer to adjustments to a counter by a given step size, where incrementing is an adjustment in the opposite direction of decrementing. While most commonly, incrementing may involve adding 1 to the counter value and decrementing may involve subtracting 1 from the counter, other implementations may act in the opposite direction, where incrementing is a subtraction and decrementing is an addition. Step sizes other than 1 may also be used.

[0031] In some embodiments, the transaction counter used to count outstanding transactions can be divided into separate counters for specific categories of memory access transactions. For example, it may be useful to provide separate counters for read transactions and write transactions. In this case, read transactions issued in a particular round would be tracked by one transaction counter, and write transactions issued in the same round would be tracked by a different transaction counter than for read transactions. This may be useful because in some memory systems, read and write channels can be managed separately with little crossover between the circuitry used to process read transactions and the circuitry used to process write transactions. To reduce the amount of cross-wiring required to track a shared counter for both reads and writes, it may be simpler to provide separate counters in the read and write channel circuitry. In this case, the transaction tracking circuitry will not indicate that all outstanding memory access transactions for a given round have completed until both the read and write transaction counters for that round have reached their reset values.

[0032] Alternatively, in some example implementations, the same counter may be used to track reads and writes.

[0033] Similarly, it is not necessary for the transaction tracking circuitry to use its transaction counter to track every memory access transaction issued. For some types of barrier termination commands, it may only be necessary to ensure that there are no remaining outstanding memory access transactions of a particular type issued before the barrier point. In this case, the transaction tracking circuitry may not need to track any memory access transactions other than a certain type or set of types. Therefore, when the transaction tracking circuitry indicates that there are no remaining outstanding memory access transactions issued in a particular round, this does not necessarily mean that all transactions issued in that round have been definitively completed, but may only mean that, among the outstanding memory access transactions of one or more types to be tracked by the transaction tracking circuitry, there are no remaining outstanding memory access transactions for that round.

[0034] For other types of barriers, the barrier may be a general barrier applicable to all types of outstanding memory access transactions, and for such a barrier, the transaction tracking circuitry may track the number of outstanding memory access transactions regardless of their type (although reads and writes may still be tracked separately as discussed above, but without further restricting the tracking of reads or writes to specific types of reads / writes).

[0035] In some examples, the maximum number of rounds supported by the transaction tracking circuitry may be two. Thus, the transaction tracking circuitry may track the number of outstanding memory access transactions for only two rounds. Two rounds may be sufficient to process a single barrier termination command at a time. In this case, if a subsequent barrier termination command is received before the completion of an earlier barrier termination command, the subsequent barrier termination command may have to wait.

[0036] Alternatively, the transaction tracking circuitry may support more than two rounds. This may be useful for handling implementations such as those discussed above where the rounds are changed in response to a barrier point identification signal distinct from a barrier termination command, but may also be provided where the barrier point signal includes the barrier termination command itself, to enable more barriers to be processed at once. In practice, the performance gains provided by supporting multiple concurrent synchronization or barrier termination operations may not justify the additional overhead of supporting more than two rounds, however this is an option for implementations where performance is particularly critical and circuit area budgets are less constrained.

[0037] Regardless of the number of rounds supported, if all rounds have been allocated and there are still some uncompleted memory access transactions remaining, and another barrier point signal is received, the round change circuitry can prevent the current round from being changed to the next round. Similarly, if there is still an earlier barrier termination command that needs to check the completion of one or more rounds of memory access transactions, including the next round, and the earlier barrier termination command has not yet been signaled as completed, the round change circuitry can prevent the current round from being changed to the next round. In these scenarios, the round may not be changed to the next round in response to the barrier point signal. This may not affect the architectural correctness of the processing, but in some cases may simply delay the completion of subsequent barrier termination commands. However, this scenario may be relatively rare in most expected scenarios because barrier termination commands may be relatively rare.

[0038] Figure 1 A part of a data processing system 2 is shown schematically. Figure 1Many components of system 2 are shown that are involved in detecting the completion of a barrier termination command. It will be appreciated that system 2 may include many other components that may not be directly involved in the barrier termination decision. System 2 includes transaction processing circuitry 4, transaction tracking circuitry 6, barrier termination circuitry 8, and round change circuitry 10. The system also includes a current round storage element 12 (such as a register) that stores an identifier that identifies which round is the current round.

[0039] The transaction processing circuitry 4 is responsible for receiving memory access transactions from upstream transaction sources, issuing transactions to downstream memory system components, receiving responses to issued transactions from downstream memory system components, and passing responses back to the upstream transaction sources. The transaction processing circuitry 4 may be located at various points within the memory system, such as within an interconnect, a memory controller, or a memory management unit, for example.

[0040] The transaction tracking circuit 6 includes a plurality of transaction counters 14, each of which tracks the number of outstanding memory access transactions issued in a specific time period, called a round. When the transaction processing circuit 4 receives a memory access transaction to be issued, it can issue the transaction downstream with an identifier of the current round appended from the current round register 12. Furthermore, the transaction processing circuit 4 can control the transaction tracking circuit 6 to increment the transaction counter 14 corresponding to the current round.

[0041] Upon receiving a barrier point signal, the round change circuit 10 can control the update of the current round to the next round. For example, the current round can cycle through the supported rounds in a certain order (e.g., 0, 1, 0, 1, ... in a system supporting two rounds, or 0, 1, 2, 3, 0, 1, 2, 3, ... in a system supporting four rounds), and the update can simply switch the current round to the next round in the cycle. The barrier point signal can be any signal that marks a barrier point in execution, at which it is useful to divide memory access transactions into a set of transactions issued before the barrier point and a set of transactions issued after the barrier point. Therefore, by appending a round identifier to each issued transaction to indicate the current round when the transaction was issued, it means that the completion of transactions associated with each round can be tracked by monitoring the round identifier specified by the corresponding transaction response. When a transaction response specifying a given round identifier is received, the transaction tracking circuit 6 decrements the transaction counter 14 for the round identified by the round identifier specified in the received transaction response. The downstream memory component may append a round identifier to the transaction response that matches the round identifier specified in the issued memory access transaction for which the response was generated.

[0042] The barrier termination circuit 8 can use the tracking provided by the transaction tracking circuit 6 to determine when the barrier termination command can be marked as complete. When the barrier termination command is received, the barrier termination circuit 8 checks the current round register 12 to determine which previous rounds need to complete all their memory access transactions before the barrier termination command can be signaled as complete. Which rounds are the relevant rounds to check can depend on how the barrier point signal is defined relative to the barrier termination command. For implementations in which the barrier point signal is the barrier termination command itself, the relevant round to check is only the current round when the barrier termination command is received. Therefore, in this case, the barrier termination circuit can check the transaction counter 14 corresponding to the current round 12 when the barrier termination command is received, and when the transaction counter returns to its reset value (the value that the counter would hold when there are no outstanding transactions issued in that round, e.g., the reset value may be zero), the barrier termination circuit 8 can then issue a barrier completion signal to indicate that it is now safe to proceed with any operations that must wait for memory accesses prior to the barrier point to complete.

[0043] On the other hand, other implementations may define a barrier point signal that is different from the barrier termination command, such that the barrier point signal may mark an earlier processing point than the point at which the barrier termination command is received. In this case, the relevant rounds checked using the barrier termination circuit 8 may be one or more rounds older than the current round indicated by the current round register 12 when the barrier termination command is received. In a system that supports two rounds, if the current round is round 0, the older round will be round 1, and if the current round is round 1, the older round will be round 0. Some systems may support more than two rounds, and in this case, it may be necessary to check multiple older rounds. In some cases, the check for older rounds may be implemented simply by checking whether the transaction counter 14 of any round other than the current round 12 when the barrier termination command is received indicates that there are no remaining uncompleted transactions for those rounds.

[0044] Therefore, regardless of how the barrier point signal is defined, the barrier termination circuitry issues a barrier completion signal when one or more transaction counters for one or more particular rounds indicate that no transactions remain. This approach allows barrier completion to be determined without requiring a complex transaction tracker that tracks identifiers of individual memory access transactions and compares each responded transaction identifier with each entry in the transaction tracker. This significantly saves circuit area by eliminating not only the storage overhead of the transaction tracker entries themselves but also the associated comparison logic. Similarly, this approach means that issuing memory access transactions does not need to cease upon receiving a barrier termination command, as memory access transactions can continue to be issued using the altered rounds while still being able to identify a set of earlier transactions that need to be completed before the barrier termination command can be considered complete.

[0045] Figure 2-5 A flow chart illustrating actions taken in response to various events is shown.

[0046] Figure 2 The actions taken by the transaction processing circuitry 4 in response to receiving a memory access transaction are shown. At step 20, a transaction is received. In response, at step 22, the transaction processing circuitry 4 obtains an identifier for the current round from the current round register 12 and issues a memory access transaction to a downstream memory system component, wherein the issued transaction specifies the current round identifier. At step 24, the transaction processing circuitry 4 controls the transaction tracking circuitry 6 to increment a transaction counter associated with the current round. It will be appreciated that this can be done in a manner similar to Figure 2 Step 22 and step 24 may be performed in the reverse order of that shown, or may be performed in parallel.

[0047] Figure 3 The following diagram illustrates actions performed in response to receiving a transaction response from a downstream memory component. At step 30, the transaction processing circuitry 4 receives a transaction response that specifies a given round identifier. The given round identifier identifies the round associated with the corresponding memory access transaction that caused the downstream component to generate the transaction response. At step 32, the transaction processing circuitry controls the transaction tracking circuitry 6 to decrement the transaction counter 14 corresponding to the round identifier specified by the transaction response.

[0048] Figure 4 shows actions performed in response to a barrier point signal, which may be executed in response to a signal generated by the CPU or Figure 1, which is generated by instructions executed by other processing elements not shown in FIG. As discussed above, this can be the barrier termination command itself or can be a separately defined barrier point signal. At step 40, the barrier point signal is received by the round change circuit 10. At step 42, in response to receiving the barrier point signal, the round change circuit 10 detects whether the round that will be the next round after the current round is still being used to process the previous synchronization (barrier termination command) or whether there are still any uncompleted transactions associated with the next round. If either of these conditions is the case, then at step 44, the round change circuit 10 does not update the current round, and the current round is retained without change. This is because all available rounds will have been used to process the previous barrier termination command, so changing the round at this stage will lead to erroneous results, as it may cause transactions issued before the barrier point and transactions issued after the barrier point to be considered to be in the same round, which may be undesirable. On the other hand, if the next round is not being used to process any previous synchronization and there are no outstanding transactions for the next round, then at step 46 the round is changed to the next round so that the transaction tracking circuit 6 can distinguish between transactions before and after the barrier point.

[0049] Figure 5, which may again be generated in response to an instruction executed by a CPU or other processing element. At step 50, barrier termination circuitry 8 receives the barrier termination command. In response, barrier termination circuitry 8 checks transaction counters 14 maintained by transaction tracking circuitry 6. At step 52, barrier termination circuitry determines whether there are no remaining incomplete transactions for any of the one or more particular rounds preceding the associated barrier point based on transaction counters 14. As discussed above, depending on whether the barrier point signal is the same as or a different signal than the barrier termination command, the one or more rounds may be the current round or may be older than the current round. In some cases, completion of the barrier termination command may also depend on whether another dependent event (such as invalidation of control data in a cache such as a TLB, as discussed further below) has also completed. Therefore, if it is determined that there is at least one remaining incomplete transaction from one or more rounds, or if any other dependent event required to complete barrier termination has not yet completed, barrier termination circuitry 8 waits and continues to check whether the condition in step 52 is met. Finally, once there are no remaining uncompleted transactions for one or more rounds prior to the barrier point, and any other dependent events are completed (if required), the barrier termination circuit 8 generates a barrier completion signal to signal the completion of the barrier termination command at step 54. This barrier completion signal can be a trigger for other events in the data processing system 2 to proceed. For example, there may be some instructions that were made dependent on the barrier termination command, so they cannot continue to execute until the barrier termination command has completed.

[0050] The round identifier attached to a memory access transaction and the corresponding transaction response may be signaled in different ways within the memory transaction protocol. Some existing architectures that define the format of memory access transactions may have specified certain user-controlled fields that have no mandatory function specified in the architecture, but are free for appropriate use by a particular microarchitecture implementation of a processor supporting the architecture. Therefore, some microarchitecture implementations of memory systems may use those user-controlled bits to encode the round identifier and then Figure 1 The circuits 4, 6, 8, 10, 12 shown may utilize those user controlled bits to keep track of transactions assigned to particular rounds in the manner discussed above.

[0051] Alternatively, in other cases, the round identifier may be defined at the architectural level such that all implementations of systems supporting a particular memory protocol architecture may need to recognize the round identifier in the memory transaction format, and in this case the round identifier may be a new field added to the architectural definition of the format that should be used to encode memory access transactions.

[0052] Another approach could be for each transaction to have a transaction identifier, and transactions associated with one round could use a transaction identifier from a different set of one or more transaction identifiers than the set of one or more transaction identifiers assigned for a different round. Thus, in some cases, the round identifier could be the transaction identifier itself. This approach could be used for protocols where assigning different transaction identifiers to transactions that would otherwise share the same transaction identifier for round tracking purposes does not cause any other side effects.

[0053] However, for other protocols, transaction identifiers may provide ordering information (e.g., transactions with the same transaction identifier may need to be processed in the same order as they were received), and in such cases, using transaction identifiers to distinguish transactions in different rounds may be inappropriate (e.g., because transactions that should be processed in sequence may be accidentally processed out of order if they are assigned transaction identifiers associated with different rounds). For protocols that use transaction identifiers for other purposes, it may be preferable to use a user-controlled field or a dedicated round identifier as discussed above.

[0054] exist Figure 1-5 The techniques shown in the general sense in

[15] are useful for tracking the completion of any type of barrier-terminating command, which causes the processing system to signal when memory transactions issued before a certain barrier point have completed. However, they are particularly useful for a specific type of barrier-terminating command, which is used to check that transactions that may have used translation data from the TLB before the invalidation point at which the translation data was invalidated from the TLB have completed before subsequent operations proceed. This is particularly useful when updating page table structures in memory and purging expired translation entries from the TLB. Figure 6 and Figure 7 A more specific hardware example is shown that uses a round-based tracking scheme to handle such synchronization after TLB invalidation. Figure 6 shows a broader view of the data processing system 2, while Figure 7 Certain components of the system memory management unit (SMMU) are shown.

[0055] like Figure 6As shown, the data processing system 2 may include one or more central processing units (CPUs) 60, which include a memory management unit (MMU) 61. The MMU 61 may have at least one translation lookaside buffer (TLB) 62 for caching page table information from a page table structure stored in memory 64. The CPU may have at least one cache 66 for caching data from memory. The MMU 61 may be responsible for controlling address translation between virtual addresses specified by instructions executed by the CPU 60 and physical addresses used by the memory system, and may also check whether memory accesses triggered by the CPU 60 meet the access rights defined in the page table structure. The TLB 62 is used to cache certain subsets of the most recently used page table entries for faster access by the CPU than if the structure and memory had to be checked every time a memory access was initiated.

[0056] Access to memory from the CPU is controlled via interconnect 66, which can route transactions from multiple masters to memory and maintain coherency between caches in different masters. Interconnect 66 may also include a system cache 68 for caching data shared by different masters and for providing faster access to certain data than would be possible by accessing memory 64.

[0057] In addition to one or more master devices (such as the CPU 60) having their own internal MMU 61, the system 2 may also include at least one device 70 that may not have an internal MMU but still needs to access the memory 64 and may need to perform some address translation function and / or access permission checking to check whether the device 70 is allowed to access certain addresses in the memory. Therefore, a system memory management unit (SMMU) 80 is provided to provide functionality equivalent to that of the MMU 61 within the CPU 60 on behalf of the device 70. Although Figure 6 Only one device 70 is shown, but the same SMMU 80 may be shared between two or more different devices 70. As in the MMU 61, the SMMU 80 may have its own internal TLB 82 that caches information derived from page table entries from the memory system.

[0058] Therefore, when software executing on CPU 60 updates the page table structures in the memory system, it may be necessary to invalidate some translation entries within TLB 62, 82 to ensure that memory access transactions initiated after the page table data is updated cannot find outdated information in TLB 62, 82. Such updates to the page table structures may typically be performed by a monitoring software process executing on CPU 60 that has more privileges than the processes whose memory accesses can be controlled through the page table structures. TLB invalidation may be performed in a more fine-grained manner than simply invalidating the entire TLB, for example, by limiting entries to be invalidated based on a context identifier that identifies a certain translation context associated with a particular entry of the TLB, which may be based on the current operating state of CPU 60 at the time the TLB invalidation is requested or based on the operands specified in the TLB invalidation instruction. Therefore, a TLB invalidation triggered by CPU 60 is unlikely to have a significant impact on the performance of CPU 60 itself because, typically, at the time the TLB invalidation is requested, the CPU may not be executing instructions from the software process that will be subject to the set of translation entries to be invalidated.

[0059] However, TLB invalidation can have a significantly greater performance overhead for device 70. Typically, when TLB information needs to be invalidated due to changes in the page table structure, it may be necessary to ensure that any outstanding transactions issued before the TLB invalidation have completed, so that processing of subsequent operations that need to be guaranteed to rely on the new page table data can be resumed. Because the device issues memory access transactions unaware of what is happening at CPU 60, and there is no guarantee that the device will process transactions from a different translation context than the one undergoing the invalidation, it is more likely that the handling of synchronization after TLB invalidation will affect the performance of device 70. Therefore, it may be useful to provide functionality in SMMU 80 for reducing the performance impact after invalidation. This means that it may be highly desirable not to use a technique for handling synchronization or barrier termination that requires SMMU 80 to stop issuing device memory access transactions to interconnect 66. Nevertheless, it is also desirable for SMMU 80 to have a relatively manageable circuit area overhead, and it is desirable for the SMMU design to be scalable to a relatively large number of outstanding transactions at once to avoid impacting performance. This is particularly problematic if the SMMU supports processing transactions from multiple devices and the number of devices with which the SMMU is to communicate is to be scalable between different system designs having different numbers of devices 70. Therefore, the round-based scheme discussed above is particularly useful for the SMMU 80.

[0060] Figure 7The components of SMMU 80 are shown in greater detail. SMMU 80 includes a bus interface unit 86, a TLB unit 88, and a translation control unit 90. Bus interface unit 86 includes the transaction processing circuitry 4 described above and is responsible for receiving memory access transactions from device 70, forwarding them to interconnect 66, and communicating corresponding transaction responses received from interconnect 66 back to device 70. TLB unit 88 handles: lookups in TLB 82 based on the target address specified by the received memory access transaction, as well as invalidation of translation data from the TLB and processing of barrier termination commands. Thus, TLB unit 88 includes the transaction tracking circuitry 6, barrier termination circuitry 8, round change circuitry 10, and current round register 12 shown above, as well as invalidation control circuitry 92 for handling TLB invalidations. Translation control unit 90 is provided for handling the generation of a page table walk memory access transaction to request the retrieval of page table data from the page table structure in memory when TLB unit 88 detects a miss in TLB 82 for a given address of a memory access transaction. For example, page table walk unit 94 within translation control unit 90 may use registers defining the base address of the page table structure, index bits extracted from the address that missed in the TLB, and any results of previous page table walk transactions (which may be single-stepping through a multi-level page table structure) to form addresses for subsequent page table walk transactions that are issued to request further page table information from memory until the required page table data can eventually be identified to provide the physical address corresponding to the address that missed in TLB 82. Figure 7 In the example of FIG, page table walk transactions are issued directly from translation control unit 90 to downstream components, such that translation control unit 90 and bus interface unit 86 have separate connections to interconnect 66. Alternatively, page table walk transactions may actually be routed to interconnect 66 via bus interface unit 86 in a manner similar to other memory access transactions that are not page table walks.

[0061] Thus, when the SMMU 80 receives a memory access transaction, it may specify a transaction identifier, a virtual address, and an indication of whether the transaction is a read or write transaction, and for write transactions, may also specify the write data. The bus interface unit 86 may provide a translation request specifying the virtual address to the TLB unit 88, which may look up the virtual address in its TLB 82. If there is a hit in the TLB 82, the matching TLB entry may be used to identify the corresponding physical address, which is returned to the bus interface unit 86 along with the identifier of the current round specified in the current round register 12. As discussed above, the translation request may also trigger the incrementing of the associated round counter 14 within the transaction tracking circuitry 6. Then, when the transaction is issued downstream, the bus interface unit 86 may provide the round identifier and physical address, along with other parameters of the memory access transaction received from the upstream source (in addition to the virtual address). When bus interface unit 86 receives a transaction response, bus interface unit 86 signals to TLB unit 88 that the transaction associated with the round identifier specified by the transaction response has completed, which causes the associated transaction counter in transaction tracking circuitry 6 to decrement. Bus interface unit 86 also passes the transaction response back to the source device, which includes the read data if the transaction that triggered the response was a read, or a write completion confirmation if the transaction was a write.

[0062] like Figure 8 As shown, in some examples, separate circuit logic portions 4-R, 4-W within bus interface unit 86 or other portions of SMMU 80 may be used to handle read and write transactions, so that reads and writes may be tracked separately in transaction tracking circuit 6 more efficiently. Transaction tracking circuit 6 may also be divided into separate read portion 6-R and write portion 6-W. Figure 8 As shown, separate sets of round counters 14-R, 14-W may be maintained for read and write transactions, respectively. In this case, the transaction processing circuitry 4 and the transaction tracking circuitry 6 are effectively divided into separate read portions 4-R, 6-R and write portions 4-W, 6-W, and when the barrier termination circuitry 8 needs to determine whether a given barrier command has completed, it will check the read counters 14-R and write counters 14-W associated with the relevant rounds.

[0063] return Figure 7, the barrier termination circuit 8 in the TLB unit 88 receives a barrier termination command (e.g., from the CPU 60 executing a barrier termination instruction) and determines, based on the transaction tracking circuit 6, whether the barrier can be signaled as complete. The invalidation control circuit 92 controls the TLB 82 to perform invalidation in response to the invalidation command (received from the CPU 60 executing the TLB invalidation instruction) and provides an invalidation response when the invalidation is complete. The barrier point signal that triggers the round change circuit 10 to change the round can be either an invalidation command received by the invalidation control circuit 92 or a barrier termination command (invalidation synchronization command) received by the barrier termination circuit 8. Different options can be used to implement this. Figure 9-13 A number of different options for controlling round updates are shown.

[0064] Figure 9 A first option is shown for a system in which the invalidate command and the synchronize command are effectively the same command. Thus, the same command triggers both the invalidation of the entry from the TLB 82 and the barrier termination circuit 8 to start checking whether the preceding memory access transaction has completed. Figure 9 In the example shown, prior to receiving the invalidate / synchronize command, the current round 12 is round 0, so all memory access transactions issued during that period have a round identifier specifying round 0. At time 100, an invalidate command (which also serves as a synchronization command) is received, triggering invalidate control circuitry 92 to traverse the entries of the TLB to invalidate entries matching a certain invalidation condition. Furthermore, this command triggers round change circuitry 10 to switch the current round to the next round, round 1. Consequently, subsequently issued memory access transactions specify a round identifier equal to 1. As mentioned above, there is some flexibility regarding the exact timing of the round change, depending on how the TLB implements its invalidation. At time 104, the transaction counter for round 0 indicates that there are no remaining incomplete transactions, so it can be determined that any transactions prior to the barrier point at time 100 have completed. Provided that the invalidate itself has also completed, barrier termination circuitry 8 issues a barrier complete signal to signal that synchronization has completed, so any operations awaiting completion of the synchronization can then proceed. Thus, for this example, the barrier point signal is a combined invalidate / sync command, and the relevant round to be checked to determine whether barrier termination can be completed is the round that is current when the combined invalidate / sync command is received (i.e., at Figure 9 In the example, it is round 0).

[0065] Figure 10A second example is shown that illustrates an implementation option for a system that supports separate commands for invalidation and invalidation synchronization (barrier termination). In this example, the barrier point is considered to be the time when the invalidation synchronization command is received, which triggers the barrier termination circuit 8 to start checking for barrier completion and then also changes the round from the current round to the next round. The invalidation command in this example that triggers the invalidation control circuit 92 to invalidate the TLB entry does not cause the round to change. Figure 10 An example timeline of a command sequence is shown, and in this example, two consecutive invalidate commands, A and B, are received before a synchronize command. Initially, the current round is round 0, and this round remains the current round even after invalidate commands have been received at times 120 and 122. The invalidations triggered by invalidate commands A and B complete at times 124 and 126, respectively. A synchronize command is received at time 128 and serves as a barrier point signal, which controls round change circuitry 10 to change the round to round 1, so that subsequent transactions issued after time 128 now specify round 1. The synchronize command also controls barrier termination circuitry 8 to begin checking whether transaction tracking circuitry 6 indicates that all transactions issued with round identifier 0 (which was the current round when the synchronize command was received) have completed. At time 130, the transaction counter for round 0 returns to 0, meaning there are no remaining uncompleted round 0 transactions, so barrier termination circuitry 8 can issue a barrier complete signal to indicate that synchronization is complete.

[0066] In options 1 and 2, it is assumed that the system supports two rounds, namely round 0 and round 1. However, by providing additional transaction counters within the transaction tracking circuit 6 and providing multiple bits to the round identifier field in the memory access transaction and response, more than two rounds can also be supported. This can be done in different ways, either by cycling through the rounds in a fixed order using a multi-bit round number represented as a binary value, or by maintaining separate round bits to track each parallel synchronization event using a separate counter for each round. Figure 11 The first of these methods is shown, and Figure 12 The second one is shown.

[0067] like Figure 11 As shown, when a round identifier represented as a binary number having multiple bits is used to track multiple synchronization events, the current round can be changed each time a synchronization command is received (until the point where all available rounds have been used without resolving earlier synchronization commands, as discussed above). Figure 442 ). In this example, the initial round is round 0, and a first synchronization command A is received at time 150, triggering the round change circuitry 10 to change the current round to the next round, round 1. Before the signaling of synchronization command A is completed, a second synchronization command B is received at time 152, and this results in the round being updated again to round 2. Support for more than two rounds means that it is not necessary to postpone the round transition from round 1 to round 2 until synchronization command A has completed, which can be useful because it means that completion of synchronization command B does not need to wait for the completion of memory access transactions issued between time 152 and time 154 when the first synchronization command completes, which might otherwise be required if only two rounds were supported, so the change of round for the second synchronization command B would have to wait until time 154.

[0068] Figure 12 A second option for tracking multiple synchronizations simultaneously is shown. In terms of the timing of events, these Figure 11 The same as shown in , but with a different form of round identifier to track rounds. In this example, Figure 12 As shown at the top of FIG, the round identifier may have a first bit 160 identifying the round relative to the first synchronization operation A and a second bit 162 identifying the round relative to the second synchronization event B. Of course, more bits can be used to extend this method to three or more different synchronization events if desired. Thus, in this example, the rounds are initially 00, indicating that the current round is round 0 relative to synchronization command A and is also round 0 relative to synchronization command B. In response to synchronization command A at time 150, bit 160 switches to indicate that the round is now 1 relative to synchronization command A, but bit 162 remains 0. In response to the second synchronization command B at time 152, bit 162 switches to indicate that the current round is now round 1 relative to synchronization command B. Therefore, in response to synchronization command A, the relevant round that barrier termination circuit 8 checks for completion will be any round that has bit 160 set to 0, but may have bit 162 set to either 0 or 1. Thus, the completion of synchronization command A will depend on the completion of the transaction marked with round identifier 00 and the transaction marked with round identifier 10, if such transactions exist. In a similar manner, for synchronization command B at time 152, the completion of this command will have to wait until there are no remaining transactions marked with 00 or with 01, since the relevant round to be checked for synchronization command B is round 0 relative to the synchronization command, as marked by bit 162. In addition to the difference in the use of round identifiers to encode the rounds, the time instants are similar to Figure 11, and this provides another way of effectively ensuring that synchronization command B does not need to defer its completion until memory transactions issued between times 152 and 154 have completed.

[0069] Figures 9 to 12 The example shown in can support changing the round to the next round in response to a synchronization command before the TLB invalidation requested by an earlier TLB invalidation command is completed. To do this, either the TLB can prevent any further lookups in the TLB while the TLB invalidation is in progress (so that no more transactions specifying the next round will be issued before the invalidation is completed), or a progress identifier used as a "watermark" can track the most recent entry checked in the invalidation traversal of the TLB so that, during the period when the invalidation is still in progress, transactions that hit earlier entries in the traversal sequence can be assigned the next-round identifier, and transactions that hit later entries in the traversal sequence can be assigned the current-round identifier.

[0070] Another alternative would be to postpone the switch to the next round until the invalidation is complete if an invalidation is still in progress when a sync command is received, to ensure that no transaction marked with a next-round identifier could have used potentially stale translation data from a TLB entry that was subsequently invalidated in the remainder of the invalidation operation. Thus, while a sync command can be a trigger for an update round (in the sense that a round would not be updated if a sync command was not received at all), the moment to update the round can be postponed until the pending invalidation is complete. If this option is selected, for example, transactions in the next round will be marked with round 0 instead of round 1. Figure 10 Transactions issued in the period between time 128 and time 126 in , and similarly, in Figure 11 and Figure 12 Transactions issued in the period between time 152 and time 154 will retain the round identifier from the round before time 152, rather than receiving a new round identifier, as shown in these examples.

[0071] Figure 13A fifth approach is shown, which may be to define the barrier point signal as an invalid command, rather than when an invalid sync command is received, in cases where separate commands are provided for invalidation and invalid sync. This approach may allow for faster response to synchronization operations, but may require supporting more rounds. In this case, the current round is not changed when a sync command is received, but rather the round is changed in response to an invalid command (again, as discussed above, there is some flexibility as to the exact timing of the round change). For an invalid sync command, the relevant rounds to be checked are all previous rounds relative to the current round when the invalid sync command is received. Thus, as indicated by the transaction tracking circuit 6, the signaling of completion of the barrier termination will wait until all those previous rounds have been exhausted of outstanding transactions.

[0072] Figure 13 The timeline in FIGURE 1 illustrates such an example. Initially, a transaction is issued in round 0. An invalidate command is received at time 170, and in this example, the completion of the invalidate triggers a change in round to round 1. When a subsequent invalidate command B is received at time 172, once the invalidate has completed, this triggers the issuance of a new transaction in the changed round 2. As described above, other TLB implementations may change rounds after receiving an invalidate command, or have a transition period when both the old and new rounds are used for a transaction, depending on the position of the hit TLB entry relative to the invalidate traversal progress. When a synchronize command is received at time 174, no round change is required. For a synchronize command, the relevant rounds to check are rounds 0 and 1, which are older than the current round 2 at the time the synchronize command is received. Therefore, once it is determined that no round 0 or round 1 transactions remain uncompleted, at time 176, the barrier termination circuit 8 can signal that the synchronization has completed. One advantage of this approach is that barrier termination completion does not depend on the completion of transactions issued in the period between time 172 and time 174. In effect, the barrier point is traced back to the completion of the most recent invalidate command preceding the synchronize command, rather than at the time of the synchronize command itself. This improves performance by preventing some memory access transactions from affecting the completion of the synchronize command. However, because multiple invalidate commands may be received and a new round is needed to track the completion of each invalidate command, this may require supporting more rounds, which may increase transaction tracking overhead.

[0073] In this application, the phrase "configured to..." is used to indicate that elements of a device have a configuration capable of performing a defined operation. In this context, "configuration" refers to the arrangement or manner in which hardware or software are interconnected. For example, a device may have dedicated hardware to provide the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not imply that the device elements need to be modified in any way in order to provide the defined operation.

[0074] Although illustrative embodiments of the present invention have been described herein in detail with reference to the accompanying drawings, it will be understood that the invention is not limited to those precise embodiments and that various changes and modifications may be effected therein by those skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims.

Claims

1. A device comprising: transaction processing circuitry for issuing memory access transactions, each memory access transaction specifying a round identifier indicating a current round in which the memory access transaction is issued; transaction tracking circuitry for tracking, for each of at least two rounds, a number of outstanding memory access transactions issued in that round; a barrier termination circuit to signal completion of a barrier termination command when the transaction tracking circuit indicates that no outstanding memory access transactions issued in one or more rounds prior to the barrier point remain; and a round changing circuit for changing a current round to a next round in response to a barrier point signal indicating the barrier point, Wherein, in response to the barrier point signal, the round changing circuit is configured to: prevent the current round from being changed to the next round when there is still at least one incomplete memory access transaction associated with the next round, or the next round is one of the one or more rounds for an earlier barrier termination command that has not been signaled as completed.

2. The device according to claim 1, wherein The barrier point signal includes the barrier termination command.

3. The device according to claim 2, wherein The one or more rounds include a round that is a current round when the barrier termination command is received, and then the current round is changed to a next round in response to the barrier termination command.

4. The device according to claim 1, wherein The barrier point signal includes a barrier point identification signal different from the barrier termination command.

5. The device according to claim 4, wherein The one or more rounds include one or more rounds older than a round that is a current round when the barrier termination command is received.

6. The device according to any one of claims 1 to 5, wherein The transaction processing circuitry is configured to initiate a lookup in a translation lookaside buffer for page table information corresponding to an address specified by a memory access transaction to be issued.

7. The device according to claim 6, wherein In response to an invalidation command, the translation lookaside buffer is configured to invalidate page table information that meets an invalidation condition; and The barrier termination command includes an invalidate synchronization command requesting the barrier termination circuit to signal completion of the barrier termination command when the invalidate has completed and at least any memory access transaction that was looked up in the translation lookaside buffer prior to receipt of the invalidate command has completed.

8. The device according to claim 7, wherein The invalidate command and the invalidate synchronization command are the same command.

9. The device according to claim 7, wherein The invalidation command is a command different from the invalidation synchronization command.

10. The device according to claim 9, wherein The barrier point signal includes the invalid synchronization command.

11. The device according to claim 9, wherein The barrier point signal includes the invalidation command.

12. The device according to claim 1, wherein The transaction tracking circuit includes at least two transaction counters, each transaction counter counting the number of outstanding memory access transactions issued in a corresponding round.

13. The device according to claim 12, wherein The transaction tracking circuitry is configured to increment a transaction counter corresponding to a current round in response to a memory access transaction to be issued by the transaction processing circuitry.

14. The device according to any one of claims 12 and 13, wherein In response to issuing a memory access transaction specifying a given round identifier, the transaction processing circuitry is configured to receive a transaction response specifying the given round identifier; and In response to receiving the transaction response, the transaction tracking circuitry is configured to decrement a transaction counter corresponding to a round indicated by the given round identifier specified by the transaction response.

15. The device according to any one of claims 1 to 5, wherein The transaction tracking circuitry is configured to track the number of outstanding memory access transactions for two rounds only.

16. The device according to any one of claims 1 to 5, wherein The transaction tracking circuitry is configured to track a number of outstanding memory access transactions for more than two rounds.

17. An apparatus comprising: means for issuing memory access transactions, each memory access transaction specifying a round identifier indicating a current round in which the memory access transaction is issued; means for tracking, for each of at least two rounds, a number of outstanding memory access transactions issued in that round; means for signaling completion of the barrier termination command when the means for tracking indicates that there are no remaining outstanding memory access transactions issued in one or more rounds prior to the barrier point; and means for changing the current round to a next round in response to a barrier point signal indicating the barrier point, Wherein, in response to the barrier point signal, the means for changing the current round to the next round in response to the barrier point signal indicating the barrier point is configured to: prevent the current round from being changed to the next round when there is still at least one uncompleted memory access transaction associated with the next round, or the next round is one of the one or more rounds for an earlier barrier termination command that has not been signaled as completed.

18. A method comprising: issuing memory access transactions, each memory access transaction specifying a round identifier indicating a current round in which the memory access transaction is issued; tracking, for each of the at least two rounds, a number of outstanding memory access transactions issued in that round; In response to a barrier point signal indicating a barrier point, changing a current round to a next round; and signaling completion of a barrier terminate command when the trace indicates that there are no remaining outstanding memory access transactions issued in one or more rounds prior to the barrier point, In response to the barrier point signal, the method includes preventing the current round from being changed to the next round when there is still at least one incomplete memory access transaction associated with the next round, or the next round is one of the one or more rounds for an earlier barrier termination command that has not been signaled as completed.

19. An apparatus comprising: transaction processing circuitry for issuing memory access transactions, each memory access transaction specifying a round identifier indicating a current round in which the memory access transaction is issued; transaction tracking circuitry for tracking, for each of at least two rounds, a number of outstanding memory access transactions issued in that round; a barrier termination circuit to signal completion of a barrier termination command when the transaction tracking circuit indicates that no outstanding memory access transactions issued in one or more rounds prior to the barrier point remain; and a round changing circuit, configured to change a current round to a next round in response to a barrier point signal indicating the barrier point, wherein: The transaction tracking circuit includes at least two transaction counters, each transaction counter counting the number of outstanding memory access transactions issued in a corresponding round, The transaction tracking circuitry is configured to increment a transaction counter corresponding to a current round in response to a memory access transaction to be issued by the transaction processing circuitry; In response to issuing a memory access transaction specifying a given round identifier, the transaction processing circuitry is configured to receive a transaction response specifying the given round identifier; and In response to receiving the transaction response, the transaction tracking circuitry is configured to decrement a transaction counter corresponding to a round indicated by the given round identifier specified by the transaction response.

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