Semiconductor memory device and method of operating semiconductor memory device

Abstract

A semiconductor memory device and a method of operating the semiconductor memory device are provided. The semiconductor memory device includes a memory cell array, an ECC engine, at least one voltage generator, and a control logic circuit. The memory cell array includes a plurality of memory cells coupled to word lines and bit lines, and a plurality of sense amplifiers for sensing data stored in the plurality of memory cells. The ECC engine reads stored data from a target page of the memory cell array, performs ECC decoding on the stored data, detects an error in the stored data based on the ECC decoding, and outputs error information associated with the error. The at least one voltage generator supplies drive voltages to the plurality of sense amplifiers respectively. The control logic circuit controls the ECC engine and, based on error mode information including the error information, controls the at least one voltage generator to increase an operation margin of each of the plurality of sense amplifiers.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2019 - 0089411, filed on July 24, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] An apparatus and method consistent with the present disclosure relate to memories, and more particularly, to a semiconductor memory device and a method of operating a semiconductor memory device. Background art

[0004] Semiconductor memory devices can be classified into non - volatile memory devices (e.g., flash memory devices) and volatile memory devices (e.g., dynamic random access memories (DRAMs)). The high - speed operation and cost - efficiency of DRAMs enable DRAMs to be used for system memories. Due to the continuous scaling of the manufacturing design rules of DRAMs, bit errors in memory cells in DRAMs may increase rapidly and the yield of DRAMs may decrease. Therefore, it is necessary to improve the reliability of semiconductor memory devices. Summary of the invention

[0005] Example embodiments may provide a semiconductor memory device capable of enhancing performance.

[0006] Example embodiments may provide a method of operating a semiconductor memory device capable of enhancing performance.

[0007] According to an aspect of an example embodiment, there is provided a semiconductor memory device including: a memory cell array including a plurality of memory cells coupled to word lines and bit lines and a plurality of sense amplifiers configured to sense data stored in the plurality of memory cells; an error correction code (ECC) engine configured to: read stored data from a target page of the memory cell array, perform ECC decoding on the stored data, detect an error in the stored data based on the ECC decoding, and output error information associated with the error; at least one voltage generator configured to provide drive voltages to the plurality of sense amplifiers, respectively; and a control logic circuit configured to: control the ECC engine and, based on error mode information, control the at least one voltage generator to increase an operation margin of each of the plurality of sense amplifiers, wherein the error mode information includes the error information.

[0008] According to an aspect of an example embodiment, a semiconductor memory device is provided, the semiconductor memory device including: a memory cell array including: a plurality of memory cells coupled to word lines and bit lines, each of the plurality of memory cells storing multi-bit data, and a plurality of sense amplifiers configured to sense the multi-bit data; an error correction code (ECC) engine configured to: read stored data from a target page of the memory cell array, perform ECC decoding on the stored data, generate error information indicating an error pattern of the multi-bit data based on the ECC decoding, and output the error information; at least one voltage generator configured to provide drive voltages to the plurality of sense amplifiers respectively; and a control logic circuit configured to: control the ECC engine; control the at least one voltage generator to increase an operation margin of each of the plurality of sense amplifiers based on error pattern information, wherein the error pattern information includes the error information; record the error pattern information, and control the at least one voltage generator to adjust a voltage level of the drive voltage based on the error pattern information.

[0009] According to an aspect of an example embodiment, a method of operating a semiconductor memory device is provided, the method including: reading stored data from a target page of a memory cell array of the semiconductor memory device, the memory cell array including a plurality of memory cells coupled to word lines and bit lines and a plurality of sense amplifiers configured to sense data stored in the plurality of memory cells; performing ECC decoding on the stored data by an error correction code (ECC) engine of the semiconductor memory device; generating error information by the ECC engine based on the ECC decoding; controlling, by a control logic circuit of the semiconductor memory device, at least one voltage generator to adjust a voltage level of a drive voltage based on error pattern information, wherein the error pattern information includes the error information, wherein the at least one voltage generator is configured to provide the drive voltage to the plurality of sense amplifiers; sensing the stored data by applying the drive voltage to at least some of the plurality of sense amplifiers; and restoring the stored data by applying the drive voltage to at least some of the plurality of sense amplifiers.

[0010] Accordingly, the control logic circuit generates error pattern information by accumulating error information obtained from results of ECC decoding, and the control logic circuit controls the voltage generator based on the error pattern information to adjust the voltage level of the drive voltage provided to the sense amplifier, thereby increasing the operation margin of the sense amplifier. Accordingly, the performance of the semiconductor memory device can be enhanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Example embodiments will be described in more detail below with reference to the accompanying drawings, in which:

[0012] Figure 1 is a block diagram showing a storage system according to an example embodiment;

[0013] Figure 2 is a block diagram showing an example of a semiconductor memory device in Figure 1 according to an example embodiment;

[0014] Figure 3 shows Figure 2 a memory cell and a sense amplifier in the semiconductor memory device in

[0015] Figure 4 shows Figure 3 multi-bit data of a memory cell sensed by the sense amplifier in

[0016] Figure 5 is a circuit diagram showing an example of a sense amplifier in Figure 3 according to an example embodiment;

[0017] Figure 6 conceptually shows Figure 5 the operation of the sense amplifier;

[0018] Figures 7A to 7K shows Figure 5 the equivalent circuit of the operation of the sense amplifier;

[0019] Figure 8 is a timing diagram of the operation according to the equivalent circuit shown in Figures 7A to 7K ;

[0020] Figures 9 to 11 are timing diagrams for explaining the operation of the sense amplifier sensing multi-bit data stored in a memory cell, respectively;

[0021] Figure 12 shows an example of an ECC engine in Figure 2 according to an example embodiment;

[0022] Figure 13 shows the encoding / decoding logic in the ECC engine in Figure 12 according to an example embodiment;

[0023] Figure 14 shows the data corrector in the ECC engine in Figure 12 according to an example embodiment;

[0024] Figure 15 shows a part of the semiconductor memory device in Figure 2 during a write operation;

[0025] Figure 16 shows a semiconductor memory device in a read operation Figure 2 ;

[0026] Figure 17 shows an error mode information register in a semiconductor memory device according to an exemplary embodiment Figure 2 ;

[0027] Figure 18 is an example of a voltage generator in a semiconductor memory device according to an exemplary embodiment Figure 2 ;

[0028] Figure 19 shows a first voltage generator in Figure 18 according to an exemplary embodiment

[0029] Figure 20 shows a trend of an error mode based on a change in a cell voltage in a semiconductor memory device based on Figure 2 ;

[0030] Figures 21A to 21F respectively show that a control logic circuit controls a voltage generator based on error mode information to adjust a voltage level of a driving voltage

[0031] Figure 22 shows an example of a memory cell array in a semiconductor memory device according to an exemplary embodiment Figure 2 ;

[0032] Figure 23 shows a part of a memory cell array in Figure 22 according to an exemplary embodiment

[0033] Figure 24 is a circuit diagram showing an example of a bit line sense amplifier that can be used as one of the bit line sense amplifiers in Figure 23 according to an exemplary embodiment

[0034] Figure 25 is a flowchart showing a method of operating a semiconductor memory device according to an exemplary embodiment; and

[0035] Figure 26 is a block diagram showing a semiconductor memory device according to an exemplary embodiment DETAILED DESCRIPTION

[0036] Various exemplary embodiments will be described more fully hereinafter with reference to the accompanying drawings

[0037] Figure 1 is a block diagram showing a storage system according to an exemplary embodiment

[0038] Referring toFigure 1 , the storage system 20 may include a storage controller 100 and a semiconductor storage device 200.

[0039] The storage controller 100 may control the overall operation of the storage system 20. The storage controller 100 may control the overall data exchange between an external host and the semiconductor storage device 200. For example, the storage controller 100 may write data into the semiconductor storage device 200 or read data from the semiconductor storage device 200 in response to a request from the host. Additionally, the storage controller 100 may issue an operation command to the semiconductor storage device 200 to control the semiconductor storage device 200. The storage controller 100 sends a clock signal CLK, a command CMD (signal), and an address (signal) ADDR to the semiconductor storage device 200 and exchanges main data MD with the semiconductor storage device 200.

[0040] In some embodiments, the semiconductor storage device 200 is a storage device including dynamic storage cells, such as, for example, a dynamic random access memory (DRAM), a double data rate 4 (DDR4) synchronous DRAM (SDRAM), a DDR5 SDRAM, a low power DDR4 (LPDDR4) SDRAM, or an LPDDR5 SDRAM.

[0041] The semiconductor storage device 200 includes a memory cell array 300 that stores main data MD and parity bits, an error correction code (ECC) engine 400, a control logic circuit 210, an error pattern information register (EPIR) 580, and at least one voltage generator 700. The EPIR 580 may be included in the control logic circuit 210.

[0042] The memory cell array 300 may include a plurality of memory cells MC coupled to a word line WL and a bit line BL and a sense amplifier BLSA 280 coupled to the bit line BL and a complementary bit line BLB.

[0043] The control logic circuit 210 controls the ECC engine 400 such that the ECC engine 400 can perform ECC encoding on data to be stored in a target page of the memory cell array 300 and can perform ECC decoding on data read from the target page. The ECC engine 400 may output error information to the control logic circuit 210, and the error information is associated with an error detected in the read data based on the result of the ECC decoding.

[0044] The control logic circuit 210 may control at least one voltage generator 700 based on error mode information including error information to adjust the voltage levels of drive voltages VLA1 and VLA2. The voltage generator 700 generates drive voltages VLA1 and VLA2 under the control of the control logic circuit 210, and supplies the drive voltages VLA1 and VLA2 to the sense amplifier 280. For example, VLA1 may be supplied as voltage VINTA1 to node LA1 of the sense amplifier 280 (e.g., see Figure 5 ), and VLA2 may be supplied as voltage VINTA2 to node LA2 of the sense amplifier 280 (e.g., see Figure 5 ). The control logic circuit 210 may control the voltage generator 700 to increase the operating margin of the sense amplifier 280 during a sense / recovery operation performed by the sense amplifier 280 based on the adjusted drive voltages VLA1 and VLA2.

[0045] Figure 2 is a block diagram showing an example of a Figure 1 semiconductor memory device in accordance with an exemplary embodiment.

[0046] Referring to Figure 2 , the semiconductor memory device 200 may include a control logic circuit 210, a memory cell array 300, a row decoder 261, a column decoder 271, an input / output (I / O) gate circuit 290, an I / O sense amplifier 286, an ECC engine 400, a data I / O buffer 296, and a voltage generator 700.

[0047] The memory cell array 300 may include a plurality of memory cells MC coupled to word lines WL and bit lines BL, and sense amplifiers BLSA 280 coupled to bit lines BL and complementary bit lines BLB. Each memory cell MC includes a cell transistor CT and a cell capacitor CC. The gate of the cell transistor CT is connected to one of the word lines WL arranged in the row direction of the memory cell array 300. One end of the cell transistor CT is connected to one of the bit lines BL arranged in the column direction of the memory cell array 300. The other end of the cell transistor CT is connected to the cell capacitor CC. The cell capacitor CC may store charges corresponding to various capacities of multi-bit data (e.g., 2-bit data) or one-bit data. The cell capacitor CC may be restored with a charge amount corresponding to the capacity of each multi-bit data item, i.e., the cell capacitor CC may be restored to a cell voltage Vcell.

[0048] The control logic circuit 210 may generate control signals for controlling the operation of the semiconductor memory device 200 based on a command CMD and an address ADDR from the memory controller 100. The control logic circuit 210 may generate a first control signal CTL11 for controlling the I / O gate circuit 290, a second control signal CTL12 for controlling the ECC engine 400, and a third control signal CTL13 for controlling the voltage generator 270. The control logic circuit 210 may include an EPIR 580.

[0049] The address register 220 receives the address ADDR from the memory controller 100, provides a row address ROW_ADDR to the row decoder 261, and provides a column address COL_ADDR to the column decoder 271. The row decoder 261 decodes the row address ROW_ADDR and may enable a word line WL of a memory cell MC corresponding to the row address ROW_ADDR. The column decoder 271 decodes the column address COL_ADDR and may select bit lines corresponding to the column address COL_ADDR.

[0050] The I / O gate circuit 290 may be connected between the I / O sense amplifier 286 and the ECC engine 400. The I / O sense amplifier 286 senses and amplifies data read from the memory cell array 300 to provide the sensed data to the I / O gate circuit 290.

[0051] In a write operation, the ECC engine 400 may perform ECC encoding on write data MD to generate parity bits, and may provide a codeword CW including the write data MD and the parity bits to the I / O gate circuit 290. The ECC engine 400 may perform ECC decoding on the codeword CW in a read operation to provide main data MD to the data I / O buffer 296, and if an error is detected in the read data based on the ECC decoding result, may provide error information EINF including an error generation signal EGS to the control logic circuit 210. The error information EINF may include information about the number of errors and the location where the errors occur.

[0052] The data I / O buffer 296 may receive a clock signal CLK and main data MD from the memory controller 100, and may provide the main data MD to the ECC engine 400. The data I / O buffer 296 may receive the main data with errors corrected from the ECC engine 400, and may provide the main data MD to the memory controller 100.

[0053] The control logic circuit 210 may accumulate error information EINF associated with a page or sub-page corresponding to an address where an error has occurred based on the error information EINF, and may record the accumulated error information as error pattern information EPI in the EPIR 580. The accumulated error information (i.e., error pattern information EPI) in the EPIR 580 may represent an error pattern or a trend of the page where the error has occurred. The control logic circuit 210 may control the voltage generator 700 to adjust the voltage level of at least one of the drive voltages VLA1 and VLA2 and the precharge voltage VBL. The precharge voltage may be used to precharge the bit lines BL and complementary bit lines BLB.

[0054] The voltage generator 700 may generate the drive voltages VLA1 and VLA2 and the precharge voltage VBL based on the voltages VCC and VSS, and may adjust the voltage level of at least one of the drive voltages VLA1 and VLA2 and the precharge voltage VBL based on the third control signal CTL13, and may supply the drive voltages VLA1 and VLA2 and the precharge voltage VBL to the sense amplifier 280.

[0055] The semiconductor memory device 200 may further include a scrubbing control circuit 500 and a victim address detector 560. The control logic circuit 210 may supply a fourth control signal CTL14 to the victim address detector 560, and may supply a fifth control signal CTL15 to the scrubbing control circuit 500.

[0056] The victim address detector 560 may count the number of accesses to a first storage area in the memory cell array 300 within a reference interval to generate at least one victim address VCT_ADDR designating at least one adjacent storage area adjacent to the first storage area when the counted number of accesses reaches a reference number. The victim address VCT_ADDR may be stored in an address storage table of the scrubbing control circuit 500.

[0057] The scrubbing control circuit 500 may output the address of a codeword associated with the victim address VCT_ADDR stored in the address storage table as a weak codeword address WCADDR. The weak codeword address WCADDR may include a weak codeword row address WCRA and a weak codeword column address WCCA. The scrubbing control circuit 500 may supply the weak codeword row address WCRA and the weak codeword column address WCCA to the row decoder 261 and the column decoder 271, respectively.

[0058] The control logic circuit 210 can provide the address of the target page associated with the detected error as the error address EADDR to the cleaning control circuit 500. The control logic circuit 210 can control the ECC engine 400 to perform a cleaning operation on the sub - pages of the target page associated with the detected error. The ECC engine 400 can perform the cleaning operation by reading data from the storage locations corresponding to the sub - pages, correcting the errors, and writing the corrected data back to the storage locations corresponding to the sub - pages.

[0059] Figure 3 illustrates Figure 2 the memory cells and sense amplifiers in the semiconductor memory device in

[0060] Referring to Figure 3 , the sense amplifier 280 can be connected to the memory cell MC and the equalization circuit 160 through a pair of bit lines BL and BLB. The equalization circuit 160 includes first to third transistors 161, 162, and 163. The first to third transistors 161, 162, and 163 equalize the pair of bit lines BL and BLB by using a pre - charge voltage VBL ( Figure 7A ) in response to an equalization signal PEQ. The equalization signal PEQ can be provided by the control logic circuit 210 according to a pre - charge command. The pre - charge voltage VBL can be set to have a level corresponding to half of the level of the power supply voltage for driving the sense amplifier 280.

[0061] The sense amplifier 280 can be configured with an open - bit - line structure and connected to the memory cell MC. In the open - bit - line structure, a pair of bit lines BL and BLB are separately located in different adjacent main cell blocks 205 and 207. In the open - bit - line structure, when the word line WL of the selected memory cell MC is enabled, data can be read from or written to the memory cell MC through the selected bit line BL. At this time, although data of the memory cell MC is accessed via the selected bit line BL, since the selected memory cell is not on the complementary bit line BLB, the level of the pre - charge voltage VBL is maintained at the reference voltage level. Therefore, the sense amplifier 280 can sense the cell voltage Vcell of the memory cell MC by using the charge shared through the bit line BL.

[0062] The sense amplifier 280 can be configured to sense the cell voltage Vcell stored in the memory cell MC as a first bit corresponding to the most significant bit (MSB) of 2 - bit data and a second bit corresponding to the least significant bit (LSB), and can be configured to restore the cell voltage Vcell corresponding to the sensed MSB and LSB to the memory cell MC after sensing. For example, the sense amplifier 280 can use the cell capacitance of the memory cell MC, the bit - line capacitance of each of the pair of bit lines BL and BLB, a pair of hold bit lines HBL and HBLB (Figure 5 the bit line capacitance of each of those in Figure 5 ), the bit line capacitance of each of a pair of first sense bit lines SBL1 and SBLB1 ( Figure 5 ), the bit line capacitance of each of a pair of second sense bit lines SBL2 and SBLB2 (

[0063] The sense amplifier 280 performs first to third charge sharing operations based on the bit line capacitance of each of those, the bit line capacitance of each of a pair of first sense bit lines SBL1 and SBLB1 (), the bit line capacitance of each of a pair of second sense bit lines SBL2 and SBLB2 (), and the change in the bit line capacitance. The sense amplifier 280 senses the MSB and LSB of 2-bit data by performing the first to third charge sharing operations, and can restore the cell voltage Vcell corresponding to the sensed MSB and LSB to the memory cell MC.

[0064] Figure 4 is shown by Figure 3 the multi-bit data of the memory cell sensed by the sense amplifier 280 in

[0065] Referring to Figure 4 , the cell voltage Vcell of the memory cell MC represents the MSB and LSB of 2-bit data. Different cell voltages Vcell stored in the memory cell MC can represent different corresponding bit combinations among the bit combinations "00", "01", "10", or "11". For example, when the power supply voltage VINTA is 1.0V, it can be set such that the voltage difference between the bit combinations is approximately 330 mV to 340 mV. That is, a cell voltage Vcell of 0V can represent the bit combination "00", a cell voltage Vcell of 0.33V can represent the bit combination "01", a cell voltage Vcell of 0.67V can represent the bit combination "10", and a cell voltage Vcell of 1.0V can represent the bit combination "11".

[0066] In the exemplary embodiment, the levels of the cell voltages Vcell representing each of the bit combinations "00", "01", "10", or "11" can vary.

[0067] In the sense amplifier 280 for sensing the MSB of the memory cell MC, when performing the first charge sharing operation, the bit line BL and the hold bit line HBL are captured to have a prescribed MSB voltage V MSB , and the first charge sharing operation includes charge sharing between the charge stored in the cell capacitor CC and the charges stored in the bit line BL and the hold bit line HBL. The bit line BL can transition from the pre-charge voltage VBL level (i.e., 0.5V) to the MSB voltage V MSBAt this time, the complementary bit line BLB can maintain the level of the pre-charged voltage VBL.

[0068] For example, through the first charge sharing operation of the cell voltage Vcell of 0V for the bit combination "00", the voltage level of the bit line BL can be captured as the MSB voltage V of approximately 0.35V MSB . Through the first charge sharing operation of the cell voltage Vcell of 0.33V for the bit combination "01", the voltage level of the bit line BL can be captured as the MSB voltage V of approximately 0.45V MSB . Through the first charge sharing operation of the cell voltage Vcell of 0.67V for the bit combination "10", the voltage level of the bit line BL can be captured as the MSB voltage V of approximately 0.55V MSB . Through the first charge sharing operation of the cell voltage Vcell of 1.0V for the bit combination "11", the voltage level of the bit line BL can be captured as the MSB voltage V of approximately 0.65V MSB .

[0069] Therefore, the voltage levels of the bit line BL for the bit combinations "00", "01", "10", and "11" according to the first charge sharing operation can be captured as the MSB voltage V of approximately 0.35V, 0.45V, 0.55V, or 0.65V respectively MSB . At this time, the complementary bit line BLB maintains the pre-charged voltage VPRE of 0.5V. Through different specified voltage differences corresponding to the bit combinations "00", "01", "10", and "11" respectively, the MSB voltage V of the bit line BL MSB and the complementary bit line voltage V of 0.5V BLB can have a specified voltage difference therebetween, that is, a voltage difference of -150mV, -50mV, 50mV, or 150mV.

[0070] In the sense amplifier 280 for sensing the LSB of the memory cell MC, when the second charge sharing operation is performed, the bit line BL is captured as the specified LSB voltage V LSB , and this second charge sharing operation includes: charge sharing generated between the charges stored in the bit line BL and the hold bit line HBL and the charges stored in the first sense bit line SBL1, and charge sharing generated between the charges stored in the complementary bit line BLB and the complementary hold bit line HBLB and the charges stored in the first complementary sense bit line SBLB1. The bit line BL can change from the MSB voltage V MSB to the LSB voltage V LSB .

[0071] For example, for the bit combination "00", having the MSB voltage V of approximately 0.35V MSBThe voltage level of the bit line BL can be captured as the LSB voltage V of approximately 0.45V in the second charge sharing operation LSB . At this time, the voltage level of the complementary bit line BLB can be captured as the complementary bit line voltage V of approximately 0.5V BLB . For the bit combination "01", the voltage level of the bit line BL with the MSB voltage V of approximately 0.45V MSB can be captured as the LSB voltage V of approximately 0.45V in the second charge sharing operation LSB , and the complementary bit line voltage V BLB can be captured as 0.5V. For the bit combination "10", the level voltage of the bit line BL with the MSB voltage V of 0.55V MSB can be captured as the LSB voltage V of approximately 0.55V in the second charge sharing operation LSB , and the complementary bit line voltage V BLB can be captured as 0.5V. For the bit combination "11", the voltage level of the bit line BL with the MSB voltage V of 0.65 MSB can be captured as the LSB voltage V of approximately 0.55V in the second charge sharing operation LSB , and the complementary bit line voltage V BLB can be captured as 0.5V.

[0072] According to the second charge sharing operation, the voltage levels of the bit line BL for the bit combinations "00" and "01" are captured as the LSB voltages V of approximately 0.45V and 0.45V respectively LSB , and the level of the complementary bit line voltage V BLB is captured as approximately 0.5V. The voltage levels of the bit line BL for the bit combinations "10" and "11" are captured as the LSB voltages V of approximately 0.55V and 0.55V respectively LSB , and the level of the complementary bit line voltage V BLB is captured as approximately 0.55V. There is a specified voltage difference corresponding to each of the bit combinations "00", "01", "10", and "11" between the LSB voltage V of the bit line BL LSB and the complementary bit line voltage V BLB (i.e., -50mV, -50mV, 50mV, or 50mV), which means that the LSB voltage V corresponding to each of the bit combinations "00", "01", "10", and "11" LSB is used as a self-reference, and no additional reference voltage is required to sense the LSB voltage V LSB .

[0073] Figure 5 is a circuit diagram showing an example of a sense amplifier in Figure 3 according to an exemplary embodiment.

[0074] Reference Figure 5

[0074] , the sense amplifier 280 may include a sense amplification circuit 281, a latch circuit 283, and a switching circuit. The switching circuit includes a bit line switch SWa, a complementary bit line switch SWb, a power supply switch SWpl, and first to sixth switches SW1 to SW6.

[0075] In some embodiments, the latch circuit 283 operates by a second power supply voltage (e.g., VINTA2) applied to LA2 and a third voltage level that may be negative with respect to the reference ground voltage of the sense amplifier 280 applied to the signal node LAB2.

[0076] The sense amplification circuit 281 is connected to a first sense signal node LA1 and a second sense signal node LAB1, and includes p-channel metal oxide semiconductor (PMOS) transistors P11 and P12 and n-channel metal oxide semiconductor (NMOS) transistors N11 and N12. The tolerance of the sense amplification circuit 281 may be the difference between the first sense signal node and the second sense signal node. According to the control of the control logic circuit 210, a first power supply voltage VINTA1, a ground voltage VSS, and a precharge voltage VBL may be applied to each of the first sense signal node LA1 and the second sense signal node LAB1 to control the operation of the sense amplifier 280. The first power supply voltage VINTA1, the ground voltage VSS, and the precharge voltage VBL may be included in the first drive voltage group. The sense amplification circuit 281 may sort the first bit and the second bit of the multi-bit data stored in the memory cell MC. In some embodiments, VINTA1 is an example of the first power supply voltage in the first drive voltage group.

[0077] One end of the PMOS transistor P11 is connected to the line of the first sense signal node LA1, the other end of the PMOS transistor P11 is connected to the first sense bit line SBL1, and the gate of the PMOS transistor P11 is connected to the first complementary sense bit line SBLB1. One end of the PMOS transistor P12 is connected to the line of the first sense signal node LA1, the other end of the PMOS transistor P12 is connected to the first complementary sense bit line SBLB1, and the gate of the PMOS transistor P12 is connected to the first sense bit line SBL1. One end of the NMOS transistor N11 is connected to the power supply switch SWpl, the other end of the NMOS transistor N11 is connected to the first sense bit line SBL1, and the gate of the NMOS transistor N11 is connected to the hold bit line HBL. One end of the NMOS transistor N12 is connected to the power supply switch SWpl, the other end of the NMOS transistor N12 is connected to the first complementary sense bit line SBLB1, and the gate of the NMOS transistor N12 is connected to the complementary hold bit line HBLB.

[0078] The bit line switch SWa is connected between the bit line BL and the holding bit line HBL, and is turned on or off in response to the control of the control logic circuit 210. The complementary bit line switch SWb is connected between the complementary bit line BLB and the complementary holding bit line HBLB, and is turned on or off in response to the control of the control logic circuit 210. The power switch SWpl is connected between one end of each of the NMOS transistors N11 and N12 and the line of the second sense signal node LAB1, and is turned on or off in response to the control of the control logic circuit 210.

[0079] The first switch SW1 is connected between the holding bit line HBL and the first sense bit line SBL1, and is turned on or off in response to the control of the control logic circuit 210. The second switch SW2 is connected between the complementary holding bit line HBLB and the first complementary sense bit line SBLB1, and is turned on or off in response to the control of the control logic circuit 210. The third switch SW3 is connected between the holding bit line HBL and the first complementary sense bit line SBLB1, and is turned on or off in response to the control of the control logic circuit 210. The fourth switch SW4 is connected between the complementary holding bit line HBLB and the first sense bit line SBL1, and is turned on or off in response to the control of the control logic circuit 210.

[0080] The latch circuit 283 is connected to the third sense signal node LA2 and the fourth sense signal node LAB2, and includes PMOS transistors P21 and P22 and NMOS transistors N21 and N22. The second power supply voltage VINTA2, the ground voltage VSS, and the negative voltage VBB or the precharge voltage VBL can be applied to each of the third sense signal node LA2 and the fourth sense signal node LAB2 according to the control of the control logic circuit 210 to control the operation of the sense amplifier 280. The second power supply voltage VINTA2, the ground voltage VSS, and the negative voltage VBB or the precharge voltage VBL can be included in the second drive voltage group. In some embodiments, VINTA2 is the second power supply voltage in the second drive voltage group. The latch circuit 283 can receive the first bit sensed by the sense amplifier circuit 281 and can store the received first bit.

[0081] One end of the PMOS transistor P21 is connected to the line of the third sense signal node LA2, the other end of the PMOS transistor P21 is connected to the second sense bit line SBL2, and the gate of the PMOS transistor P21 is connected to the second complementary sense bit line SBLB2. One end of the PMOS transistor P22 is connected to the line of the third sense signal node LA2, the other end of the PMOS transistor P22 is connected to the second complementary sense bit line SBLB2, and the gate of the PMOS transistor P22 is connected to the second sense bit line SBL2. One end of the NMOS transistor N21 is connected to the line of the fourth sense signal node LAB2, the other end of the NMOS transistor N21 is connected to the second sense bit line SBL2, and the gate of the NMOS transistor N21 is connected to the second complementary sense bit line SBLB2. One end of the NMOS transistor N22 is connected to the line of the fourth sense signal node LAB2, the other end of the NMOS transistor N22 is connected to the second complementary sense bit line SBLB2, and the gate of the NMOS transistor N22 is connected to the second sense bit line SBL2.

[0082] The fifth switch SW5 is connected between the first sense bit line SBL1 and the second sense bit line SBL2, and is turned on or off in response to the control of the control logic circuit 210. The sixth switch SW6 is connected between the first complementary sense bit line SBLB1 and the second complementary sense bit line SBLB2, and is turned on or off in response to the control of the control logic circuit 210.

[0083] Figure 6 is conceptually shown Figure 5 of the flowchart of the operation of the sense amplifier.

[0084] Referring to Figure 6 , in operation S110, the sense amplifier 280 performs a precharge operation. The sense amplifier 280 precharges the bit line BL, the hold bit line HBL, the complementary bit line BLB, the complementary hold bit line HBLB, the first sense bit line SBL1, the first complementary sense bit line SBLB1, the second sense bit line SBL2, the second complementary sense bit line SBLB2, the first sense signal node LA1, the second sense signal node LAB1, the third sense signal node LA2, and the fourth sense signal node LAB2 to the precharge voltage VBL.

[0085] In operation S120, the sense amplifier 280 performs an offset cancellation operation. In Figure 3In the sense amplifier 280 with an open bit line structure as shown, noise caused by, for example, process variations, temperature, or threshold voltage differences between transistors may vary in a pair of bit lines BL and BLB. The noise of the pair of bit lines BL and BLB may be used as offset noise during the sensing operation of the sense amplifier 280, and may reduce the effective sensing tolerance of the sense amplifier 280. Therefore, the sense amplifier 280 may be configured to perform an offset cancellation operation before the sensing operation to increase the effective sensing tolerance.

[0086] In operation S130, the sense amplifier 280 senses the MSB (first bit) of the 2-bit combination represented by the cell voltage Vcell stored in the memory cell MC. The MSB sensing operation may include a first charge sharing operation, which may include: charge sharing generated between the charge stored in the memory cell MC and the charges stored in the bit line BL and the hold bit line HBL.

[0087] The sense amplifier 280 senses and amplifies the MSB voltage V of the bit line BL and the hold bit line HBL MSB and the complementary bit line voltage V of the complementary bit line BLB BLB and may latch the MSB of logic "1" with the level of the first supply voltage VINTA1 or the MSB of logic "0" with the level of the ground voltage VSS.

[0088] In operation S140, the sense amplifier 280 may sense the LSB (second bit) of the 2-bit combination represented by the cell voltage Vcell stored in the memory cell MC. The LSB sensing operation may include a second charge sharing operation.

[0089] The sense amplifier 280 senses and amplifies the LSB voltage V of the bit line BL and the hold bit line HBL LSB and the complementary bit line voltage V of the complementary hold bit line HBLB BLB and may latch the LSB of logic "1" with the level of the first supply voltage VINTA1 or the LSB of logic "0" with the level of the ground voltage VSS.

[0090] In operation S150, the sense amplifier 280 performs a restore operation to rewrite the cell voltage Vcell generated by combining the sensed MSB and LSB to the memory cell MC. The restore operation may include a third charge sharing operation.

[0091] Through the sensing operation S130 of the MSB and the sensing operation S140 of the LSB, the LSBs of the corresponding logic levels are stored in the bit line BL and the hold bit line HBL, and the MSBs of the corresponding logic levels are stored in the first sense bit line SBL1, the complementary bit line BLB, the complementary hold bit line HBLB, and the first complementary sense bit line SBLB1.

[0092] The third charge sharing operation can be performed by using the cell capacitance of the memory cell MC, the bit line capacitance of each of the pair of bit lines BL and BLB, the bit line capacitance of each of the pair of hold bit lines HBL and HBLB, the bit line capacitance of each of the pair of first sense bit lines SBL1 and SBLB1, and the change in capacitance. The sensed MSB and LSB can be combined by the third charge sharing operation. The sense amplifier 280 can restore the cell voltage Vcell generated by combining the sensed MSB and LSB into the memory cell MC.

[0093] Figures 7A to 7K is a schematic diagram Figure 5 of the operation of the sense amplifier.

[0094] Figure 8 is a timing diagram Figures 7A to 7K of the operation according to the equivalent circuit shown in

[0095] For simplicity of illustration, the switches that are turned on in Figures 7A to 7K are shown as short circuits, and the switches that are turned off are shown as open circuits. Figures 7A to 7K shows the operation of the sense amplifier sensing the cell voltage Vcell of 0.33V (i.e., the 2-bit data "01") stored in the memory cell MC.

[0096] Precharge operation

[0097] Referring to Figure 7A and Figure 8 at the time point T0, the sense amplifier 280 precharges the bit line BL, the hold bit line HBL, the complementary bit line BLB, the complementary hold bit line HBLB, the first sense bit line SBL1, the first complementary sense bit line SBLB1, the second sense bit line SBL2, the second complementary sense bit line SBLB2, the first sense signal node LA1, the second sense signal node LAB1, the third sense signal node LA2, and the fourth sense signal node LAB2 to the precharge voltage VBL.

[0098] For example, at Figure 3In the equalization circuit 160, the bit line BL and the complementary bit line BLB may be precharged to a precharge voltage VBL. During the precharge operation, the sense amplifier circuit 281 and the latch circuit 283 are in an off state, the bit line switch SWa, the complementary bit line switch SWb, and the power supply switch SWpl are in an on state, and the first switch SW1 to the sixth switch SW6 are in an off state. Hereinafter, when the sense amplifier circuit 281 is in an off state, the precharge voltage VBL is applied to the first sense signal node LA1 and the second sense signal node LAB1, and when the latch circuit 283 is in an off state, the precharge voltage VBL is applied to the third sense signal node LA2 and the fourth sense signal node LAB2.

[0099] Offset cancellation operation

[0100] Refer to Figure 7B and Figure 8 At the time point T1 as shown in, the sense amplifier 280 performs an offset cancellation operation. In order to increase the effective sensing tolerance of the sense amplifier 280, the sense amplifier 280 turns on the sense amplifier circuit 281 and turns on the first switch SW1 and the second switch SW2 to perform the offset cancellation operation. The first power supply voltage VINTA1 is applied to the first sense signal node LA1 of the sense amplifier circuit 281, and the ground voltage VSS is applied to the second sense signal node LAB1.

[0101] In the sense amplifier circuit 281, due to the offset noise of a pair of bit lines BL and BLB, the complementary bit line BLB increases or decreases to a specified level compared to the bit line BL, and thus, there is a specified voltage difference between the bit line BL and the complementary bit line BLB. The voltage difference can be interpreted as an offset voltage according to the offset noise, which means that the difference between the bit line BL and the complementary bit line BLB is set as the offset voltage, and thus, the offset noise of the sense amplifier 280 is eliminated. That is, the sense amplifier 280 can compensate for the offset through the offset cancellation operation.

[0102] First charge sharing operation

[0103] Refer to Figure 7C and Figure 8 At the time point T2 as shown in, the sense amplifier 280 performs a first charge sharing operation between the memory cell MC and the bit line BL. The sense amplifier 280 turns off the sense amplifier circuit 281 and the first switch SW1 and the second switch SW2. At this time, the word line WL connected to the memory cell MC is enabled, and charge sharing occurs between the charge stored in the capacitor of the memory cell MC and the charge stored in the bit line BL and the hold bit line HBL.

[0104] When the cell voltage Vcell of 0.33V is stored in the memory cell MC, during the charge sharing operation, the voltage level of each of the bit line BL and the hold bit line HBL decreases from the level of the precharge voltage VBL to a specified level. That is, the voltage level of each of the bit line BL and the hold bit line HBL decreases from 0.5V to approximately 0.45V. At this time, each of the complementary bit line BLB and the complementary hold bit line HBLB maintains the level of the precharge voltage VBL, that is, 0.5V.

[0105] Charge holding operation

[0106] Refer to Figure 7D and Figure 8 At the time point T3 of

[0107] MSB sensing operation

[0108] Refer to Figure 7E and Figure 8 At the time point T4 of Figure 7E , the sense amplifier 280 performs an MSB sensing operation for sensing the MSB of the 2-bit combination represented by the cell voltage Vcell stored in the memory cell MC. The sense amplifier 280 turns on the sense amplifier circuit 281 and the third switch SW3 and the fourth switch SW4 to perform the MSB sensing operation. The first power supply voltage VINTA1 is applied to the first sense signal node LA1 of the sense amplifier circuit 281, and the ground voltage VSS is applied to the second sense signal node LAB1. In the

[0109] The sense amplifier circuit 281 senses the MSB of the 2-bit combination based on the difference between the 0.45V hold bit line HBL voltage applied to the gate of NMOS transistor N11 and the 0.5V complementary hold bit line HBLB voltage applied to the gate of NMOS transistor N12, can raise the voltage of the first sense bit line SBL1 to the logic "1" level, and can lower the voltage of the first complementary sense bit line SBLB1 to the logic "0" level. The voltage of the complementary hold bit line HBLB connected to the first sense bit line SBL1 is raised to the logic "1" level, and the voltage of the hold bit line HBL connected to the first complementary sense bit line SBLB1 is lowered to the logic "0" level.

[0110] First MSB latch operation

[0111] Refer to Figure 7F and Figure 8 At time point T5 with reference to and, the sense amplifier 280 performs a first MSB latch operation to latch the MSB of the 2-bit data. The sense amplifier 280 performs the first MSB latch operation by disconnecting the sense amplifier circuit 281, turning on the latch circuit 283, disconnecting the power switch SWpl, and turning on the fifth switch SW5 and the sixth switch SW6. The second power supply voltage VINTA2 is applied to the third sense signal node LA2 of the latch circuit 283, and the ground voltage VSS is applied to the fourth sense signal node LAB2. The first sense bit line SBL1 and the second sense bit line SBL2 are connected through the fifth switch SW5, and the first complementary sense bit line SBLB1 and the second complementary sense bit line SBLB2 are connected through the sixth switch SW6. The power switch SWpl can be disconnected to block the leakage current path that prohibits the operation of the latch circuit 283 in the conducting state.

[0112] The latch circuit 283 senses the MSB of the 2-bit combination based on the voltage difference between the second sense bit line SBL2 and the second complementary sense bit line SBLB2, can raise the voltage of the second sense bit line SBL2 to the logic "1" level, and can lower the voltage of the second complementary sense bit line SBLB2 to the logic "0" level. The voltage of each of the first sense bit line SBL1 and the complementary hold bit line HBLB connected to the second sense bit line SBL2 is at the logic "1" level. The voltage of each of the first complementary sense bit line SBLB1 and the hold bit line HBL connected to the second complementary sense bit line SBLB2 is at the logic "0" level.

[0113] After the MSB latch operation, the charge on the line between SBLB2 and SBLB1 represents the information indicating the logic value of the MSB. That is, when the MSB is logic 1 or logic 0, the charge is different.

[0114] Second MSB latch operation

[0115] Refer to Figure 7G and Figure 8 At time point T6, the sense amplifier 280 performs a second MSB latch operation. The sense amplifier 280 performs the second MSB latch operation by turning off the third switch SW3 to the sixth switch SW6. The voltage of the second sense bit line SBL2 is maintained at the logic "1" level, the voltage of the second complementary sense bit line SBLB2 is maintained at the logic "0" level, the voltage of the first sense bit line SBL1 is maintained at the logic "1" level, the voltage of the first complementary sense bit line SBLB1 is maintained at the logic "0" level, the voltage of the hold bit line HBL is maintained at the logic "0" level, and the voltage of the complementary hold bit line HBLB is maintained at the logic "1" level. The logic "0" level can be latched as the MSB of the memory cell MC to the second complementary sense bit line SBLB2 of the latch circuit 283.

[0116] Second charge sharing operation

[0117] Refer to Figure 7H and Figure 8 At time point T7, the sense amplifier 280 performs a second charge sharing operation between the first sense bit line SBL1, the hold bit line HBL, and the bit line BL, and between the first complementary sense bit line SBLB1, the complementary hold bit line HBLB, and the complementary bit line BLB. The sense amplifier 280 turns on the bit line switch SWa, the complementary bit line switch SWb, and the first switch SW1 and the second switch SW2.

[0118] The bit line BL, the hold bit line HBL, and the first sense bit line SBL1 are connected through the bit line switch SWa and the first switch SW1. The complementary bit line BLB, the complementary hold bit line HBLB, and the first complementary sense bit line SBLB1 are connected through the complementary bit line switch SWb and the second switch SW2.

[0119] Charge sharing occurs among the charge stored in the bit line BL, the charge stored in the hold bit line HBL, and the charge stored in the first sense bit line SBL1. Charge sharing also occurs among the charge stored in the complementary bit line BLB, the charge stored in the complementary hold bit line HBLB, and the charge stored in the first complementary sense bit line SBLB1.

[0120] In the second charge sharing operation, the voltage of each of the bit line BL, the hold bit line HBL, and the first sense bit line SBL1 is captured to be approximately 0.5V, and the voltage of each of the complementary bit line BLB, the complementary hold bit line HBLB, and the first complementary sense bit line SBLB1 is captured to be approximately 0.45V.

[0121] The sense amplifier circuit 281 from Figure 8At time point T7, it is not in the active setting because both LA1 and LAB1 are set to the same voltage VBL. Charge sharing occurs as described above, and the charge states of HBL and HBLB correspond to the LSB. That is, when the LSB is logic 1 or logic 0, the charge states of HBL and HBLB are different.

[0122] LSB sensing operation

[0123] Refer to Figure 7I and Figure 8 At time point T8, the sense amplifier 280 performs an LSB read operation to sense the LSB of the 2-bit combination represented by the cell voltage Vcell stored in the memory cell MC. The sense amplifier 280 performs the LSB sensing operation by turning on the sense amplifier circuit 281 and the power switch SWpl, turning off the first switch SW1 and the second switch SW2, and turning on the third switch SW3 and the fourth switch SW4.

[0124] The first power supply voltage VINTA1 is applied to the first sense signal node LA1 of the sense amplifier circuit 281, and the ground voltage VSS is applied to the second sense signal node LAB1. The bit line BL, the hold bit line HBL, and the first complementary sense bit line SBLB1 are connected through the bit line switch SWa and the third switch SW3. The complementary bit line BLB, the complementary hold bit line HBLB, and the first sense bit line SBL1 are connected through the complementary bit line switch SWb and the fourth switch SW4.

[0125] The sense amplifier circuit 281 senses the LSB of the 2-bit combination based on the difference between the 0.5V bit line BL voltage applied to each of the gates of the PMOS transistor P11 and the NMOS transistor N11 and the 0.45V complementary bit line BLB voltage applied to each of the gates of the PMOS transistor P12 and the NMOS transistor N12. The voltage of the first sense bit line SBL1 can be reduced to the logic "0" level, and the voltage of the first complementary sense bit line SBLB1 can be raised to the logic "1" level.

[0126] The voltage of each of the complementary bit line BLB and the complementary hold bit line HBLB connected to the first sense bit line SBL1 is reduced to the logic "0" level, and the voltage of each of the bit line BL and the hold bit line HBL connected to the first complementary sense bit line SBLB1 is raised to the logic "1" level. The logic "1" level can be latched as the LSB of the memory cell MC into the bit line BL of the sense amplifier circuit 281.

[0127] From Figure 8 time point T8 and as Figure 7IAs shown, as indicated by LA1 = VINTA1 and LAB1 = VSS, the sense amplifier circuit 281 is activated. Then, as Figure 7H shown and as discussed above, the voltage state of the sense amplifier circuit 281 is determined by the charge state established between time point T7 and time point T8.

[0128] Combining MSB and LSB

[0129] Referring to Figure 7J and Figure 8 at time point T9, the sense amplifier 280 can perform an operation of combining the sensed MSB and LSB of the memory cell MC. The sense amplifier 280 can combine the sensed MSB and LSB by disconnecting the sense amplifier circuit 281 and the power switch SWp1, turning on the second switch SW2, disconnecting the third switch SW3, and turning on the sixth switch SW6.

[0130] The MSB of logic "0" level is latched to the second complementary sense bit line SBLB2 of the latch circuit 283, and the LSB of logic "1" level is latched to the first complementary sense bit line SBLB1 of the sense amplifier circuit 281.

[0131] The second complementary sense bit line SBLB2, a pair of first sense bit lines SBL1 and SBLB1, the complementary hold bit line HBLB, and the complementary bit line BLB can be connected through the complementary bit line switch SWb, the second switch SW2, the fourth switch SW4, and the sixth switch SW6. The voltages of each of the pair of first sense bit lines SBL1 and SBLB1, the complementary hold bit line HBLB, and the complementary bit line BLB connected to the second complementary sense bit line SBLB2 are reduced to the logic "0" level. At this time, the voltages of each of the bit line BL and the hold bit line HBL are maintained at the logic "1" level.

[0132] From Figure 8 at time point T9, the SBLB2 (related to the MSB) of the latch circuit 283 and the SBLB1 (related to the LSB) of the sense amplifier circuit 281 establish an electrical connection through the closing of the sixth switch SW6. Refer to Figure 7J for the circuit configuration. This will start the recovery operation. During the time interval from T9 to T10 in Figure 8 the charge generated affects the SBL1 of the sense amplifier circuit 281.

[0133] Third charge sharing operation

[0134] Referring to Figure 7K and Figure 8At time point T10, the sense amplifier 280 performs a third charge sharing operation among a pair of first sense bit lines SBL1 and SBLB1, a pair of hold bit lines HBL and HBLB, and a pair of bit lines BL and BLB. The sense amplifier 280 can perform the third charge sharing operation by disconnecting the sense amplifier circuit 281, turning on the first switch SW1 and the third switch SW3, and disconnecting the sixth switch SW6. The pair of bit lines BL and BLB, the pair of hold bit lines HBL and HBLB, and the pair of first sense bit lines SBL1 and SBLB1 can be connected by the bit line switch SWa, the complementary bit line switch SWb, and the first switch SW1 to the fourth switch SW4.

[0135] The sense amplifier 280 can perform the third charge sharing operation by using the cell capacitance of the memory cell MC, the bit line capacitance of each of the pair of bit lines BL and BLB, the bit line capacitance of each of the pair of hold bit lines HBL and HBLB, the bit line capacitance of each of the pair of first sense bit lines SBL1 and SBLB1, and the change in capacitance. In the third charge sharing operation, the voltage of each of the pair of bit lines BL and BLB, the pair of hold bit lines HBL and HBLB, and the pair of first sense bit lines SBL1 and SBLB1 has a level of approximately 0.33V. The voltage of the bit line BL drops from the logic "1" level to 0.33V, and the 0.33V bit line BL voltage is restored to the memory cell MC as the cell voltage Vcell.

[0136] The above-mentioned sense amplifier 280 senses the 0.33V cell voltage Vcell stored in the memory cell MC as the MSB and LSB bits "01", and restores the 0.33V bit line BL voltage corresponding to the sensed MSB and LSB bits "01" to the memory cell MC as the cell voltage Vcell.

[0137] Therefore, the variation of the data that has been read from the memory cell MC (e.g., Figure 7A ) is reduced, as Figure 20 marked as "restored" 793 at the logical value 01 with hatching (right below the center on the right side of Figure 20 ).

[0138] Figures 9 to 11 is a timing diagram for explaining the operation of the sense amplifier to sense multi-bit data stored in the memory cell.

[0139] Figure 9 is a timing diagram showing the operation of the sense amplifier to sense the 0V cell voltage Vcell (i.e., 2-bit data "00") stored in the memory cell MC.

[0140] Figure 9 And Figure 8The difference is that the cell voltage Vcell is 0V, and the voltage levels of the bit line pair BL and BLB, the hold bit line pair HBL and HBLB, and the first sense bit line pair SBL1 and SBLB1 change according to the cell voltage Vcell of 0V.

[0141] Figure 10 is a timing diagram showing the operation of the sense amplifier sensing the cell voltage Vcell of 0.67V (i.e., the 2-bit data "10") stored in the memory cell MC.

[0142] Figure 10 and Figure 8 The difference is that the cell voltage Vcell is 0.67V, and the voltage levels of the bit line pair BL and BLB, the hold bit line pair HBL and HBLB, and the first sense bit line pair SBL1 and SBLB1 change according to the cell voltage Vcell of 0.67V.

[0143] Figure 11 is a timing diagram showing the operation of the sense amplifier sensing the cell voltage Vcell of 1.0V (i.e., the 2-bit data "11") stored in the memory cell MC.

[0144] Figure 11 and Figure 8 The difference is that the cell voltage Vcell is 1.0V, and the voltage levels of the bit line pair BL and BLB, the hold bit line pair HBL and HBLB, and the first sense bit line pair SBL1 and SBLB1 change according to the cell voltage Vcell of 1.0V.

[0145] Figure 12 shows an example of the ECC engine according to the exemplary embodiment Figure 2 in

[0146] Referring to Figure 12 , the ECC engine 400 may include a multiplexer 410, encoding / decoding logic 420, a buffer unit 440, and a data corrector 460. The buffer unit 440 may include a first buffer 441 to a fourth buffer 444.

[0147] In a write operation, multiplexer 410 provides write data WMD to encoding / decoding logic 420 in response to a first select signal SS1. In a read operation, multiplexer 431 provides read data RMD from buffer 442 to encoding / decoding logic 420 in response to the first select signal SS1. Buffers 441 and 443 can be enabled in a write operation in response to a mode signal MS and provide write data WMD and parity bit PRT to I / O gate circuit 290. Buffers 442 and 444 can be enabled in a read operation in response to the mode signal MS. Buffer 442 can provide read data RMD to multiplexer 410 and data corrector 460, and buffer 444 can provide parity bit PRT to encoding / decoding logic 420.

[0148] In a write operation, encoding / decoding logic 420 can perform ECC encoding on write data WMD to provide parity bit PRT to buffer 443. In a read operation, encoding / decoding logic 420 can perform ECC decoding on read data RMD from multiplexer 410 based on parity bit PRT from buffer 444 to provide syndrome data SDR to data corrector 460. Data corrector 460 corrects errors in read data RMD based on syndrome data SDR from encoding / decoding logic 420 to provide corrected main data C_MD, and can provide error information EINF including an error generation signal EGS to control logic circuit 210 when an error is detected in read data RMD. The first select signal SS1 and the mode signal MS can be included in a second control signal CTL12.

[0149] Figure 13 Illustrated is the encoding / decoding logic in the ECC engine according to an example embodiment Figure 12 in.

[0150] Referring to Figure 13 , encoding / decoding logic 420 can include a parity checker 421, a check bit generator 423, and a syndrome generator 430.

[0151] Parity checker 421 can generate parity bit PRT based on write data WMD using an exclusive-OR gate array.

[0152] Check bit generator 423 can generate check bit CHB based on read data RMD. Syndrome generator 430 can generate syndrome data SDR based on check bit CHB and parity bit PRT from buffer 444.

[0153] Figure 14 Illustrated is the data corrector in the ECC engine according to an example embodiment Figure 12 in.

[0154] Refer to Figure 14 , the data corrector 460 may include a syndrome decoder 461, a bit inverter 463, and a selection circuit 465 implemented by a multiplexer.

[0155] The syndrome decoder 461 may decode the syndrome data SDR to generate a decoded signal DS, a second selection signal SS2, and an error information EINF including an error generation signal EGS. The decoded signal DS may indicate the position of at least one error bit, and the second selection signal SS2 may have a logic level depending on the number of at least one error bit. The bit inverter 463 may invert at least one error bit in response to the decoded signal DS. The selection circuit 465 may select one of the read data RMD and the output of the bit inverter 463 in response to the second selection signal SS2 to provide the corrected main data C_MD.

[0156] Figure 15 Shown in the write operation Figure 2 a part of the semiconductor memory device.

[0157] In Figure 15 , the control logic circuit 210, the memory cell array 300a, the I / O gate circuit 290, and the ECC engine 400 in the semiconductor memory device 200 are shown.

[0158] Refer to Figure 15 , the memory cell array 300a includes a normal cell array NCA and a redundant cell array RCA. The normal cell array NCA includes a plurality of first memory blocks MB0 to MB15 (i.e., 311 to 313), and the redundant cell array RCA includes at least a second memory block 314. The first memory blocks 311 to 313 are memory blocks that determine the storage capacitance of the semiconductor memory device 200. The second memory block 314 is used for ECC and / or redundant repair. Since the second memory block 314 for ECC and / or redundant repair is used for ECC, data line repair, and block repair to repair the "faulty" cells generated in the first memory blocks 311 to 313, the second memory block 314 is also referred to as an EDB block. In each of the first memory blocks 311 to 313, a plurality of first memory cells are arranged in rows and columns. In the second memory block 314, a plurality of second memory cells are arranged in rows and columns. The first memory cell connected to the intersection of the word line WL and the bit line BL may be a dynamic memory cell. The second memory cell connected to the intersection of the word line WL and the redundant bit line RBL may be a dynamic memory cell.

[0159] The I / O gate circuit 290 includes a plurality of switch circuits (e.g., multiplexers MUX) 291a to 291d respectively connected to the first memory blocks 311 to 313 and the second memory block 314.

[0160] The ECC engine 400 can be connected to the switching circuits 291a to 291d via the first data lines GIO[0:127] and the second data lines EDBIO[0:7].

[0161] When the command CMD is a write command, the control logic circuit 210 provides a second control signal CTL12 to the ECC engine 400, and the ECC engine 400 performs ECC encoding on the main data MD to generate parity bits associated with the main data MD, and provides a codeword CW including the main data MD and the parity bits to the I / O gate circuit 290. The control logic circuit 210 provides a first control signal CTL11 to the I / O gate circuit 290 such that the codeword CW will be stored in a sub-page of a target page in the memory cell array 300a.

[0162] Figure 16 Illustrated in a read operation Figure 2 of the semiconductor memory device.

[0163] In Figure 16 are shown the control logic circuit 210, the memory cell array 300a, the I / O gate circuit 290, the ECC engine 400, and the voltage generator 700. Additionally, the control logic circuit 210 includes a counter 214 and an EPIR 580.

[0164] Referring to Figure 16 , when the command CMD is a read command specifying a read operation, the control logic circuit 210 provides a first control signal CTL11 to the I / O gate circuit 290 so that the codeword RCW stored in a sub-page of a target page in the memory cell array 300a is provided to the ECC engine 400.

[0165] In a read operation, the ECC engine 400 performs a scrubbing operation by performing ECC decoding on the codeword RCW, correcting at least one error in the codeword RCW, and writing the corrected data back to the storage location of the storage sub-page. When at least one error is detected during the scrubbing operation, each time an error is detected, the ECC engine 400 provides error information EINF including an error generation signal EGS to the control logic circuit 210. The counter 214 in the control logic circuit 210 counts the error generation signal EGS, and the control logic circuit 210 records error pattern information EPI indicating the error occurrence trend associated with each page in some pages in the EPIR 580 by accumulating the error information EINF. Based on counting the error generation signal EGS, the error information EINF can at least include the number of error occurrences in a selected memory cell row. In a refresh operation, the ECC engine 400 performs a scrubbing operation and provides error information EINF to the control logic circuit 210.

[0166] The control logic circuit 210 may control the voltage generator 700 using the third control signal CTL13 to adjust the voltage levels of the driving voltages VLA1 and VLA2 based on the error mode information.

[0167] Figure 17 illustrates an Figure 2 error mode information register in a semiconductor memory device according to an exemplary embodiment.

[0168] Referring to Figure 17 , each of the indexes (e.g., entries) Idx1, Idx2, ……, Idxu (u is a natural number greater than 2) may include page error information for each page in some pages of the memory cell array 300. Each entry may correspond to one page. The error mode information register 580 includes a plurality of columns 581, 582, 583, 584, 585, and 586.

[0169] The first column 581 stores ranking information RNK that ranks the number of error occurrences based on the number of error occurrences for each page in some pages. The entry with the lowest value (e.g., 1) of the ranking information RNK may be considered the highest rank, while the entry with the highest value of the ranking information RNK may be considered the lowest rank. For example, the first page associated with idx1 that has 2 errors during a given time period may receive an RNK of 2, while when the second page associated with idx2 has 4 errors during the given time period, it may receive a higher RNK of 1.

[0170] The second column 582 stores address information ADDINF for each page in some pages. In an exemplary embodiment, the address information ADDINF includes at least one of a bank group address (“BGA”), a bank address (“BA”), and a row address (“RA”). Although Figure 3 a group of memory bank arrays (e.g., 310 to 340) is illustrated, there may be additional groups of memory bank arrays. The bank group address may identify one of these groups. For example, if there is a first group of memory bank arrays including memory bank arrays 310 to 380 and a second group of memory bank arrays, and an error occurs in the first group, the BGA will identify the first group. The bank address may identify one of the memory banks in the identified group. The row address may identify the page of the memory bank.

[0171] The third column 583 stores the number of error occurrences ECNT for each page in some pages. For example, Figure 17The error pattern information register 580 in [[]] shows that the error occurrence count ECNT of the page with address A is 2 and the error occurrence count ECNT of the page with address B is 4. The fourth column 584 stores the number FCWCNT of sub - pages including bit errors in each of some pages. For example, if the second page has 4 bit errors (ECNT = 4), the second page has 64 sub - pages, but only 3 sub - pages out of 64 have bit errors (for example, sub - page 1 and 12 each have 1 bit error, and sub - page 43 has 2 bit errors), then the FCWCNT in the entry of the second page can be 3.

[0172] The fifth column 585 stores flag information FG. The flag information FG indicates whether the error information of the corresponding page is initially written into the error pattern information register 580. When the error information of the corresponding page is initially written into the error pattern information register 580, the flag information FG has a first logic level (for example, 0). In an embodiment, if the flag information FG of a page has a second logic level (for example, 1), then the page previously had error information.

[0173] Figure 18 is an example of a voltage generator in a Figure 2 semiconductor memory device according to an exemplary embodiment.

[0174] Referring to Figure 18 , the voltage generator 700 may include a first voltage generator 710 and a second voltage generator 730. The first voltage generator 710 may generate a first power supply voltage VINTA1, a second power supply voltage VINTA2, and a pre - charge voltage VBL, and may adjust the voltage level of each of the first power supply voltage VINTA1, the second power supply voltage VINTA2, and the pre - charge voltage VBL based on a first voltage control signal VCTL1. The second voltage generator 720 may generate a negative voltage VBB2, and may adjust the voltage level of the negative voltage VBB2 based on a second voltage control signal VCTL2. Regarding VINTA1 and VINTA2, in some embodiments, VBB2 may be referred to as a third voltage or a negative voltage. The first voltage control signal VCTL1 and the second voltage control signal VCTL2 may be included in a third control signal CTL13.

[0175] Figure 19 shows a first voltage generator in a Figure 18 according to an exemplary embodiment.

[0176] Referring to Figure 19, the first voltage generator 710 includes an oscillator 711, a charge pump (CP) 713, and a voltage divider 714. The oscillator 711 operates in response to a first voltage control signal VCTL1 and generates a pulse signal. The charge pump 713 performs a pumping operation in response to the pulse signal to generate a second power supply voltage VINTA2. The voltage divider 714 includes a plurality of resistors R1-Rk connected in series between an output node NO and a ground voltage, divides the second power supply voltage VINTA2, and generates a first power supply voltage VINTA1 and a precharge voltage VBL. Although one charge pump 713 is shown in Figure 19 , the first voltage generator 710 may include a plurality of charge pumps, and the voltage levels of each of the first power supply voltage VINTA1, the second power supply voltage VINTA2, and the precharge voltage VBL may be adjusted.

[0177] Figure 18 The configuration of the second voltage generator 730 in Figure 19 may be similar to the configuration of the first voltage generator 710 in

[0178] Figure 20 shows the trend of error patterns based on the change of the cell voltage in the semiconductor memory device based on Figure 2 .

[0179] In Figure 20 , reference numeral 751 represents the trend of error patterns caused by the change of the cell voltage Vcell in the memory cells coupled to the following bit lines: the bit line is coupled to the sense amplifier 280 and the length of the bit line from the sense amplifier 280 is relatively long; reference numeral 753 represents the trend of error patterns caused by the change of the cell voltage Vcell in the memory cells coupled to the following bit lines: the bit line is coupled to the sense amplifier 280 and the length of the bit line from the sense amplifier 280 is relatively short. Referring to Figure 20 , the cell voltage Vcell often makes errors within some specific ranges.

[0180] Reference numeral 761 represents that the sense amplifier 280 performs a sensing operation, reference numeral 773 represents that the sense amplifier 280 performs a recovery operation. Reference numeral 762 represents that the voltage generator 700 raises the voltage level of the precharge voltage VBL, reference numeral 763 represents that the voltage generator 700 lowers the voltage level of the precharge voltage VBL, reference numerals 764 and 765 respectively represent that the voltage generator 700 raises / lowers the voltage level of the first power supply voltage VINTA1, and reference numerals 766 and 767 respectively represent that the voltage generator 700 raises / lowers the voltage level of the first power supply voltage VINTA1.

[0181] In addition, reference numeral 781 indicates that the voltage generator 700 raises the voltage difference between the second power supply voltage VINTA2 and the negative voltage VBB2, reference numeral 782 indicates that the voltage generator 700 reduces the voltage level of the first power supply voltage VINTA1, and reference numeral 783 indicates that the voltage generator 700 reduces the voltage level of the first power supply voltage VINTA1. In addition, reference numeral 791 indicates that no error occurs in the multi-bit data at the corresponding cell voltage Vcell, reference numeral 792 indicates that an error occurs in the multi-bit data at the corresponding cell voltage Vcell, and reference numeral 792 indicates the level of the voltage restored to the memory cell MC. Reference numeral 793 indicates the value after the restoration of Vcell (corresponding to Figure 6 in operation S150).

[0182] Figures 21A to 21F Respectively show that the control logic circuit controls the voltage generator to adjust the voltage level of the drive voltage based on the error mode information.

[0183] In Figures 21A to 21F a rectangle indicates that an error is associated with the corresponding bit.

[0184] Referring to Figures 21A to 21F , the control logic circuit 210 controls the voltage generator 700 to adjust the voltage level of at least one of the first drive voltage group, the second drive voltage group, and the precharge voltage VBL based on the error mode information EPI stored in the EPIR 580. The first drive voltage group may include the first power supply voltage VINTA1 and the ground voltage VSS provided to the sense amplifier circuit 281, and the second drive voltage group may include the second power supply voltage VINTA2 and the negative voltage VBB2 provided to the latch circuit 283.

[0185] Referring to Figure 21A and Figure 21B , if the error mode information EPI indicates that the error is associated with the second bit in each data read from the target page, the control logic circuit 210 may control the voltage generator 700 to adjust the voltage level of the first power supply voltage VINTA1. If each data read from the target page includes a first bit and a second bit having different logic levels, and if the error mode information EPI indicates that the error is associated with the second bit, the control logic circuit 210 may control the voltage generator 700 to raise the voltage level of the first power supply voltage VINTA1. If each data read from the target page includes a first bit and a second bit having the same logic level, and if the error mode information EPI indicates that the error is associated with the second bit, the control logic circuit 210 may control the voltage generator 700 to reduce the voltage level of the first power supply voltage VINTA1.

[0186] In Figures 21A to 21FIn the error pattern, an example of a multi-bit data with two bits is given: the first bit at the leftmost bit position and the second bit at the rightmost bit position. For example, in Figure 21A for the multi-bit values 10 and 01, the error trend is associated with the second bit position. For the multi-bit value 10, the leftmost bit is 1. For the multi-bit value 01, the leftmost bit is 0. For many memory cells, the first bit or the first bit position can be referred to as "a first bit", which usually represents the leftmost bit position. Similarly, for many memory cells, the second bit or the second bit position can be referred to as "a second bit", which usually represents the rightmost bit position.

[0187] Referring to Figure 21C and Figure 21D , if the error pattern information EPI indicates that the error is associated with the bits having the same logic level in the first bit and the second bit of each data read from the target page, the control logic circuit 210 can control the voltage generator 700 to adjust the voltage level of the precharge voltage VBL. If the error pattern information EPI indicates that the error is associated with the bits having a logic high level in the first bit and the second bit, the control logic circuit 210 can control the voltage generator 700 to lower the voltage level of the precharge voltage VBL. If the error pattern information EPI indicates that the error is associated with the bits having a logic low level in the first bit and the second bit, the control logic circuit 210 can control the voltage generator 700 to raise the voltage level of the precharge voltage VBL.

[0188] Referring to Figure 21E and Figure 21F , if the error pattern information EPI indicates that the error is associated with all combinations of the first bit and the second bit of each data read from the target page, the control logic circuit 210 can control the voltage generator 700 to adjust the voltage level of the second power supply voltage VINTA2 and the voltage level of the negative voltage VBB2. If the first bit and the second bit of the data have the same logic level and if the error pattern information EPI indicates that the error is associated with the second bit, and if the first bit and the second bit of the data have different logic levels and if the error pattern information EPI indicates that the error is associated with the first bit, the control logic circuit 210 can control the voltage generator 700 to raise the voltage level of the second power supply voltage VINTA2 and the voltage level of the negative voltage VBB2. If the first bit and the second bit of the data have the same logic level and if the error pattern information EPI indicates that the error is associated with the first bit, and if the first bit and the second bit of the data have different logic levels and if the error pattern information EPI indicates that the error is associated with the second bit, the control logic circuit 210 can control the voltage generator 700 to lower the voltage level of the second power supply voltage VINTA2 and the voltage level of the negative voltage VBB2.

[0189] Thus, by adjusting the first drive voltage set of the sense amplifier circuit 281, the second drive voltage set of the latch circuit 283, and Figure 3 the precharge voltage VBL shown in

[0190] the operation margin of the semiconductor memory device is increased. The increase in the operation margin means that the semiconductor memory device can store data at a higher density (multiple bits per memory cell) with improved reliability. The improved reliability means a reduced error rate of the data read from the memory device for use by another device. Figures 21A to 21F By identifying the relationships between error patterns (see Figures 7A to 7K above), adjusting the drive voltages, and sensing and restoring data (e.g., see Figure 8 and Figure 20 ), improvements are obtained.

[0191] Figure 22 shows an example of a memory cell array in a semiconductor memory device according to an example embodiment of Figure 2 .

[0192] Referring to Figure 22 , in the memory cell array 300b, I sub-array blocks SCB can be set in the second direction D2, and J sub-array blocks SCB can be set in the first direction D1 that is substantially perpendicular to the second direction D2. Multiple bit lines, multiple word lines, and multiple memory cells can be set in each sub-array block SCB.

[0193] I + 1 sub-word line driver regions SWB can be set between the sub-array blocks SCB along the second direction D2. Sub-word line drivers can be set in the sub-word line driver regions SWB. J + 1 bit line sense amplifier regions BLSAB can be set, for example, between the sub-array blocks SCB along the first direction D1. Bit line sense amplifiers for sensing data stored in the memory cells can be set in the bit line sense amplifier regions BLSAB.

[0194] Multiple coupling regions CONJ can be set adjacent to the sub-word line driver regions SWB and the bit line sense amplifier regions BLSAB. Voltage generators are set in each coupling region CONJ.

[0195] A portion 390 of the memory cell array 300b will be described in Figure 23 .

[0196] Figure 23 shows a portion of a memory cell array according to an example embodiment of Figure 22 .

[0197] Referring to Figure 22 and Figure 23, in a portion 390 of the memory cell array 300b ( Figure 22 ), a sub-array block SCB, a bit line sense amplifier region BLSAB, a sub-word line driver region SWB, and a coupling region CONJ are provided. Voltage generators (VG) 610, 620, 630, and 640 may be respectively provided in the coupling region CONJ. The sub-array block SCB includes a plurality of word lines WL1 - WL4 extending in the row direction (second direction D2) and a plurality of bit line pairs BL1 - BL2 and BLB1 - BL2 extending in the column direction (first direction D1). The sub-array block SCB includes a plurality of memory cells MC provided at intersections between the word lines WL1 - WL4 and the bit line pairs BL1 - BL2 and BLB1 - BL2.

[0198] Continuing to refer to Figure 23 , the sub-word line driver region SWB includes a plurality of sub-word line drivers (SWD) 571, 572, 573, and 574 that respectively drive the word lines WL1 - WL4. The sub-word line drivers 571 and 572 may be provided in the sub-word line driver region SWB located on the left side of the sub-array block SCB (in this example). Additionally, the sub-word line drivers 573 and 574 may be provided in the sub-word line driver region SWB located on the right side of the sub-array block SCB (in this example).

[0199] The bit line sense amplifier region BLSAB includes bit line sense amplifiers BLSA 650 and 650a respectively coupled to the bit line pairs BL1 and BLB1, and BL2 and BLB2, and local sense amplifier (LSA) circuits 680 and 690. The bit line sense amplifier 650 may sense and amplify the voltage difference between the bit line pair BL and BLB to provide the amplified voltage difference to the local I / O line pairs LIO1 and LIOB1.

[0200] The local sense amplifier circuit 680 controls the connection between the local I / O line pairs LIO1 and LIOB1 and the global I / O line pairs GIO1 and GIOB1, and the local sense amplifier circuit 690 controls the connection between the local I / O line pairs LIO2 and LIOB2 and the global I / O line pairs GIO2 and GIOB2.

[0201] Each of the bit line sense amplifiers BLSA 650 and 650a may employ Figure 5 the sense amplifier 280, and each of the voltage generators 610, 620, 630, and 640 may employ Figure 18 the voltage generator 700.

[0202] Figure 24 is a circuit diagram showing an example of a bit line sense amplifier that can be used as one of the bit line sense amplifiers in Figure 23 .

[0203] Referring to Figure 24 , the bit line sense amplifier 650b can be coupled to the bit lines BL1 and BLB1 of each of the memory cells 660 and 670 in the memory cell array 300b. The memory cell 660 can correspond to the memory cell MC at the intersection of the bit line BL1 and the word line WL1 in the sub-array block SCB, and the memory cell 670 can correspond to the memory cell MC at the intersection of the bit line BLB1 and the word line WL2 in the sub-array block SCB. The bit line sense amplifier 650b includes an N-type sense amplifier 651, a P-type sense amplifier 652, a precharge circuit 653, column selection switches 654a and 654b, an N-type sense amplifier (NSA) driver 655, and a P-type sense amplifier (PSA) driver 656.

[0204] The N-type sense amplifier 651 discharges the low-level bit line of the bit lines (or bit line pair) BL1 and BLB1 to a low level during the sensing operation. The N-type sense amplifier 651 includes two n-channel metal oxide semiconductor (NMOS) transistors NM1 and NM2. The gate of the NMOS transistor NM1 is connected to the bit line (second bit line) BLB1, the drain of the NMOS transistor NM1 is connected to the bit line (first bit line) BL1, and the source of the NMOS transistor NM1 is connected to the sense enable line LAB. The NMOS transistor NM2 has a gate connected to the bit line BL1, a drain connected to the sense enable line LAB, and a source connected to the bit line BLB1. The N-type sense amplifier 651 connects the low-level bit line to the sense enable line LAB. The sense enable line LAB is connected to the ground voltage VSS.

[0205] The N-type sense amplifier 651 discharges the low-level bit line in the bit lines BL1 and BLB1 with the ground voltage VSS provided at the sense enable line LAB.

[0206] The P-type sense amplifier 652 charges the high-level bit line in the bit lines BL1 and BLB1 with the power supply voltage VDD during the sensing operation. The P-type sense amplifier 652 includes two p-channel metal oxide semiconductor (PMOS) transistors PM1 and PM2. The PMOS transistor PM1 has a gate connected to the bit line BLB1, a source connected to the bit line BL1, and a drain connected to the sense enable line LA. The PMOS transistor PM2 has a gate connected to the bit line BL1, a source connected to the sense enable line LA, and a drain connected to the bit line BLB1.

[0207] The P-type sense amplifier 652 charges the high-level bit line in the bit lines BL1 and BLB1 with the power supply voltage VDD provided to the sense enable line LA.

[0208] The PSA driver 656 supplies the power supply voltage VDD to the sense enable line LA. Thus, since the gate of the transistor PM2 is coupled to the bit line BL1 having a voltage raised by charge sharing, the transistor PM2 is turned off.

[0209] The precharge circuit 653 precharges the bit lines BL1 and BLB1 to half the power supply voltage VDD / 2 in response to the control signal PEQ during the sensing operation. When the control signal PEQ is activated, the precharge circuit 653 supplies the precharge voltage VBL to the bit lines BL1 and BLB1. The precharge voltage VBL may be half the power supply voltage VDD / 2. The bit lines BL1 and BLB1 are connected such that their voltages are equal. If the bit lines BL1 and BLB1 are charged with the precharge voltage VBL, the control signal PEQ is deactivated. The precharge circuit 653 includes NMOS transistors N3, N4, and N5.

[0210] The column selection switches 654a and 654b supply the data sensed by the N-type sense amplifier 651 and the P-type sense amplifier 652 to the local I / O line pair LIO1 and LIOB1 in response to the column selection signal CSL. The column selection switches 654a and 654b are turned on so that the sensed data is transferred to the local I / O line pair LIO1 and LIOB1. For example, in a read operation, when the sense levels of the N-type sense amplifier 651 and the P-type sense amplifier 652 are stable, the column selection signal CSL is activated. Then, the column selection switches 654a and 654b are turned on so that the sensed data is transferred to the local I / O line pair LIO1 and LIOB1. When the charges of the bit lines BL1 and BLB1 are shared with the local I / O line pair LIO1 and LIOB1, the voltages of the bit lines BL1 and BLB1 change. The column selection switches 654a and 654b include NMOS transistors N6 and N7, respectively.

[0211] The NSA driver 655 supplies a drive signal to the sense enable line LAB of the N-type sense amplifier 651. The NSA driver 655 receives the control signal LANG from the control logic circuit 210. Based on the control signal LANG, the NSA driver 655 grounds the sense enable line LAB. The NSA driver 655 includes a grounding transistor N1 for controlling the voltage of the sense enable line LAB. The PSA driver 656 supplies the charging voltage VINTA to the sense enable line LA of the P-type sense amplifier 652. The PSA driver 656 is controlled by the control signal LAPG from the control logic circuit 210. The control signals LAPG and LANG are complementary to each other. The control logic circuit 210 may control the voltage generator 610 based on the error mode information EPI to adjust the voltage level of the charging voltage VINTA.

[0212] Figure 25It is a flowchart showing a method of operating a semiconductor memory device according to an exemplary embodiment.

[0213] Referring to Figures 2 to 25 , a method of operating a semiconductor memory device is provided. The semiconductor memory device includes a memory cell array 300, which includes a plurality of memory cells coupled to word lines and bit lines, and a plurality of sense amplifiers 280 for sensing data stored in the plurality of memory cells. In this method, data (codeword) is read from a target page of the memory cell array 300 (S210). The ECC engine 400 generates error information by performing ECC decoding on the read data (S220). The control logic circuit 210 controls at least one voltage generator 700 to adjust the voltage level of the driving voltage based on error pattern information EPI including the error information (S230). The voltage generator 700 supplies the driving voltage to the sense amplifiers 280. The voltage generator 700 applies the adjusted driving voltage to at least some of the sense amplifiers 280 to sense / recover data (S240).

[0214] According to an exemplary embodiment of the present disclosure, the control logic circuit generates error pattern information by accumulating error information obtained from the result of ECC decoding, and the control logic circuit controls the voltage generator based on the error pattern information to adjust the voltage level of the driving voltage supplied to the sense amplifier, so that the operating margin of the sense amplifier can be increased. Therefore, the performance of the semiconductor memory device can be improved.

[0215] Figure 26 It is a block diagram showing a semiconductor memory device according to an exemplary embodiment.

[0216] Referring to Figure 26 , the semiconductor memory device 800 may include a first group of dies 810 and a second group of dies 820.

[0217] The first group of dies 810 may include at least one buffer or logic die 811. The second group of dies 820 may include a plurality of memory dies 820-1 to 820-p stacked on the buffer die 811 and transmitting data through a plurality of through-substrate via lines (e.g., through-silicon via (TSV) lines). At least one of the memory dies 820-1 to 820-p may include a voltage generator (VG) 823 and a cell core 822, which includes a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines, and sense amplifiers.

[0218] The buffer die 811 may include an ECC engine 812 and an error pattern information register (EPIR) 813. When a transmission error is detected in the transmission data received via the TSV lines, the ECC engine 812 corrects the transmission error using the transmission parity bits and generates error-corrected data, and the error pattern information register 813 stores error pattern information associated with the error pattern of the error. The ECC engine 812 may employ Figure 12 the ECC engine 400, and the error pattern information register 813 may employ Figure 17 the EPIR 580.

[0219] The semiconductor memory device 800 may be a stacked chip type memory device or a stacked memory device that transmits data and control signals via TSV lines. The TSV lines may also be referred to as "through electrodes".

[0220] The transmission error that occurs at the transmission data may be caused by the noise that occurs at the TSV lines. Since the data failure caused by the noise that occurs at the TSV lines can be distinguished from the data failure caused by the malfunction of the memory die, it can be regarded as a soft data failure (or soft error). The soft data failure may be caused by the transmission failure on the transmission path and can be detected and corrected by the ECC operation.

[0221] The data TSV line group 832 formed at one memory die 820-p may include TSV lines L1 to Lp, and the parity check TSV line group 834 may include TSV lines L10 to Lq. The TSV lines L1 to Lp in the data TSV line group 832 and the parity check TSV lines L10 to Lq in the parity check TSV line group 834 may be connected to the microbumps MCB formed correspondingly between the memory dies 820-1 to 820-p.

[0222] The semiconductor memory device 800 may have a three-dimensional (3D) chip structure or a 2.5D chip structure that communicates with a host via a data bus B10. The buffer die 810 may be connected to the memory controller 100 via the data bus B10.

[0223] Aspects of the present disclosure may be applied to a system using a semiconductor memory device employing DRAM cells and an ECC engine.

[0224] The foregoing is an illustration of example embodiments and should not be construed as a limitation of the example embodiments. Although some example embodiments have been described, those skilled in the art will readily recognize that many modifications can be made to the example embodiments without substantially departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined by the claims.

Claims

1. A semiconductor memory device, comprising: A memory cell array including a plurality of memory cells coupled to word lines and bit lines, and a plurality of sense amplifiers configured to sense data stored in the plurality of memory cells, wherein each of the plurality of memory cells stores multi-bit data; An error correction code engine configured to: Read stored data from a target page of the memory cell array, Perform error correction code decoding on the stored data, Detect an error in the stored data based on the error correction code decoding, and Output error pattern information indicating an error pattern of the multi-bit data; At least one voltage generator configured to provide drive voltages to the plurality of sense amplifiers respectively; and A control logic circuit configured to: Control the error correction code engine, and Based on the error pattern information, control the at least one voltage generator to increase an operation margin of each of the plurality of sense amplifiers, wherein the error correction code engine is further configured to: Apply a first charge sharing operation to a first sense amplifier among the plurality of sense amplifiers to read a first bit from a first memory cell of the target page, wherein the first charge sharing operation is performed based on the increased operation margin, Apply a second charge sharing operation to the first sense amplifier to read a second bit from the first memory cell of the target page, and Apply a third charge sharing operation to the first sense amplifier to restore the first bit and the second bit to the first memory cell of the target page.

2. The semiconductor memory device according to claim 1, Among them, The error correction code engine is further configured to generate the error pattern information indicating the error pattern of the multi-bit data, and wherein the control logic circuit is further configured to: Record the error pattern information, and Based on the error pattern information, control the at least one voltage generator to adjust a voltage level of the drive voltage.

3. The semiconductor memory device according to claim 2, wherein, The first sense amplifier among the plurality of sense amplifiers is coupled to a bit line and a complementary bit line of the first memory cell among the plurality of memory cells, and the bit line is associated with the multi-bit data of the first memory cell, wherein the first sense amplifier includes: A sense amplifier circuit configured to: Receive a first set of drive voltages among the drive voltages, and Based on the first set of drive voltages, sense the first bit of the multi-bit data of the first memory cell and the second bit of the multi-bit data of the first memory cell; and A latch circuit configured to: Receive a second set of drive voltages among the drive voltages, Receive the first bit of the multi-bit data of the first memory cell from the sense amplifier circuit, and Based on the second set of drive voltages, store the first bit of the multi-bit data of the first memory cell. Wherein, the control logic circuit is further configured to: based on the error mode information, control the at least one voltage generator to adjust at least one of a first voltage level of the first driving voltage group, a second voltage level of the second driving voltage group, or a pre-charge voltage, wherein the pre-charge voltage is configured to pre-charge the bit line and the complementary bit line, and Wherein, for each memory cell of the target page, the stored data includes a first bit and a second bit.

4. The semiconductor memory device according to claim 3, wherein, The control logic circuit is further configured to: based on the error mode information indicating an error trend and the error trend being associated with the one second bit in each of the stored data, control the at least one voltage generator to adjust the first voltage level of the first driving voltage group, and Wherein, the first voltage level is a first power supply voltage.

5. The semiconductor memory device according to claim 4, wherein The control logic circuit is further configured to: based on the error mode information indicating that the error trend is associated with the one second bit and the one first bit not having the same logic level as the one second bit, control the at least one voltage generator to increase the first voltage level of the first driving voltage group.

6. The semiconductor memory device according to claim 4, wherein, The control logic circuit is further configured to: based on the error mode information indicating that the error trend is associated with the one second bit and the one first bit having the same logic level as the one second bit, control the at least one voltage generator to decrease the first voltage level of the first driving voltage group.

7. The semiconductor memory device according to claim 3, wherein, The control logic circuit is further configured to: based on the error mode information indicating that the error trend is associated with the one first bit and the one second bit having the same logic level, control the at least one voltage generator to adjust the pre-charge voltage.

8. The semiconductor memory device according to claim 7, wherein, The control logic circuit is further configured to: based on the error mode information indicating that the error trend is associated with the one first bit and the one second bit both having a high logic level, control the at least one voltage generator to decrease the pre-charge voltage.

9. The semiconductor memory device according to claim 7, wherein, The control logic circuit is further configured to: based on the error mode information indicating that the error trend is associated with the one first bit and the one second bit having a low logic level, control the at least one voltage generator to increase the pre-charge voltage.

10. The semiconductor memory device according to claim 3, wherein The control logic circuit is further configured to: based on the error mode information indicating that the error trend is associated with all combinations of the one first bit and the one second bit, control the at least one voltage generator to adjust the second voltage level of the second driving voltage group and a third voltage level of a negative voltage, and Wherein, the second voltage level is a second power supply voltage, and the negative voltage is applied to a signal node of the latch circuit.

11. The semiconductor memory device according to claim 10, wherein, The control logic circuit is further configured to control the at least one voltage generator to increase the second voltage level of the second drive voltage group and increase the third voltage level of the negative voltage based on the one first bit and the one second bit having the same logic level and the error mode information indicating that the error trend is associated with the one second bit, or based on the one first bit and the one second bit having different logic levels and the error mode information indicating that the error trend is associated with the one first bit.

12. The semiconductor memory device according to claim 10, wherein The control logic circuit is further configured to control the at least one voltage generator to decrease the second voltage level of the second drive voltage group and decrease the third voltage level of the negative voltage based on the one first bit and the one second bit having the same logic level and the error mode information indicating that the error trend is associated with the one first bit, or based on the one first bit and the one second bit having different logic levels and the error mode information indicating that the error trend is associated with the one second bit.

13. The semiconductor memory device according to claim 3, wherein, The control logic circuit is further configured to control the at least one voltage generator to increase the sensing tolerance for sensing the first bit and the second bit based on the first sense amplifier sensing the first bit of the multi-bit data of the first memory cell and the second bit of the multi-bit data of the first memory cell, based on the error mode information.

14. The semiconductor memory device according to claim 3, wherein The first sense amplifier is configured to perform a recovery operation of writing a cell voltage corresponding to the first bit of the multi-bit data of the first memory cell to the first memory cell, and wherein the control logic circuit is further configured to control the at least one voltage generator to increase the difference between the second power supply voltage and the third voltage level of the drive voltage used by the first sense amplifier in the recovery operation.

15. The semiconductor memory device according to claim 14, wherein, The first sense amplifier is further configured to perform the recovery operation by combining the most significant bit and the least significant bit, the most significant bit corresponding to the first bit of the multi-bit data of the first memory cell latched into the latch circuit, and the least significant bit corresponding to the second bit of the multi-bit data of the first memory cell sensed by the sense amplifier circuit.

16. The semiconductor memory device according to claim 1, wherein the semiconductor memory device further comprises: a cleaning control circuit configured to generate a cleaning address for performing a cleaning operation, wherein the error correction code engine is further configured to perform the cleaning operation based on the cleaning address, and wherein the control logic circuit is further configured to control the error correction code engine to perform the cleaning operation on a sub-page associated with the error.

17. A semiconductor memory device, comprising: a memory cell array, the memory cell array comprising: a plurality of memory cells coupled to word lines and bit lines, each of the plurality of memory cells storing multi-bit data, and a plurality of sense amplifiers configured to sense the multi-bit data; An error correction code engine, the error correction code engine being configured to: Read stored data from a target page of the memory cell array, Perform error correction code decoding on the stored data, Based on the error correction code decoding, generate error pattern information indicating an error pattern of the multi-bit data, and Output the error pattern information; At least one voltage generator, the at least one voltage generator being configured to supply drive voltages to the plurality of sense amplifiers respectively; and A control logic circuit, the control logic circuit being configured to: Control the error correction code engine, Based on the error pattern information, control the at least one voltage generator to increase an operation margin of each of the plurality of sense amplifiers, Record the error pattern information, and Based on the error pattern information, control the at least one voltage generator to adjust a voltage level of the drive voltage, wherein the error correction code engine is further configured to: Apply a first charge sharing operation to a first sense amplifier among the plurality of sense amplifiers to read a first bit of the multi-bit data from a first memory cell of the target page, wherein the first charge sharing operation is performed based on the increased operation margin, Apply a second charge sharing operation to the first sense amplifier to read a second bit of the multi-bit data from the first memory cell of the target page, and Apply a third charge sharing operation to the first sense amplifier to restore the first bit and the second bit to the first memory cell of the target page.

18. The semiconductor memory device according to claim 17, wherein, The first sense amplifier among the plurality of sense amplifiers is coupled to a bit line and a complementary bit line of the first memory cell among the plurality of memory cells, and the bit line is associated with the multi-bit data of the first memory cell, wherein the first sense amplifier includes: A sense amplifier circuit, the sense amplifier circuit being configured to: Receive a first set of drive voltages among the drive voltages, and Based on the first set of drive voltages, sense the first bit of the multi-bit data of the first memory cell and the second bit of the multi-bit data of the first memory cell; and A latch circuit, the latch circuit being configured to: Receive a second set of drive voltages among the drive voltages, Receive the first bit of the multi-bit data of the first memory cell from the sense amplifier circuit, and Based on the second set of drive voltages, store the first bit of the multi-bit data of the first memory cell, wherein the control logic circuit is further configured to: based on the error pattern information, control the at least one voltage generator to adjust a voltage level of at least one of the first set of drive voltages, the second set of drive voltages, or a precharge voltage, wherein the precharge voltage is configured to precharge the bit line and the complementary bit line.

19. A method of operating a semiconductor memory device, the method comprising: Read stored data from a target page of a memory cell array of the semiconductor memory device, the memory cell array including a plurality of memory cells coupled to word lines and bit lines and a plurality of sense amplifiers configured to sense data stored in the plurality of memory cells, wherein each of the plurality of memory cells stores multiple bits of data; Perform error correction code decoding on the stored data by an error correction code engine of the semiconductor memory device; Generate error pattern information by the error correction code engine based on the error correction code decoding, wherein the error pattern information indicates an error pattern of the multiple bits of data; Control at least one voltage generator by a control logic circuit of the semiconductor memory device to adjust a voltage level of a drive voltage based on the error pattern information, wherein the at least one voltage generator is configured to supply the drive voltage to the plurality of sense amplifiers; Sense the stored data by applying the drive voltage to at least some of the plurality of sense amplifiers; and Restore the stored data by applying the drive voltage to at least some of the plurality of sense amplifiers, wherein reading the stored data includes: Applying a first charge sharing operation to a first sense amplifier of the plurality of sense amplifiers to read a first bit from a first memory cell of the target page, wherein the first charge sharing operation is performed based on an increased operation margin; Applying a second charge sharing operation to the first sense amplifier to read a second bit from the first memory cell of the target page; and Applying a third charge sharing operation to the first sense amplifier to restore the first bit and the second bit to the first memory cell of the target page.

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