Display device

Abstract

The present disclosure relates to a display device, which includes: pixels; a first scan line connected to the pixels so as to supply a first scan signal to the pixels at a second frequency corresponding to an image refresh rate of the pixels; a second scan line connected to the pixels so as to supply a second scan signal different from the first scan signal to the pixels at the second frequency; a third scan line connected to the pixels so as to supply a third scan signal to the pixels at the first frequency; an emission control line connected to the pixels so as to supply an emission control signal to the pixels at the first frequency; and a data line connected to the pixels so as to supply a data signal to the pixels based on the second frequency.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0091290 filed on Jul. 26, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The inventive concept relates to a display device, and more particularly, to a display device applied to various driving frequencies. Background Art

[0004] With the development of information technology, the importance of display devices as a connecting medium between users and information is being emphasized.

[0005] The display device includes a plurality of pixels. Each pixel includes a plurality of transistors, a light-emitting element, and a capacitor, and the light-emitting element is electrically connected to the transistor. The transistor is turned on in response to a signal supplied through a signal line, thereby generating a certain driving current. The light-emitting element emits light in response to the driving current.

[0006] Recently, in order to improve the driving efficiency of a display device and minimize its power consumption, a method of driving a display device at a low frequency has been used. Therefore, there is a need for a method capable of improving display quality when driving a display device at a low frequency. Summary of the invention

[0007] Exemplary embodiments of the inventive concept provide a display device driven at various driving frequencies.

[0008] However, it should be understood that the purpose of the inventive concept may not be limited to the aforementioned purpose, but may be variously extended without departing from the spirit and scope of the inventive concept.

[0009] A display device according to an exemplary embodiment of the present invention includes: pixels connected to a first scan line, a second scan line, a third scan line, an emission control line, and a data line; a scan driver that supplies a bias scan signal to each of the third scan lines at a first frequency, and supplies a scan signal to each of the first scan line and the second scan line at a second frequency corresponding to an image refresh rate of each of the pixels; an emission driver that supplies an emission control signal to each of the emission control lines at the first frequency; a data driver that supplies a data signal to each of the data lines at the second frequency; and a timing controller that controls driving of the scan driver, the emission driver, and the data driver.

[0010] According to an exemplary embodiment, the first frequency may be greater than the second frequency.

[0011] According to an exemplary embodiment, the second frequency may correspond to a proper divisor of the first frequency.

[0012] According to an exemplary embodiment, the first frequency corresponds to twice a maximum refresh rate of the display device.

[0013] According to an exemplary embodiment, the emission driver may supply the emission control signal to each of the emission control lines at the first frequency, the first frequency being twice the maximum refresh rate of the display device.

[0014] According to an exemplary embodiment, the scan driver may include: a first scan driver, which supplies a write scan signal to the first scan line at the second frequency; a second scan driver, which supplies a compensation scan signal to the second scan line at the second frequency; and a third scan driver, which supplies a bias scan signal to the third scan line at the first frequency.

[0015] According to an exemplary embodiment, the first scan driver and the second scan driver may supply the write scan signal and the compensation scan signal during a display scan period in one frame period. The first scan driver and the second scan driver may not supply the write scan signal and the compensation scan signal during a self scan period in the one frame period. The data signal may be written into the pixel in the display scan period, and the third scan driver may supply the bias scan signal in the self scan period so that a bias may be applied to a driving transistor included in each of the pixels.

[0016] According to an exemplary embodiment, when the pixel is driven at a maximum refresh rate, the number of repetitions of the display scanning period may be the same as the number of repetitions of the self scanning period.

[0017] According to an exemplary embodiment, when the image refresh rate decreases, the number of the self-scanning cycles may increase.

[0018] According to an exemplary embodiment, the emission driver may include: a first emission driver which supplies a first emission control signal to a first emission control line connected to the pixel at the first frequency; and a second emission driver which supplies a second emission control signal to a second emission control line connected to the pixel at the first frequency.

[0019] According to an exemplary embodiment, each pixel located in the i-th horizontal line of the pixels may include: a light emitting element including a first electrode and a second electrode connected to a second power supply; a first transistor including a first electrode connected to a first node and controlling a driving current based on a voltage of a second node, the first node being electrically connected to the first power supply; a second transistor connected between a data line and the first node and turned on by the write scan signal supplied to the i-th first scan line; a third transistor connected between a third node and the second node and turned on by the compensation scan signal supplied to the i-th second scan line, the second transistor of the first transistor being turned on by the compensation scan signal supplied to the i-th second scan line; an electrode connected to the third node; a fourth transistor, which is connected between the third node and the i-th first emission control line and is turned on by the bias scan signal supplied to the i-th third scan line; a fifth transistor, which is connected between the first power supply and the first node and is turned off by the first emission control signal supplied to the i-th first emission control line; a sixth transistor, which is connected to the third node and the first electrode of the light-emitting element and is turned off by the second emission control signal supplied to the i-th second emission control line; and a storage capacitor, which is connected between the first power supply and the second node, wherein i is a natural number.

[0020] According to an exemplary embodiment, each of the pixels located in the i-th horizontal line may further include: a seventh transistor connected between the first electrode of the light emitting element and an initialization power source and turned on by the first emission control signal or the second emission control signal.

[0021] According to an exemplary embodiment, each of the pixels located in the i-th horizontal line may further include an eighth transistor connected between the fifth transistor and the first node and turned off by the second emission control signal supplied to the i-th second emission control line.

[0022] According to example embodiments, the first transistor, the second transistor, the fourth transistor, the fifth transistor, and the sixth transistor may be p-type transistors, and the third transistor and the seventh transistor may be n-type oxide semiconductor transistors.

[0023] According to an exemplary embodiment, a turn-on period of the third transistor and a turn-on period of the fourth transistor may not overlap with each other.

[0024] According to an exemplary embodiment, each of the second scan driver, the third scan driver, the first emission driver, and the second emission driver may equally control pixels in the (2i-1)th horizontal line and pixels in the 2i-th horizontal line, and the first scan driver may control pixels in the (2i-1)th horizontal line and pixels in the 2i-th horizontal line at different times.

[0025] According to an exemplary embodiment, each of the pixels located in the i-th horizontal line of the pixels may include: a light emitting element including a first electrode and a second electrode connected to a second power supply; a first transistor including a first electrode connected to a first node and controlling a driving current based on a voltage of a second node, the first node being electrically connected to the first power supply; a second transistor connected between a data line and the first node and turned on by the write scan signal supplied to the i-th first scan line; a third transistor connected between a third node and the second node and turned on by the compensation scan signal supplied to the i-th second scan line, the third node being connected to the second electrode of the first transistor; and a fourth transistor turned on by the bias scan signal supplied to the i-th third scan line to apply a bias voltage to the first node, wherein i is a natural number. The first electrode of the fourth transistor may be connected to one of the i-th first scan line, the i-th first emission control line, the i-th second emission control line and the bias power supply, and the second electrode of the fourth transistor is connected to the first node.

[0026] According to an exemplary embodiment, the scan driver may further include a fourth scan driver which supplies an initialization scan signal to a fourth scan line at the second frequency.

[0027] According to an exemplary embodiment, each pixel located in the i-th horizontal line of the pixels may include: a light emitting element including a first electrode and a second electrode connected to a second power supply; a first transistor including a first electrode connected to a first node and controlling a driving current based on a voltage of a second node, the first node being electrically connected to the first power supply; a second transistor connected between a data line and the first node and turned on by the write scan signal supplied to the i-th first scan line; a third transistor connected between a third node and the second node and turned on by the compensation scan signal supplied to the i-th second scan line, the second electrode of the first transistor being connected to the third node; and a fourth transistor connected between the third node and the i-th emission control line or between the third node and a bias power supply. , and is turned on by the bias scan signal supplied to the i-th third scan line; a fifth transistor, which is connected between the first power supply and the first node, and is turned off by the first emission control signal supplied to the i-th emission control line; a sixth transistor, which is connected to the third node and the first electrode of the light-emitting element, and is turned off together with the fifth transistor; a seventh transistor, which is connected between the first electrode of the light-emitting element and the first initialization power supply, and is turned on by the emission control signal or the bias scan signal; an eighth transistor, which is connected between the second node and the second initialization power supply, and is turned on by the initialization scan signal supplied to the i-th fourth scan line; and a storage capacitor, which is connected between the first power supply and the second node, wherein i is a natural number.

[0028] According to an exemplary embodiment, after the fourth transistor is turned on, the eighth transistor may be turned on, and a turn-on period of the fourth transistor and a turn-on period of the eighth transistor may not overlap with each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a block diagram illustrating a display device according to an exemplary embodiment of the inventive concept.

[0030] Figure 2A It is shown Figure 1 A circuit diagram of an example of a pixel included in a display device.

[0031] Figure 2B It is shown Figure 2A A circuit diagram showing an example of a connection relationship of pixels.

[0032] Figure 2C It shows the supply to Figure 2B Conceptual diagram of the scanning signal and emission control signal of a pixel.

[0033] Figure 3A It is shown Figure 2B A timing diagram of an example of driving of a pixel.

[0034] Figure 3B It is shown Figure 2B A timing diagram of an example of driving of a pixel.

[0035] Figure 4 It shows that Figure 1 A timing diagram of an example of a driving method when a display device is driven at a first image refresh rate.

[0036] Figure 5 It shows that Figure 1 A timing diagram of an example of a driving method when a display device is driven at a second image refresh rate.

[0037] Fig. 6A It is shown Figure 2B A timing diagram of an example of driving of a pixel.

[0038] Figure 6B It is shown Figure 2B A timing diagram of another example of driving of a pixel.

[0039] Fig. 7A , Figure 7B , Figure 7C and Fig.7D is a timing diagram showing an example of a gate start pulse supplied to an emission driver and a scan driver included in a display device according to an image refresh rate.

[0040] Figure 8 is a conceptual diagram illustrating an example of a driving method of a display device according to an image refresh rate.

[0041] Fig. 9A , Fig. 9B , Fig. 9C and Fig.9D It is shown Figure 1 A circuit diagram of an example of a pixel included in a display device.

[0042] Fig. 10A and Fig. 10B It is shown Figure 1 A circuit diagram of an example of a pixel included in a display device.

[0043] Fig.11 is a block diagram illustrating a display device according to an exemplary embodiment.

[0044] Fig. 12A , Fig. 12B , Fig. 12C and Fig.12D It is shown Fig.11 A circuit diagram of an example of a pixel included in a display device.

[0045] Fig.13 It is shown FIG. 12A to FIG. 12D A timing diagram of an example of driving of a pixel.

[0046] Fig.14A , Fig. 14B , Fig. 14C and Fig.14D is a timing chart showing an example of a driving method of a display device according to an image refresh rate. DETAILED DESCRIPTION

[0047] Hereinafter, exemplary embodiments of the inventive concept will be described in more detail with reference to the accompanying drawings. The same reference numerals refer to the same elements throughout the description of the drawings, and the description of the same components will not be repeated.

[0048] Figure 1 is a block diagram illustrating a display device according to an exemplary embodiment of the inventive concept.

[0049] refer to Figure 1 , the display device 1000 includes a pixel unit 100 , scan drivers 200 , 300 and 400 , emission drivers 500 and 600 , and a timing controller 800 .

[0050] The scan drivers 200, 300, and 400 may include a first scan driver 200, a second scan driver 300, and a third scan driver 400. The emission drivers 500 and 600 may include a first emission driver 500 and a second emission driver 600. However, the classification of the scan driver and the emission driver is for convenience of description, and at least some of the scan drivers and the emission drivers may be integrated into one driving circuit, module, etc.

[0051] The display device 1000 can display images at various image refresh rates (driving frequency or screen refresh rate) according to driving conditions. The image refresh rate is the frequency at which a data signal is written to the driving transistor of the pixel PX. For example, the image refresh rate is called the screen refresh rate or screen refresh frequency, and refers to the number of times the display screen is updated with a new image per second.

[0052] In an exemplary embodiment, the image refresh rate corresponds to an output frequency of the data driver 700 and / or the first scan driver 200 outputting a write scan signal. For example, the refresh rate for driving a moving picture may be about 60 Hz or higher, such as a frequency of 120 Hz.

[0053] In an exemplary embodiment, the display device 1000 may adjust the output frequency of the first scan driver 200 and the second scan driver 300 and the output frequency of the data driver 700 corresponding to the image refresh rate according to the driving conditions. For example, the display device 1000 may display images in response to various image refresh rates of 1 Hz to 120 Hz. However, this is only an example, and the display device 1000 may display images even at an image refresh rate of 120 Hz or higher, such as 240 Hz or 480 Hz.

[0054] The timing controller 800 may receive input image data IRGB and timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a clock signal CLK from a host system such as an application processor (AP) or a graphic controller through some interface.

[0055] The timing controller 800 may generate a data drive control signal DCS based on the input image data IRGB and timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a clock signal CLK. The data drive control signal DCS may be supplied to the data driver 700. The timing controller 800 may transform the input image data IRGB into a visual output RGB for display on the display panel, and supply the visual output RGB to the data driver 700.

[0056] The timing controller 800 supplies gate start pulses GSP1 , GSP2 , and GSP3 and a clock signal CLK to the first to third scan drivers 200 , 300 , and 400 in response to the timing signal.

[0057] The timing controller 800 supplies the emission start pulses ESP1 and ESP2 and the clock signal CLK to the first emission driver 500 and the second emission driver 600 in response to the timing signal. The emission start pulses ESP1 and ESP2 control the rising edge or falling edge of the emission control signal. The clock signal CLK is used for synchronization of the emission start pulses ESP1 and ESP2.

[0058] The first gate start pulse GSP1 controls a rising edge or a falling edge of a scan signal (eg, a write scan signal) supplied from the first scan driver 200. The clock signal CLK is used for synchronization of the first gate start pulse GSP1.

[0059] The second gate start pulse GSP2 controls a rising edge or a falling edge of a scan signal (eg, a compensation scan signal) supplied from the second scan driver 300. The clock signal CLK is used for synchronization of the second gate start pulse GSP2.

[0060] The third gate start pulse GSP3 controls a rising edge or a falling edge of a scan signal (eg, a bias scan signal) supplied from the third scan driver 400. The clock signal CLK is used for synchronization of the third gate start pulse GSP3.

[0061] In an exemplary embodiment, the pulse width of at least one of the first to third gate start pulses GSP1 to GSP3 may be different. Therefore, the width of the corresponding scan signal may also be changed.

[0062] The data driver 700 supplies the data signal to the data line D in response to the data driving control signal DCS. The data signal supplied to the data line D is supplied to the pixel PX selected by the scan signal.

[0063] The data driver 700 supplies the data signal to the data line D during one frame period according to the image refresh rate. For example, the data driver 700 supplies the data signal to the data line D at the same frequency as the image refresh rate. In this case, the data signal supplied to the data line D may be supplied synchronously with the scan signal supplied to the first scan line S1.

[0064] The first scan driver 200 supplies a scan signal to the first scan line S1 in response to the first gate start pulse GSP1. For example, the first scan driver 200 may sequentially supply the scan signal to the first scan line S1. Here, the scan signal is set to have a gate-on voltage so that a plurality of transistors connected to the respective first scan lines are turned on.

[0065] In an exemplary embodiment, the scan signal supplied to the first scan line S1 may be a write scan signal. That is, when the write scan signal is supplied, the data signal may be supplied to the pixel PX.

[0066] The first scan driver 200 may supply a scan signal to the first scan line S1 at the same frequency (eg, second frequency) as the image refresh rate of the display device 1000. In an exemplary embodiment, the second frequency may correspond to an output frequency of the first gate start pulse GSP1 supplied from the timing controller 800 to the first scan driver 200.

[0067] The second frequency may be set to a true multiple of the first frequency for driving the transmit drivers 500 and 600 .

[0068] The first scan driver 200 supplies a scan signal to the first scan line S1 during a display scan period of one frame. For example, the first scan driver 200 may supply at least one scan signal to each first scan line S1 during the display scan period.

[0069] The second scan driver 300 supplies a scan signal to the second scan line S2 in response to the second gate start pulse GSP2. For example, the second scan driver 300 may sequentially supply the scan signal to the second scan line S2. Here, the scan signal supplied from the second scan driver 300 is set to have a gate-on voltage so that the transistor included in the pixel PX is turned on.

[0070] In an exemplary embodiment, the scan signal supplied to the second scan line S2 may be a compensation scan signal. That is, when supplied with the compensation scan signal, the driving transistor of the pixel PX may be connected in the form of a diode.

[0071] The second scan driver 300 may supply a scan signal to the second scan line S2 at the same frequency (eg, a second frequency) as the output frequency of the first scan driver 200. The second frequency may correspond to the output frequency of the second gate start pulse GSP2 supplied from the timing controller 800 to the second scan driver 300.

[0072] The second scan driver 300 supplies a scan signal to the second scan line S2 during a display scan period of one frame. In an example, the second scan driver 300 may supply at least one scan signal to each second scan line S2 during the display scan period.

[0073] The third scan driver 400 supplies a scan signal to the third scan line S3 in response to the third gate start pulse GSP3. In an example, the third scan driver 400 may sequentially supply the scan signal to the third scan line S3. Here, the scan signal is set to have a gate-on voltage so that the transistor included in the pixel PX is turned on.

[0074] In an exemplary embodiment, the scan signal supplied to the third scan line S3 may be a bias scan signal. That is, when the bias scan signal is supplied, a certain bias voltage is applied to the source electrode and / or drain electrode of the driving transistor of the pixel PX, and the driving transistor may be turned on and biased.

[0075] On the other hand, the third scan driver 400 may always supply the scan signal to the third scan line S3 at a constant first frequency regardless of the frequency of the image refresh rate of the display device 1000. Here, the first frequency may correspond to the output frequency of the third gate start pulse GSP3 supplied from the timing controller 800 to the third scan driver 400.

[0076] In addition, the first frequency at which the third scan driver 400 supplies the scan signal is greater than the image refresh rate. In one embodiment, the frequency (and the second frequency) of the image refresh rate can be set to a true factor of the first frequency. For example, the first frequency can be set to about twice the maximum refresh rate (maximum drive frequency) of the display device 1000. When the maximum refresh rate of the display device 1000 is 120 Hz, the first frequency can be set to 240 Hz. Therefore, within one frame period, the scan operation in which the scan signal is sequentially output to the third scan line S3 can be repeated multiple times at a certain period.

[0077] For example, the third scan driver 400 may perform scanning once during the display scanning period, and may perform scanning at least once during the self-scanning period according to the image refresh rate, at all driving frequencies at which the display device 1000 may be driven. That is, the scan signal may be sequentially output to the third scan line S3 once during the display scanning period, and may be sequentially output to the third scan line S3 at least once during the self-scanning period.

[0078] In addition, when the image refresh rate decreases, the number of times the third scan driver 400 supplies the scan signal to each third scan line S3 within one frame period may increase.

[0079] The first emission driver 500 supplies a first emission control signal to the first emission control line E1 in response to the first emission start pulse ESP1.

[0080] In an example, the first emission driver 500 may sequentially supply a first emission control signal to the first emission control line E1. When the first emission control signal is sequentially supplied to the first emission control line E1, the pixel PX connected to the first emission control line E1 does not emit light. To this end, the first emission control signal may be set to have a gate-off voltage (e.g., a logic high level) so that some transistors (e.g., p-type transistors) included in the pixel PX are turned off.

[0081] The second emission driver 600 supplies the second emission control signal to the second emission control line E2 in response to the second emission start pulse ESP2. In an example, the second emission driver 600 may sequentially supply the second emission control signal to the second emission control line E2. To this end, the second emission control signal may be set to have a gate-off voltage (e.g., a logic high level H) so that the p-type transistor included in the pixel PX that receives the second emission control signal is turned off.

[0082] In an exemplary embodiment, the second emission control signal supplied to the pixel PX may be a signal in which the first emission control signal is offset by a certain horizontal period (e.g., four horizontal periods). For example, the second emission control signal supplied to the i-th pixel row may have the same waveform as the first emission control signal supplied to the (i+5)-th pixel row (where i is a natural number). However, this is only an example, and the length of the second emission control signal may be less than the length of the first emission control signal.

[0083] In an exemplary embodiment, similar to the third scan driver 400, the first emission driver 500 and the second emission driver 600 may supply the first emission control signal and the second emission control signal to the first emission control line E1 and the second emission control line E2 at a first frequency. Therefore, within one frame period, the emission control signal may be supplied to the first emission control line E1 and the second emission control line E2 more than once.

[0084] Therefore, when the image refresh rate decreases, the number of times the first emission driver 500 and the second emission driver 600 supply the first emission control signal and the second emission control signal within one frame period may increase.

[0085] The pixel unit 100 is connected to the data line D, the scan lines S1, S2 and S3, and the emission control lines E1 and E2. The pixel PX may receive voltages of a first power source VDD, a second power source VSS, and an initialization power source Vint from the outside.

[0086] According to an exemplary embodiment of the inventive concept, the signal lines (scan lines S1, S2, S3, emission control lines E1, E2, and data lines D) connected to the pixel PX may be differently arranged according to the circuit structure of the pixel PX. For ease of description, the scan lines S1, S2, S3 may be collectively referred to as the i-th first scan line S1i, the i-th second scan line S2i, and the i-th third scan line S3i described below; the emission control lines E1 and E2 may be collectively referred to as the i-th first control line E1i and the second control line E2i described below; and the data line D may be collectively referred to as the j-th data line Dj described below.

[0087] Figure 2A It is shown Figure 1 A circuit diagram of an example of a pixel included in a display device.

[0088] For ease of description, Figure 2A The pixels 10 located in the i-th horizontal line and connected to the j-th data line Dj are shown.

[0089] refer to Figure 2A, the pixel 10 may include a light emitting element LD, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and a storage capacitor Cst.

[0090] A first electrode (anode electrode or cathode electrode) of the light emitting element LD is connected to the fourth node N4, and a second electrode (anode electrode or cathode electrode) of the light emitting element LD is connected to the second power supply VSS. The light emitting element LD generates light with a certain brightness corresponding to the amount of current supplied from the first transistor M1.

[0091] In an exemplary embodiment, the light emitting element LD may be an organic light emitting diode including an organic light emitting layer. In another exemplary embodiment, the light emitting element LD may be an organic light emitting diode made of an organic material. Alternatively, the light emitting element LD may have the following form: a plurality of inorganic light emitting elements are connected in parallel and / or in series between the second power source VSS and the fourth node N4.

[0092] A first electrode of the first transistor M1 (or the driving transistor) is connected to the first node N1, and a second electrode of the first transistor M1 is connected to the third node N3. A gate electrode of the first transistor M1 is connected to the second node N2. The first transistor M1 can control the amount of current flowing from the first power supply VDD to the second power supply VSS through the light emitting element LD in response to the voltage of the second node N2. To this end, the first power supply VDD can be set to have a voltage higher than the voltage of the second power supply VSS.

[0093] The second transistor M2 is connected between the jth data line Dj and the first node N1. The gate electrode of the second transistor M2 is connected to the i-th first scan line S1i. When the scan signal is supplied to the i-th first scan line S1i, the second transistor M2 is turned on to electrically connect the j-th data line Dj and the first node N1.

[0094] The third transistor M3 is connected between the second electrode of the first transistor M1 (ie, the third node N3 ) and the second node N2 .

[0095] The gate electrode of the third transistor M3 is connected to the i-th second scan line S2i. When the scan signal is supplied to the i-th second scan line S2i, the third transistor M3 is turned on to electrically connect the second electrode of the first transistor M1 and the second node N2. Therefore, when the third transistor M3 is turned on, the first transistor M1 is connected in the form of a diode.

[0096] In an exemplary embodiment, in a state where the second transistor M2 is turned off and the third transistor M3 is turned on, the voltage of the initialization power source Vint may be supplied to the gate electrode of the first transistor M1 through the third transistor M3 .

[0097] The fourth transistor M4 (bias scan transistor) is connected between the third node N3 and the i-th first emission control line E1i. The gate electrode of the fourth transistor M4 is connected to the i-th third scan line S3i. When the scan signal is supplied to the i-th third scan line S3i, the fourth transistor M4 is turned on to supply the voltage of the i-th first emission control line E1i to the third node N3. In this case, a gate-off voltage (logic high level voltage) can be supplied to the i-th first emission control line E1i. For example, the gate-off voltage has a level of about 5V to about 7V.

[0098] Therefore, by turning on the fourth transistor M4 , a certain high voltage may be applied to the drain electrode (and the source electrode) of the first transistor M1 , and the first transistor M1 may have an on-bias state (that is, be on-biased).

[0099] The fifth transistor M5 is connected between the first power supply VDD and the first node N1. The gate electrode of the fifth transistor M5 is connected to the i-th first emission control line E1i. When the emission control signal is supplied to the i-th first emission control line E1i, the fifth transistor M5 is turned off, and in other cases, the fifth transistor M5 is turned on.

[0100] The sixth transistor M6 is connected between the second electrode of the first transistor M1 (that is, the third node N3) and the first electrode of the light emitting element LD (that is, the fourth node N4). The gate electrode of the sixth transistor M6 is connected to the i-th second emission control line E2i. When the emission control signal is supplied to the i-th second emission control line E2i, the sixth transistor M6 is turned off, and in other cases, the sixth transistor M6 is turned on. Therefore, the turn-on time of the fifth transistor M5 and the sixth transistor M6 can partially overlap each other.

[0101] The seventh transistor M7 is connected between the first electrode of the light emitting element LD (that is, the fourth node N4) and the initialization power supply Vint. The gate electrode of the seventh transistor M7 is connected to the i-th first emission control line E1i. When the emission control signal is supplied to the i-th first emission control line E1i, the seventh transistor M7 is turned on to supply the voltage of the initialization power supply Vint to the first electrode of the light emitting element LD. The seventh transistor M7 can be a transistor of a type opposite to that of the fifth transistor M5. Therefore, when the fifth transistor M5 is turned off, the seventh transistor M7 is turned on.

[0102] However, this is merely an example, and the gate electrode of the seventh transistor M7 may be connected to the i-th second emission control line E2i.

[0103] When the voltage of the initialization power supply Vint is supplied to the first electrode of the light emitting element LD, the parasitic capacitor of the light emitting element LD may be discharged. Since the residual voltage charged in the parasitic capacitor is discharged (removed), unexpected micro-luminescence can be prevented. Therefore, the black display capability of the pixel 10 can be improved.

[0104] In low-frequency driving in which the length of one frame period increases, when a turn-on bias is applied to the first transistor M1 using a signal supplied from the j-th data line Dj by turning on the second transistor M2, a hysteresis difference caused by a grayscale level difference between adjacent pixels may be seriously generated. Therefore, an afterimage phenomenon (ghosting phenomenon) may occur due to a difference between threshold voltage shifts of driving transistors of adjacent pixels.

[0105] In the display device according to the exemplary embodiment of the inventive concept, by using the fourth transistor M4, the voltage for turning on the driving transistor bias can be applied to the drain electrode (and / or source electrode) of the driving transistor at a constant voltage. Therefore, the hysteresis deviation caused by the grayscale level difference between adjacent pixels can be eliminated, and thus the afterimage phenomenon can be reduced (eliminated).

[0106] The storage capacitor Cst is connected between the first power source VDD and the second node N2. The storage capacitor Cst may store a voltage applied to the second node N2.

[0107] At the same time, the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 can be formed as polycrystalline silicon semiconductor transistors. For example, the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 may include a polycrystalline silicon semiconductor layer as an active layer (channel), which is formed by a low temperature polysilicon process (LTPS). At the same time, the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 may be p-type transistors. Therefore, the gate-on voltage for turning on the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 may have a logic low level.

[0108] Since the polysilicon semiconductor transistor has a fast response speed, the polysilicon semiconductor transistor can be applied to switch elements that require fast switching.

[0109] The third transistor M3 and the seventh transistor M7 may be formed as oxide semiconductor transistors. For example, the third transistor M3 and the seventh transistor M7 may be n-type oxide semiconductor transistors and may include an oxide semiconductor layer as an active layer. Therefore, the gate-on voltage for turning on the third transistor M3 and the seventh transistor M7 may have a logic high level.

[0110] A low temperature process can be performed on the oxide semiconductor transistor, and the oxide semiconductor transistor has a low charge mobility compared to the polysilicon semiconductor transistor. That is, the oxide semiconductor transistor has excellent cut-off current characteristics. Therefore, when the third transistor M3 and the seventh transistor M7 are formed as oxide semiconductor transistors, the leakage current from the second node N2 can be minimized, thereby improving the display quality.

[0111] Figure 2B It is shown Figure 2A A circuit diagram showing an example of a connection relationship of pixels, and Figure 2C It shows the supply to Figure 2B Conceptual diagram of the scanning signal and emission control signal of a pixel.

[0112] refer to Figures 1 to 2C , the i-th pixel PXi located in the i-th pixel row (i-th horizontal line) can have a pixel structure that is basically the same as the (i+1)-th pixel PXi+1 located in the (i+1)-th pixel row ((i+1)-th horizontal line).

[0113] Assuming that the i-th pixel PXi and the (i+1)-th pixel PXi+1 are connected to the j-th data line Dj, the i-th pixel PXi and the (i+1)-th pixel PXi+1 will be described.

[0114] The i-th write scan signal GWi may be supplied to the i-th first scan line S1i, and the (i+1)-th write scan signal GWi+1 may be supplied to the (i+1)-th first scan line S1i+1. The (i+1)-th write scan signal GWi+1 may be a scan signal in which the i-th write scan signal GWi is shifted (delayed) by one horizontal period (1H).

[0115] The pth compensation scan signal GCp may be commonly supplied to the i-th second scan line S2i and the (i+1)-th second scan line S2i+1 (where p is a natural number). That is, the i-th pixel PXi and the (i+1)-th pixel PXi+1 may be commonly controlled by the same compensation scan signal GCp.

[0116] The pth bias scan signal Bp may be commonly supplied to the i-th third scan line S3i and the (i+1)-th third scan line S3i+1. That is, the i-th pixel PXi and the (i+1)-th pixel PXi+1 may be commonly controlled by the same bias scan signal Bp.

[0117] The pth first emission control signal EM1_p may be commonly supplied to the i-th first emission control line E1i and the (i+1)-th first emission control line E1i+1. That is, the i-th pixel PXi and the (i+1)-th pixel PXi+1 may be commonly controlled by the same first emission control signal EM1_p.

[0118] The pth second emission control signal EM2_p may be commonly supplied to the i-th second emission control line E2i and the (i+1)-th second emission control line E2i+1. That is, the i-th pixel PXi and the (i+1)-th pixel PXi+1 may be commonly controlled by the same emission control signal EM2_p.

[0119] In other words, each first scan line can be connected to each pixel in one pixel row and control the pixels in one pixel row, and the second scan line, the third scan line, the first emission control line and the second emission control line can be connected to each pixel in two adjacent pixel rows and control the pixels in two consecutive pixel rows. Therefore, high-speed driving of the display device 1000 with a driving frequency exceeding 60 Hz can be easily achieved.

[0120] In an exemplary embodiment, the first scan driver 200, the second scan driver 300, the third scan driver 400, the first emission driver 500, and the second emission driver 600 may have the following configurations: Figure 2C The output configuration shown in .

[0121] The i-th first scanning stage SST1_i included in the first scanning driver 200 may be connected to the i-th pixel row PXLi through the i-th first scanning line S1i. The (i+1)-th first scanning stage SST1_i+1 may be connected to the (i+1)-th pixel row PXLi+1 through the (i+1)-th first scanning line S1i+1. According to an exemplary embodiment, the first scanning driver 200 may be disposed at both sides of the pixel unit 100.

[0122] The p-th second scanning stage SST2_p included in the second scan driver 300 is connected to the i-th second scan line S2i and the (i+1)-th second scan line S2i+1. The p-th second scanning stage SST2_p may simultaneously supply the p-th compensation scan signal GCp to the i-th pixel row PXLi and the (i+1)-th pixel row PXLi+1 through the i-th second scan line S2i and the (i+1)-th second scan line S2i+1.

[0123] The p-th third scanning stage SST3_p included in the third scanning driver 400 is connected to the i-th third scanning line S3i and the (i+1)-th third scanning line S3i+1. The p-th third scanning stage SST3_p may simultaneously supply the p-th bias scanning signal Bp to the i-th pixel row PXLi and the (i+1)-th pixel row PXLi+1 through the i-th third scanning line S3i and the (i+1)-th third scanning line S3i+1.

[0124] The p-th first emission stage EST1_p included in the first emission driver 500 is connected to the i-th first emission control line E1i and the (i+1)-th first emission control line E1i+1. The p-th first emission stage EST1_p may simultaneously supply the p-th first emission control signal EM1_p to the i-th pixel row PXLi and the (i+1)-th pixel row PXLi+1 through the i-th first emission control line E1i and the (i+1)-th first emission control line E1i+1.

[0125] The p-th second emission stage EST2_p included in the second emission driver 600 is connected to the i-th second emission control line E2i and the (i+1)-th second emission control line E2i+1. The p-th second emission stage EST2_p can simultaneously supply the p-th second emission control signal EM2_p to the i-th pixel row PXLi and the (i+1)-th pixel row PXLi+1 through the i-th second emission control line E2i and the (i+1)-th second emission control line E2i+1.

[0126] Therefore, the second scan driver 300 and the third scan driver 400 may include fewer stage circuits than the first scan driver 200. Similarly, the first emission driver 500 and the second emission driver 600 may also include fewer stage circuits than the first scan driver 200.

[0127] Figure 3A It is shown Figure 2B A timing diagram of an example of driving of a pixel.

[0128] refer to Figure 2B and Figure 3A , the pixels PXi and PXi+1 may receive a signal for displaying an image during a display scanning period. The display scanning period may include a period in which a data signal Dm corresponding to an output image is written.

[0129] Hereinafter, for ease of description, the i-th emission control lines E1i and E2i may be the i-th first emission control line E1i and the i-th second emission control line E2i, respectively. The i-th scan lines S1i, S2i, and S3i may be the i-th first scan line S1i, the i-th second scan line S2i, and the i-th third scan line S3i, respectively.

[0130] First, the first emission control signal EM1_p is supplied to the i-th first emission control line E1i, and the compensation scan signal GCp is supplied to the i-th second scan line S2i. The first emission control signal EM1_p may be maintained from the first period P1 to the fourth period P4. The compensation scan signal GCp may be maintained from the first period P1 to the third period P3.

[0131] In the first period P1, the fifth transistor M5 is turned off and the seventh transistor M7 is turned on by the first emission control signal EM1_p having a logic high level H. In addition, the third transistor M3 is turned on by the compensation scan signal GCp having a logic high level H. Since the third transistor M3, the sixth transistor M6, and the seventh transistor M7 remain in a turned-on state in the first period P1, the voltage of the initialization power supply Vint can be supplied to the first electrode (the fourth node N4) of the light emitting element LD and the gate electrode (the second node N2) of the first transistor M1.

[0132] Therefore, in the first period P1 , initialization of the light emitting element LD and the first transistor M1 may be performed.

[0133] Meanwhile, the seventh transistor M7 may maintain a turned-on state until the fourth period P4 by the first emission control signal EM1_p having a logic high level H. Therefore, until the fourth period P4, the voltage of the initialization power source Vint may be supplied to the fourth node N4.

[0134] In the second period P2, the second emission control signal EM2_p having a logic high level H is supplied to the i-th second emission control line E2i. In an exemplary embodiment, before the fifth period P5 starts, the supply of the second emission control signal EM2_p may be stopped. The sixth transistor M6 is turned off by the second emission control signal EM2_p having a logic high level H.

[0135] In addition, in the second period P2, the write scan signals GWi and GWi+1 may be sequentially supplied to the first scan lines S1i and S1i+1. Therefore, the second transistor M2 may be turned on so that the i-th data signal DVi and the (i+1)-th data signal DVi+1 may be supplied to the i-th pixel PXi and the (i+1)-th pixel PXi+1, respectively.

[0136] Since the second transistor M2 is turned on in a state where the third transistor M3 is turned on, the first transistor M1 is diode-connected. That is, the second period P2 may be a data writing and threshold voltage compensation period.

[0137] In the third period P3, the second transistor M2 is turned off, and the third transistor M3 is kept in the on state. In the third period P3, since the third transistor M3 is turned on by the compensation scanning signal GCp having a logic high level H, the first transistor M1 is diode-connected. Therefore, the third period P3 is a threshold voltage compensation period, and sufficient time for compensating the threshold voltage in high-speed driving can be ensured.

[0138] Thereafter, when supply of the compensation scan signal GCp to the i-th second scan line S2i is stopped, the third transistor M3 may be turned off.

[0139] In the fourth period P4, the bias scan signal Bp may be supplied to the i-th third scan line S3i. The fourth transistor M4 may be turned on by the bias scan signal Bp having a logic low level L. When the fourth transistor M4 is turned on, the gate-off voltage (logic high level H) of the first emission control signal EM1_p may be supplied to the third node N3. The gate-off voltage of the first emission control signal EM1_p may be in a range of about 5V to about 7V, and the first transistor M1 may be turned on and biased in the fourth period P4.

[0140] Meanwhile, in the fourth period P4, since the first transistors M1 of all pixels arranged in the i-th pixel row are turned on and biased by the first emission control signal EM1_p having a logic high level H, the bias deviation (difference) can be eliminated. Therefore, the hysteresis difference of the pixels can be eliminated (reduced).

[0141] Thereafter, the bias scan signal Bp having a logic high level H, the first emission control signal EM1_p having a logic low level L, and the second emission control signal EM2_p having a logic low level L may be supplied to the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6, respectively. Therefore, the fourth transistor M4 and the seventh transistor M7 may be turned off, and the fifth transistor M5 and the sixth transistor M6 may be turned on.

[0142] In addition, the turn-on period of the third transistor M3 and the turn-on period of the fourth transistor M4 do not overlap with each other. That is, the initialization / compensation period and the bias period of the first transistor M1 are separated from each other.

[0143] In the fifth period P5, the fifth transistor M5 and the sixth transistor M6 are turned on, and the first transistor M1 controls the driving current flowing through the light emitting element LD in response to the voltage of the second node N2. Then, the light emitting element LD generates light with a brightness corresponding to the amount of current flowing through the light emitting element LD. The fifth period P5 may be an emission period. At the same time, the first period P1, the second period P2, the third period P3, and the fourth period P4 may be non-emission periods.

[0144] Such an operation of the display scan period may be implemented by the scan signals supplied to the i-th first scan line S1 i and the i-th second scan line S2 i , and may be synchronized with the frequencies of the first scan driver 200 and the second scan driver 300 .

[0145] For ease of description, Figure 3A , a scan signal is shown, which is supplied to each of the scan lines S1, S2, and S3 during the first period, but the present invention is not limited thereto. For example, multiple scan signals may be supplied to each of the scan lines S1, S2, and S3. In this case, the actual operation process is the same as Figure 3A are the same, and thus a detailed description thereof will be omitted.

[0146] Figure 3B It is shown Figure 2B FIG. 1 is a timing diagram of a self-scanning period of an example of driving a pixel.

[0147] refer to Figure 2B and Figure 3B In order to maintain the brightness of the image output in the display scanning period, the gate-off voltage of the first emission control signal EM1_p may be applied to one electrode (eg, the drain electrode or the third node N3) of the first transistor M1 in the self scanning period.

[0148] According to the image frame rate, one frame may include at least one self-scanning period. The self-scanning period includes a bias application period and an emission period. The operation of the self-scanning period is substantially the same as the operation of the display scanning period except for the supply of the write scanning signal and the compensation scanning signal.

[0149] In an exemplary embodiment, in the self-scan period, the scan signal is not supplied to the second transistor M2 and the third transistor M3. For example, in the self-scan period, each of the write scan signal GWi and the compensation scan signal GCp supplied to the i-th first scan line S1i and the i-th second scan line S2i may have a gate-off voltage.

[0150] For example, the write scan signals GWi and GWi+1 for controlling the p-type transistor may be supplied at a logic high level H, and the compensation scan signal GCp for controlling the n-type transistor may be supplied at a logic low level L. Therefore, the self-scanning period does not include an initialization period ( Figure 3A The first period P1) and the writing period ( Figure 3A The second period P2) and the compensation period ( Figure 3A The third period P3).

[0151] Since the third transistor M3 and the fourth transistor M4 maintain the off state, the gate voltage of the first transistor M1 (that is, the second node N2) is affected by the driving of the self-scanning period.

[0152] The bias scan signal Bp may be supplied to the i-th third scan line S3i in the fourth period P4 of the non-emission period. The fourth transistor M4 may be turned on by the bias scan signal Bp having a logic low level L. When the fourth transistor M4 is turned on, the gate cut-off voltage (logic high level) of the first emission control signal EM1_p may be supplied to the third node N3. Therefore, since the on-bias is applied to the first transistor M1 in the fourth period P4, flicker in low-frequency driving may be reduced.

[0153] The bias scan signal Bp and the emission control signals EM1_p and EM2_p are supplied at a first frequency regardless of the image refresh rate. Therefore, even when the image refresh rate changes, the application of the bias scan signal Bp having a logic low level L during the fourth period P4 can be unaffected by the changed image refresh rate, but can be applied periodically. Therefore, even when various image refresh rates (especially low-frequency driving) are used, flicker can be reduced.

[0154] Thereafter, the bias scan signal Bp may be changed to a logic high level H to turn off the fourth transistor M4 , and the first and second emission control signals EM1_p and EM2_p may be changed to a logic low level L to turn on the fifth and sixth transistors M5 and M6 .

[0155] In an exemplary embodiment, the data driver 700 may not supply the data signal Dm to the pixel unit 100 in the self-scan period. Therefore, power consumption may be further reduced.

[0156] Figure 4 It shows that Figure 1 A timing diagram of an example of a driving method when a display device is driven at a first image refresh rate.

[0157] Here, the first image refresh rate may be a maximum refresh rate that can be achieved by the display device 1000. For example, the first image refresh rate may be set to a high frequency of 120 Hz or higher. In addition, the first image refresh rate may be understood as a period during which a data signal is supplied to the data line D, and one frame period may correspond to the first image refresh rate.

[0158] refer to Figure 1 and Figure 4 , when the display device 1000 is driven at the first image refresh rate, one frame period may include a display scanning period DSP and one self scanning period SSP.

[0159] In an exemplary embodiment, when the display device 1000 is driven at the first image refresh rate, the lengths of the display scanning period DSP and the self scanning period SSP may be substantially the same.

[0160] In an exemplary embodiment, the third scan driver 400 may sequentially supply a scan signal (bias scan signal) to the third scan lines S31 to S36 at a first frequency. The first emission driver 500 may sequentially supply a first emission control signal to the first emission control lines E11 to E16 at a first frequency. The second emission driver 600 may sequentially supply a second emission control signal to the second emission control lines E21 to E26 at a first frequency. Here, the first frequency may be twice the first image refresh rate (that is, the maximum refresh rate).

[0161] The first scan driver 200 may sequentially supply scan signals (write scan signals) to the first scan lines S11 to S16 at a second frequency the same as the first image refresh rate. The second scan driver 300 may sequentially supply scan signals (compensation scan signals) to the second scan lines S21 to S26 at a second frequency.

[0162] In an exemplary embodiment, in the display scanning period DSP, the first emission control signal supplied to the i-th pixel row (i-th horizontal line) may overlap with the write scanning signal, the compensation scanning signal, and the bias scanning signal supplied to the i-th pixel row (i-th horizontal line). In addition, in the display scanning period DSP, the second emission control signal supplied to the i-th pixel row (i-th horizontal line) may completely overlap with the write scanning signal and the compensation scanning signal supplied to the i-th pixel row (i-th horizontal line). However, the second emission control signal may partially overlap with a portion of the compensation scanning signal.

[0163] In the display scanning period DSP, the compensation scanning signal supplied to the i-th pixel row (i-th horizontal line) may overlap with the write scanning signal supplied to the i-th pixel row (i-th horizontal line). However, the compensation scanning signal supplied to the i-th pixel row (i-th horizontal line) does not overlap with the bias scanning signal supplied to the i-th pixel row (i-th horizontal line).

[0164] In the self-scan period SSP, the scan signal is not supplied to the first scan lines S11 to S16 and the second scan lines S21 to S26. In the self-scan period SSP, only the bias application and light emission of the first transistor M1 may be performed. Therefore, power consumption may be reduced.

[0165] As reference Figure 3AAs described, during the display scanning period DSP, the voltage of the data signal Dm is stored in each pixel PX, and the pixel PX may emit light based on the voltage of the data signal Dm stored in each pixel PX.

[0166] In addition, as referenced Figure 3B As described, during the self-scan period SSP, a substantially uniform voltage may be applied to the first transistor M1 by the bias scan signal supplied to each of the third scan lines S31 to S36. Therefore, a hysteresis difference of the first transistor M1 in a frame period may be reduced.

[0167] At the same time, the first frequency, which is the output frequency of the third scan driver 400 and the emission drivers 500 and 600, is set to be greater than the image refresh rate of the display device 1000, so that images output at various image refresh rates can reduce flickering in various image refresh rate driving and improve display quality. For example, the image refresh rate (driving frequency) of the display device 1000 may include a frequency that is a true factor of the first frequency.

[0168] Figure 5 It shows that Figure 1 A timing diagram of an example of a driving method when a display device is driven at a second image refresh rate.

[0169] refer to Figure 1 , Figure 4 and Figure 5 , when the display device 1000 is driven at the first image refresh rate, one frame period may include a display scanning period DSP and a plurality of self scanning periods SSP.

[0170] Here, the first frequency may be set to about 240 Hz, and the second refresh rate may be set to a frequency less than 100 Hz. Figure 5 An example is shown in which the second refresh rate is set to 80 Hz.

[0171] In an exemplary embodiment, the third scan driver 400 and the emission drivers 500 and 600 may drive each of the third scan lines S31 to S36 and the emission control lines E11 to E16 and E21 to E26 at a constant first frequency regardless of an image refresh rate of the display device 1000 .

[0172] The first scan driver 200 and the second scan driver 300 may drive the second scan lines S21 to S26 and the third scan lines S31 to S36 at a second frequency substantially the same as a second image refresh rate.

[0173] In an exemplary embodiment, when the second refresh rate is set to 80 Hz, the self-scanning period SSP may be repeated twice. The on-bias may be periodically (that is, at the first frequency) applied to the first transistor M1 of each pixel PX. For example, the on-bias applied to the first transistor M1 may mean that the first transistor M1 is in an on-bias state. Therefore, the hysteresis characteristics of the first transistor M1 in the frame period may be improved in response to various driving frequencies.

[0174] Fig. 6A It is shown Figure 2B The timing diagram of an example of driving of a pixel, and Figure 6B It is shown Figure 2B A timing diagram of another example of driving of a pixel.

[0175] In addition to the timing of supplying the second emission control signal EM2_p and the bias scan signal Bp, Fig. 6A and Figure 6B Drive and Figure 3A and Figure 3B The pixel operations are the same, the same figure numbers will be used to represent the same or corresponding components, and redundant descriptions will be omitted.

[0176] Fig. 6A shows the operation of the display scan cycle, and Figure 6B The operation of the self-scan cycle is shown.

[0177] refer to Figure 2B , Fig. 6A and Figure 6B , in the display scanning period or the self scanning period, the on bias may be applied to the first transistor M1 twice.

[0178] like Fig. 6A As shown in the display scan cycle ( Figure 4 The non-emission period of the DSP may include a first bias period B_P1, an initialization period I_P, a write period W_P, a compensation period C_P, and a second bias period B_P2. In an exemplary embodiment, the first bias period B_P1 may occur before the initialization period I_P. In addition, the second bias period B_P2 may occur after the compensation period C_P.

[0179] The operations of the first bias period B_P1 and the second bias period B_P2 can be Figure 3A The operation of the fourth period P4 is the same as that of the initialization period I_P. Figure 3A The operation of the first period P1 of the writing period W_P can be the same as Figure 3A The operation of the second period P2 is the same as that of the compensation period C_P. Figure 3A The operation of the third period P3 is the same.

[0180] like Figure 6B As shown in the figure, the self-scanning cycle ( Figure 4 The non-emission period of the SSP may include a first bias period B_P1, an initialization period I_P, and a second bias period B_P2. In the self-scan cycle, the write scan signals GWi and GWi+1 and the compensation scan signal GCp are not switched. Therefore, the power consumption of the display device 1000 can be reduced.

[0181] As described above, in each of the display scanning period and the self scanning period, the number of times the bias is applied to the first transistor M1 increases, thereby reducing flicker in various image refresh rate driving and improving display quality.

[0182] FIG. 7A to FIG. 7D is a timing diagram showing an example of a gate start pulse supplied to an emission driver and a scan driver included in a display device according to an image refresh rate. Figure 8 is a conceptual diagram illustrating an example of a driving method of a display device according to an image refresh rate.

[0183] refer to FIG. 7A to FIG. 7D and Figure 8 The output frequencies of the first gate start pulse GSP1 and the second gate start pulse GSP2 may be changed according to the image refresh rate RR.

[0184] In an exemplary embodiment, pulse widths of the first emission start pulse ESP1 and the second emission start pulse ESP2 may be greater than pulse widths of the first gate start pulse GSP1 , the second gate start pulse GSP2 , and the third gate start pulse GSP3 .

[0185] In an exemplary embodiment, regardless of the driving frequency, the timing controller 800 may output the first emission start pulse ESP1, the second emission start pulse ESP2, and the third gate start pulse GSP3 at a constant frequency (first frequency; 240 Hz). For example, the output frequency of the first emission start pulse ESP1, the second emission start pulse ESP2, and the third gate start pulse GSP3 may be set to twice the maximum refresh rate of the display device 1000.

[0186] The timing controller 800 may output the first gate start pulse GSP1 and the second gate start pulse GSP2 at the same frequency as the image refresh rate RR (a second frequency 120 Hz less than the first frequency). One frame period of the display device 1000 may be determined by the output period of the first gate start pulse GSP1 and the second gate start pulse GSP2.

[0187] In an exemplary embodiment, in the display scanning period DSP, the first emission start pulse ESP1, the second emission start pulse ESP2, the first gate start pulse GSP1, the second gate start pulse GSP2 and the third gate start pulse GSP3 may all be output. For example, each pixel PX may perform during the display scanning period DSP. Figure 3A or Fig. 6A Each pixel PX may store a data signal corresponding to an image to be displayed in a display scanning period DSP.

[0188] In an exemplary embodiment, in the self-scan period SSP, the first emission start pulse ESP1, the second emission start pulse ESP2, and the third gate start pulse GSP3 may be output. For example, each pixel PX may perform Figure 3B or Figure 6B In the self-scan period SSP, a certain high voltage may be supplied to the first electrode and / or the second electrode of the first transistor M1 of each pixel PX.

[0189] In an exemplary embodiment, the lengths of the display scanning period DSP and the self scanning period SSP may be substantially the same. However, the number of self scanning periods SSP included in one frame period may be determined according to the image refresh rate RR.

[0190] like Fig. 7A and Figure 8 As shown in , when the display device 1000 is driven at an image refresh rate RR of 120 Hz, the number of each of the first gate start pulse GSP1 and the second gate start pulse GSP2 supplied during one frame period may be half the number of the third gate start pulse GSP3. Therefore, when the image refresh rate RR is 120 Hz, one frame period may include one display scanning period DSP and one self scanning period SSP.

[0191] Meanwhile, the first emission start pulse ESP1 and the second emission start pulse ESP2 may be supplied at the same frequency as the third gate start pulse GSP3. When the display device 1000 is driven at an image refresh rate RR of 120 Hz, each pixel PX may alternately perform emission and non-emission operations twice during a frame period.

[0192] like Figure 7B and Figure 8As shown in , when the display device 1000 is driven at an image refresh rate RR of 80 Hz, the number of each of the first gate start pulse GSP1 and the second gate start pulse GSP2 supplied for one frame period may be one third of the number of the third gate start pulse GSP3. Therefore, when the display device 1000 is driven at an image refresh rate RR of 80 Hz, one frame period may include one display scanning period DSP and two consecutive self scanning periods SSP. In this case, each pixel PX may alternately perform an emission operation and a non-emission operation three times.

[0193] like Figure 7C and Figure 8 As shown in , when the display device 1000 is driven at an image refresh rate RR of 60 Hz, the number of each of the first gate start pulse GSP1 and the second gate start pulse GSP2 supplied for one frame period may be one quarter of the number of the third gate start pulse GSP3. Therefore, when the display device 1000 is driven at an image refresh rate RR of 60 Hz, one frame period may include one display scanning period DSP and three consecutive self-scanning periods SSP. In this case, each pixel PX may alternately perform an emission operation and a non-emission operation four times.

[0194] like Fig.7D and Figure 8 As shown in , when the display device 1000 is driven at an image refresh rate RR of 48 Hz, the number of each of the first gate start pulse GSP1 and the second gate start pulse GSP2 supplied for one frame period may be one fifth of the number of the third gate start pulse GSP3. Therefore, when the display device 1000 is driven at an image refresh rate RR of 48 Hz, one frame period may include one display scanning period DSP and four consecutive self scanning periods SSP. In this case, each pixel PX may alternately perform emission operation and non-emission operation five times.

[0195] like Figure 8 As shown in , the light waveform LW detected from the pixel unit 100 through the experiment can be output in the same period as the third gate start pulse GSP3.

[0196] In a manner similar to that described above, by adjusting the number of self-scan periods SSP included in one frame period, the display device 1000 can be driven at a driving frequency of 60 Hz, 30 Hz, 24 Hz, or 1 Hz. In other words, the display device 1000 can support various image refresh rates RR as frequencies corresponding to true factors of the first frequency.

[0197] In addition, as the driving frequency decreases, the number of self-scanning periods SSP increases, and thus, a conduction bias having a certain magnitude may be periodically applied to each first transistor M1 included in the pixel unit 100. Therefore, brightness reduction, flickering, and afterimage phenomena may be improved under low-frequency driving.

[0198] Figures 9A to 9D It is shown Figure 1 A circuit diagram of an example of a pixel included in a display device.

[0199] Due to the configuration of the fourth transistor M4, Figures 9A to 9D Pixels and Figure 2A If the pixels are the same or similar, the same reference numerals will be used to represent the same or corresponding components, and redundant descriptions will be omitted.

[0200] refer to Figures 9A to 9D , the pixels 11, 12, 13 and 14 may include a light emitting element LD, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7 and a storage capacitor Cst.

[0201] In an exemplary embodiment, a gate electrode of the seventh transistor M7 may be connected to the i-th first emission control line E1i or the i-th second emission control line E2i. Since the seventh transistor M7 is of a different type from the fifth transistor M5 and the sixth transistor M6, the seventh transistor M7 may be connected to one of the i-th first emission control line E1i and the i-th second emission control line E2i.

[0202] like Fig. 9A As shown in , the first electrode of the fourth transistor M4 can be connected to one of the i-th first emission control line E1i, the i-th second emission control line E2i and the i-th first scan line S1i. The second electrode of the fourth transistor M4 can be connected to the third node N3 (that is, the drain electrode of the first transistor M1). When the fourth transistor M4 is turned on, since the logic high level voltage is supplied to all of the i-th first emission control line E1i, the i-th second emission control line E2i and the i-th first scan line S1i, the first electrode of the fourth transistor M4 can be connected to any one of the i-th first emission control line E1i, the i-th second emission control line E2i and the i-th first scan line S1i. As shown in Fig. 9A As shown in , the first electrode of the fourth transistor M4 may be connected to one of the i-th first emission control line E1i, the i-th second emission control line E2i, and the i-th first scan line S1i.

[0203] like Fig. 9BAs shown in , the first electrode of the fourth transistor M4 can be connected to one of the i-th first emission control line E1i, the i-th second emission control line E2i, and the i-th first scan line S1i. The second electrode of the fourth transistor M4 can be connected to the first node N1 (that is, the source electrode of the first transistor M1). As described above, a voltage for conducting bias can be supplied to one of the source electrode and the drain electrode of the first transistor M1.

[0204] like Fig. 9C As shown in , the fourth transistor M4 may be connected to a bias power supply VEH and a third node N3 (that is, the drain electrode of the first transistor M1). The bias power supply VEH may have a voltage level of about 5V to about 8V. The voltage level of the bias power supply VEH may be easily adjusted according to the driving conditions of the display device 1000. In addition, since the bias power supply VEH is implemented as a direct current (DC) voltage source, the bias difference between the first transistors M1 may be further reduced.

[0205] like Fig.9D As shown in , the fourth transistor M4 may be connected to a certain bias power supply VEH and the first node N1 (that is, the source electrode of the first transistor M1).

[0206] Fig. 10A and Fig. 10B It is shown Figure 1 A circuit diagram of an example of a pixel included in a display device.

[0207] Due to the configuration of the eighth transistor M8, Fig. 10A and Fig. 10B Pixels and 9A to 9D If the pixels are the same or similar, the same reference numerals will be used to represent the same or corresponding components, and redundant descriptions will be omitted.

[0208] refer to Fig. 10A and Fig. 10B , the pixels 15 and 16 may include a light emitting element LD, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a storage capacitor Cst.

[0209] In an exemplary embodiment, if Fig. 10A As shown in , the fourth transistor M4 may be connected to the third node N3. In another exemplary embodiment, as Fig. 10B As shown in , the fourth transistor M4 may be connected to the first node N1.

[0210] One electrode of the fourth transistor M4 may be connected to one of the i-th first emission control line E1i, the i-th second emission control line E2i, and the i-th first scan line S1i. Alternatively, one electrode of the fourth transistor M4 may be connected to a bias power source.

[0211] The eighth transistor M8 may be connected between the fifth transistor M5 and the first node N1. The eighth transistor M8 may be turned off by the second emission control signal supplied to the i-th second emission control line E2i. Therefore, the eighth transistor M8 may be controlled simultaneously with the sixth transistor M6.

[0212] Adding the eighth transistor M8 can facilitate the layout design of the pixel PX. Therefore, due to the addition of the eighth transistor M8, the aperture ratio and the resolution of the pixel PX can be improved.

[0213] Fig.11 is a block diagram illustrating a display device according to an exemplary embodiment.

[0214] In addition to the configuration of the fourth scan driver 600' and the timing controller 800', Fig.11 The display device and Figure 1 For displays that are the same or similar to the display devices of the present invention, the same reference numerals will be used to represent the same or corresponding components, and redundant descriptions will be omitted.

[0215] refer to Fig.11 , the display device 1001 includes a pixel unit 100, a first scan driver 200, a second scan driver 300, a third scan driver 400, an emission driver 500, a fourth scan driver 600', a data driver 700 and a timing controller 800'.

[0216] The timing controller 800' supplies the first gate start pulse GSP1, the second gate start pulse GSP2, the third gate start pulse GSP3 and the fourth gate start pulse GSP4 and the clock signal CLK to the first scan driver 200, the second scan driver 300, the third scan driver 400 and the fourth scan driver 600' based on the timing signals, such as the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DE and the clock signal CLK.

[0217] The first gate start pulse GSP1 controls the rising edge or falling edge of the scan signal supplied from the first scan driver 200. The second gate start pulse GSP2 controls the rising edge or falling edge of the scan signal supplied from the second scan driver 300. The third gate start pulse GSP3 controls the rising edge or falling edge of the scan signal supplied from the third scan driver 400.

[0218] The fourth gate start pulse GSP4 controls a rising edge or a falling edge of a scan signal supplied from the fourth scan driver 600 ′.

[0219] In an exemplary embodiment, the pulse width of at least one of the first gate start pulse GSP1, the second gate start pulse GSP2, the third gate start pulse GSP3, and the fourth gate start pulse GSP4 may be different. Therefore, the width of the corresponding scan signal may also be changed.

[0220] The data driver 700 supplies the data signal to the data line D in response to the data driving control signal DCS. The data signal supplied to the data line D is supplied to the pixel PX selected by the scan signal.

[0221] The first scan driver 200 supplies a scan signal (write scan signal) to the first scan line S1 in response to the first gate start pulse GSP1. The first scan driver 200 may supply the scan signal to the first scan line S1 at a second frequency corresponding to an image refresh rate. The first scan driver 200 may generate the scan signal in a display scan period.

[0222] The second scan driver 300 supplies a scan signal to the second scan line S2 in response to the second gate start pulse GSP2. The second scan driver 300 supplies a scan signal (compensated scan signal) to the second scan line S2 at a second frequency.

[0223] The third scan driver 400 supplies a scan signal to the third scan line S3 in response to the third gate start pulse GSP3. The third scan driver 400 may always supply a scan signal (bias scan signal) to the third scan line S3 at a first frequency regardless of an image refresh rate. That is, the third scan driver 400 may output a scan signal in a display scan period and a self-scan period.

[0224] The fourth scan driver 600' supplies a scan signal (initialization scan signal) to the fourth scan line S4 in response to the fourth gate start pulse GSP4. The fourth scan driver 600' may supply a scan signal to the fourth scan line S4 at a second frequency. For ease of description, the fourth scan line S4 may be collectively referred to as the i-th fourth scan line S4i described below.

[0225] The emission driver 500 supplies an emission control signal to the emission control line E in response to the first emission start pulse ESP1. The emission driver 500 may supply the emission control signal to the emission control line E at a first frequency. That is, the emission driver 500 may output a scan signal in a display scan period and a self-scan period. For ease of description, the emission control line E may be collectively referred to as the i-th emission control line Ei described below.

[0226] In an exemplary embodiment, the scan signals output from the first scan driver 200 and the third scan driver 400 may have a gate-on voltage having a logic low level L, thereby controlling the p-type transistor. The scan signals output from the second scan driver 300 and the fourth scan driver 600' may have a gate-on voltage having a logic high level H, thereby controlling the n-type transistor.

[0227] FIG. 12A to FIG. 12D Show Fig.11 A circuit diagram of an example of a pixel included in a display device.

[0228] Due to some connection configurations except for the fourth transistor M4 to the seventh transistor M7, Fig. 12A and Fig. 12B Pixels and Figure 2A If the pixels are the same or similar, the same reference numerals will be used to represent the same or corresponding components, and redundant descriptions will be omitted.

[0229] refer to FIG. 12A to FIG. 12D , the pixels 17, 18, 19 and 20 may include a light emitting element LD, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8 and a storage capacitor Cst.

[0230] In an exemplary embodiment, if Fig. 12A and Fig. 12B As shown in , the fourth transistor M4 is connected between the third node N3 and the i-th emission control line Ei. The gate electrode of the fourth transistor M4 is connected to the i-th third scan line S3i. When the scan signal with a logic low level L is supplied to the i-th third scan line S3i, the fourth transistor M4 is turned on to supply the voltage of the i-th emission control line Ei to the third node N3. In this case, the gate cut-off voltage (logic high level voltage) can be supplied to the i-th emission control line Ei. That is, when the fourth transistor M4 is turned on, the first transistor M1 can be biased by being turned on.

[0231] However, this is merely an example, and the fourth transistor M4 may be connected between the third node N3 and a certain bias power source VEH.

[0232] In another exemplary embodiment, Fig. 12C and Fig.12D As shown in , the fourth transistor M4 is connected between the first node N1 and the i-th emission control line Ei or between the first node N1 and the bias power source VEH.

[0233] The fifth transistor M5 is connected between the first power source VDD and the first node N1. A gate electrode of the fifth transistor M5 is connected to the i-th emission control line Ei.

[0234] The sixth transistor M6 is connected between the second electrode (that is, the third node N3) of the first transistor M1 and the first electrode (that is, the fourth node N4) of the light emitting element LD. The gate electrode of the sixth transistor M6 is connected to the i-th emission control line Ei. That is, the fifth transistor M5 and the sixth transistor M6 can be controlled simultaneously by the emission control signal.

[0235] The eighth transistor M8 may be connected between the second node N2 and the second initialization power supply Vint. The gate electrode of the eighth transistor M8 is connected to the i-th fourth scan line S4i. When the initialization scan signal is supplied to the i-th fourth scan line S4i, the eighth transistor M8 is turned on to supply the voltage of the second initialization power supply Vint to the second node N2 (that is, the gate electrode of the first transistor M1). Therefore, the gate voltage of the first transistor M1 may be initialized.

[0236] The seventh transistor M7 is connected between the fourth node N4 (ie, the first electrode of the light emitting element LD) and the first initialization power source Aint. When the seventh transistor M7 is turned on, the voltage of the first initialization power source Aint may be supplied to the fourth node N4.

[0237] In an exemplary embodiment, if Fig. 12A and Fig. 12C As shown in , the gate electrode of the seventh transistor M7 can be connected to the i-th third scan line S3i. In this case, the seventh transistor M7 can be a p-type transistor and can be controlled simultaneously with the fourth transistor M4. That is, when the conduction bias is applied to the first transistor M1, the voltage of the first initialization power supply Aint can be applied to the first electrode of the light emitting element LD.

[0238] In an exemplary embodiment, if Fig. 12B and Fig.12D As shown in , the gate electrode of the seventh transistor M7 can be connected to the i-th emission control line Ei. In this case, the seventh transistor M7 can be an n-type transistor and can be controlled in a manner opposite to the fifth transistor M5. Therefore, when the fifth transistor M5 and the sixth transistor M6 are turned on, the seventh transistor M7 can be turned off. Therefore, during the non-emission period, the voltage of the first initialization power supply Aint can be applied to the first electrode (fourth node N4) of the light emitting element LD.

[0239] In an exemplary embodiment, the first initialization power source Aint and the second initialization power source Vint may generate different voltages. That is, a voltage for initializing the second node N2 and a voltage for initializing the fourth node N4 may be set differently.

[0240] In low-frequency driving in which the length of one frame period increases, when the voltage of the second initialization power supply Vint supplied to the second node N2 is too low, the hysteresis of the first transistor M1 in the corresponding frame period changes suddenly. This hysteresis change may cause flickering in low-frequency driving. Therefore, a display device driven at a low frequency may require a voltage of the second initialization power supply Vint that is higher than the voltage of the second power supply VSS.

[0241] On the other hand, in order to prevent the parasitic capacitor of the light emitting element LD from being charged by the voltage of the first initialization power supply Aint supplied to the fourth node N4, the first initialization power supply Aint may have a voltage lower than a certain reference level. For example, the first initialization power supply Aint may have a voltage similar to the voltage of the second power supply VSS. However, this is only an example, and the voltage of the first initialization power supply Aint may be higher or lower than the voltage of the second power supply VSS according to the driving conditions of the display device.

[0242] As mentioned above, FIG. 12A to FIG. 12D The pixels 17, 18, 19, and 20 can also initialize the gate voltage of the first transistor M1. Therefore, the image quality of the display device 1001 can be improved.

[0243] Fig.13 It is shown FIG. 12A to FIG. 12D A timing diagram of an example of driving of a pixel.

[0244] refer to FIG. 12A to FIG. 13 , the pixels 17, 18, 19, and 20 may receive a signal for displaying an image during a display scanning period. The display scanning period may include a period in which a data signal corresponding to an output image is written.

[0245] The non-emission period of the display scanning cycle may include a bias period B_P, an initialization period I_P, a writing period W_P, and a compensation period C_P. Thereafter, the pixels 17, 18, 19, and 20 may emit light having a certain brightness in the emission period E_P.

[0246] The bias period B_P may be before the initialization period I_P. In the bias period B_P, the fourth transistor M4 and the seventh transistor M7 are turned on in response to the scan signal (bias scan signal) supplied to the i-th third scan line S3i and the emission control signal supplied to the i-th emission control line Ei, respectively. Therefore, a turn-on bias may be applied to the first transistor M1, and the voltage of the first initialization power supply Aint may be applied to the fourth node N4. When the fourth transistor M4 is turned off, the bias period B_P ends.

[0247] Thereafter, in the initialization period I_P, the third transistor M3 may be turned on in response to the scan signal (compensation scan signal) supplied to the i-th second scan line S2i, and the eighth transistor M8 may be turned on in response to the scan signal (initialization scan signal) supplied to the i-th fourth scan line S4i. Therefore, the voltage of the second initialization power supply Vint may be supplied to the second node N2. The third transistor M3 may remain in the on state during the compensation period C_P. When the eighth transistor M8 is turned off, the initialization period I_P ends.

[0248] Thereafter, in the writing period W_P, the second transistor M2 may be turned on in response to the scanning signal (writing scanning signal) supplied to the i-th first scanning line S1i. Thus, the data signal may be supplied to the first node N1. When the second transistor M2 is turned off, the writing period W_P ends.

[0249] Thereafter, in the compensation period C_P, the threshold voltage of the first transistor M1 may be compensated by the turned-on third transistor M3. When the third transistor M3 is turned off, the compensation period C_P ends.

[0250] Thereafter, in the emission period E_P, the fifth transistor M5 and the sixth transistor M6 may be turned on, and the light emitting element LD may emit light in response to the data signal supplied to the first node N1.

[0251] FIG. 14A to FIG. 14D A timing diagram illustrating an example of a driving method of a display device according to an image refresh rate.

[0252] Due to the driving method of the fourth gate start pulse GSP4, the first initialization power supply Aint and the bias power supply VEH, FIG. 14A to FIG. 14D The driving method and FIG. 7A to FIG. 7D The driving method is the same or similar, the same figure numbers will be used to represent the same or corresponding components, and redundant descriptions will be omitted.

[0253] refer to Fig.11 as well as FIG. 14A to FIG. 14DThe output frequencies of the first gate start pulse GSP1, the second gate start pulse GSP2 and the fourth gate start pulse GSP4 can be changed according to the image refresh rate RR. In addition, the voltage level of the first initialization power supply Aint and / or the voltage level of the bias power supply VEH can be controlled according to the image refresh rate RR.

[0254] In an exemplary embodiment, the voltages of the first initialization power supply Aint and the bias power supply VEH may be output and controlled from a certain power driver.

[0255] Regardless of the driving frequency, the timing controller 800 ′ may output the emission start pulse ESP and the third gate start pulse GSP3 at a constant frequency (first frequency) of, for example, 240 Hz.

[0256] The timing controller 800' may output the first gate start pulse GSP1, the second gate start pulse GSP2 and the fourth gate start pulse GSP4 at the same frequency (second frequency) as the image refresh rate RR, for example, 120 Hz, 80 Hz, 60 Hz or 40 Hz. One frame period of the display device may be determined by the output period of the first gate start pulse GSP1.

[0257] As the image refresh rate RR decreases, the number of self-scan periods SSP included in one frame period may increase.

[0258] At the same time, modulation of the bias power supply VEH may be applied in response to a change in the image refresh rate RR. In an exemplary embodiment, the voltage level of the bias power supply VEH may be increased in response to a repetition of the self-scanning period SSP. That is, as the image refresh rate RR decreases, a stronger on-bias may be applied to the first transistor M1 over time in one frame period.

[0259] For example, the voltage level of the bias power supply VEH may be increased at intervals of about 8.3 ms corresponding to 120 Hz. The voltage of the bias power supply VEH may vary within a range of about 5V to about 7.5V.

[0260] On the other hand, the voltage level of the bias power supply VEH returns again to the value set to the lowest value in the display scanning period DSP. That is, the change in the voltage of the bias power supply VEH can be repeated in units of frames.

[0261] In an exemplary embodiment, modulation of the first initialization power supply Aint may be applied in response to a change in the image refresh rate RR. In an exemplary embodiment, the voltage level of the first initialization power supply Aint may be gradually reduced in response to a repetition of the self-scanning period SSP. That is, as the image refresh rate RR decreases, a lower initialization voltage may be applied to the light emitting element LD over time within a frame period.

[0262] For example, the voltage level of the bias power source VEH may be increased at intervals of about 8.3 ms corresponding to 120 Hz. The voltage of the first initialization power source Aint may vary within a range of about -1V to about 5V.

[0263] On the other hand, the voltage level of the first initialization power source Aint returns again to the value set to the highest in the display scanning period DSP. That is, the change in the voltage of the first initialization power source Aint may be repeated in units of frames.

[0264] As described above, the voltage level of the bias power supply VEH and / or the first initialization power supply Aint can be adaptively adjusted according to the image refresh rate RR. Therefore, the image quality under low-frequency driving can be further improved.

[0265] As described above, the display device according to the exemplary embodiment of the inventive concept can include one display scanning cycle and at least one self-scanning cycle in one frame to support image output at various driving frequencies. In addition, as the driving frequency decreases, the number of self-scanning cycles increases, and therefore, the reduction in brightness and flicker visibility can be improved in low-frequency driving.

[0266] In addition, regardless of the grayscale of the data signal and the image, the voltage for biasing can be periodically applied to the first transistor M1 at a constant voltage through the bias scanning transistor (fourth transistor M4), thereby reducing the hysteresis (threshold shift difference) between adjacent pixels caused by the conduction bias difference (and grayscale level difference). Therefore, the afterimage phenomenon (ghosting phenomenon) caused by the hysteresis deviation can be reduced or eliminated.

[0267] However, the effects of the inventive concept are not limited to the above-described effects, but various modifications may be made without departing from the spirit and scope of the inventive concept.

[0268] Although the inventive concept has been described with reference to exemplary embodiments, it will be understood by those skilled in the art that various modifications and variations may be made within the inventive concept without departing from the spirit and scope of the inventive concept.

Claims

1. A display device, comprising: Pixels; a first scanning line connected to the pixel so as to supply a first scanning signal as a writing scanning signal to the pixel at a second frequency corresponding to an image refresh rate of the pixel; a second scanning line connected to the pixel so as to supply a second scanning signal as a compensation scanning signal different from the first scanning signal to the pixel at the second frequency; a third scanning line connected to the pixel so as to supply a third scanning signal as a bias scanning signal to the pixel at a first frequency greater than the second frequency; an emission control line connected to the pixel so as to supply an emission control signal to the pixel at the first frequency; as well as A data line is connected to the pixel to supply a data signal to the pixel based on the second frequency.

2. The display device according to claim 1, wherein: The second frequency corresponds to a true factor of the first frequency.

3. The display device according to claim 1, wherein: The first frequency corresponds to twice the maximum refresh rate of the display device.

4. The display device according to claim 3, wherein: Each of the emission control lines supplies the emission control signal at the first frequency, which is twice the maximum refresh rate of the display device.

5. The display device according to claim 1, further comprising: a first scan driver configured to supply the first scan signal to the first scan line; a second scan driver configured to supply the second scan signal to the second scan line; a third scan driver configured to supply the third scan signal to the third scan line; an emission driver configured to supply the emission control signal to the emission control line; as well as A data driver is configured to supply the data signal to the data line.

6. The display device according to claim 5, wherein: The first scan driver and the second scan driver supply the first scan signal and the second scan signal during a display scan period in one frame period, and do not supply the first scan signal and the second scan signal during a self scan period in the one frame period, wherein, during the display scanning period, the data signal is written into the pixel, and The third scan driver supplies the third scan signal in the self-scan period so that a bias is applied to a driving transistor included in each of the pixels.

7. The display device according to claim 6, wherein: When the pixel is driven at a maximum refresh rate, the display scan period is repeated the same number of times as the self scan period is repeated.

8. The display device according to claim 6, wherein: As the image refresh rate decreases, the number of self-scan cycles increases.

9. The display device according to claim 5, further comprising: a fourth scanning line connected to the pixel so as to supply a fourth scanning signal to the pixel at the second frequency, Wherein, the scanning driver further includes: The fourth scan driver is configured to supply the fourth scan signal different from the first scan signal to the fourth scan line at the second frequency.

10. A display device, comprising: Pixels; a first scan line connected to the pixel so as to supply a first scan signal to the pixel at a second frequency corresponding to an image refresh rate of the pixel; a second scanning line connected to the pixel so as to supply a second scanning signal different from the first scanning signal to the pixel at the second frequency; a third scanning line connected to the pixel so as to supply a third scanning signal to the pixel at a first frequency; an emission control line connected to the pixel so as to supply an emission control signal to the pixel at the first frequency; a data line connected to the pixel so as to supply a data signal to the pixel based on the second frequency, Wherein, each pixel arranged on the i-th horizontal line of pixels comprises: a light emitting element including a first electrode and a second electrode connected to a second power source; a first transistor including a first electrode connected to a first node, the first node being electrically connected to a first power source, and the first transistor being configured to control a driving current based on a voltage of a second node; a second transistor connected between one of the data lines and the first node and turned on by the first scan signal supplied to an i-th first scan line among the first scan lines; a third transistor connected between the second node and a third node, the third node being connected to the second electrode of the first transistor, and the third transistor being turned on by the second scan signal supplied to an i-th second scan line among the second scan lines; a fourth transistor connected between the third node and an i-th emission control line, between the third node and a bias power supply, between the first node and the i-th emission control line, or between the first node and the bias power supply, and the fourth transistor is turned on by the third scan signal supplied to the i-th third scan line; a fifth transistor connected between the first power source and the first node and configured to be turned off by the emission control signal supplied to the i-th emission control line among the emission control lines; and a storage capacitor connected between the first power source and the second node, and Wherein, i is a natural number.

11. The display device according to claim 10, in, Each of the pixels arranged on the i-th horizontal line further includes: a sixth transistor connected between the third node and the first electrode of the light emitting element and turned off together with the fifth transistor; a seventh transistor connected between the first electrode of the light emitting element and a first initialization power source, and the seventh transistor is turned on by the emission control signal or the third scan signal; and An eighth transistor is connected between the second node and a second initialization power source, and the eighth transistor is turned on by a fourth scan signal supplied to an i-th fourth scan line.

12. The display device according to claim 11, further comprising: A fourth scan line is connected to the pixel to supply the fourth scan signal different from the first scan signal to the pixel at the second frequency.

13. The display device according to claim 11, wherein: After the fourth transistor is turned on, the eighth transistor is turned on, and a turn-on period of the fourth transistor and a turn-on period of the eighth transistor do not overlap with each other.

14. The display device according to claim 11, in, Each of the first transistor, the second transistor, the fifth transistor, and the sixth transistor is a p-type transistor, and Wherein, each of the third transistor and the eighth transistor is an n-type oxide semiconductor transistor.

15. The display device according to claim 10, wherein the emission control line comprises: a first emission control line configured to supply a first emission control signal to the pixel at the first frequency; and A second emission control line is configured to supply a second emission control signal to the pixel at the first frequency.

16. The display device according to claim 15, wherein: Each of the pixels arranged on the i-th horizontal line further includes: a sixth transistor connected between the third node and the first electrode of the light emitting element and turned off by the second emission control signal supplied to the i-th second emission control line; and A seventh transistor is connected between the first electrode of the light emitting element and an initialization power source and is turned on by the first emission control signal or the second emission control signal.

17. The display device according to claim 16, wherein: The first transistor, the second transistor, the fourth transistor, the fifth transistor, and the sixth transistor are p-type transistors, and the third transistor and the seventh transistor are n-type oxide semiconductor transistors.

18. The display device according to claim 16, wherein: A turn-on period of the third transistor and a turn-on period of the fourth transistor do not overlap with each other.

19. The display device according to claim 16, wherein: Each of the pixels arranged on the i-th horizontal line further includes: an eighth transistor connected between the fifth transistor and the first node and turned off by the second emission control signal supplied to the i-th second emission control line.

Images