Vertical memory device and method of manufacturing the same

Abstract

A vertical memory device includes: a channel extending in a vertical direction on a substrate; a charge storage structure on an outer sidewall of the channel and including a tunnel insulation pattern, a charge trapping pattern, and a first barrier pattern sequentially stacked in a horizontal direction; and gate electrodes spaced apart from each other in the vertical direction, each gate electrode surrounding the charge storage structure. The charge storage structure includes charge trapping patterns, each charge trapping pattern facing one of the gate electrodes in a horizontal direction. The length of the inner sidewall of each charge trapping pattern facing the tunnel insulation pattern in the vertical direction is less than the length of the outer sidewall thereof facing the first barrier pattern in the vertical direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0092525 filed on July 30, 2019, in the Korean Intellectual Property Office (KIPO), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The inventive concept relates to a vertical memory device and / or a method of manufacturing the same. Background Art

[0004] In a VNAND flash memory device, a charge trapping layer on an outer sidewall of a vertical channel may extend in a vertical direction, and thus charges trapped in the charge trapping layer may move in a vertical direction through a plurality of gate electrodes at a plurality of levels, respectively. As a result, the retention characteristics of the VNAND flash memory device may deteriorate, which may cause reliability issues. Summary of the invention

[0005] Some example embodiments provide a vertical memory device having improved characteristics.

[0006] Some example embodiments provide a method of manufacturing a vertical memory device having improved characteristics.

[0007] According to some example embodiments, a vertical memory device is provided, including: a channel on a substrate, the channel extending in a vertical direction perpendicular to an upper surface of the substrate; a charge storage structure on an outer sidewall of the channel, the charge storage structure including a tunnel insulating pattern, a charge trapping pattern, and a first barrier pattern sequentially stacked in a horizontal direction, the horizontal direction being parallel to the upper surface of the substrate; and gate electrodes spaced apart from each other in the vertical direction, each of the gate electrodes surrounding the charge storage structure. The charge storage structure includes charge trapping patterns spaced apart from each other in the vertical direction, each of the charge trapping patterns facing one of the gate electrodes in the horizontal direction. A first length in the vertical direction of an inner sidewall of at least one of the charge trapping patterns facing the tunnel insulating pattern is less than a second length in the vertical direction of an outer sidewall of a corresponding at least one of the charge trapping patterns facing the first barrier pattern.

[0008] According to some example embodiments, a vertical memory device is provided, including: a channel on a substrate, the channel extending in a vertical direction perpendicular to an upper surface of the substrate; a charge storage structure on an outer sidewall of the channel, the charge storage structure including a tunnel insulation pattern, a charge trapping pattern structure, and a blocking pattern sequentially stacked in a horizontal direction parallel to the upper surface of the substrate; and gate electrodes spaced apart from each other in the vertical direction, each of the gate electrodes surrounding the charge storage structure. The charge storage structure includes charge trapping pattern structures spaced apart from each other in the vertical direction, each of the charge trapping pattern structures facing a corresponding one of the gate electrodes in the horizontal direction. Each of the charge trapping pattern structures includes a first charge trapping pattern and a second charge trapping pattern sequentially stacked in the horizontal direction on the outer sidewall of the tunnel insulation pattern, the first charge trapping pattern and the second charge trapping pattern including materials different from each other.

[0009] According to some example embodiments, a vertical memory device is provided, comprising: a channel on a substrate, the channel extending in a vertical direction perpendicular to an upper surface of the substrate; a charge storage structure on an outer sidewall of the channel, the charge storage structure comprising a tunnel insulation pattern, a charge trapping pattern, and a blocking pattern sequentially stacked in a horizontal direction parallel to the upper surface of the substrate; a dummy charge storage structure on the substrate spaced apart from the charge storage structure in a vertical direction, the dummy charge storage structure comprising a dummy tunnel insulation pattern, a dummy charge trapping pattern, and a dummy blocking pattern sequentially stacked; and gate electrodes spaced apart from each other in the vertical direction, each of the gate electrodes surrounding the charge storage structure. The charge storage structure comprises charge trapping patterns spaced apart from each other in the vertical direction, each of the charge trapping patterns facing a corresponding one of the gate electrodes in the horizontal direction. The dummy tunnel insulation pattern and the dummy blocking pattern respectively comprise materials substantially the same as those of the tunnel insulation pattern and the blocking pattern, and the dummy charge trapping pattern comprises a material different from that of the charge trapping pattern.

[0010] According to some example embodiments, a vertical memory device is provided, including: a channel on a substrate, each of the channels extending in a first direction perpendicular to an upper surface of the substrate; a channel connection pattern on the substrate, the channel connection pattern contacting the channel; a charge storage structure on an outer sidewall of the channel on the channel connection pattern, the charge storage structure including a tunnel insulation pattern, a charge trapping pattern, a blocking pattern, and a separation pattern, the tunnel insulation pattern, the charge trapping pattern, and the blocking pattern being sequentially stacked in a horizontal direction parallel to the upper surface of the substrate; gate electrodes spaced apart from each other in the first direction, each of the gate electrodes surrounding the charge storage structure; a separation structure on the substrate, each of the separation structures extending through the gate electrode in a second direction parallel to the upper surface of the substrate, the separation structure separating each of the gate electrodes in a third direction parallel to the upper surface of the substrate and crossing the second direction; and a bit line on the channel, each of the bit lines extending in the third direction to be electrically connected to the channel. The charge storage structure includes charge trapping patterns spaced apart from each other in the first direction, each of the charge trapping patterns facing one of the gate electrodes in a horizontal direction. A first length of an inner sidewall of each of the charge trapping patterns facing the tunnel insulating pattern in the first direction is less than a second length of an outer sidewall of each of the charge trapping patterns facing the blocking pattern in the first direction. A separation pattern is interposed between charge trapping patterns adjacent to each other in the first direction, the separation pattern contacts the tunnel insulating pattern and the blocking pattern, and the separation pattern includes an insulating material.

[0011] According to some example embodiments, a method for manufacturing a vertical memory device is provided, comprising: forming a molding on a substrate, the molding comprising an insulating layer and a first sacrificial layer stacked alternately and repeatedly; forming a channel and a preliminary charge storage structure on the substrate, the channel extending through the molding, and the preliminary charge storage structure covering an outer sidewall of the channel and comprising a tunnel insulating pattern, a preliminary charge trapping pattern, and a first blocking pattern stacked sequentially; forming an opening through the molding to expose an upper surface of the substrate; removing the first sacrificial layer through the opening to form a first gap exposing the outer sidewall of the preliminary charge storage structure; performing a first nitridation process on the preliminary charge trapping pattern through the first gap to form charge trapping patterns spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate; performing a first oxidation process on the preliminary charge trapping pattern through the first gap to form a separation pattern between the charge trapping patterns; and forming a gate electrode in the first gap.

[0012] According to some example embodiments, there is provided a method for manufacturing a vertical memory device, comprising: forming a molding on a substrate, the molding comprising an insulating layer and a sacrificial layer alternately and repeatedly stacked; forming a channel and a preliminary charge storage structure on the substrate, the channel extending through the molding, and the preliminary charge storage structure covering an outer sidewall of the channel and comprising a tunnel insulating pattern, a preliminary charge trapping pattern, and a first blocking pattern sequentially stacked; forming an opening through the molding to expose an upper surface of the substrate; removing the sacrificial layer through the opening to form a gap exposing the outer sidewall of the preliminary charge storage structure; performing a first nitridation process on the preliminary charge trapping pattern through the gap to Oxidation reduction patterns are formed that are spaced apart from each other in a vertical direction perpendicular to an upper surface of a substrate; a first oxidation process is performed on the preliminary charge trapping patterns through a gap to form a preliminary separation pattern between the oxidation reduction patterns; a second oxidation process is performed on the oxidation reduction patterns and the preliminary charge trapping patterns through the gap to divide the preliminary charge trapping patterns into a plurality of pieces spaced apart from each other in the vertical direction; a second nitridation process is performed on each of the preliminary charge trapping patterns through the gap to form a charge trapping pattern at a lower end, an upper end and an outer side wall of each of the preliminary charge trapping patterns; and a gate electrode is formed in the gap.

[0013] In a method of manufacturing a vertical memory device according to some example embodiments, a nitridation process and / or an oxidation process may be performed on a preliminary charge trapping pattern extending in a vertical direction to more easily form a plurality of charge trapping patterns spaced apart from each other in the vertical direction. Therefore, charges trapped in the charge trapping pattern may not move in the vertical direction, or may move a reduced amount in the vertical direction, through gate electrodes at other levels, so that retention characteristics may be enhanced. Therefore, a vertical memory device including the charge trapping pattern may have enhanced reliability and / or enhanced retention characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 and Figure 2 is a cross-sectional view illustrating a vertical memory device according to some example embodiments.

[0015] Figures 3 to 11 is a cross-sectional view illustrating a method of manufacturing a vertical memory device according to some example embodiments.

[0016] Fig.12 is a cross-sectional view illustrating a vertical memory device according to some example embodiments, and is Figure 1 An enlarged cross-sectional view of region X.

[0017] Figures 13 to 16 is a cross-sectional view illustrating a method of manufacturing a vertical memory device according to some example embodiments, and particularly Figure 1 An enlarged cross-sectional view of region X.

[0018] Fig.17 is a cross-sectional view illustrating a vertical memory device according to some example embodiments, and is Figure 1 An enlarged cross-sectional view of region X.

[0019] Figures 18 to 22 is a cross-sectional view illustrating a method of manufacturing a vertical memory device according to some example embodiments, and particularly Figure 1 An enlarged cross-sectional view of region X.

[0020] Fig.23 is a cross-sectional view illustrating a vertical memory device according to some example embodiments, and is Figure 1 An enlarged cross-sectional view of region X.

[0021] Figure 24 to Figure 26 is a cross-sectional view illustrating a method of manufacturing a vertical memory device according to some example embodiments, and particularly Figure 1 An enlarged cross-sectional view of region X.

[0022] Fig. 27 is a cross-sectional view illustrating a vertical memory device according to some example embodiments.

[0023] Figures 28 to 30 is a cross-sectional view illustrating a vertical memory device according to some example embodiments. DETAILED DESCRIPTION

[0024] The above and other aspects and features of the vertical memory device and / or the manufacturing method thereof according to some example embodiments will become readily understood from the following detailed description with reference to the accompanying drawings. Below in the specification (not necessarily in the claims), a direction substantially perpendicular to the upper surface of the substrate may be defined as a first direction, and two directions substantially parallel to the upper surface of the substrate and intersecting each other may be defined as a second direction and a third direction, respectively. In some example embodiments, the second direction and the third direction may be substantially perpendicular to each other.

[0025] Figure 1 and Figure 2 is a cross-sectional view illustrating a vertical memory device according to some example embodiments. Figure 2 yes Figure 1 An enlarged cross-sectional view of region X.

[0026] Reference Figure 1 and Figure 2, the vertical memory device may include a channel 260, a first charge storage structure 252, and a gate electrode structure on a substrate 100. The vertical memory device may also include a dummy charge storage structure 250, a channel connection pattern 330, an insulating pattern 175, a second barrier pattern 360, a common source pattern (CSP) 390, a second spacer 380, a support layer 160, a support pattern 165, a filling pattern 270, a pad 280, first to third insulating interlayers 190, 290 and 400, a contact plug 410, and a bit line 430.

[0027] The substrate 100 may be or include a wafer, and may include silicon, germanium, silicon germanium, or a III-V compound such as GaP, GaAs, GaSb, etc. In some example embodiments, the substrate 100 may be or include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. For example, n-type impurities may be doped into the substrate 100.

[0028] The channel 260 may extend in the first direction on the substrate 100 and may have, for example, a cup shape. The channel 260 may include polysilicon, for example, undoped polysilicon.

[0029] In some example embodiments, the channel 260 may be formed in each of the second direction and the third direction to form a channel array. The CSP 390 and the second spacer 380 on each of the opposite sidewalls of the CSP 390 in the third direction may form a partition structure, and the channel 260 surrounded by the gate electrode structure between the partition structures adjacent to each other in the third direction may form a channel block. The channel array may include a plurality of channel blocks arranged in the third direction. The channels 260 included in each of the channel blocks may be connected to each other by the channel connection pattern 330.

[0030] The channel connection pattern 330 may extend in the second direction between the separation structures adjacent in the third direction to contact the lower outer sidewall of each of the channels 260, and a plurality of channel connection patterns 330 may be formed in the third direction. The channel connection pattern 330 may include, for example, undoped polysilicon or polysilicon doped with impurities (e.g., p-type impurities and / or n-type impurities). An air gap 340 may be formed in the channel connection pattern 330.

[0031] The first charge storage structure 252 may be formed on the channel connection pattern 330 to cover the outer sidewall of the portion of the channel 260 extending through the gate electrode structure, and the dummy charge storage structure 250 may be formed between the upper surface of the substrate 100 and the channel connection pattern 330 to cover the bottom surface and the outer sidewall of the lower end of the channel 260. For example, the first charge storage structure 252 and the dummy charge storage structure 250 may be spaced apart from each other in the first direction by the channel connection pattern 330 contacting the lower sidewall of the channel 260. The lower surface of the first charge storage structure 252 and the upper surface of the dummy charge storage structure 250 may contact the channel connection pattern 330.

[0032] The first charge storage structure 252 may include a tunnel insulation pattern 240, a charge trapping pattern 232, and a first barrier pattern 220 sequentially stacked in a horizontal direction. The horizontal direction may be substantially parallel to the upper surface of the substrate 100. The tunnel insulation pattern 240, the charge trapping pattern 232, and the first barrier pattern 220 may be sequentially stacked from the outer sidewall of the channel 260. The first charge storage structure 252 may also include a separation pattern 234. Each of the tunnel insulation pattern 240 and the first barrier pattern 220 may include an oxide (e.g., silicon oxide), and the charge trapping pattern 232 may include a nitride (e.g., silicon nitride). The charge trapping pattern 232 may not include an oxide, and either or both of the tunnel insulation pattern 240 and the first barrier pattern 220 may not include a nitride.

[0033] The gate electrode structure may include gate electrodes 372, 374, and 376 stacked at multiple levels, respectively, spaced apart from each other in the first direction, and an insulating pattern 175 may be formed between adjacent gate electrodes of the gate electrodes 372, 374, and 376. The insulating pattern 175 may include an oxide (e.g., silicon oxide). Each of the gate electrodes 372, 374, and 376 may surround the channel 260 and the first charge storage structure 252 covering the outer sidewall of the channel 260, respectively, between the adjacent separation structures in the third direction.

[0034] In some example embodiments, the gate electrode structure may include at least one first gate electrode 372, a plurality of second gate electrodes 374, and at least one third gate electrode 376 sequentially stacked in a first direction. The first gate electrode may function as a ground selection line (GSL), each of the second gate electrodes 374 may function as a word line, and the third gate electrode 376 may function as a string selection line (SSL).

[0035] In the third direction, a plurality of gate electrode structures may be formed to be spaced apart from each other by the separation structure. In some example embodiments, the gate electrode structure may form a stepped structure whose length in the second direction may decrease from a lowest level toward a highest level in the first direction.

[0036] Each of the first to third gate electrodes 372, 374, and 376 may include a gate conductive pattern and a gate barrier pattern covering a surface of the gate conductive pattern. The gate conductive pattern may include a low resistance metal (e.g., at least one of tungsten, titanium, tantalum, platinum, etc.), and the gate barrier pattern may include a metal nitride (e.g., at least one of titanium nitride, tantalum nitride, etc.).

[0037] The upper and lower surfaces of each of the first to third gate electrodes 372, 374, and 376 and the sidewall facing the first charge storage structure 252 may be covered by the second barrier pattern 360, and the second barrier pattern 360 may extend in the first direction between the first to third gate electrodes 372, 374, and 376 to cover the sidewall of the insulating pattern 175. The second barrier pattern 360 may include a metal oxide (e.g., aluminum oxide).

[0038] In some example embodiments, each of the tunnel insulating pattern 240 and the first blocking pattern 220 included in the first charge storing structure 252 may extend through the gate electrode structure in the first direction, and a plurality of charge trapping patterns 232 may be spaced apart from each other in the first direction to face the gate electrodes 372, 374, and 376, respectively, in the horizontal direction.

[0039] However, a first length L1 of each of the charge trapping patterns 232 in the first direction may be greater than a third length L3 in the first direction of each of the second gaps 350 for forming the gate electrodes 372, 374, and 376, respectively, between the insulating patterns 175. One of the gate electrodes 372, 374, and 376 and the second blocking pattern 360 may be formed in each of the second gaps 350, and thus the first length L1 may be greater than a fourth length L4 in the first direction of each of the gate electrodes 372, 374, and 376.

[0040] In some example embodiments, the length of each of the charge trapping patterns 232 in the first direction may gradually increase from the tunnel insulating pattern 240 to the first barrier pattern 220. Therefore, in each of the charge trapping patterns 232, a first length L1 of the inner sidewall contacting the tunnel insulating pattern 240 may be smaller than a second length L2 of the outer sidewall contacting the first barrier pattern 220. In some example embodiments, an absolute value of a slope of an upper surface or a lower surface of each of the charge trapping patterns 232 relative to the upper surface of the substrate 100 may gradually decrease from the tunnel insulating pattern 240 to the first barrier pattern 220. The charge trapping pattern 232 may be concave, for example, may be concave in the third direction from the tunnel insulating pattern 240 to the first barrier pattern 220.

[0041] The separation pattern 234 may be formed between the charge trapping patterns 232 adjacent in the first direction, so that the charge trapping patterns 232 may be spaced apart from each other. The separation pattern 234 may face the insulating pattern 175 in the horizontal direction, and more specifically, may face the central portion of the insulating pattern 175 in the first direction, for example, across the first barrier pattern 220. The separation pattern 234 may include an oxide (e.g., silicon oxide).

[0042] The length of the separation pattern 234 in the first direction may be less than the length of a corresponding one of the insulating patterns 175 in the first direction, and may gradually decrease from the tunnel insulating pattern 240 to the first barrier pattern 220. In some example embodiments, the absolute value of the slope of the upper surface or the lower surface of each of the separation patterns 234 relative to the upper surface of the substrate 100 may gradually decrease from the tunnel insulating pattern 240 to the first barrier pattern 220. The separation pattern 234 may be convex, for example, may be convex in the third direction from the tunnel insulating pattern 240 to the first barrier pattern 220.

[0043] In some example embodiments, bottom surfaces of the tunnel insulating pattern 240 and the charge trapping pattern 232 of the first charge storing structure 252 may be higher than a bottom surface of the first blocking pattern 220 of the first charge storing structure 252 .

[0044] The dummy charge storage structure 250 may include a tunnel insulation pattern 240, a dummy charge trapping pattern 230, and a first barrier pattern 220 sequentially stacked from the channel 260. Hereinafter, the tunnel insulation pattern 240 and the first barrier pattern 220 of the dummy charge storage structure 250 may be referred to as a dummy tunnel insulation pattern and a dummy first barrier pattern, respectively, to be distinguished from the tunnel insulation pattern 240 and the first barrier pattern 220 of the first charge storage structure 252. Therefore, the dummy charge storage structure 250 may include a dummy tunnel insulation pattern 240, a dummy charge trapping pattern 230, and a dummy first barrier pattern 220 sequentially stacked. Each of the dummy tunnel insulation pattern 240 and the dummy first barrier pattern 220 may include an oxide (e.g., the same silicon oxide as the first charge storage structure 252).

[0045] The dummy charge trapping pattern 230 may include at least one of silicon and a silicon compound, for example, at least one of silicon carbonitride, silicon boronitride, silicon doped with carbon, silicon doped with nitrogen, and the like.

[0046] Each of the dummy tunnel insulating pattern 240 , the dummy charge trapping pattern 230 , and the dummy first barrier pattern 220 included in the dummy charge storing structure 250 may have a single-layered structure covering the bottom surface and outer sidewalls of the lower end of the channel 260 .

[0047] In some example embodiments, an upper surface of the dummy charge storage structure 250 may have a shape corresponding to a lower surface of the first charge storage structure 252. Thus, upper surfaces of the dummy tunnel insulating pattern 240 and the dummy charge trapping pattern 230 of the dummy charge storage structure 250 may be lower than an upper surface of the first barrier pattern 220 of the dummy charge storage structure 250.

[0048] An inner space formed by the cup-shaped channel 260 may be filled with a filling pattern 270. The filling pattern 270 may include oxide (eg, silicon oxide).

[0049] The pad 280 may be formed on the channel 260, the first charge storing structure 252, and the filling pattern 270, and thus may be connected to the channel 260. The pad 280 may include polysilicon (eg, undoped polysilicon or doped polysilicon).

[0050] The CSP 390 may extend in the second direction and may form a separation structure together with a second spacer 380 on each of the opposite sidewalls of the CSP 390 in the third direction to separate each of the gate electrodes 372, 374, and 376 in the third direction. A plurality of CSPs 390 may be spaced apart from each other in the third direction. The CSP 390 may include a metal (e.g., at least one of tungsten, copper, aluminum, etc.).

[0051] When the second spacer 380 covers the sidewalls of the CSP 390, the CSP 390 may be electrically insulated from the adjacent gate electrodes 372, 374, and 376. The second spacer 380 may include an oxide (eg, silicon oxide).

[0052] An impurity region 105 may be formed at an upper portion of the substrate 100 contacting the bottom surface of the CSP 390. The impurity region 105 may include silicon (e.g., single crystal silicon doped with n-type impurities such as phosphorus and / or arsenic). When the impurity region 105 is formed, the contact resistance between the CSP 390 and the substrate 100 may be reduced.

[0053] The support layer 160 may be formed on the channel connection pattern 330, and the support pattern 165 may be connected to the support layer 160 on the substrate 100. The support layer 160 may extend in the second direction between the separation structures adjacent in the third direction, and a plurality of support patterns 165 may be formed in each of the second direction and the third direction. The support layer 160 and the support pattern 165 may include substantially the same material (e.g., doped polysilicon or undoped polysilicon), and may be formed integrally with each other, for example, may be formed simultaneously.

[0054] The first to third insulating interlayers 190 , 290 , and 400 may include oxide (eg, silicon oxide) and thus may be merged with each other, eg, may be homogenized with each other, eg, may be homogenized with each other through a thermal process and / or other processing steps.

[0055] The contact plug 410 may extend through the second insulating interlayer 290 and the third insulating interlayer 400 to contact the upper surface of the pad 280, and the bit line 430 may extend in the third direction to be electrically connected to the contact plug 410 arranged in the third direction. Therefore, a current generated by a voltage applied from the bit line 430 may flow to the channel 260 through the contact plug 410 and the pad 280. In some example embodiments, a plurality of bit lines 430 may be formed to be spaced apart from each other in the second direction.

[0056] The contact plug 410 and the bit line 430 may include at least one of metal, metal nitride, metal silicide, doped polysilicon, and the like.

[0057] The vertical memory device may include a first charge storage structure 252 covering the outer sidewall of the portion of the channel 260 extending through the gate electrode structure, and the first charge storage structure 252 may include charge trapping patterns 232 that are spaced apart from each other in the first direction by the separation pattern 234 and face one of the gate electrodes 372, 374, and 376 in the horizontal direction. Therefore, the charges trapped in each charge trapping pattern 232 do not move / be moved in the first direction through the gate electrodes 372, 374, and 376 at other levels, and the retention characteristics may be enhanced and / or improved. Therefore, the vertical memory device including the first charge storage structure 252 may have improved reliability.

[0058] Figures 3 to 11 is a cross-sectional view illustrating a method of manufacturing a vertical memory device according to some example embodiments. Fig. 9 and Fig.10 yes Figure 8 An enlarged cross-sectional view of region X.

[0059] Reference Figure 3 , a sacrificial layer structure 140 may be formed on the substrate 100, and may be partially removed to form a first opening 150 exposing the upper surface of the substrate 100. The sacrificial layer structure 140 may be formed using a chemical vapor deposition (CVD) process such as an atomic layer deposition (ALD) and / or a plasma enhanced chemical vapor deposition (PECVD) process. The first opening 150 may be formed using a photolithography process. A support layer 160 may be formed on the substrate 100 and the sacrificial layer structure 140 to at least partially fill the first opening 150. The support layer 160 may be formed using a suitable process such as a PECVD process.

[0060] The sacrificial layer structure 140 may include first to third sacrificial layers 110, 120, and 130 sequentially stacked in a first direction on the substrate 100. Each of the first sacrificial layer 110 and the third sacrificial layer 130 may include an oxide (e.g., silicon oxide), and the second sacrificial layer 120 may include a nitride (e.g., silicon nitride). Each of the first to third sacrificial layers 110, 120, and 130 may be formed simultaneously.

[0061] The support layer 160 may include a material having an etching selectivity with respect to the first to third sacrificial layers 110, 120, and 130. For example, the support layer 160 may be formed of doped polysilicon or undoped polysilicon or may include doped polysilicon or undoped polysilicon. In some example embodiments, the support layer 160 may be formed by depositing doped polysilicon or undoped amorphous silicon, and by performing a heat treatment or by thermal crystallization generated during a deposition process of other structures to include doped polysilicon or undoped polysilicon. The support layer 160 may be deposited using a CVD process.

[0062] The support layer 160 may be conformally deposited. The support layer 160 may have a uniform thickness, and thus a first recess may be formed on a portion of the support layer 160 in the first opening 150. Hereinafter, the portion of the support layer 160 in the first opening 150 may be referred to as a support pattern 165.

[0063] An insulating layer 170 may be formed on the supporting layer 160 to fill the first recess, and an upper portion of the insulating layer 170 may be planarized. The planarization process may include a chemical mechanical polishing (CMP) process and / or an etch-back process.

[0064] The fourth sacrificial layer 180 and the insulating layer 170 may be alternately and repeatedly formed on the insulating layer 170, and thus a mold layer may be formed on the substrate 100. Each of the fourth sacrificial layer 180 and the insulating layer 170 may be formed simultaneously; however, the inventive concept is not limited thereto. Figure 3 , eight layers of the fourth sacrificial layer 180 and the insulating layer 170 are shown, but the inventive concept is not limited thereto, and the number of layers of the fourth sacrificial layer 180 and the insulating layer 170 alternately stacked may be an integer greater than 8 or less than 8. The fourth sacrificial layer 180 may include a material having an etching selectivity relative to the insulating layer 170 (e.g., a nitride such as silicon nitride).

[0065] A patterning process using a photoresist pattern (not shown) as an etching mask may be performed on the insulating layer 170 and the fourth sacrificial layer 180, and a trimming process for reducing the area of ​​the photoresist pattern may also be performed. The patterning process and the trimming process may be alternately and repeatedly performed to form a molding having a plurality of stepped layers, each of which includes the fourth sacrificial layer 180 and the insulating layer 170 sequentially stacked on the substrate 100.

[0066] Reference Figure 4 A first insulating interlayer 190 may be formed on the uppermost insulating layer 170, and a channel hole 200 may be formed through the first insulating interlayer 190 and the molding to expose the upper surface of the substrate 100 by a dry etching process capable of etching a high aspect ratio hole (e.g., by a dry etching process such as a reactive ion etching (RIE) process).

[0067] In some example embodiments, the dry etching process may be performed until the upper surface of the substrate 100 may be exposed, and the upper portion of the substrate 100 may also be removed in the dry etching process. In some example embodiments, a plurality of channel holes 200 may be formed in each of the second direction and the third direction, and thus a channel hole array may be defined.

[0068] A preliminary charge storage structure 250, a channel 260, a filling pattern 270, and a pad 280 may be formed in the channel hole 200. The preliminary charge storage structure 250, the channel 260, and the filling pattern 270 may be simultaneously formed in situ using an ALD process; however, the inventive concept is not limited thereto. For example, the preliminary charge storage structure 250 may be formed at a different time than either or both of the channel 260 and the filling pattern 270.

[0069] Specifically, a preliminary charge storage structure layer and a channel layer may be sequentially formed on the sidewalls of the channel hole 200, the exposed upper surface of the substrate 100, and the upper surface of the first insulating interlayer 190, a filling layer may be formed on the channel layer to fill the remaining portion of the channel hole 200, and the filling layer, the channel layer, and the preliminary charge storage structure layer may be planarized (for example, planarized using CMP and / or etch-back processes) until the upper surface of the first insulating interlayer 190 may be exposed.

[0070] Through the planarization process, a preliminary charge storage structure 250 and a channel 260 , each of which may have a cup shape and be sequentially stacked on the sidewall of the channel hole 200 and the upper surface of the substrate 100 , may be formed, and a filling pattern 270 may fill an inner space formed by the channel 260 .

[0071] Since the channel hole 200 formed with the channels 260 may define a channel hole array, the channels 260 in the channel hole 200 may also define a channel array.

[0072] In some example embodiments, the preliminary charge storage structure 250 may include a first barrier pattern 220, a preliminary charge trapping pattern 230, and a tunnel insulating pattern 240, which are sequentially stacked. For example, the first barrier pattern 220 and the tunnel insulating pattern 240 may include an oxide (e.g., silicon oxide). The preliminary charge trapping pattern 230 may include silicon or a silicon compound, for example, at least one of silicon carbon nitride, silicon boron nitride, and silicon doped with nitrogen and / or carbon.

[0073] The filling pattern 270, the trench 260 and the upper portion of the preliminary charge storage structure 250 may be removed to form a second recess, a pad layer may be formed on the first insulating interlayer 190 to fill the recess, and the pad layer may be planarized using, for example, a CMP and / or etch-back process until the upper surface of the first insulating interlayer 190 may be exposed to form a pad 280.

[0074] Reference Figure 5 , a second insulating interlayer 290 may be formed on the first insulating interlayer 190 and the pad 280, and a second opening 300 may be formed through the first insulating interlayer 190 and the second insulating interlayer 290 and the molding by a dry etching process (e.g., an RIE process) capable of etching a high aspect ratio hole.

[0075] In some example embodiments, the dry etching process may be performed until the upper surface of the supporting layer 160 and / or the upper surface of the supporting pattern 165 are exposed, and the upper portion of the supporting layer 160 and / or the upper portion of the supporting pattern 165 may also be removed during the dry etching process. When the second opening 300 is formed, the insulating layer 170 and the fourth sacrificial layer 180 of the molding may be exposed.

[0076] In some example embodiments, the second opening 300 may extend in the second direction, and a plurality of second openings 300 may be formed in the third direction. When forming the second opening 300, the insulating layer 170 may be transformed into the insulating pattern 175 extending in the second direction, and the fourth sacrificial layer 180 may be transformed into the fourth sacrificial pattern 185 extending in the second direction.

[0077] A first spacer layer can be formed on the sidewalls of the second opening 300, the exposed upper surface of the second opening 300, and the upper surface of the second insulating interlayer 290, for example, using a PECVD process, and the first spacer layer can be anisotropically etched, for example, using a dry etching process, to remove portions of the first spacer layer on the upper surfaces of the support layer 160 and the support pattern 165, so that the first spacer 310 is formed and the upper surfaces of the support layer 160 and the support pattern 165 can be exposed again.

[0078] In some example embodiments, the first spacer 310 may include, for example, undoped amorphous silicon and / or undoped polysilicon. When the first spacer 310 includes undoped amorphous silicon, the undoped amorphous silicon may be crystallized during a subsequent deposition and / or thermal process.

[0079] Portions of the support layer 160 and the support pattern 165 that are not covered by the first spacer 310 and portions of the sacrificial layer structure 140 below the portions may be removed to expand the second opening 300 in a downward direction. Thus, the second opening 300 may expose the upper surface of the substrate 100 and further extend through the upper portion of the substrate 100 (e.g., extend into the upper portion of the substrate 100).

[0080] When the sacrificial layer structure 140 is partially removed, the sidewall of the second opening 300 may be covered by the first spacer 310, and the first spacer 310 includes a material different from that of the sacrificial layer structure 140 so that the insulating pattern 175 and the fourth sacrificial pattern 185 included in the molded part may not be removed.

[0081] Reference Figure 6 , the sacrificial layer structure 140 exposed by the second opening 300 may be removed to form a first gap 320 exposing the lower outer sidewall of the preliminary charge storage structure 250 , and the portion of the preliminary charge storage structure 250 exposed by the first gap 320 may be further removed to expose the lower outer sidewall of the channel 260 .

[0082] The sacrificial layer structure 140 and the preliminary charge storage structure 250 may be removed by a wet etching process using, for example, hydrofluoric acid (treated with a buffer) and / or by a dry etching process using, for example, hydrogen fluoride. When forming the first gap 320, the support layer 160 and the support pattern 165 may not be removed so that the molded part does not collapse.

[0083] When the first gap 320 is formed, the preliminary charge storage structure 250 may be divided into an upper portion extending through the molding to cover almost the entire outer sidewall of the channel 260 and a lower portion covering the bottom surface of the channel 260 on the substrate 100 .

[0084] Hereinafter, the upper portion of the preliminary charge storage structure 250 covering almost the entire outer sidewall of the channel 260 may be referred to as the preliminary charge storage structure 250, and the lower portion of the preliminary charge storage structure 250 covering the bottom surface of the channel 260 on the substrate 100 may be referred to as a dummy charge storage structure. The tunnel insulating pattern 240, the preliminary charge trapping pattern 230, and the first barrier pattern 220 included in the dummy charge storage structure 250 may be referred to as a dummy tunnel insulating pattern, a dummy charge trapping pattern, and a dummy first barrier pattern, respectively.

[0085] Reference Figure 7 , after removing the first spacer 310 , a channel connection pattern 330 may be formed to fill the first gap 320 .

[0086] By forming a channel connection layer on the substrate 100 and the second insulating interlayer 290 to fill the second opening 300 and the first gap 320 and performing an etch-back process on the channel connection layer, the channel connection pattern 330 may be formed, for example, using a PECVD process and / or using a low pressure chemical vapor deposition (LPCVD) process. For example, the channel connection layer may include amorphous silicon doped with n-type impurities (e.g., phosphorus), and may be crystallized by heat generated during a subsequent deposition / thermal process to include polysilicon doped with n-type impurities. When the channel connection pattern 330 is formed, the channels 260 between the second openings 300 adjacent in the third direction may be connected to each other to form a channel block.

[0087] The air gap 340 may be formed in the channel connection pattern 330 ; however, the inventive concept is not limited thereto.

[0088] Reference Figure 8 For example, impurities (e.g., n-type impurities including at least one of phosphorus and arsenic and / or p-type impurities including boron) can be implanted into the upper portion of the substrate 100 exposed by the second opening 300 to form an impurity region 105, for example, using a beam-line implantation process.

[0089] The fourth sacrificial pattern 185 may be removed to form a second gap 350 exposing the outer sidewalls of the preliminary charge storage structure 250. The fourth sacrificial pattern 185 may be removed by a wet etching process using, for example, phosphoric acid and / or hydrofluoric acid (treated with a buffer) and / or by a dry etching process.

[0090] Reference Fig. 9 , a first nitridation process may be performed on the preliminary charge storage structure 250 through the second gap 350 .

[0091] In some example embodiments, the first nitridation process may include using nitrogen (N), nitric oxide (NO), ammonia (NH 3 ) and / or a rapid thermal nitridation (RTN) process, and / or an annealing process. Through the first nitridation process, the preliminary charge trapping pattern 230 of the preliminary charge storage structure 250 may be partially nitrided to form a charge trapping pattern 232.

[0092] A first nitridation process may be performed on preliminary charge trapping pattern 230 through portions of first barrier pattern 220 exposed by second gap 350. Thus, nitrogen may be implanted into portions of preliminary charge trapping pattern 230 overlapping second gap 350 in a horizontal direction substantially parallel to the upper surface of substrate 100 and portions of preliminary charge trapping pattern 230 adjacent to second gap 350 in the first direction, so that portions of preliminary charge trapping pattern 230 including silicon (e.g., silicon without nitrogen) may be transformed into charge trapping pattern 232 including silicon nitride (SiN).

[0093] In some example embodiments, a plurality of charge trapping patterns 232 may be formed to be spaced apart from each other in the first direction, and a first length L1 in the first direction of an inner sidewall of each of the charge trapping patterns 232 contacting the tunnel insulating pattern 240 may be smaller than a second length L2 in the first direction of an outer sidewall of each of the charge trapping patterns 232 contacting the first barrier pattern 220. However, the first length L1 of each of the charge trapping patterns 232 may be greater than a third length L3 in the first direction of a corresponding one of the second gaps 350.

[0094] In some example embodiments, the length of each of the charge trapping patterns 232 in the first direction may gradually increase from the tunnel insulating pattern 240 to the first barrier pattern 220, and the absolute value of the slope of the upper surface or the lower surface of each of the charge trapping patterns 232 relative to the upper surface of the substrate 100 may decrease from the tunnel insulating pattern 240 to the first barrier pattern 220. In some example embodiments, the charge trapping pattern 232 may be concave, for example, concave in the third direction from the tunnel insulating pattern 240 to the first barrier pattern 220.

[0095] Reference Fig.10 , a first oxidation process may be performed on the preliminary charge storage structure 250 through the second gap 350 .

[0096] In some example embodiments, the first oxidation process may include at least one of a rapid thermal oxidation (RTO) process, an annealing process, a dry oxidation process, a wet oxidation process, and the like. The first oxidation process may be or may include a selective oxidation process in which the charge trapping pattern 232 including silicon nitride may not be oxidized or may be only partially oxidized, for example, the charge trapping pattern 232 including silicon nitride may not be oxidized due to the inclusion of nitride. For example, the charge trapping pattern 232 may be used as an oxidation preventing pattern (or oxidation reducing pattern) during the first oxidation process. Through the first oxidation process, the remaining portion of the preliminary charge trapping pattern 230 in the preliminary charge storage structure 250 may be oxidized, and the separation pattern 234 may be formed.

[0097] However, a lower portion of the preliminary charge trapping pattern 230 may not be affected by the first nitridation process or the first oxidation process so as not to be converted into the charge trapping pattern 232 or the separation pattern 234 but remain, eg, remain as the preliminary charge trapping pattern 230 .

[0098] Through the first oxidation process, a portion of the preliminary charge trapping pattern 230 between the charge trapping patterns 232 adjacent to each other in the first direction may be oxidized to form a silicon oxide (SiO 2 ) of the separation pattern 234. In some example embodiments, an absolute value of a slope of an upper surface or a lower surface of the separation pattern 234 relative to an upper surface of the substrate 100 may gradually decrease from the tunnel insulating pattern 240 to the first barrier pattern 220.

[0099] Hereinafter, the tunnel insulating pattern 240, the charge trapping pattern 232, the separation pattern 234, and the first barrier pattern 220 may be referred to as a first charge storage structure 252. For example, the first charge storage structure 252 may be formed on the outer sidewall of the channel 260 on the channel connection pattern 330, and the dummy charge storage structure 250 may be formed on the outer sidewall and bottom surface of the channel 260 below the channel connection pattern 330.

[0100] Reference Fig.11 A second blocking layer may be formed on the exposed outer sidewalls of the first charge storage structure 252, the inner wall of the second gap 350, the surface of the insulating pattern 175, the sidewalls of the support layer 160 and the support pattern 165, the sidewalls of the channel connection pattern 330, the upper surface of the substrate 100, and the upper surface of the second insulating interlayer 290, and a gate electrode layer may be formed on the second blocking layer. The gate electrode layer may include a gate barrier layer and a gate conductive layer sequentially stacked.

[0101] The gate electrode layer may be partially removed to form a gate electrode in each of the second gaps 350. In some example embodiments, the gate electrode layer may be partially removed by a wet etching process.

[0102] In some example embodiments, the gate electrode may extend in the second direction, and a plurality of gate electrodes may be formed in the first direction. Additionally or alternatively, a plurality of gate electrodes may be formed in the third direction. For example, the gate electrodes, each of which may extend in the second direction, may be spaced apart from each other by the second opening 300.

[0103] The gate electrodes may include a first gate electrode 372 , a second gate electrode 374 , and a third gate electrode 376 .

[0104] A second spacer layer may be formed on the second barrier layer (eg, within the second opening 300) and anisotropically etched to form second spacers 380 on sidewalls of the second opening 300. Thus, an upper surface of the second barrier layer on the substrate 100 may be partially exposed.

[0105] Portions of the second barrier layer not covered by the second spacers 380 may be etched to form a second barrier pattern 360, and portions of the second barrier layer on the upper surface of the second insulating interlayer 290 may also be removed. In addition, an upper portion of the impurity region 105 may be partially removed.

[0106] A conductive layer may be formed on the upper surface of the impurity region 105, the second spacer 380, and the second insulating interlayer 290 (e.g., using a PECVD process or using a PECVD process and a sputtering process) to fill the remaining portion of the second opening 300. The conductive layer may be planarized, for example, the conductive layer may be planarized using a CMP process and / or using an etch-back process until the upper surface of the second insulating interlayer 290 may be exposed to form the CSP 390. The CSP 390 may include a metal such as tungsten, and / or may include a (doped) polysilicon layer; however, the inventive concept is not limited thereto.

[0107] Refer again Figure 1 and Figure 2 After forming a third insulating interlayer 400 on the second insulating interlayer 290 , the CSP 390 , the second spacer 380 , and the second barrier pattern 360 , a contact plug 410 may be formed through the second insulating interlayer 290 and the third insulating interlayer 400 to contact an upper surface of the pad 280 .

[0108] The bit line 430 may be formed to contact an upper surface of the contact plug 410 , so that a vertical memory device may be manufactured.

[0109] As described above, a first nitridation process may be performed on preliminary charge storage structure 250 including preliminary charge trapping patterns 230 to form a plurality of charge trapping patterns 232 spaced apart from one another, and a first oxidation process may be performed to form separation patterns 234 between charge trapping patterns 232. For example, instead of performing a physical process such as a cutting process and / or a patterning process on preliminary charge trapping patterns 230 extending in the first direction, a chemical process such as a nitridation process and / or an oxidation process may be performed so that charge trapping patterns 232 facing gate electrodes 372, 374, and 376 may be formed to be spaced apart from one another in the first direction.

[0110] Fig.12 is a cross-sectional view illustrating a vertical memory device according to some example embodiments, and is Figure 1 In addition to the charge storage structure, the vertical memory device can be connected with Figure 1 and Figure 2 Therefore, the same reference numerals denote the same elements, and repeated descriptions thereof are omitted herein.

[0111] Reference Fig.12 , the vertical memory device may include a second charge storage structure 254 instead of or in addition to the first charge storage structure 252, and the second charge storage structure 254 may include a tunnel insulating pattern 240, a preliminary charge trapping pattern 230, a charge trapping pattern 232, and a first barrier pattern 220 sequentially stacked in a horizontal direction from an outer sidewall of the channel 260. The second charge storage structure 254 may also include a separation pattern 234.

[0112] The preliminary charge trapping pattern 230 may be a remaining portion of the preliminary charge trapping pattern 230 that is not converted into the charge trapping pattern 232 by the first nitridation process, which may be referred to as a first charge trapping pattern hereinafter, and the charge trapping pattern 232 may be referred to as a second charge trapping pattern.

[0113] For example, the second charge storage structure 254 may include a first charge trapping pattern 230 and a second charge trapping pattern 232, which face a corresponding one of gate electrodes 372, 374, and 376 spaced apart from each other in the first direction between a tunnel insulating pattern 240 and a first barrier pattern 220, each of which may extend in the first direction. The first charge trapping pattern 230 may include silicon or a silicon compound, for example, at least one of silicon carbon nitride, silicon boron nitride, and silicon doped with at least one of nitrogen and carbon. The second charge trapping pattern 232 may include, for example, silicon nitride.

[0114] In some example embodiments, a fifth length L5 of the first charge trapping pattern 230 in the first direction may gradually decrease from the tunnel insulating pattern 240 to the second charge trapping pattern 232 .

[0115] In some example embodiments, second charge trapping pattern 232 may include a first portion 232a covering an outer sidewall of first charge trapping pattern 230 and contacting first barrier pattern 220, and a second portion 232b extending from first portion 232a toward tunnel insulating pattern 240 to cover upper and lower surfaces of first charge trapping pattern 230. A length of first portion 232a of second charge trapping pattern 232 in the first direction may gradually increase as it approaches first barrier pattern 220, and second portion 232b of second charge trapping pattern 232 may be inclined with respect to an upper surface of substrate 100.

[0116] In some example embodiments, a length of the second charge trapping pattern 232 in the first direction, such as a maximum length, i.e., a sixth length L6 of the first portion 232a of the second charge trapping pattern 232 contacting the first barrier pattern 220 may be greater than a fourth length L4 of a corresponding one of the gate electrodes 372, 374, and 376 in the first direction or may be greater than a third length L3 of the second gap 350 in which each of the gate electrodes 372, 374, and 376 may be formed in the first direction.

[0117] The separation pattern 234 may be formed between the first and second charge trapping patterns 230 and 232 adjacent in the first direction, so that the first and second charge trapping patterns 230 and 232 may be spaced apart from each other in the first direction. The separation pattern 234 may face the insulating pattern 175 in the horizontal direction, specifically, the central portion of the insulating pattern 175 in the first direction.

[0118] In some example embodiments, the separation pattern 234 may include a first portion 234a whose length in the first direction may gradually increase from the tunnel insulating pattern 240 toward the first barrier pattern 220, and a second portion 234b whose length in the first direction may gradually decrease from the first portion 234a toward the first barrier pattern 220. A length such as a minimum length of the first portion 234a of the separation pattern 234 in the first direction, i.e., a seventh length L7 of the first portion 234a of the separation pattern 234 contacting an inner sidewall of the tunnel insulating pattern 240 in the first direction may be greater than a length such as a minimum length of the second portion 234b of the separation pattern 234 in the first direction, i.e., an eighth length L8 of the second portion 234b of the separation pattern 234 contacting an outer sidewall of the first barrier pattern 220 in the first direction.

[0119] In some example embodiments, the separation pattern 234 may include substantially the same material as that of the first barrier pattern 220 (eg, silicon oxide), and thus may be merged therewith, for example, may be merged therewith in a subsequent heat treatment step.

[0120] Figures 13 to 16 is a cross-sectional view illustrating a method of manufacturing a vertical memory device according to some example embodiments, and specifically, Figure 1 The method may include: Figures 3 to 11 as well as Figure 1 and Figure 2 The processes are substantially the same or similar processes, and thus repeated description thereof is omitted herein.

[0121] Reference Fig.13 , executable and reference Figures 3 to 9 The processes shown are substantially the same or similar processes.

[0122] However, in addition to referring to Figures 3 to 9 In addition to or instead of the illustrated process, a first nitridation process may be performed on the preliminary charge storing structure 250 through the second gap 350 so that only a portion of the preliminary charge trapping pattern 230 adjacent to the first barrier pattern 220 may be nitrided to form a charge trapping pattern 232 .

[0123] Reference Fig.14 , executable and reference Fig.10 The processes shown are substantially the same or similar processes.

[0124] For example, a first oxidation process may be performed on the preliminary charge storing structure 250 through the second gap 350 , and thus portions of the preliminary charge trapping pattern 230 facing the insulating pattern 175 in a horizontal direction may be oxidized to form the separation pattern 234 .

[0125] The charge trapping pattern 232 contacting the first barrier pattern 220 and the preliminary charge trapping pattern 230 contacting the tunnel insulating pattern 240 may be formed between the separation patterns 234 adjacent in the first direction.

[0126] Reference Fig.15 , a second nitridation process may be performed on the preliminary charge storage structure 250 through the second gap 350 to form a second charge storage structure 254 .

[0127] The second nitridation process may be substantially the same as the first nitridation process, and thus the preliminary charge trapping pattern 230 may be partially nitrided to further form the charge trapping pattern 232 .

[0128] In some example embodiments, the lower and upper ends of the preliminary charge trapping pattern 230 may be nitrided by a second nitridation process, and the nitrided portions may be merged into the already formed charge trapping pattern 232 .

[0129] Reference Fig.16 , a curing process may be performed on the second charge storage structure 254 through the second gap 350 .

[0130] The curing process may be performed on the first barrier pattern 220 including, for example, silicon oxide, and may cure the first barrier pattern 220 damaged by the previous first and second nitridation processes. In some example embodiments, the curing process may include a wet etching process.

[0131] The wet etching process may affect the separation pattern 234 , and thus the separation pattern 234 and the first barrier pattern 220 may include substantially the same material to be merged therewith.

[0132] Executable and Reference Fig.11 as well as Figure 1 and Figure 2 The processes shown are substantially the same or similar processes to complete the fabrication of a vertical memory device.

[0133] Fig.17 is a cross-sectional view illustrating a vertical memory device according to some example embodiments, and is Figure 1 An enlarged cross-sectional view of region X.

[0134] Reference Fig.17 , the vertical memory device may include a third charge storage structure 256 instead of or in addition to the first charge storage structure 252, and the third charge storage structure 256 may include a tunnel insulating pattern 240, a first charge trapping pattern 230, a third charge trapping pattern 236, and a first blocking pattern 220 sequentially stacked in a horizontal direction from an outer sidewall of the channel 260. The third charge storage structure 256 may also include a separation pattern 234.

[0135] The third charge storage structure 256 may include a first charge trapping pattern 230 and a third charge trapping pattern 236 facing a corresponding one of gate electrodes 372, 374, and 376 spaced apart from each other in the first direction between a tunnel insulating pattern 240 and a first barrier pattern 220 each of which may extend in the first direction. The third charge trapping pattern 236 may include, for example, silicon nitride.

[0136] In some example embodiments, third charge trapping pattern 236 may cover outer sidewalls and lower and upper surfaces of first charge trapping pattern 230. Separation pattern 234 may extend in the first direction to cover outer sidewalls and lower and upper surfaces of third charge trapping pattern 236. Thus, first charge trapping pattern 230 and third charge trapping pattern 236 may be spaced apart from each other in the first direction by separation pattern 234.

[0137] In some example embodiments, the separation pattern 234 may have a thickness greater than that of the tunnel insulating pattern 240 or the first barrier pattern 220. The separation pattern 234 may include substantially the same material as that of the first barrier pattern 220 and thus may be merged therewith.

[0138] Figures 18 to 22 is a cross-sectional view illustrating a method of manufacturing a vertical memory device according to some example embodiments, and specifically, Figure 1 An enlarged cross-sectional view of region X.

[0139] Reference Fig.18 , executable and reference Figures 3 to 9 The processes shown are substantially the same or similar processes.

[0140] However, the thickness of the preliminary charge trapping pattern 230 may be greater than the thickness of the tunnel insulating pattern 240 or the first barrier pattern 220, and when the first nitridation process is performed on the preliminary charge storage structure 250 through the second gap 350, only the portion of the preliminary charge trapping pattern 230 adjacent to the first barrier pattern 220 may be nitrided to form a charge trapping pattern 232.

[0141] Reference Fig.19 , executable and reference Fig.10 The processes shown are substantially the same or similar processes.

[0142] For example, the first oxidation process may be performed on preliminary charge storing structure 250 through second gap 350, and thus a portion of preliminary charge trapping pattern 230 facing insulating pattern 175 in a horizontal direction may be oxidized to form separation pattern 234. However, since preliminary charge trapping pattern 230 has a relatively large thickness, only a portion of preliminary charge trapping pattern 230 adjacent to insulating pattern 175 may be oxidized to form separation pattern 234, and preliminary charge trapping pattern 230 may not be divided into a plurality of pieces in the first direction by the first oxidation process.

[0143] Reference Fig. 20 , a second oxidation process may be performed on the preliminary charge storage structure 250 through the second gap 350 .

[0144] In some example embodiments, the second oxidation process may include a radical oxidation process using at least one of oxygen radicals (O*), hydroxyl radicals (OH*), etc., and unlike the first oxidation process, not only the preliminary charge trapping pattern 230 but also the charge trapping pattern 232 including silicon nitride may be oxidized.

[0145] Therefore, the separation pattern 234 may be expanded by the second oxidation process to cover the outer sidewalls and the lower and upper surfaces of the preliminary charge trapping pattern 230 that may extend in the first direction and have not yet been converted into the charge trapping pattern 232. The separation pattern 234 before expansion may be referred to as a preliminary separation pattern compared to the separation pattern 234 after expansion. The preliminary charge trapping pattern 230 may be divided into a plurality of pieces spaced apart from each other in the first direction by the second oxidation process.

[0146] Reference Fig.21 , a second nitridation process may be performed on the preliminary charge storage structure 250 through the second gap 350 to form a third charge storage structure 256 .

[0147] When the second nitridation process is performed, the outer sidewalls and the lower and upper surfaces of the preliminary charge trapping pattern 230 may be nitrided to form a third charge trapping pattern 236 including silicon nitride.

[0148] Reference Fig. 22 , a curing process may be performed on the third charge storing structure 256 through the second gap 350 , and thus the first barrier pattern 220 damaged due to the previous first and second nitridation processes may be cured.

[0149] The curing process may affect the separation pattern 234 , and thus the separation pattern 234 and the first barrier pattern 220 may include substantially the same material to be merged therewith.

[0150] Executable and Reference Fig.11 as well as Figure 1 and Figure 2 The processes shown are substantially the same or similar processes to complete the fabrication of a vertical memory device.

[0151] Fig.23 is a cross-sectional view illustrating a vertical memory device according to some example embodiments, and is Figure 1 In addition to the separation pattern and the first barrier pattern, the vertical memory device may be Fig.17 The vertical memory devices are substantially the same or similar.

[0152] Reference Fig.23 , the vertical memory device may include a fourth charge storage structure 258 instead of or in addition to the third charge storage structure 256, and the fourth charge storage structure 258 may include a tunnel insulating pattern 240, a first charge trapping pattern 230, a third charge trapping pattern 236, and a first barrier pattern 220 sequentially stacked in a horizontal direction from an outer sidewall of a channel 260. The first barrier pattern 220 may extend in the first direction to separate each of the first charge trapping pattern 230 and the third charge trapping pattern 236, and thus may serve as a separation pattern 234.

[0153] Figure 24 to Figure 26 is a cross-sectional view illustrating a method of manufacturing a vertical memory device according to some example embodiments, and specifically, Figure 1 The method may include referring to Figures 18 to 22 and Fig.17 The processes shown are substantially the same or similar processes, and thus repeated descriptions thereof are omitted herein.

[0154] Reference Fig.24 , executable and reference Fig.18 The processes shown are substantially the same or similar processes.

[0155] However, the preliminary charge storage structure 250 may not include the first barrier pattern 220, and thus the first nitridation process may be performed directly on the preliminary charge trapping pattern 230 without passing through the first barrier pattern 220. Through the first nitridation process, only a portion of the preliminary charge trapping pattern 230 adjacent to the second gap 350 may be nitrided to form the charge trapping pattern 232.

[0156] Reference Fig.25 , executable and reference Fig.19 The illustrated process is substantially the same or similar process, and thus a portion of the preliminary charge trapping pattern 230 adjacent to the insulating pattern 175 may be oxidized to form a separation pattern 234 .

[0157] Reference Fig.26 , executable and reference Fig. 20 and Fig.21 The illustrated process is substantially the same or similar process such that the first charge trapping pattern 230 and the third charge trapping pattern 236 spaced apart from each other by the separation pattern 234 may be formed.

[0158] Executable and Reference Fig. 22 The process shown is substantially the same or similar to the process for forming the fourth charge storage structure 258 .

[0159] For example, a curing process such as a wet etching process may be performed to cure the separation pattern 234 , and the cured separation pattern 234 may serve as the first barrier pattern 220 .

[0160] Executable and Reference Fig.11 as well as Figure 1 and Figure 2 The processes shown are substantially the same or similar processes to complete the fabrication of a vertical memory device.

[0161] Fig. 27 is a cross-sectional view showing a vertical memory device according to some example embodiments. In addition to the channel, the dummy charge storage structure and the gate electrode, the vertical memory device may be Figure 1 and Figure 2 The vertical memory devices are substantially the same or similar.

[0162] Reference Fig. 27 ,and Figure 1 and Figure 2 Differently, the vertical memory device may not include the dummy charge storing structure 250 , the channel connection pattern 330 , the supporting layer 160 , and the supporting pattern 165 .

[0163] Furthermore, a semiconductor pattern 210 may be formed in a lower portion of the channel hole 200 , and a channel 260 and a first charge storage structure 252 may be formed on the semiconductor pattern 210 .

[0164] The first gate electrode 372 may surround a sidewall of the semiconductor pattern 210 , and each of the second gate electrode 374 and the third gate electrode 376 may surround an outer sidewall of the first charge storage structure 252 .

[0165] Fig. 27 It is illustrated that the vertical memory device includes a first charge storage structure 252 , however, the inventive concept may not be limited thereto and may include one of the second to fourth charge storage structures 254 , 256 , and 258 .

[0166] Figures 28 to 30 is a cross-sectional view illustrating a vertical memory device according to some example embodiments.

[0167] Reference Fig.28 , executable and reference Figure 3 However, the sacrificial layer structure 140 , the support layer 160 , and the support pattern 165 may not be formed on the substrate 100 , and a molding including the insulating layer 170 and the fourth sacrificial layer 180 alternately and repeatedly stacked may be formed on the substrate 100 .

[0168] Reference Fig.29 , executable and reference Figure 4 However, the semiconductor pattern 210 may be formed by a selective epitaxial growth (SEG) process to fill the lower portion of the channel hole 200, and a preliminary charge storage structure 250, a channel 260, a filling pattern 270, and a pad 280 may be formed on the semiconductor pattern 210 to fill the channel hole 200.

[0169] Reference Fig.30 , executable and reference Figures 5 to 8 However, the channel connection pattern 330 may not be formed on the substrate 100 , and the fourth sacrificial pattern 185 exposed by the second opening 300 may be removed to form a second gap 350 exposing the preliminary charge storage structure 250 and the semiconductor pattern 210 .

[0170] Refer again Fig. 27 , executable and reference Figures 9 to 11 as well as Figure 1 and Figure 2 The processes shown are substantially the same or similar processes to complete the fabrication of a vertical memory device.

[0171] While example embodiments have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and scope of the claims.

Claims

1. A vertical memory device, comprising: a channel on a substrate, the channel extending in a vertical direction perpendicular to an upper surface of the substrate; a charge storage structure on an outer sidewall of the channel, the charge storage structure comprising a tunnel insulating pattern, a charge trapping pattern, and a first blocking pattern sequentially stacked in a horizontal direction, the horizontal direction being parallel to an upper surface of the substrate; as well as gate electrodes spaced apart from each other in the vertical direction, each of the gate electrodes surrounding the charge storage structure, wherein the charge storage structure comprises charge trapping patterns spaced apart from each other in the vertical direction, each of the charge trapping patterns facing one of the gate electrodes in the horizontal direction, and Among them, a first length of an inner sidewall of at least one of the charge trapping patterns facing the tunnel insulation pattern in the vertical direction is smaller than a second length of an outer sidewall of a corresponding at least one of the charge trapping patterns facing the first blocking pattern in the vertical direction.

2. The vertical memory device according to claim 1, wherein: The first length of the at least one of the charge trapping patterns is greater than a third length of a corresponding one of the gate electrodes in the vertical direction.

3. The vertical memory device according to claim 1, wherein: An absolute value of a slope of an upper surface of each of the charge trapping patterns relative to an upper surface of the substrate gradually decreases from the tunnel insulating pattern toward the first barrier pattern.

4. The vertical memory device according to claim 1, wherein: The charge storage structure is located between charge trapping patterns among the charge trapping patterns adjacent to and contacting the tunnel insulating pattern and the first barrier pattern in the vertical direction, and wherein the charge storage structure further includes a separation pattern including silicon oxide.

5. The vertical memory device according to claim 4, wherein: An absolute value of a slope of an upper surface of the separation pattern relative to an upper surface of the substrate gradually decreases from the tunnel insulation pattern toward the first barrier pattern.

6. The vertical memory device according to claim 1, wherein: Each of the tunnel insulating pattern and the first barrier pattern extends in the vertical direction, and the charge trapping pattern is located between the tunnel insulating pattern and the first barrier pattern.

7. The vertical memory device according to claim 1, wherein: The charge trapping pattern includes silicon nitride, and each of the tunnel insulating pattern and the first barrier pattern includes silicon oxide.

8. The vertical memory device of claim 1, further comprising: A second barrier pattern covers a lower surface, an upper surface and a sidewall of each of the gate electrodes, the second barrier pattern includes a metal oxide, and the sidewall faces the charge storage structure in the horizontal direction.

9. The vertical memory device of claim 1 , further comprising: A dummy charge storage structure on the substrate, the dummy charge storage structure being spaced apart from the charge storage structure in the vertical direction, the dummy charge storage structure comprising a dummy tunnel insulating pattern, a dummy charge trapping pattern and a dummy first blocking pattern sequentially stacked from a bottom surface and a lower outer sidewall of the channel.

10. The vertical memory device of claim 9, wherein The dummy tunnel insulating pattern and the dummy first barrier pattern include the same material as that of the tunnel insulating pattern and the first barrier pattern, respectively, and The dummy charge trapping pattern includes a material different from that of the charge trapping pattern.

11. The vertical memory device according to claim 10, wherein: The dummy charge trapping pattern includes at least one of silicon carbonitride, silicon boronitride, silicon, and silicon doped with at least one of nitrogen and carbon.

12. The vertical memory device according to claim 9, wherein: The lowest gate electrode among the gate electrodes is configured to be used as a ground selection line, the uppermost gate electrode among the gate electrodes and at least one gate electrode directly below the uppermost gate electrode are respectively configured to be used as string selection lines, and each gate electrode between the ground selection line and the string selection line is respectively configured to be used as a word line.

13. The vertical memory device according to claim 1, wherein: The gate electrodes include a second gate electrode and a third gate electrode configured to function as a word line and a string selection line, respectively, and Wherein, the vertical memory device further includes a semiconductor pattern on the substrate, the semiconductor pattern contacting the channel and a bottom surface of the charge storage structure, and A first gate electrode is provided on the substrate below the second gate electrode, the first gate electrode surrounding the semiconductor pattern and configured to function as a ground selection line.

14. A vertical memory device comprising: a channel on a substrate, the channel extending in a vertical direction perpendicular to an upper surface of the substrate; a charge storage structure on an outer sidewall of the channel, the charge storage structure comprising a tunnel insulation pattern, a charge trapping pattern structure, and a blocking pattern sequentially stacked in a horizontal direction parallel to an upper surface of the substrate; as well as gate electrodes spaced apart from each other in the vertical direction, each of the gate electrodes surrounding the charge storage structure, The charge storage structure includes charge trapping pattern structures spaced apart from each other in the vertical direction, each of the charge trapping pattern structures faces a corresponding one of the gate electrodes in the horizontal direction, and Each of the charge trapping pattern structures includes a first charge trapping pattern and a second charge trapping pattern sequentially stacked in the horizontal direction on the outer sidewall of the tunnel insulation pattern, and the first charge trapping pattern and the second charge trapping pattern include different materials from each other.

15. The vertical memory device of claim 14, wherein: The first charge trapping pattern includes at least one of: silicon carbonitride, silicon boronitride, silicon, and silicon doped with at least one of nitrogen and carbon, And the second charge trapping pattern includes silicon nitride.

16. The vertical memory device of claim 14, wherein: A length of the first charge trapping pattern in the vertical direction gradually decreases from the tunnel insulating pattern toward the second charge trapping pattern.

17. The vertical memory device of claim 14, wherein: The second charge trapping pattern covers outer sidewalls and lower and upper surfaces of the first charge trapping pattern.

18. The vertical memory device of claim 14, wherein: A length of the second charge-trapping pattern in the vertical direction is greater than a length of a corresponding one of the gate electrodes in the vertical direction.

19. The vertical memory device of claim 14, wherein: The second charge trapping pattern comprises: a first portion covering an outer sidewall of the first charge trapping pattern and extending in the vertical direction; and A second portion extends from the first portion toward the tunnel insulating pattern to cover lower and upper surfaces of the first charge trapping pattern.

20. The vertical memory device of claim 14, wherein: The blocking pattern extends in the vertical direction and covers outer sidewalls and lower and upper surfaces of the charge trapping pattern.

21. A vertical memory device comprising: a channel on a substrate, the channel extending in a vertical direction perpendicular to an upper surface of the substrate; a charge storage structure on an outer sidewall of the channel, the charge storage structure comprising a tunnel insulating pattern, a charge trapping pattern, and a blocking pattern sequentially stacked in a horizontal direction parallel to an upper surface of the substrate; a dummy charge storage structure spaced apart from the charge storage structure in the vertical direction on the substrate, the dummy charge storage structure comprising a dummy tunnel insulating pattern, a dummy charge trapping pattern, and a dummy blocking pattern stacked sequentially; as well as gate electrodes spaced apart from each other in the vertical direction, each of the gate electrodes surrounding the charge storage structure, The charge storage structure includes charge trapping patterns spaced apart from each other in the vertical direction, each of the charge trapping patterns faces a corresponding one of the gate electrodes in the horizontal direction, and The dummy tunnel insulating pattern and the dummy barrier pattern include materials that are the same as those of the tunnel insulating pattern and the barrier pattern, respectively, and the dummy charge trapping pattern includes a material that is different from that of the charge trapping pattern.

22. The vertical memory device of claim 21, wherein: Each of the charge trapping patterns includes silicon nitride, and the dummy charge trapping pattern includes at least one of silicon carbonitride, silicon boronitride, silicon, and silicon doped with at least one of nitrogen and carbon.

23. The vertical memory device of claim 21, wherein Each of the charge trapping patterns includes a first charge trapping pattern and a second charge trapping pattern sequentially stacked in the horizontal direction from the tunnel insulating pattern, and The first charge trapping pattern includes a same material as that of the dummy charge trapping pattern, and the second charge trapping pattern includes a different material from that of the dummy charge trapping pattern.

24. The vertical memory device of claim 21, wherein: A length of an inner sidewall of each of the charge trapping patterns contacting the tunnel insulating pattern in the vertical direction is smaller than a length of an outer sidewall of each of the charge trapping patterns contacting the blocking pattern in the vertical direction.

25. The vertical memory device of claim 21, further comprising: A separation pattern is located between adjacent charge trapping patterns among the charge trapping patterns in the vertical direction, the separation pattern contacts the tunnel insulating pattern and the blocking pattern, and includes silicon oxide.

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