Display device

Abstract

The present disclosure relates to a display device, the display device including: a plurality of pixel circuits located at a display area having a non-quadrilateral shape; a first signal line extending in a first direction over the display area and electrically connected to a first pixel circuit among the plurality of pixel circuits; a first voltage line extending in the first direction over the display area; a first load compensation capacitor adjacent to an end of the first signal line and an end of the first voltage line; a test circuit located outside the display area; an output line electrically connected to the test circuit; and a connection portion configured to electrically connect the output line, the first signal line, and electrodes of the first load compensation capacitor to each other.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10-2019-0092034, filed on Jul. 29, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] One or more aspects of the exemplary embodiments relate to a display device, and more particularly, to a display device having a non-quadrilateral shape. Background Art

[0004] With the rapid development of display devices for visually presenting various electrical signal information, various display devices having excellent characteristics such as being thin, light, and low power consumption have been introduced. A display device includes a plurality of pixels disposed at a display area (e.g., disposed in or on the display area) and one or more driving circuits disposed around the display area (e.g., adjacent to the display area or surrounding an outer periphery of the display area) and configured to drive the plurality of pixels. Recently, there has been an increasing demand for display devices having various shapes (e.g., display devices having a non-quadrilateral shape). However, when the display area of a display device has a non-quadrilateral shape, a dead area of the display device may increase and an area of the display area may decrease. Accordingly, a display device in which the dead area is reduced and / or in which the area of the display area is increased may be desirable.

[0005] The above information disclosed in this Background Art section is only for enhancing an understanding of the background of the present disclosure, and thus, the above information may include information that does not constitute the prior art. Summary of the Invention

[0006] One or more embodiments relate to a display device having a non-quadrilateral shape.

[0007] Additional aspects and / or features will be set forth in part in the description which follows, and in part will become apparent from the description of the exemplary embodiments, or may be learned by practice of one or more exemplary embodiments of the present disclosure.

[0008] According to one or more embodiments, a display device includes: a plurality of pixel circuits located at a display area having a non-quadrilateral shape; a first signal line extending in a first direction over the display area and electrically connected to a first pixel circuit among the plurality of pixel circuits; a first voltage line extending in the first direction over the display area; a first load compensation capacitor adjacent to an end of the first signal line and an end of the first voltage line; a test circuit located outside the display area; an output line electrically connected to the test circuit; and a connection portion configured to electrically connect the output line, the first signal line, and an electrode of the first load compensation capacitor to each other.

[0009] In an embodiment, the connection portion may be between the first pixel circuit and the first load compensation capacitor.

[0010] In an embodiment, the first load compensation capacitor may include a first electrode and a second electrode overlapping each other, and one of the first electrode and the second electrode may be electrically connected to the output line and the first signal line via the connection portion.

[0011] In an embodiment, the other of the first electrode and the second electrode may be electrically connected to the first voltage line.

[0012] In an embodiment, the first load compensation capacitor may further include a third electrode overlapping the first electrode and the second electrode.

[0013] In an embodiment, the third electrode may be electrically connected to the first voltage line.

[0014] In an embodiment, the first pixel circuit may include: a first thin film transistor including a first semiconductor layer and a first gate electrode, a part of the first gate electrode overlapping the first semiconductor layer; a first capacitor electrically connected to the first thin film transistor; and a second thin film transistor located on the first thin film transistor and including a second semiconductor layer and a second gate electrode, a part of the second gate electrode overlapping the second semiconductor layer.

[0015] In an embodiment, one of the first semiconductor layer and the second semiconductor layer may include a silicon semiconductor, and the other of the first semiconductor layer and the second semiconductor layer may include an oxide semiconductor.

[0016] In an embodiment, the first load compensation capacitor may include at least two electrodes, one of the at least two electrodes including a material the same as that of the first gate electrode or the second gate electrode, and the other of the at least two electrodes including a material the same as that of the electrode of the first capacitor.

[0017] In an embodiment, the plurality of pixel circuits may have a stepped configuration at an outer periphery of the display area.

[0018] In an embodiment, the display device may further include: a second signal line that extends in the first direction over the display area and is electrically connected to a second pixel circuit different from the first pixel circuit; and a second load compensation capacitor that is adjacent to an end of the second signal line and has a capacitance smaller than that of the first load compensation capacitor.

[0019] In an embodiment, the second load compensation capacitor may be closer to a first virtual line than the first load compensation capacitor, the first virtual line extending in the first direction through a center of the display area.

[0020] In an embodiment, the display area may have a circular shape, an oval shape, or a curved polygon shape.

[0021] According to one or more embodiments, a display device includes: a plurality of pixel circuits located at a display area having a non-quadrilateral shape; a first signal line that extends in a first direction over the display area; a load compensation capacitor located outside the display area and adjacent to the first signal line, the load compensation capacitor including a first electrode and a second electrode; a connection portion between the first signal line and the load compensation capacitor, the connection portion configured to connect the first signal line to the load compensation capacitor; a test circuit located outside the display area; and an output line configured to electrically connect the test circuit to the connection portion.

[0022] In an embodiment, the connection portion may include a conductive layer between the second electrode of the load compensation capacitor and the first signal line or a conductive layer between the second electrode of the load compensation capacitor and the output line.

[0023] In an embodiment, the display device may further include a first power line adjacent to the first signal line and extending through the display area, and the first electrode of the load compensation capacitor may be electrically connected to the first power line.

[0024] In an embodiment, the load compensation capacitor may further include a third electrode positioned opposite to the first electrode, and the second electrode is between the third electrode and the first electrode.

[0025] In an embodiment, one of the plurality of pixel circuits may include: a first thin film transistor including a first semiconductor layer and a first gate electrode, a part of the first gate electrode overlapping with the first semiconductor layer; a first capacitor electrically connected to the first thin film transistor; and a second thin film transistor including a second semiconductor layer and a second gate electrode, a part of the second gate electrode overlapping with the second semiconductor layer.

[0026] In an embodiment, the second thin film transistor may be located at a layer different from that of the first thin film transistor.

[0027] In an embodiment, the first electrode and the second electrode of the load compensation capacitor may include a material the same as that of the first gate electrode, an electrode of the first capacitor, or the second gate electrode.

[0028] In an embodiment, the first semiconductor layer and the second semiconductor layer may include different materials from each other.

[0029] In an embodiment, the first semiconductor layer may include a silicon semiconductor, and the second semiconductor layer may include an oxide semiconductor.

[0030] In an embodiment, the plurality of pixel circuits may have a stepped configuration at the outer periphery of the display area.

[0031] In an embodiment, the display device may further include a pad located at one side of the display area, and the load compensation capacitor may be positioned at a side opposite to one side of the pad with respect to a virtual line that extends through the center of the display area in a second direction intersecting with the first direction.

[0032] In an embodiment, the display area may have a circular shape or an oval shape. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] From the following detailed description with reference to the accompanying drawings, the above and other aspects and features of the present disclosure will become more apparent to those skilled in the art. In the drawings:

[0034] Figure 1 is a block diagram schematically showing a display device according to an embodiment;

[0035] Figure 2is a plan view schematically showing a display device according to an embodiment;

[0036] Figure 3 is an equivalent circuit diagram of a pixel of a display device according to an embodiment;

[0037] Figure 4 is along the Figure 2 sectional view of the display device taken along line IV-IV';

[0038] Figure 5A is a plan view schematically showing the arrangement of a pixel circuit included in a pixel of a display device according to an embodiment;

[0039] Figure 5B is a plan view schematically showing a pixel circuit and a load compensation capacitor of a display device according to an embodiment;

[0040] Figure 6 is an enlarged plan view of a part of a display device according to an embodiment;

[0041] Figure 7A and Figure 7B is a circuit diagram schematically showing a sub-test circuit according to one or more embodiments;

[0042] Figure 8 is a plan view showing a part of a display device according to an embodiment;

[0043] Figure 9 is along the Figure 8 sectional view of the display device taken along line IX-IX';

[0044] Figure 10 is along the Figure 8 sectional view of the display device taken along line X-X';

[0045] Figure 11 is along the Figure 8 sectional view of the display device taken along line XI-XI';

[0046] Figure 12 is along the Figure 8 sectional view of the display device taken along line XII-XII';

[0047] Figure 13 is along the Figure 8 sectional view of the display device taken along line XIII-XIII';

[0048] Figure 14 is a sectional view showing a load compensation capacitor according to an embodiment;

[0049] Figure 15is a plan view showing a load matching part of a display device according to an embodiment;

[0050] Figure 16 is a part of the display device Figure 15 an enlarged plan view of part XVI;

[0051] Figure 17 is a part of the display device Figure 15 an enlarged plan view of part XVII;

[0052] Figure 18 is a part of the display device Figure 15 an enlarged plan view of part XVIII; and

[0053] Figure 19 is a part of the display device Figure 15 an enlarged plan view of part XIX. Detailed Description

[0054] Hereinafter, example embodiments will be described in more detail with reference to the accompanying drawings, in which like reference numerals always refer to like elements. However, the present disclosure may be implemented in various different forms and should not be construed as being limited only to the embodiments shown herein. Rather, these embodiments are provided as examples so that the present disclosure will be sufficient and complete and will fully convey the aspects and features of the present disclosure to those skilled in the art. Accordingly, unnecessary processes, elements, and techniques for those of ordinary skill in the art to fully understand the aspects and features of the present disclosure may not be described. Unless otherwise indicated, throughout the drawings and the written description, like reference numerals refer to like elements and thus, their description may not be repeated.

[0055] When a particular embodiment can be implemented differently, a particular process order may be performed differently from the described order. For example, two consecutively described processes may be performed simultaneously or substantially simultaneously, or may be performed in an order opposite to the described order.

[0056] In the accompanying drawings, for clarity, the relative dimensions of elements, layers, and regions may be exaggerated and / or simplified. For ease of illustration, spatially relative terms such as "beneath," "below," "lower," "under," "above," and "upper" may be used herein to describe the relationship of one element or feature to another element(s) or feature(s) as shown in the drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device in the drawings is flipped, an element described as "beneath" or "below" or "under" another element or feature will then be oriented "above" the other element or feature. Thus, the exemplary terms "beneath" and "below" can encompass both an upper and a lower orientation. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and thus, the spatially relative descriptors used herein should be interpreted accordingly.

[0057] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, a first element, component, region, layer, or part described below may be termed a second element, component, region, layer, or part without departing from the spirit and scope of the present disclosure.

[0058] It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, the element or layer may be directly on, directly connected to, or directly coupled to the other element or layer, or there may be one or more intervening elements or layers. For example, it will be understood that when a layer, region, or component is referred to as being "formed on" another layer, region, or component, the layer, region, or component may be formed directly or indirectly on the other layer, region, or component. That is, for example, there may be intervening layers, regions, or components. Additionally, it will also be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer may be the sole element or layer between the two elements or layers, or there may also be one or more intervening elements or layers.

[0059] The terms used herein are for the purpose of describing particular embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly dictates otherwise, the singular forms "a" and "an" are also intended to include the plural forms. It will be further understood that when used in this specification, the terms "comprises," "comprising," "includes," and "including" specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. When an expression such as "at least one of..." follows a list of elements, it modifies the entire list of elements and not individual elements in the list. For example, throughout the present disclosure, an expression such as "at least one of a, b, and c" can represent only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, and / or variations thereof.

[0060] As used herein, the terms "substantially," "about," and similar terms are used as approximate terms and not as terms of degree, and are intended to account for the inherent deviations of measured or calculated values recognized by those of ordinary skill in the art. Further, when describing embodiments of the present disclosure, the use of "may" means "one or more embodiments of the present disclosure." As used herein, the term "use" may be considered synonymous with the term "utilize." Further, the term "exemplary" is intended to mean an example or illustration.

[0061] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense.

[0062] Figure 1 is a block diagram schematically showing a display device according to an embodiment.

[0063] Referring to Figure 1 , the display device 1 may include a pixel array AY. The pixel array AY may include a plurality of pixels PX, and the plurality of pixels PX may be arranged according to a prescribed rule. The pixel array AY may display an image to a user.

[0064] A plurality of pixels PX may be electrically connected to a plurality of signal lines respectively. In addition, each pixel PX may be connected to a plurality of signal lines among the signal lines. For example, the signal lines connected to each pixel PX may include a data line DL, a first scan line SL1, a second scan line SL2, a third scan line SL3, a fourth scan line SL4, and an emission control line EL. The data line DL may extend in a first direction. The first scan line SL1 to the fourth scan line SL4 and the emission control line EL may extend in a second direction intersecting the first direction.

[0065] The above-mentioned signal lines may be electrically connected to one or more driving circuits located outside the display area DA. For example, the driving circuits may include a first scan driving circuit 120, a second scan driving circuit 130, an emission control circuit 140, and a data driving circuit 150.

[0066] The first scan driving circuit 120 may output a plurality of scan signals and may provide the first scan signal and the second scan signal to each pixel PX via the first scan line SL1 and the second scan line SL2 respectively. The second scan driving circuit 130 may output a plurality of scan signals and may provide the third scan signal and the fourth scan signal to each pixel PX via the third scan line SL3 and the fourth scan line SL4 respectively. The emission control circuit 140 may output an emission control signal and may provide the emission control signal to each pixel PX via the emission control line EL (for example, via the corresponding emission control line EL).

[0067] The data driving circuit 150 may output a plurality of data signals and may provide the plurality of data signals to each pixel PX via the data line DL (for example, via the corresponding data line DL).

[0068] A data distribution circuit 160 may be provided between the data driving circuit 150 and the display area DA. The data distribution circuit 160 may transfer the data signals from the data driving circuit 150 to the data line DL. For example, the data distribution circuit 160 may perform time division on the data signals and may distribute the divided data signals to a plurality of data lines DL. The data signals may be applied to the data distribution circuit 160 through the output line FL (for example, one output line or the corresponding output line FL) of the data driving circuit 150. The data distribution circuit 160 may include a plurality of demultiplexers, and each demultiplexer among the plurality of demultiplexers may correspond to one output line FL among the output lines FL. For example, the plurality of demultiplexers may have the same or substantially the same number as the output lines FL. When the display device 1 includes the data distribution circuit 160, the size of the external area PA (for example, see Figure 2) the pitch (or space) of signal lines (e.g., data lines DL) at a location (e.g., in the outer region PA or on the outer region PA). In another embodiment, the data distribution circuit 160 between the data driving circuit 150 and the display region DA may be omitted.

[0069] In some embodiments, the test circuit 170 may apply a test signal to the data line DL. The test circuit 170 may include a plurality of switching elements (e.g., a plurality of transistors). The test circuit 170 may apply a test signal to check whether the pixel PX is operating normally.

[0070] Figure 2 is a plan view schematically showing a display device according to an embodiment. For example, Figure 2 is a view of the display device 1 observed from a direction perpendicular to a plane parallel to or substantially parallel to the top surface of the display device 1.

[0071] Referring to Figure 2 , the display device 1 may include a display region DA and an outer region PA surrounding the display region DA (e.g., around the outer periphery of the display region DA).

[0072] The display region DA is a region where an image is displayed (e.g., therein or thereon). A plurality of pixels PX where an image can be displayed (e.g., therein or thereon) are arranged at the display region DA of the display device 1 (e.g., arranged in the display region DA of the display device 1 or arranged on the display region DA of the display device 1). The display region DA may have a non-quadrilateral shape. For example, the display region DA may have various suitable shapes as non-quadrilaterals (e.g., not including square shapes and / or rectangular shapes, etc.), such as, for example, circular shapes, elliptical shapes, and / or polygonal shapes having curved portions, etc.

[0073] The outer region PA may be a region where a plurality of pixels PX are not arranged (e.g., therein or thereon), and thus, an image may not be provided. Thus, the outer region PA may be a non-display region and may completely surround the display region DA (e.g., around the outer periphery of the display region DA).

[0074] The outer region PA may include a first outer region PA1 that generally surrounds the display region DA (e.g., around the outer periphery of the display region DA), and a second outer region PA2 that protrudes from a first portion of the first outer region PA1 in a desired direction (e.g., one direction). For example, the first outer region PA1 may extend along a plurality of ends (e.g., outer peripheral edges or peripheral edges) of the display region DA having a non-quadrilateral shape, and may have an annular shape with a specific (or certain) width. The second outer region PA2 may be at one side (e.g., a single side) of the first outer region PA1, and may be connected to the first outer region PA1. The second outer region PA2 may be bent (e.g., or may be folded), and may overlap a part (or a portion) of the first outer region PA1.

[0075] Figure 2 The plan view of the display device 1 shown in may be a plan view of the substrate 100 of the display device 1 (e.g., a view observed from a direction perpendicular to a plane parallel or substantially parallel to the top surface). For example, the substrate 100 may have the same or substantially the same shape as the display device 1. The substrate 100 may include a first region corresponding to the display region DA of the display device 1 and a second region corresponding to the outer region PA of the display device 1. The first region of the substrate 100 may have a non-quadrilateral shape corresponding to the shape of the display region DA. For example, the first region of the substrate 100 may have various suitable shapes as non-quadrilaterals (e.g., excluding square shapes and / or rectangular shapes, etc.), such as, for example, circular shapes, oval shapes, and / or polygonal shapes having curved portions, etc. The second region of the substrate 100 having a shape corresponding to the shape of the outer region PA may include a second-first region corresponding to the first outer region PA1 and a second-second region corresponding to the second outer region PA2.

[0076] The driving circuit may be disposed in the outer region PA (e.g., disposed in the outer region PA or disposed on the outer region PA). A part (or a portion) of the driving circuit may at least partially surround the display region DA (e.g., around at least a part of the outer periphery of the display region DA). In this regard, Figure 2 It is shown that the driving circuit region DCR where the driving circuit is disposed (e.g., in or on which) is located in the first outer region PA1 of the outer region PA (e.g., located in the first outer region PA1 of the outer region PA or located on the first outer region PA1 of the outer region PA).

[0077] In an embodiment, as referred to above Figure 1The described first scan driving circuit 120, second scan driving circuit 130, and emission control circuit 140 may be positioned at the driving circuit region DCR (e.g., may be positioned within the driving circuit region DCR or may be positioned on the driving circuit region DCR). The data distribution circuit 160 and the test circuit 170 may be positioned at the driving circuit region DCR (e.g., may be positioned within the driving circuit region DCR or may be positioned on the driving circuit region DCR). Each of the first scan driving circuit 120, second scan driving circuit 130, emission control circuit 140, data distribution circuit 160, and test circuit 170 may include a plurality of sub - circuits. The plurality of sub - circuits may be disposed at the external region PA (e.g., may be disposed within the external region PA or may be disposed on the external region PA), for example, may be disposed at the first external region PA1 (e.g., may be disposed within the first external region PA1 or may be disposed on the first external region PA1). The first external region PA1 may include a plurality of regions. For example, in the embodiment shown in Figure 2 the first external region PA1 includes a plurality of first sub - external regions SPA1 - 1, second sub - external regions SPA1 - 2, third sub - external regions SPA1 - 3, and fourth sub - external regions SPA1 - 4. The first sub - external regions SPA1 - 1, second sub - external regions SPA1 - 2, third sub - external regions SPA1 - 3, and fourth sub - external regions SPA1 - 4 may be defined (e.g., or may be divided) by a first virtual line VL1 and a second virtual line VL2. The first virtual line VL1 passes through the center (or central portion) C of the display region DA and extends in a first direction, and the second virtual line VL2 passes through the center C of the display region DA and extends in a second direction.

[0078] The sub - circuits of the first scan driving circuit 120, the sub - circuits of the emission control circuit 140, and the sub - circuits of the test circuit 170 can be arranged at the first sub - external area SPA1 - 1 (e.g., can be arranged in the first sub - external area SPA1 - 1 or can be arranged on the first sub - external area SPA1 - 1). The sub - circuits of the first scan driving circuit 120, the sub - circuits of the emission control circuit 140, and the sub - circuits of the data distribution circuit 160 can be arranged at the second sub - external area SPA1 - 2 (e.g., can be arranged in the second sub - external area SPA1 - 2 or can be arranged on the second sub - external area SPA1 - 2). The sub - circuits of the second scan driving circuit 130 and the sub - circuits of the test circuit 170 can be arranged at the third sub - external area SPA1 - 3 (e.g., can be arranged in the third sub - external area SPA1 - 3 or can be arranged on the third sub - external area SPA1 - 3). The sub - circuits of the second scan driving circuit 130 and the sub - circuits of the data distribution circuit 160 can be arranged at the fourth sub - external area SPA1 - 4 (e.g., can be arranged in the fourth sub - external area SPA1 - 4 or can be arranged on the fourth sub - external area SPA1 - 4).

[0079] The data driving circuit 150 can be disposed at the second external area PA2 (e.g., can be disposed in the second external area PA2 or can be disposed on the second external area PA2). In an embodiment, as Figure 2 shown, the data driving circuit 150 can be disposed (e.g., directly disposed) at the second external area PA2 as a chip - on - glass (COG) type or as a chip - on - plastic (COP) type (e.g., disposed in the second external area PA2 or disposed on the second external area PA2). In another embodiment, the data driving circuit 150 can be disposed as a chip - on - film (COF) type on an additional flexible film. In this case, the flexible film on which the data driving circuit 150 is disposed can be connected to (e.g., attached to) the pad PAD at the external area PA (e.g., at the second external area PA2) (e.g., can be in the external area PA or can be on the external area PA).

[0080] Figure 3 is an equivalent circuit diagram of a pixel of a display device according to an embodiment.

[0081] Refer to Figure 3, the pixel PX includes a plurality of first transistors T1, second transistors T2, third transistors T3, fourth transistors T4, fifth transistors T5, sixth transistors T6, and seventh transistors T7, a first capacitor Cst, a second capacitor Cbt, a display element (e.g., an organic light-emitting diode) OLED, a plurality of signal lines SL1, SL2, SL3, SL4, EL, and DL connected to the pixel PX, an initialization voltage line VIL, and a power supply voltage line PL. In another embodiment, at least one of the signal lines SL1, SL2, SL3, SL4, EL, and DL, the initialization voltage line VIL, and / or the power supply voltage line PL may be shared with an adjacent pixel. The first transistor T1 to the seventh transistor T7 may be implemented using thin film transistors. In Figure 3 , among the first transistor T1 to the seventh transistor T7, the third transistor T3 and the fourth transistor T4 are implemented using n-channel metal oxide semiconductor (NMOS) field effect transistors (FETs) (e.g., NMOSFETs), and the other remaining transistors among the first transistor T1 to the seventh transistor T7 may be implemented using p-channel MOSFETs (e.g., PMOSFETs).

[0082] The signal lines may include a data line DL, a first scan line SL1, a second scan line SL2, a third scan line SL3, a fourth scan line SL4, and an emission control line EL. In an embodiment, a plurality of second scan lines SL2 may be connected to a plurality of first scan lines SL1. In this case, the first scan signal GP1 may include (e.g., may be) the second scan signal GP2.

[0083] The power supply voltage line PL may transmit a first power supply voltage ELVDD to the first transistor T1, and the initialization voltage line VIL may transmit an initialization voltage Vint for initializing the first transistor T1 of the pixel PX and the organic light-emitting diode OLED.

[0084] The first scan line SL1, the second scan line SL2, the third scan line SL3, the fourth scan line SL4, a plurality of emission control lines EL, and the initialization voltage line VIL may extend in any suitable direction (e.g., the second direction) and may be spaced apart from each other (e.g., from one another). The plurality of data lines DL and the power supply voltage line PL may extend in another suitable direction (e.g., the first direction) and may be spaced apart from each other (e.g., from one another).

[0085] The first transistor T1 may be connected to the power supply voltage line PL via the fifth transistor T5 and may be electrically connected to the organic light-emitting diode OLED via the sixth transistor T6. The first transistor T1 may, for example, be used as a driving transistor such that the first transistor T1 may receive a signal corresponding to the data signal DATA according to the switching operation of the second transistor T2 and may output a driving current IOLED Supplied to the organic light-emitting diode OLED.

[0086] The second transistor T2 can be connected to the first scan line SL1 and the data line DL, and can be connected to the power supply voltage line PL via the fifth transistor T5. The second transistor T2 can be turned on according to the first scan signal GP1 transmitted via the first scan line SL1, and can perform a switching operation of transmitting the data signal DATA transmitted from the data line DL to the node N. For example, when the second transistor T2 is turned on according to the first scan signal GP1, the second transistor T2 can transmit the data signal DATA from the data line DL to the node N through the first transistor T1 and the third transistor T3.

[0087] The third transistor T3 can be connected to the fourth scan line SL4, and can be connected to the organic light-emitting diode OLED via the sixth transistor T6. The third transistor T3 can be turned on according to the fourth scan signal GN2 transmitted via the fourth scan line SL4, and can be connected to the first transistor T1 in a diode manner.

[0088] The fourth transistor T4 can be connected to the third scan line SL3 and the initialization voltage line VIL. The fourth transistor T4 can be turned on according to the third scan signal GN1 transmitted via the third scan line SL3, and can transmit the initialization voltage Vint from the initialization voltage line VIL to the gate electrode of the first transistor T1. Therefore, the fourth transistor T4 can initialize the voltage of the gate electrode of the first transistor T1.

[0089] Each of the fifth transistor T5 and the sixth transistor T6 can be connected to the emission control line EL. The fifth transistor T5 and the sixth transistor T6 can be concurrently (e.g., simultaneously) turned on according to the emission control signal EM transmitted via the emission control line EL, and can (e.g., together with the first transistor T1) form a current path on which the drive current I OLED can flow from the power supply voltage line PL in the direction toward the organic light-emitting diode OLED.

[0090] The seventh transistor T7 can be connected to each of the second scan line SL2 and the initialization voltage line VIL, and can be turned on according to the second scan signal GP2 transmitted via the second scan line SL2. When the seventh transistor T7 is turned on, the seventh transistor T7 can transmit the initialization voltage Vint from the initialization voltage line VIL to the organic light-emitting diode OLED, thereby initializing the organic light-emitting diode OLED. However, the present disclosure is not limited thereto, and in another embodiment, the seventh transistor T7 can be omitted.

[0091] The first capacitor Cst may include a first electrode CE1 and a second electrode CE2. The first electrode CE1 may be connected to the gate electrode of the first transistor T1, and the second electrode CE2 may be connected to the power supply voltage line PL. The first capacitor Cst may define (e.g., may be) a storage capacitor. For example, the first capacitor Cst may store and hold or substantially hold a voltage corresponding to the difference between the voltage of the power supply voltage line PL and the voltage (e.g., the voltage across both ends) of the gate electrode of the first transistor T1, so as to hold or substantially hold the voltage applied to the gate electrode of the first transistor T1.

[0092] The second capacitor Cbt may include a third electrode CE3 and a fourth electrode CE4. The third electrode CE3 may be connected to the first scan line SL1 and the gate electrode of the second transistor T2. The fourth electrode CE4 may be connected to the gate electrode of the first transistor T1 and the first electrode CE1 of the first capacitor Cst. The second capacitor Cbt may define (or may be) a boosting capacitor, for example, so that when the first scan signal GP1 of the first scan line SL1 corresponds to (e.g., is or includes) a voltage for turning off the second transistor T2, the second capacitor Cbt may increase the voltage of the node N, such that the voltage for displaying a black image (e.g., the black voltage) is reduced.

[0093] The organic light emitting diode OLED may be electrically connected to the pixel circuit PC that may include the above-mentioned transistors and capacitors. The organic light emitting diode OLED may include a pixel electrode and a counter electrode. The second power supply voltage ELVSS may be applied to the counter electrode. The organic light emitting diode OLED may receive the driving current I OLED from the first transistor T1 OLED and may emit light according to the driving current I

[0094] The detailed operation of the pixel (e.g., each pixel) PX according to the embodiment will be described in more detail below.

[0095] During the initialization period, when the third scan signal GN1 is supplied to the pixel (e.g., supplied to each pixel) PX via the third scan line (e.g., via a plurality of third scan lines) SL3, the fourth transistor T4 may be turned on according to the third scan signal GN1, and the first transistor T1 may be initialized by the initialization voltage Vint supplied from the initialization voltage line VIL.

[0096] During the data programming period, a first scan signal GP1, a second scan signal GP2, and a fourth scan signal GN2 are respectively supplied to a pixel (e.g., each pixel) PX via a first scan line SL1, a second scan line SL2, and a fourth scan line SL4, and second transistor T2, seventh transistor T7, and third transistor T3 can be turned on according to the first scan signal GP1, the second scan signal GP2, and the fourth scan signal GN2. In this case, the first transistor T1 can be connected in a diode manner through the turned-on third transistor T3, and the first transistor T1 can be forward-biased. Subsequently, a voltage in which the threshold voltage Vth of the first transistor T1 is compensated in the data signal DATA supplied from the data line DL can be applied to the gate electrode of the first transistor T1. The organic light-emitting diode OLED can be initialized by the initialization voltage Vint supplied from the initialization voltage line VIL through the turned-on seventh transistor T7. A first power supply voltage ELVDD and a compensation voltage can be applied to respective ends (e.g., respective electrodes CE1 and CE2) of the first capacitor Cst, and the first capacitor Cst can store a voltage difference corresponding to the voltage difference between the first power supply voltage ELVDD and the compensation voltage.

[0097] During the emission period, fifth transistor T5 and sixth transistor T6 can be turned on according to an emission control signal EM supplied from the emission control line EL. The driving current I OLED can be generated due to the voltage difference between the voltage of the gate electrode of the first transistor T1 and the first power supply voltage ELVDD, and the driving current I OLED can be supplied to the organic light-emitting diode OLED via the sixth transistor T6.

[0098] In the present embodiment, at least one of the plurality of transistors T1 to T7 includes a semiconductor layer containing an oxide, and at least one of the other remaining transistors among the plurality of transistors T1 to T7 can include a semiconductor layer containing silicon. More specifically, for example, when the first transistor T1 directly affects the brightness of the display device, the first transistor T1 can be configured to include a semiconductor layer that can have high reliability, such as polysilicon. Accordingly, a display device with high resolution can be realized.

[0099] The oxide semiconductor can have a high carrier mobility and a low leakage current, and thus, even when the driving time is long (e.g., extended), the voltage drop may not be large. In other words, even during low-frequency driving, due to the voltage drop, the color change of the image may not be large (e.g., may not be significantly large). Thus, a low-frequency driving method can be performed. Because the oxide semiconductor has a low leakage current, at least one of the third transistor T3 and the fourth transistor T4 connected to the gate electrode of the first transistor T1 can include (e.g., can be used as) an oxide semiconductor. Therefore, the leakage current that may flow into the gate electrode of the first transistor T1 can be prevented or substantially prevented, and the power consumption can be reduced (e.g., concurrently reduced or simultaneously reduced).

[0100] Figure 4 is a cross-sectional view of a display device taken along the line IV-IV' according to an embodiment Figure 2 of FIG.

[0101] Referring to Figure 4 , the display device according to an embodiment Figure 2 may include: a substrate 100, a first thin-film transistor TFT1 including a silicon semiconductor, a second thin-film transistor TFT2 including an oxide semiconductor, a first capacitor Cst, and a second capacitor Cbt. Figure 4 The first thin-film transistor TFT1 of Figure 3 may define (e.g., may include or may be) any suitable one of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 described above with reference to Figure 4 The second thin-film transistor TFT2 of Figure 3 may define (e.g., may include or may be) any suitable one of the third transistor T3 and the fourth transistor T4 described above with reference to

[0102] The substrate 100 may include a glass material, a ceramic material, a metal material, and / or a flexible or bendable material, etc. When the substrate 100 is flexible or bendable, the substrate 100 may include a polymer resin, e.g., such as polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, and / or cellulose acetate propionate. The substrate 100 may have a single-layer structure or a multi-layer structure including one or more of the above materials. When the substrate 100 has a multi-layer structure, the substrate 100 may further include an inorganic layer. For example, in some embodiments, the substrate 100 may have a stacked structure including (e.g., sequentially stacked) an organic material, an inorganic material, and an organic material, or a stacked structure including (e.g., sequentially stacked) an organic material, an inorganic material, an organic material, and an inorganic material.

[0103] The buffer layer 110 can improve the smoothness of the top surface of the substrate 100 (e.g., or provide a smooth surface to the top surface of the substrate 100). The buffer layer 110 can include an inorganic insulating material, such as, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0104] The first semiconductor layer AS of the first thin film transistor TFT1 can be disposed on the buffer layer 110. The first semiconductor layer AS can include a silicon semiconductor. The first semiconductor layer AS can include a source region S1, a drain region D1 spaced apart from the source region S1, and a channel region C1 between the source region S1 and the drain region D1. The source region S1 and the drain region D1 can have impurities doped therein to have conductivity. The source region S1 and the drain region D1 can correspond to the source electrode and the drain electrode of the first thin film transistor TFT1, respectively. In another embodiment, the positions of the source region S1 and the drain region D1 can be changed (e.g., swapped) with each other.

[0105] The gate electrode GE1 of the first thin film transistor TFT1 can be disposed on the first semiconductor layer AS, and the first insulating layer 111 can be disposed between the first semiconductor layer AS and the gate electrode GE1. The first insulating layer 111 can include an inorganic material that includes an oxide or a nitride. For example, the first insulating layer 111 can include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and / or hafnium oxide.

[0106] The gate electrode GE1 of the first thin film transistor TFT1 can overlap with the channel region C1 of the first semiconductor layer AS. The gate electrode GE1 can include molybdenum (Mo), copper (Cu), and / or titanium (Ti), and can have a single-layer structure or a multi-layer structure including one or more of the above materials.

[0107] The first electrode CE1 of the first capacitor Cst and the third electrode CE3 of the second capacitor Cbt can be disposed at the same or substantially the same layer as the layer of the gate electrode GE1 of the first thin film transistor TFT1 (e.g., can be disposed on the same or substantially the same layer as the layer of the gate electrode GE1 of the first thin film transistor TFT1). The first electrode CE1 of the first capacitor Cst and the third electrode CE3 of the second capacitor Cbt can include the same or substantially the same material as the material of the gate electrode GE1 of the first thin film transistor TFT1.

[0108] The second insulating layer 112 may be disposed on the gate electrode GE1 of the first thin film transistor TFT1, the first electrode CE1 of the first capacitor Cst, and the third electrode CE3 of the second capacitor Cbt. The second insulating layer 112 may include an inorganic material including an oxide or a nitride. For example, the second insulating layer 112 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and / or hafnium oxide.

[0109] The second electrode CE2 of the first capacitor Cst may be disposed on the second insulating layer 112 to overlap with the first electrode CE1 of the first capacitor Cst. The second electrode CE2 may include, for example, Mo, Cu, and / or Ti, and may have a single-layer structure or a multi-layer structure including one or more of the above materials.

[0110] The third insulating layer 113 may be disposed on the second electrode CE2 of the first capacitor Cst. The third insulating layer 113 may include an inorganic material including an oxide or a nitride. For example, the third insulating layer 113 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and / or hafnium oxide.

[0111] In Figure 4 FIG., the first capacitor Cst is shown overlapping with the first thin film transistor TFT1. However, the present disclosure is not limited thereto, and in another embodiment, the first capacitor Cst may be spaced apart from the first thin film transistor TFT1 (e.g., along the surface of the substrate 100). For example, when the first thin film transistor TFT1 defines (or is) the driving transistor (e.g., the first transistor T1) described above with reference to Figure 3 FIG., the second electrode CE2 of the first capacitor Cst may be disposed on the gate electrode GE1 of the first thin film transistor TFT1 and may overlap with the gate electrode GE1. In this case, the gate electrode GE1 of the first thin film transistor TFT1 may serve as both the gate electrode of the first thin film transistor TFT1 and the first electrode CE1 of the first capacitor Cst.

[0112] The second semiconductor layer AO of the second thin film transistor TFT2 may be disposed on the third insulating layer 113. The second semiconductor layer AO may include an oxide semiconductor. The second semiconductor layer AO may include a source region S2, a drain region D2 spaced apart from the source region S2, and a channel region C2 between the source region S2 and the drain region D2. The oxide semiconductor may include, for example, zinc oxide (Zn), indium (In) zinc oxide, and / or gallium (Ga) zinc oxide as zinc oxide-based materials. For example, the second semiconductor layer AO may include, for example, an indium gallium zinc oxide (IGZO) semiconductor, an indium tin (Sn) zinc oxide (ITZO) semiconductor, and / or an indium gallium tin zinc oxide (IGTZO) semiconductor formed by combining (or adding) various suitable metals such as In, Ga, and / or Sn to ZnO. Each of the source region S2 and the drain region D2 may have conductivity. The source region S2 and the drain region D2 of the second semiconductor layer AO may be formed by controlling the carrier concentration of the oxide semiconductor and making the oxide semiconductor conductive. For example, the source region S2 and the drain region D2 may be formed by increasing the carrier concentration through plasma treatment of the oxide semiconductor using a hydrogen (H)-based gas, a fluorine (F)-based gas, or a combination thereof.

[0113] The second thin film transistor TFT2 may include a dual gate electrode. For example, a first gate electrode GEa may be disposed below the second semiconductor layer AO of the second thin film transistor TFT2 (e.g., may overlap with the second semiconductor layer AO of the second thin film transistor TFT2), and a second gate electrode GEb may be disposed above the second semiconductor layer AO of the second thin film transistor TFT2 (e.g., may be disposed on the second semiconductor layer AO of the second thin film transistor TFT2). The third insulating layer 113 may be disposed between the first gate electrode GEa and the second semiconductor layer AO of the second thin film transistor TFT2. The first gate electrode GEa of the second thin film transistor TFT2 may be positioned at the same or substantially the same layer as the layer of the second electrode CE2 of the first capacitor Cst (e.g., may be positioned on the same or substantially the same layer as the layer of the second electrode CE2 of the first capacitor Cst), and may be formed using the same or substantially the same material as the material of the second electrode CE2 of the first capacitor Cst. The first gate electrode GEa may overlap with the channel region C2 of the second semiconductor layer AO.

[0114] The fourth insulating layer 114 may be disposed between the second semiconductor layer AO of the second thin film transistor TFT2 and the second gate electrode GEb. The second gate electrode GEb may overlap with the channel region C2 of the second semiconductor layer AO. The fourth insulating layer 114 may be formed using the same or substantially the same masking process as that of the second gate electrode GEb (e.g., using the same mask as that of the second gate electrode GEb). In this case, the fourth insulating layer 114 may be formed to have the same or substantially the same shape as that of the second gate electrode GEb.

[0115] The fourth insulating layer 114 may include an inorganic material, which includes an oxide or a nitride. For example, the fourth insulating layer 114 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and / or hafnium oxide. The second gate electrode GEb may include, for example, Mo, Cu, and / or Ti, and may have a single-layer structure or a multi-layer structure including one or more of the above materials.

[0116] The fourth electrode CE4 of the second capacitor Cbt may be disposed on the third insulating layer 113 and may overlap with the third electrode CE3. The fourth electrode CE4 of the second capacitor Cbt may include an oxide semiconductor. In an embodiment, the fourth electrode CE4 of the second capacitor Cbt may extend from the second semiconductor layer AO of the second thin film transistor TFT2 and may overlap with the third electrode CE3. The second insulating layer 112 and the third insulating layer 113 may be disposed between the third electrode CE3 and the fourth electrode CE4.

[0117] The fifth insulating layer 115 may cover the second thin film transistor TFT2. The fifth insulating layer 115 may be disposed above the second gate electrode GEb (e.g., may be disposed on the second gate electrode GEb), and the power supply voltage line PL and the first connection electrode 167 may be disposed on the fifth insulating layer 115.

[0118] The fifth insulating layer 115 may include an inorganic material, which includes an oxide or a nitride. For example, the fifth insulating layer 115 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and / or hafnium oxide.

[0119] The power supply voltage line PL and the first connection electrode 167 may include one or more materials having relatively high conductivity. The power supply voltage line PL and the first connection electrode 167 may include, for example, Al, Cu, and / or Ti, and may have a single-layer structure or a multi-layer structure including one or more of the above materials. For example, in some embodiments, each of the power supply voltage line PL and the first connection electrode 167 may have a stacked structure that may be stacked on each other (e.g., sequentially disposed), and the stacked structure includes three layers of Ti, Al, and Ti.

[0120] The first connection electrode 167 may be connected to the first semiconductor layer AS via the contact hole H1. The contact hole H1 may extend through (e.g., pass through) the first insulating layer 111, the second insulating layer 112, the third insulating layer 113, and the fifth insulating layer 115, and may expose a part (or portion) of the first semiconductor layer AS. A part (or portion) of the first connection electrode 167 may be electrically connected to the first semiconductor layer AS via the contact hole H1.

[0121] The sixth insulating layer 116 may be a planarization layer and may be disposed on the power supply voltage line PL and the first connection electrode 167. In an embodiment, the sixth insulating layer 116 may include an organic material, e.g., such as acrylic acid, benzocyclobutene (BCB), polyimide, and / or hexamethyldisiloxane (HMDSO). In another embodiment, the sixth insulating layer 116 may include an inorganic material. The sixth insulating layer 116 may serve as a protective layer by covering the first thin film transistor TFT1 and the second thin film transistor TFT2, and the upper portion of the sixth insulating layer 116 may be flat. For example, the sixth insulating layer 116 may have a flat upper surface. The sixth insulating layer 116 may have a single-layer structure or a multi-layer structure.

[0122] The data line DL and the second connection electrode 177 may be disposed on the sixth insulating layer 116. A part (or portion) of the data line DL may overlap with the power supply voltage line PL. In other words, the data line DL may partially overlap with the power supply voltage line PL. The second connection electrode 177 may be connected to the first connection electrode 167 via a contact hole H2 defined in the sixth insulating layer 116. In other words, the contact hole H2 may extend through (e.g., pass through) the sixth insulating layer 116 such that the second connection electrode 177 may be connected to the first connection electrode 167. The data line DL and the second connection electrode 177 may include a conductive material, e.g., such as a metal and / or a conductive oxide. For example, each of the data line DL and the second connection electrode 177 may include Al, Cu, and / or Ti, and may have a single-layer structure or a multi-layer structure including one or more of the above materials. In an embodiment, each of the data line DL and the second connection electrode 177 may have a stacked structure that may be stacked (e.g., sequentially arranged) with each other, the stacked structure including three layers of Ti, Al, and Ti. The seventh insulating layer 117 may be disposed above (e.g., may be disposed on) the data line DL and the second connection electrode 177.

[0123] The organic light emitting diode OLED may be disposed on the seventh insulating layer 117. The organic light emitting diode OLED may include a pixel electrode 310, a counter electrode 330, and an intermediate layer 320 interposed between the pixel electrode 310 and the counter electrode 330. The intermediate layer 320 may include an emission layer.

[0124] The pixel electrode 310 may be connected to the second connection electrode 177 via a contact hole H3 defined at the seventh insulating layer 117 (e.g., defined in or on the seventh insulating layer 117). In other words, the contact hole H3 may extend through (e.g., pass through) the seventh insulating layer 117 such that the pixel electrode 310 may be connected to the second connection electrode 177. The pixel electrode 310 may be connected to the first thin film transistor TFT1 via each of the second connection electrode 177 and the first connection electrode 167.

[0125] The eighth insulating layer 118 may be disposed above the seventh insulating layer 117 (e.g., may be disposed on the seventh insulating layer 117). The eighth insulating layer 118 may be a pixel defining layer and may have an opening (e.g., an opening OP that overlaps a part or portion of the pixel electrode 310 and exposes a part or portion of the pixel electrode 310) corresponding to each pixel PX, thereby defining the emission region of the pixel (e.g., each pixel) PX. In addition, the eighth insulating layer 118 may increase the distance between one end (e.g., an edge) of the pixel electrode 310 and one end (e.g., an edge) of the counter electrode 330 located above (e.g., on) the pixel electrode 310, thereby preventing or substantially preventing arcing from occurring at the edge of the pixel electrode 310 (e.g., in or on the edge of the pixel electrode 310). The eighth insulating layer 118 may include an inorganic material such as, for example, polyimide and / or HMDSO.

[0126] The pixel electrode 310 may be disposed on the seventh insulating layer 117 and may include a conductive oxide such as, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and / or aluminum zinc oxide (AZO). In another embodiment, the pixel electrode 310 may include a reflective layer including, for example, silver (Ag), magnesium (Mg), Al, platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a suitable compound thereof. In another embodiment, the pixel electrode 310 may further include a layer located above and below the above-mentioned reflective layer, and the layer may include, for example, ITO, IZO, ZnO, and / or In2O3.

[0127] The intermediate layer 320 of the organic light-emitting diode OLED includes an emission layer. The emission layer may include a polymer or a small-molecule organic material that emits light of a desired (e.g., certain) color. For example, in an embodiment, the emission layer may include a red emission layer, a green emission layer, or a blue emission layer. In another embodiment, the emission layer may have a multi-layer structure in which the red emission layer, the green emission layer, and the blue emission layer are stacked on one another to emit white light or a single-layer structure including a red emission material, a green emission material, and a blue emission material. In an embodiment, the intermediate layer 320 may include a first functional layer below the emission layer and / or a second functional layer above the emission layer. Each of the first functional layer and the second functional layer may be formed (e.g., integrally formed or formed together) as one body to cover the plurality of pixel electrodes 310, or may be each patterned to correspond to each of the plurality of pixel electrodes 310.

[0128] The first functional layer may have a single-layer structure or a multi-layer structure. For example, when the first functional layer includes a polymer material, the first functional layer may include (or may be) a hole transport layer (HTL) having a single-layer structure including, for example, poly(3,4)-ethylenedioxythiophene (PEDOT) or polyaniline (PANI). In another example, when the first functional layer includes a small-molecule material, the first functional layer may include a hole injection layer (HIL) and an HTL.

[0129] The second functional layer may be optionally (or selectively) provided. For example, when the first functional layer and the emission layer include a polymer material, the second functional layer may be formed such that the organic light-emitting diode OLED has improved (e.g., excellent) characteristics. The second functional layer may have a single-layer structure or a multi-layer structure. The second functional layer may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0130] The counter electrode 330 may be disposed to face the pixel electrode 310, with the intermediate layer 320 therebetween. The counter electrode 330 may include a conductive material having a small work function. For example, in an embodiment, the counter electrode 330 may include a transparent or semi-transparent layer including, for example, Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, calcium (Ca), or a suitable alloy thereof. In another embodiment, the counter electrode 330 may further include a layer such as ITO, IZO, ZnO, or In2O3, which is disposed on the transparent or semi-transparent layer including one or more of the above materials. The counter electrode 330 may be positioned above the intermediate layer 320 and the eighth insulating layer 118 (e.g., may be positioned on the intermediate layer 320 and the eighth insulating layer 118). The counter electrode 330 may include a common electrode that is formed integrally (e.g., commonly formed) for a plurality of organic light-emitting diodes OLEDs in the display area DA (e.g., in or on the display area DA) and faces the plurality of pixel electrodes 310.

[0131] A thin film encapsulation layer or a sealing substrate may be disposed above (e.g., may be disposed on) the organic light-emitting diode OLED to cover and protect the organic light-emitting diode OLED. The thin film encapsulation layer may cover the display area DA and may extend outside the display area DA. The thin film encapsulation layer may include an inorganic encapsulation layer including at least one inorganic material and an organic encapsulation layer including at least one organic material. In some embodiments, the thin film encapsulation layer may include a structure in which a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer are stacked on one another (e.g., sequentially stacked). The sealing substrate may face the substrate 100 and may be connected to (e.g., attached or adhered to) the substrate 100 outside the display area DA using a sealing member such as a sealant and / or frit.

[0132] Spacers that prevent or substantially prevent the mask from being stamped may be further disposed on the eighth insulating layer 118. As will be known to those skilled in the art, various suitable functional layers may be provided on the thin film encapsulation layer, such as, for example, a polarization layer for reducing external light reflection, a black matrix, a color filter, and / or a touch screen layer having a touch electrode.

[0133] Figure 5A is a plan view schematically showing the arrangement of a pixel circuit included in a pixel of a display device according to an embodiment, and Figure 5B is a plan view showing a pixel circuit and a load compensation capacitor of a display device according to an embodiment.

[0134] A plurality of pixels are arranged on a substrate 100. The plurality of pixels may define a surface (e.g., an image surface) for displaying an image having a non-quadrilateral shape. An image displayed by light emitted from a plurality of organic light-emitting display devices may be displayed on a side (e.g., a circular image side) of the display device corresponding to the image surface having the non-quadrilateral shape, and the plurality of organic light-emitting display devices are disposed in pixels (e.g., disposed in each pixel) located at a display area DA (e.g., located in the display area DA or on the display area DA).

[0135] Each pixel located at the display area DA (e.g., located in the display area DA or on the display area DA) may include an organic light-emitting diode. As described above with reference to Figure 3 Each organic light-emitting diode may be electrically connected to a corresponding one of the pixel circuits PC in the pixel circuit PC. Similar to the organic light-emitting diode, the pixel circuit PC may be disposed at the display area DA (e.g., disposed in the display area DA or disposed on the display area DA). For example, a plurality of pixel circuits PC may be disposed in each pixel, and the plurality of pixel circuits PC may be repeatedly arranged along a first direction and a second direction.

[0136] Since the display area DA has a non-quadrilateral shape, the plurality of pixel circuits PC may have a stepped configuration along a plurality of ends (e.g., a plurality of edges or one edge) of the display area DA. In this regard, Figure 5A A structure in which the plurality of pixel circuits PC are arranged in a stepped manner is shown. As Figure 5A shown, a box may represent a pixel circuit group PC-U, and a pixel circuit group PC-U may include a plurality of pixel circuits (e.g., three pixel circuits) PC. For convenience, Figure 5A one pixel circuit group PC-U corresponding to three pixel circuits PC is shown. However, in another embodiment, there may be various suitable modifications, for example, where one pixel circuit group PC-U corresponds to less than three pixel circuits PC (e.g., two pixel circuits PC or one pixel circuit PC), or where one pixel circuit group PC-U corresponds to more than three pixel circuits PC (e.g., four pixel circuits PC). Hereinafter, for convenience, the case where one pixel circuit group PC-U includes three pixel circuits PC will be described. In addition, for convenience, the three pixel circuits PC may be referred to as including a first pixel circuit PC1, a second pixel circuit PC2, and a third pixel circuit PC3.

[0137] A plurality of pixel circuit groups PC-U may be arranged on the substrate 100 and may form columns in a first direction. Similarly, the pixel circuits PC may be arranged on the substrate 100 and may form columns in a first direction. For example, asFigure 5B As shown, a plurality of pixel circuit groups PC-U arranged along a first direction may form a column (hereinafter, this one column may be referred to as a column circuit group) PUCL. As described above (e.g., and as shown in the enlarged view of Figure 5A ), when the pixel circuit group PC-U includes three pixel circuits PC, one column circuit group PUCL may include three columns PCCL of pixel circuits PC that extend in the first direction and are arranged along a second direction with respect to each other (hereinafter, one column PCCL of pixel circuits PC among the three columns PCCL of pixel circuits PC may be referred to as a pixel circuit column PCCL). Thus, a plurality of pixel circuit columns PCCL may be arranged at (e.g., arranged in or arranged on) the display area DA.

[0138] Since the display area DA has a non-quadrilateral shape, the lengths of the pixel circuit columns PCCL at (e.g., in or on) the display area DA may be different from each other (e.g., from one another). For example, the number of pixel circuits PC adjacent to a first virtual line VL1 that extends through (e.g., passes through) (e.g., across) the center C of the display area DA in a pixel circuit column PCCL (e.g., an adjacent pixel circuit column PCCL) may be greater than the number of pixel circuits PC in another pixel circuit column PCCL that is further away from the first virtual line VL1 in the second direction than the adjacent pixel circuit column PCCL.

[0139] In a comparative example, when pixel circuits are arranged at (e.g., arranged in or arranged on) a display area having a quadrilateral shape (e.g., a simple quadrilateral shape), the number of pixel circuits in a pixel circuit column may be constant (e.g., may be equal to or substantially equal to each other), and the lengths of the lines for supplying signals or voltages to the corresponding pixel circuits may be constant (e.g., may be equal to or substantially equal to each other). Thus, the load applied to each pixel circuit column may be constant (e.g., may be equal to or substantially equal to each other). However, as Figure 5A and Figure 5BAs shown, the number of pixel circuits PC provided in at least some of the pixel circuit columns PCCL in the non-quadrilateral display area DA (e.g., in or on the non-quadrilateral display area DA) may be different from each other according to the position of the pixel circuit column PCCL, and the lengths of at least some of the lines for supplying signals or voltages to the pixel circuit columns PCCL may be different from each other. Thus, the load applied to each pixel circuit column PCCL may not be constant (e.g., may not be equal or substantially equal to each other). For example, the lengths of some of the data lines and / or some of the drive voltage lines extending in their respective pixel circuit columns PCCL may be different from each other according to the position of their respective pixel circuit columns PCCL. Thus, the load applied to the data lines and / or the drive voltage lines may not be constant (e.g., may not be equal or substantially equal to each other), and the load difference between their loads may deteriorate the quality of the image. However, according to an embodiment of the present disclosure, as Figure 5B shown, a load matching section CLM may be arranged at each column circuit group PUCL (e.g., may be in or on each column circuit group PUCL). Therefore, the above problems can be prevented or substantially prevented. For example, deterioration of the quality of the image caused by the load difference between the loads can be prevented or substantially prevented.

[0140] For example, the load matching section CLM may include one or more load compensation capacitors Clm. As described above, each column circuit group PUCL may include three pixel circuit columns PCCL. In this case, as Figure 5B shown in the enlarged partial view of, the load matching section CLM includes three load compensation capacitors Clm, and each load compensation capacitor Clm corresponds to one of the pixel circuit columns PCCL in the pixel circuit column PCCL of the column circuit group PUCL corresponding to the respective column. The load compensation capacitor Clm may compensate for the above load difference corresponding to each pixel circuit column PCCL.

[0141] The load matching section CLM (or more specifically, for example, the load compensation capacitor Clm) may be located at one side of the second virtual line VL2, and the one side is opposite to the side where the pad PAD of the second virtual line VL2 is centered. The second virtual line VL2 extends through (e.g., passes through) (e.g., across) the center C of the display area DA in the second direction.

[0142] The size and / or area of the load compensation capacitor Clm of the load matching section CLM can be different from each other (e.g., mutually) according to the position (e.g., location) of the load compensation capacitor Clm and / or the load matching section CLM. For example, the size and / or area of the load compensation capacitor Clm of the load matching section CLM corresponding to a column of circuit groups PUCL adjacent to the first virtual line VL1 (e.g., the circuit groups PUCL of an adjacent column) can be smaller than the size and / or area of the load compensation capacitor Clm of the load matching section CLM corresponding to a column of circuit groups PUCL that is farther from the first virtual line VL1 than the circuit groups PUCL of the adjacent column in the second direction. For example, the capacitance of the load compensation capacitor Clm corresponding to a column of pixel circuits PCCL adjacent to the first virtual line VL1 (e.g., an adjacent column of pixel circuits PCCL) can be smaller than the capacitance of the load compensation capacitor Clm corresponding to a column of pixel circuits PCCL that is farther from the first virtual line VL1 than the adjacent column of pixel circuits PCCL in the second direction. Since the number of pixel circuits PC provided in the column of pixel circuits PCCL can decrease as the distance between the corresponding column of circuit groups PUCL and the first virtual line VL1 increases, the size and / or area of the load compensation capacitor Clm of the corresponding load matching section CLM can increase as the distance between the corresponding column of circuit groups PUCL and the first virtual line VL1 increases.

[0143] Figure 6 is an enlarged plan view of a part (or portion) of a display device according to an embodiment.

[0144] Referring to Figure 6 , the test circuit 170 (e.g., see Figure 1 ) can include a plurality of sub-test circuits 170S, and the plurality of sub-test circuits 170S can be sub-circuit portions of the test circuit 170. The sub-test circuits 170S can be arranged at the external area PA (e.g., can be arranged in the external area PA or can be arranged on the external area PA), and can be spaced apart from each other (e.g., mutually). One or more sub-circuit portions of the driving circuit can be arranged between adjacent sub-test circuits 170S among the sub-test circuits 170S. For example, Figure 6 shows that a sub-emission control circuit 140S and a sub-first scan driving circuit 120S are provided between adjacent sub-test circuits 170S among the sub-test circuits 170S. In another embodiment, a sub-emission control circuit and a sub-second scan driving circuit can be provided between adjacent sub-test circuits 170S (e.g., mutually adjacent) according to the position (e.g., location) of the sub-test circuits 170S.

[0145] The first input line group IL1 can be connected to the sub-test circuit 170S and can be disposed at the input line region ILR (e.g., can be disposed in the input line region ILR or can be disposed on the input line region ILR), and the input line region ILR is located outside the drive circuit region DCR. The first input line group IL1 can include one or more input signal lines. For example, in an embodiment, the first input line group IL1 can include a plurality of input signal lines for applying control signals and test signals to the sub-test circuit 170S.

[0146] Each sub-test circuit 170S can operate according to the control signal transmitted to each sub-test circuit 170S via the first input line group IL1, and can output the test signal transmitted via the first input line group IL1 to the signal line (e.g., data line) of the pixel circuit and the electrode of the load compensation capacitor. In an embodiment, as Figure 6 shown, each sub-test circuit 170S can output the test signal to the corresponding signal lines of the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 through the first output line WL1, the second output line WL2, and the third output line WL3, and output to the corresponding electrodes of the first load compensation capacitor Clm1, the second load compensation capacitor Clm2, and the third load compensation capacitor Clm3. The first load compensation capacitor Clm1, the second load compensation capacitor Clm2, and the third load compensation capacitor Clm3 can be positioned corresponding to the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3.

[0147] The sub-test circuit 170S can be electrically connected to the first connection portion 210 via a first output line WL1 located at the output line region OLR (e.g., within the output line region OLR or on the output line region OLR). The first connection portion 210 can be connected to a first load compensation capacitor Clm1 and a data line DL of the first pixel circuit PC1 corresponding to a first pixel (e.g., a red pixel PXr). Similarly, the sub-test circuit 170S can be electrically connected to the second connection portion 220 via a second output line WL2. The second connection portion 220 can be connected to a signal line (e.g., a data line) of the second pixel circuit PC2 of a second pixel (e.g., a green pixel PXg) and connected to a second load compensation capacitor Clm2. The sub-test circuit 170S can be electrically connected to the third connection portion 230 via a third output line WL3. The third connection portion 230 can be connected to a signal line (e.g., a data line) of the third pixel circuit PC3 of a third pixel (e.g., a blue pixel PXb) and connected to a third load compensation capacitor Clm3. Each of the first connection portion 210, the second connection portion 220, and the third connection portion 230 can be positioned between the respective pixel circuits of the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 and the respective load compensation capacitors of the first load compensation capacitor Clm1, the second load compensation capacitor Clm2, and the third load compensation capacitor Clm3.

[0148] The second input line group IL2 and the third input line group IL3 can be positioned at the input line region ILR (e.g., can be positioned within the input line region ILR or can be positioned on the input line region ILR), and the input line region ILR is positioned outside the drive circuit region DCR. The second input line group IL2 and the third input line group IL3 can be respectively connected to the sub-transmission control circuit 140S and the sub-first scan drive circuit 120S. The second input line group IL2 and the third input line group IL3 can include a plurality of voltage lines and a plurality of clock lines.

[0149] Each sub-first scan drive circuit 120S can output a scan signal to each pixel circuit PC via at least one line located at the output line region OLR (e.g., within the output line region OLR or on the output line region OLR). In an embodiment, Figure 6The figure shows a row in which a scan signal output from the sub-first scan driving circuit 120S is transmitted in a second direction to the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 via two output lines (for example, a first output line L1 and a second output line L2 branched from each other). Each sub-emission control circuit 140S can output an emission control signal to each corresponding pixel circuit PC via a third output line L3 located at the output line region OLR (for example, located in the output line region OLR or on the output line region OLR).

[0150] A common initialization voltage line CVIL can be provided at the driving circuit region DCR (for example, can be provided in the driving circuit region DCR or on the driving circuit region DCR). The initialization voltage provided by the common initialization voltage line CVIL can be supplied to each pixel circuit PC via a fourth output line L4 located at the output line region OLR (for example, located in the output line region OLR or on the output line region OLR).

[0151] A line located at the output line region OLR (for example, located in the output line region OLR or on the output line region OLR) can have a bent shape at the output line region OLR (for example, in the output line region OLR or on the output line region OLR). For example, Figure 6 The figure shows that the first output line WL1, the second output line WL2, and the third output line WL3, and the first output line L1, the second output line L2, the third output line L3, and the fourth output line L4 can be bent at the output line region OLR (for example, can be bent in the output line region OLR or on the output line region OLR).

[0152] Figure 7A and Figure 7B is a circuit diagram showing the electrical connection of a sub-test circuit, a pixel circuit, and a load compensation capacitor provided in a display device according to various embodiments.

[0153] Referring to Figure 6 and Figure 7A , the sub-test circuit 170S can include a plurality of switches SW that operate according to a control signal DC_GATE transmitted via a fourth input signal line IL1-4 in the first input line group IL1. Each switch SW can include a thin film transistor.

[0154] Each switch SW can be turned on according to the control signal DC_GATE, and can supply a corresponding one of the test signals DC_R, DC_G, and DC_B applied to the sub-test circuit 170S to a corresponding one of the data lines DL of the corresponding pixel circuits among the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3, and to an electrode of a corresponding one of the first load compensation capacitor Clm1, the second load compensation capacitor Clm2, and the third load compensation capacitor Clm3.

[0155] For example, the first switch SW of the sub-test circuit 170S can be turned on according to the control signal DC_GATE, and can output the test signal DC_R applied from the first input signal line IL1-1 to the first node N1 via the first output line WL1. The test signal DC_R can be supplied to a corresponding data line DL of the first pixel circuit PC1 of the red pixel PXr, and to an electrode of the first load compensation capacitor Clm1. The corresponding data line DL and the electrode of the first load compensation capacitor Clm1 are connected to the first node N1. Similarly, the second switch SW of the sub-test circuit 170S can be turned on according to the control signal DC_GATE, and can output the test signal DC_G applied from the second input signal line IL1-2 to the second node N2 via the second output line WL2. The test signal DC_G can be supplied to a corresponding data line DL of the second pixel circuit PC2 of the green pixel PXg, and to an electrode of the second load compensation capacitor Clm2 connected to the second node N2. The third switch SW of the sub-test circuit 170S can be turned on according to the control signal DC_GATE, and can output the test signal DC_B applied from the third input signal line IL1-3 to the third node N3 via the third output line WL3. The test signal DC_B can be supplied to a corresponding data line DL of the third pixel circuit PC3 of the blue pixel PXb, and to an electrode of the third load compensation capacitor Clm3, and each of the corresponding data line DL of the third pixel circuit PC3 of the blue pixel PXb and the electrode of the third load compensation capacitor Clm3 is connected to the third node N3.

[0156] Other electrodes (e.g., opposite electrodes) of the first load compensation capacitor Clm1, the second load compensation capacitor Clm2, and the third load compensation capacitor Clm3 that are not connected to the first node N1, the second node N2, and the third node N3 can have (e.g., can be supplied with) a level of a constant or substantially constant voltage (e.g., the first power supply voltage ELVDD).

[0157] Figure 7AEach of a first load compensation capacitor Clm1, a second load compensation capacitor Clm2, and a third load compensation capacitor Clm3 connected to a corresponding node (e.g., N1, N2, or N3) includes one capacitor. However, in another embodiment, at least one of the first load compensation capacitor Clm1, the second load compensation capacitor Clm2, and the third load compensation capacitor Clm3 may include a plurality of sub-capacitors connected in parallel with each other. For example, Figure 7B It is shown that each of the first load compensation capacitor Clm1, the second load compensation capacitor Clm2, and the third load compensation capacitor Clm3 includes a plurality of sub-capacitors (e.g., two sub-capacitors) connected in parallel. When each of the first load compensation capacitor Clm1, the second load compensation capacitor Clm2, and the third load compensation capacitor Clm3 includes a plurality of sub-capacitors connected in parallel, even when the first load compensation capacitor Clm1, the second load compensation capacitor Clm2, and the third load compensation capacitor Clm3 are arranged in a relatively narrow area (e.g., arranged in a relatively narrow area or arranged on a relatively narrow area), sufficient capacitance can be obtained. Thus, the load difference can be sufficiently compensated, and the area (or size) of the external area can be reduced.

[0158] In Figure 6 , Figure 7A and Figure 7B , one sub-test circuit 170S is described as including three switches SW, such that each switch SW is electrically connected to a corresponding one of a first pixel circuit PC1 corresponding to a red pixel PXr, a second pixel circuit PC2 corresponding to a green pixel PXg, and a third pixel circuit PC3 corresponding to a blue pixel PXb. In this case, the red pixel PXr, the green pixel PXg, and the blue pixel PXb may form a unit (e.g., one pixel or one pixel unit). However, the present disclosure is not limited thereto. For example, in another embodiment, the red pixel PXr and the green pixel PXg may form a unit (e.g., one pixel or one pixel unit), and the green pixel PXg and the blue pixel PXb may form another unit (e.g., another pixel or another pixel unit). In this case, as will be understood by those skilled in the art, each sub-test circuit 170S may include two switches or four switches according to the layout composition of the pixel circuit.

[0159] Figure 8 is a plan view showing a part of a display device according to an embodiment, Figure 9 is a cross-sectional view of the display device taken along the line IX-IX' of Figure 8 , Figure 10 is a cross-sectional view of the display device taken along the line X-X' of Figure 8 , Figure 11is a cross-sectional view of a display device taken along the line XI-XI' of Figure 8 , is a cross-sectional view of a display device taken along the line XII-XII' of Figure 12 , and is a cross-sectional view of a display device taken along the line XIII-XIII' of Figure 8 . And Figure 13 is a cross-sectional view of a display device taken along the line XIII-XIII' of Figure 8 .

[0160] Referring to Figure 8 , a first pixel circuit PC1, a second pixel circuit PC2, and a third pixel circuit PC3 corresponding to a first pixel to a third pixel (e.g., a red pixel PXr, a green pixel PXg, and a blue pixel PXb), respectively, may be arranged along a second direction with respect to each other. A plurality of first pixel circuits PC1 may be arranged along a first direction with respect to each other, and may be respectively connected to a data line DL and a power supply voltage line PL extending in the first direction. In other words, the data line DL may be electrically connected to the plurality of first pixel circuits PC1 arranged along the first direction. Similarly, the power supply voltage line PL may be electrically connected to each of the plurality of first pixel circuits PC1 arranged along the first direction. Similarly, a plurality of second pixel circuits PC2 may be arranged along the first direction with respect to each other, and may be respectively connected to corresponding data lines DL and corresponding power supply voltage lines PL. In addition, a plurality of third pixel circuits PC3 may be arranged along the first direction with respect to each other, and may be connected to corresponding data lines DL and corresponding power supply voltage lines PL. Further, the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 arranged along the second direction with respect to each other may be connected to a scan line, an emission control line, and an initialization voltage line extending in the second direction as described above with reference to Figure 6 .

[0161] A load compensation capacitor may be provided at one side of each data line DL, e.g., may be provided at the upper side of each data line DL in Figure 8 . For example, a first load compensation capacitor Clm1 may be provided at the upper side of the data line DL extending through (e.g., passing through) (e.g., across) the first pixel circuit PC1, a second load compensation capacitor Clm2 may be provided at the upper side of the data line DL extending through (e.g., passing through) (e.g., across) the second pixel circuit PC2, and a third load compensation capacitor Clm3 may be provided at the upper side of the data line DL extending through (e.g., passing through) (e.g., across) the third pixel circuit PC3.

[0162] Each of the first load compensation capacitor Clm1, the second load compensation capacitor Clm2, and the third load compensation capacitor Clm3 may include at least two electrodes overlapping each other. For example, in an embodiment, Figure 9It is shown that each of a first load compensation capacitor Clm1, a second load compensation capacitor Clm2, and a third load compensation capacitor Clm3 includes three electrodes.

[0163] Referring Figure 9 , a first electrode 510, a second electrode 520, and a third electrode 530 stacked on one another (e.g., stacked in sequence) may be disposed on a substrate 100, and an insulating layer may be interposed between adjacent electrodes among the first electrode 510, the second electrode 520, and the third electrode 530. For example, the first electrode 510 may be positioned on a buffer layer 110 and a first insulating layer 111, the second electrode 520 may be positioned on a second insulating layer 112, and the third electrode 530 may be positioned on a third insulating layer 113. The first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may include an inorganic material, e.g., such as silicon oxide, silicon nitride, and / or silicon oxynitride. A fifth insulating layer 115, a sixth insulating layer 116, and a seventh insulating layer 117 stacked on one another (e.g., stacked in sequence) may be disposed on the third electrode 530.

[0164] The first electrode 510 may include Mo, Cu, and / or Ti, and may have a single-layer structure or a multi-layer structure including one or more of the above materials. The first electrode 510 may be positioned at the same layer as the gate electrode of the first thin film transistor, the first electrode of the first capacitor, and / or the third electrode of the second capacitor (e.g., may be positioned on the same layer as the gate electrode of the first thin film transistor, the first electrode of the first capacitor, and / or the third electrode of the second capacitor), and may include the same or substantially the same material as one or more of the materials for forming the gate electrode of the first thin film transistor, the first electrode of the first capacitor, and / or the third electrode of the second capacitor.

[0165] The second electrode 520 may include Mo, Cu, and / or Ti, and may have a single-layer structure or a multi-layer structure. As referred to above Figure 4 described, the second electrode 520 may be positioned at the same layer as the first gate electrode of the second thin film transistor and / or the second electrode of the first capacitor (e.g., may be positioned on the same layer as the first gate electrode of the second thin film transistor and / or the second electrode of the first capacitor), and may include the same or substantially the same material as the first gate electrode of the second thin film transistor and / or the second electrode of the first capacitor.

[0166] The third electrode 530 may include Mo, Cu, and / or Ti, and may have a single-layer structure or a multi-layer structure including one or more of the above materials. As referred to above Figure 4As described, the third electrode 530 may be positioned on the same layer as the second gate electrode of the second thin film transistor and / or the fourth electrode of the second capacitor, and may include one or more materials that are the same as or substantially the same as the materials used to form the second gate electrode of the second thin film transistor and / or the fourth electrode of the second capacitor.

[0167] The first electrode 510 and the second electrode 520 that overlap each other with the second insulating layer 112 therebetween may define (e.g., may form) a first sub-capacitor LC1, and the second electrode 520 and the third electrode 530 that overlap each other with the third insulating layer 113 therebetween may define (e.g., may form) a second sub-capacitor LC2. The load compensation capacitor may include the first sub-capacitor LC1 and the second sub-capacitor LC2 connected in parallel with each other. In this regard, Figure 9 An example of the third load compensation capacitor Clm3 is shown.

[0168] In some embodiments, the first load compensation capacitor Clm1, the second load compensation capacitor Clm2, and the third load compensation capacitor Clm3 may share a part of one or more electrodes (e.g., the first electrode 510, the second electrode 520, and the third electrode 530). For example, in an embodiment, referring to Figure 8 and Figure 10 , each of the first load compensation capacitor Clm1, the second load compensation capacitor Clm2, and the third load compensation capacitor Clm3 may include the first electrode 510, the second electrode 520, and the third electrode 530. The first electrode 510 and the third electrode 530 may be shared (e.g., the first electrode 510 and the third electrode 530 may be a single electrode or may be electrically coupled as a common electrode). For example, unlike the plurality of second electrodes 520 spaced apart from each other (or from one another), the first electrode 510 may be formed integrally (e.g., may be formed as a single electrode or may be formed as a common electrode) while having an area corresponding to the area of the plurality of second electrodes 520 spaced apart from each other (e.g., having the same or substantially the same area as the area of the plurality of second electrodes 520 spaced apart from each other). Similarly, the third electrode 530 may be formed integrally (e.g., may be formed as a single electrode or may be formed as a common electrode) while having an area corresponding to the area of the plurality of second electrodes 520 (e.g., having the same or substantially the same area as the area of the plurality of second electrodes 520). In other words, each of the first electrode 510 and the third electrode 530 may have an area corresponding to the total area of the three second electrodes 520.

[0169] Similar to the embodiments described above with reference to Figure 9 In Figure 10In this case, each of the first load compensation capacitor Clm1, the second load compensation capacitor Clm2, and the third load compensation capacitor Clm3 may include a first sub-capacitor LC1 and a second sub-capacitor LC2 connected in parallel with each other.

[0170] Return reference Figure 8 , a connection portion may be provided between a column of pixel circuits and the load compensation capacitor. For example, as Figure 8 shown in, the first connection portion 210 may be positioned between the first pixel circuit PC1 of a column of red pixels PXr adjacent to each other and the first load compensation capacitor Clm1. The second connection portion 220 may be positioned between the second pixel circuit PC2 of a column of green pixels PXg adjacent to each other and the second load compensation capacitor Clm2. The third connection portion 230 may be positioned between the third pixel circuit PC3 of a column of blue pixels PXb adjacent to each other and the third load compensation capacitor Clm3.

[0171] The first connection portion 210 may have a connection structure in which a first output line WL1, a data line DL of the first pixel circuit PC1, and a second electrode 520 of the first load compensation capacitor Clm1 are electrically connected to each other (e.g., mutually). The first connection portion 210 may correspond to Figure 7A and Figure 7B the first node N1 shown in. For example, the first connection portion 210 may have a structure in which one end of the first output line WL1, one end of the data line DL of the first pixel circuit PC1, and one end of the second electrode 520 of the first load compensation capacitor Clm1 are connected to each other (e.g., mutually).

[0172] Reference Figure 8 and Figure 11 , the second electrode 520 of the first load compensation capacitor Clm1 may include a first end portion 521 protruding toward the first pixel circuit PC1. A first conductive layer 541 having an island shape (e.g., island or plate shape) and overlapping with the first end portion 521 may be provided on the first end portion 521. The first conductive layer 541 may be positioned on the fifth insulating layer 115 and may be connected to the first end portion 521 via a contact hole Cnt1 that extends through (e.g., passes through) the insulating layers (e.g., the third insulating layer 113 and the fifth insulating layer 115) between the first conductive layer 541 and the first end portion 521.

[0173] The end portion WL1p extending from the first output line WL1 may be positioned on the first conductive layer 541, and the end portion WL1p of the first output line WL1 may be connected to the first conductive layer 541 via a second contact hole Cnt2 extending through (e.g., passing through) the sixth insulating layer 116 between the end portion WL1p and the first conductive layer 541. The second contact hole Cnt2 may not overlap with the first contact hole Cnt1, or may overlap with the first contact hole Cnt1. The end portion WL1p of the first output line WL1 may be connected to the data line DL. For example, the first output line WL1 and the data line DL may include the same or substantially the same material as each other, and may be connected to each other (e.g., mutually) as a whole (e.g., connected to each other as a single component).

[0174] like Figure 8 As shown in , a portion of the data line DL extending through (e.g., passing through) (e.g., crossing) a column of pixel circuits PC, a portion of the second electrode 520 of the load compensation capacitor Clm, and a portion of the first output line WL1 may be electrically connected to each other (e.g., mutually) through the structure of the first connection portion 210 described above. Thus, as described above with reference to Figures 6 to 7B As described above, the test signal output from the sub test circuit may be provided to the data line DL connected to the first pixel circuit PC1 and the second electrode 520 of the first load compensation capacitor Clm1 via the first output line WL1.

[0175] For example, each of the first electrode 510 and the third electrode 530 of the first load compensation capacitor Clm1 may have a voltage level that is the same as or substantially the same as a voltage level of a power supply voltage line PL extending through (e.g., through) (e.g., across) a column of first pixel circuits PC1. In an embodiment, each of the first electrode 510 and the third electrode 530 of the first load compensation capacitor Clm1 may be electrically connected to a power supply voltage line PL extending through (e.g., through) (e.g., across) a column of first pixel circuits PC1.

[0176] Reference Figure 8 and Figure 12 The first electrode 510 may include a first end portion 511 that protrudes in one direction (eg, in a direction toward the pixel circuit PC). The end portion PLp of the power supply voltage line PL may be positioned on the first end portion 511. Figure 8 As shown in FIG. 1 , the end portion PLp of the power supply voltage line PL may have a width greater than the width of the power supply voltage line PL. The power supply voltage line PL may be positioned on the fifth insulating layer 115 and may include the same as described above with reference to FIG. Figure 4 The material of the described first connection electrode is the same or substantially the same material (eg, Al, Cu and / or Ti).

[0177] The end portion PLp of the power supply voltage line PL may overlap with the first end portion 511 of the first electrode 510. The end portion PLp of the power supply voltage line PL may be connected to the first end portion 511 of the first electrode 510 via a contact hole Cnt3 that extends through (e.g., passes through) an insulating layer (e.g., the second insulating layer 112, the third insulating layer 113, and the fifth insulating layer 115) between the end portion PLp of the power supply voltage line PL and the first end portion 511 of the first electrode 510.

[0178] Referring to Figure 8 and Figure 13 , the third electrode 530 may include a first end portion 531 that protrudes in one direction (e.g., in a direction toward the pixel circuit PC). The end portion PLp of the power supply voltage line PL may be positioned on the first end portion 531. The end portion PLp of the power supply voltage line PL may overlap with the first end portion 531 of the third electrode 530 and may be connected to the first end portion 531 of the third electrode 530 via a fourth contact hole Cnt4. For example, the end portion PLp of the power supply voltage line PL may be connected to the first end portion 531 of the third electrode 530 via a fourth contact hole Cnt4 that extends through (e.g., passes through) an insulating layer (e.g., the fifth insulating layer 115) between the end portion PLp of the power supply voltage line PL and the first end portion 531 of the third electrode 530.

[0179] The structure of the second connection portion 220 and / or the structure of the third connection portion 230 may be the same as or substantially the same as the structure of the first connection portion 210 described with reference to Figure 11 For example, the second connection portion 220 may have a structure in which the end portion of the second output line WL2, an island-shaped (e.g., island-shaped or plate-shaped) conductive layer, and the end portion of the second electrode 520 of the second load compensation capacitor Clm2 adjacent to the green pixel PXg are connected to each other (e.g., mutually) and a structure in which the end portion of the second output line WL2 is connected to the corresponding data line DL. The second connection portion 220 may correspond to the second node N2 shown in Figure 7A and Figure 7B . The portion of the data line DL that extends through (e.g., passes through) (e.g., across) a column of the second pixel circuits PC2, the portion of the second electrode 520 of the second load compensation capacitor Clm2, and the portion of the end portion of the second output line WL2 may be electrically connected to each other (e.g., mutually) by the structure of the second connection portion 220. A test signal output from the sub-test circuit may be provided to the data line DL connected to the second pixel circuit PC2 and to the second electrode 520 of the second load compensation capacitor Clm2 via the second output line WL2.

[0180] Similarly, the third connection portion 230 may have a structure in which the end of the third output line WL3, an island-shaped (e.g., island or plate-shaped) conductive layer, and the end of the second electrode 520 of the third load compensation capacitor Clm3 adjacent to the blue pixel PXb are connected to each other (e.g., mutually), and a structure in which the end of the third output line WL3 is connected to the corresponding data line DL. The third connection portion 230 may correspond to the third node N3 shown in Figure 7A and Figure 7B . A portion of the data line DL extending through (e.g., passing through) (e.g., across) a column of the third pixel circuits PC3 and a portion of the second electrode 520 of the third load compensation capacitor Clm3 may be electrically connected to each other (e.g., mutually), and a test signal output from the sub-test circuit may be provided to the corresponding data line DL connected to the third pixel circuit PC3 and the second electrode 520 of the third load compensation capacitor Clm3 via the third output line WL3.

[0181] In one or more of the embodiments described above with reference to Figures 8 to 13 , each of the first load compensation capacitor Clm1, the second load compensation capacitor Clm2, and the third load compensation capacitor Clm3 adjacent to the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 corresponding to the red pixel, the green pixel, and the blue pixel, respectively, shares the first electrode 510 and the third electrode 530 with each other. In another embodiment, for example, as shown in Figure 14 , the electrodes of the first load compensation capacitor Clm1, the electrodes of the second load compensation capacitor Clm2, and the electrodes of the third load compensation capacitor Clm3 may be separated from each other (e.g., mutually).

[0182] Figure 14 is a cross-sectional view showing a load compensation capacitor according to an embodiment. For example, Figure 14 shows an embodiment that may correspond to a modified embodiment of Figure 10 .

[0183] Referring to Figure 8 and Figure 14, each of the first load compensation capacitor Clm1, the second load compensation capacitor Clm2, and the third load compensation capacitor Clm3 may include at least two electrodes (e.g., a first electrode 510, a second electrode 520, and a third electrode 530). The first electrode 510, the second electrode 520, and the third electrode 530 provided in each of the first load compensation capacitor Clm1, the second load compensation capacitor Clm2, and the third load compensation capacitor Clm3 may be formed independently of each other (e.g., formed separately from each other). For example, the first electrode 510 provided in one load compensation capacitor Clm among adjacent load compensation capacitors Clm in the load compensation capacitor Clm may be spaced apart from the first electrode 510 provided in another load compensation capacitor Clm among adjacent load compensation capacitors Clm in the load compensation capacitor Clm. Similarly, the second electrode 520 and / or the third electrode 530 provided in one load compensation capacitor Clm may be spaced apart from the second electrode 520 or the third electrode 530 provided in another load compensation capacitor Clm.

[0184] In the embodiment described above with reference to Figure 8 , the lengths of the first load compensation capacitor Clm1, the second load compensation capacitor Clm2, and the third load compensation capacitor Clm3 adjacent to the pixel circuits of the red pixels, the pixel circuits of the green pixels, and the pixel circuits of the blue pixels corresponding to one load matching portion CLM are different from each other (e.g., from one another). For example, the length of the first load compensation capacitor Clm1 adjacent to the first pixel circuit PC1 of the red pixel PXr, the length of the second load compensation capacitor Clm2 adjacent to the second pixel circuit PC2 of the green pixel PXg, and the length of the third load compensation capacitor Clm3 adjacent to the third pixel circuit PC3 of the blue pixel PXb may be different from each other (e.g., from one another). This reflects the differences between pixels emitting light of different colors and can be distinguished from the increase in the size and / or area of the load matching capacitors included in each load matching portion CLM due to an increase in the distance between the load matching portion CLM (or its load matching capacitor) and the first virtual line VL1 (e.g., see Figure 5B and Figure 15 ). This will be described in more detail below with reference to Figure 15 .

[0185] Figure 15 is a plan view showing a display device according to an embodiment.

[0186] Referring to Figure 15, the load matching portion CLM may be located at one side of a column of pixel circuits. In an embodiment, the load matching portion CLM may be located at a side opposite to one side of the pad "PAD" relative to (e.g., based on) the second virtual line VL2, the second virtual line VL2 intersecting the center of the display area DA and extending in a second direction. Each load matching portion CLM may include a plurality of load compensation capacitors (e.g., a first load compensation capacitor Clm1, a second load compensation capacitor Clm2, and a third load compensation capacitor Clm3).

[0187] The lengths of the load compensation capacitors provided in each load matching portion CLM may vary (e.g., may be different from each other) according to the position (e.g., location) of the load matching portion CLM. For example, a first length d1 of a first load compensation capacitor Clm1 of a first load matching portion CLM-1 adjacent to the first virtual line VL1 may be less than a second length d2 of a first load compensation capacitor Clm1 of an Nth load matching portion CLM-N, the Nth load matching portion CLM-N being farther from the first virtual line VL1 than the first load matching portion CLM-1 in the second direction. Similarly, the length of a second load compensation capacitor Clm2 of the first load matching portion CLM-1 adjacent to the first virtual line VL1 may be less than the length of a second load compensation capacitor Clm2 of the Nth load matching portion CLM-N, the Nth load matching portion CLM-N being farther from the first virtual line VL1 than the first load matching portion CLM-1 in the second direction. The length of a third load compensation capacitor Clm3 of the first load matching portion CLM-1 adjacent to the first virtual line VL1 may be less than the length of a third load compensation capacitor Clm3 of the Nth load matching portion CLM-N, the Nth load matching portion CLM-N being farther from the first virtual line VL1 than the first load matching portion CLM-1 in the second direction.

[0188] As used herein, the phrase "the length of one load matching capacitor is less than the length of another load matching capacitor" may refer to a case where the overlapping area of the electrodes of the one load matching capacitor is less than the overlapping area of the electrodes of the another load matching capacitor. In an embodiment, the capacitance of the one load matching capacitor may be relatively less than the capacitance of the another load matching capacitor.

[0189] The drive circuit region DCR where (e.g., in which or on which) the drive circuit is provided may be located at the external region PA (e.g., located in the external region PA or on the external region PA). The drive circuit located at the drive circuit region DCR (e.g., located in the drive circuit region DCR or on the drive circuit region DCR) may vary (e.g., may be different) according to its position (e.g., location). This will be described below with reference toFigures 16 to 19 Describe the arrangement of the driving circuit in more detail.

[0190] Figure 16 is Figure 15 an enlarged plan view of part XVI of the display device shown in Figure 17 is Figure 15 an enlarged plan view of part XVII of the display device shown in Figure 18 is Figure 15 an enlarged plan view of part XVIII of the display device shown in, and Figure 19 is Figure 15 an enlarged plan view of part XIX of the display device shown in.

[0191] Referring to Figure 16 , a plurality of sub-first scan driving circuits 120S that can be sub-circuits of the first scan driving circuit 120 (for example, see Figure 1 ), a plurality of sub-transmission control circuits 140S that can be sub-circuits of the transmission control circuit 140 (for example, see Figure 1 ), and a plurality of sub-test circuits 170S that can be sub-circuits of the test circuit 170 (for example, see Figure 1 ) can be provided (for example, alternately provided) at the first sub-external region SPA1-1 (for example, can be provided in the first sub-external region SPA1-1 or can be provided on the first sub-external region SPA1-1).

[0192] Referring to Figure 17 , a plurality of sub-first scan driving circuits 120S that can be sub-circuits of the first scan driving circuit 120, a plurality of sub-transmission control circuits 140S that can be sub-circuits of the transmission control circuit 140, and a plurality of sub-data distribution circuits 160S that can be sub-circuits of the data distribution circuit 160 (for example, see Figure 1 ) can be provided (for example, alternately provided) at the second sub-external region SPA1-2 (for example, can be provided in the second sub-external region SPA1-2 or can be provided on the second sub-external region SPA1-2).

[0193] Referring to Figure 18 , a plurality of sub-second scan driving circuits 130S that can be sub-circuits of the second scan driving circuit 130 (for example, see Figure 1 ) and a plurality of sub-test circuits 170S that can be sub-circuits of the test circuit 170 can be provided (for example, alternately provided) at the third sub-external region SPA1-3 (for example, can be provided in the third sub-external region SPA1-3 or can be provided on the third sub-external region SPA1-3).

[0194] Referring to Figure 19, a plurality of sub-second scan driving circuits 130S that can be sub-circuits of the second scan driving circuit 130 and a plurality of sub-data distribution circuits 160S that can be sub-circuits of the data distribution circuit 160 may be provided (e.g., alternately provided) at the fourth sub-external region SPA1-4 (e.g., may be provided in the fourth sub-external region SPA1-4 or may be provided on the fourth sub-external region SPA1-4).

[0195] In a display device according to one or more embodiments, a load difference caused by the shape of a non-quadrilateral display region can be prevented or reduced, and a high-quality display device that effectively utilizes (e.g., makes full use of) the space of the display device can be provided.

[0196] It should be understood that the embodiments described herein should be considered only in a descriptive sense and not for purposes of limitation. The description of features and / or aspects within each embodiment should generally be considered available for other similar features and / or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those of ordinary skill in the art will understand that various modifications in form and / or detail can be made herein without departing from the spirit and scope of the disclosure as defined by the present disclosure and its equivalents.

Claims

1. A display device, wherein, The display device includes: a plurality of pixel circuits located at a display area having a non-quadrilateral shape; a first signal line extending in a first direction over the display area and electrically connected to a first pixel circuit among the plurality of pixel circuits; a first voltage line extending in the first direction over the display area; a first load compensation capacitor adjacent to an end portion of the first signal line extending from the first pixel circuit and an end portion of the first voltage line extending from the first pixel circuit; a test circuit located outside the display area; an output line electrically connected to the test circuit; and a connection portion configured to electrically connect the output line, the end portion of the first signal line, and electrodes of the first load compensation capacitor to each other.

2. The display device according to claim 1, wherein, The connection portion is between the first pixel circuit and the first load compensation capacitor.

3. The display device according to claim 1, wherein, The first load compensation capacitor includes a first electrode and a second electrode overlapping each other, and one of the first electrode and the second electrode is electrically connected to the output line and the first signal line via the connection portion.

4. The display device according to claim 3, wherein, The other of the first electrode and the second electrode is electrically connected to the first voltage line.

5. The display device according to claim 3, wherein, The first load compensation capacitor further includes a third electrode overlapping the first electrode and the second electrode.

6. The display device according to claim 5, wherein, The third electrode is electrically connected to the first voltage line.

7. The display device according to claim 1, wherein, The first pixel circuit includes: a first thin film transistor including a first semiconductor layer and a first gate electrode, a part of the first gate electrode overlapping the first semiconductor layer; a first capacitor electrically connected to the first thin film transistor; and a second thin film transistor located on the first thin film transistor and including a second semiconductor layer and a second gate electrode, a part of the second gate electrode overlapping the second semiconductor layer.

8. The display device according to claim 7, wherein, One of the first semiconductor layer and the second semiconductor layer includes a silicon semiconductor, and the other of the first semiconductor layer and the second semiconductor layer includes an oxide semiconductor.

9. The display device according to claim 7, wherein, The first load compensation capacitor includes at least two electrodes, one of the at least two electrodes including a material the same as that of the first gate electrode or the second gate electrode, and the other of the at least two electrodes including a material the same as that of an electrode of the first capacitor.

10. The display device according to claim 1, wherein, The plurality of pixel circuits have a stepped configuration at a periphery of the display area.

11. The display device according to claim 1, wherein, The display device further includes: a second signal line extending in the first direction over the display area and electrically connected to a second pixel circuit different from the first pixel circuit; and a second load compensation capacitor adjacent to an end portion of the second signal line and having a capacitance smaller than that of the first load compensation capacitor.

12. The display device according to claim 11, wherein, The second load compensation capacitor is closer to a first virtual line than the first load compensation capacitor, and the first virtual line extends through the center of the display area in the first direction.

13. The display device according to claim 11, wherein, The display area has a circular shape, an elliptical shape, or a curved polygon shape.

14. A display device, wherein, The display device includes: a plurality of pixel circuits located at a display area having a non-quadrilateral shape; a first signal line extending in a first direction on the display area; a load compensation capacitor located outside the display area and adjacent to the first signal line, the load compensation capacitor including a first electrode and a second electrode; a connection portion between the first signal line and the load compensation capacitor, the connection portion being configured to connect the first signal line to the load compensation capacitor; a test circuit located outside the display area; and an output line configured to electrically connect the test circuit to the connection portion.

15. The display device according to claim 14, wherein, The connection portion includes a conductive layer between the second electrode of the load compensation capacitor and the first signal line or a conductive layer between the second electrode of the load compensation capacitor and the output line.

16. The display device according to claim 14, wherein, The display device further includes a first power supply line adjacent to the first signal line and extending through the display area, wherein the first electrode of the load compensation capacitor is electrically connected to the first power supply line.

17. The display device according to claim 14, wherein, The load compensation capacitor further includes a third electrode positioned opposite to the first electrode, and the second electrode is between the third electrode and the first electrode.

18. The display device according to claim 14, wherein, One of the plurality of pixel circuits includes: a first thin film transistor including a first semiconductor layer and a first gate electrode, a part of the first gate electrode overlapping with the first semiconductor layer; a first capacitor electrically connected to the first thin film transistor; and a second thin film transistor including a second semiconductor layer and a second gate electrode, a part of the second gate electrode overlapping with the second semiconductor layer.

19. The display device according to claim 18, wherein, The second thin film transistor is located at a layer different from the layer of the first thin film transistor.

20. The display device according to claim 18, wherein, The first electrode and the second electrode of the load compensation capacitor include the same material as the material of the first gate electrode, the electrode of the first capacitor, or the second gate electrode.

21. The display device according to claim 18, wherein, The first semiconductor layer and the second semiconductor layer include different materials from each other.

22. The display device according to claim 21, wherein, The first semiconductor layer includes a silicon semiconductor, and the second semiconductor layer includes an oxide semiconductor.

23. The display device according to claim 14, wherein, The plurality of pixel circuits have a stepped configuration at the outer periphery of the display area.

24. The display device according to claim 14, wherein, The display device further includes a pad located at one side of the display area, wherein the load compensation capacitor is positioned at a side opposite to one side of the pad with respect to a virtual line, and the virtual line extends through the center of the display area in a second direction intersecting with the first direction.

25. The display device according to claim 14, wherein, The display area has a circular shape or an elliptical shape.

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