Display device and method of manufacturing a display device

Abstract

The present disclosure relates to a display device and a method of manufacturing the same, the display device including: a substrate having a display area and a pad area; a gate conductive layer disposed on the substrate, including a gate conductive metal layer and a gate cover layer, and forming a gate electrode in the display area and a wiring pad exposed by a pad opening in the pad area; an interlayer insulating film disposed on the gate conductive layer, covering the gate electrode; a data conductive layer disposed on the interlayer insulating film in the display area, including a source electrode and a drain electrode; a passivation layer disposed on the data conductive layer, covering the source electrode and the drain electrode; a via layer disposed on the passivation layer; a pixel electrode disposed on the via layer, connected to the source electrode through a contact hole penetrating the via layer and the passivation layer; and the via layer including a first area overlapping the pixel electrode in the display area and a second area not overlapping the pixel electrode in the display area and having a height smaller than that of the first area.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0091444, filed on July 29, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a display device and a method for manufacturing a display device. Background Technology

[0004] Many electronic devices include display devices for displaying images to a viewer, such as televisions (TVs), smartphones, tablet PCs (PCs), digital cameras, laptops, navigation devices, etc. Display devices may include multiple pixels and multiple pixel circuits for driving the pixels. Pixel circuits include wiring and thin-film transistors (TFTs) formed on an insulating substrate. Pixel circuits may also include wiring pads disposed at the ends of the wiring. External devices may be mounted on the wiring pads.

[0005] Display devices can be formed through multiple masking processes. Masking processes are useful for patterning wiring or insulating films. However, as the number of masking processes increases, the manufacturing process efficiency decreases. Furthermore, the reactive chemicals used in masking processes can cause corrosion of the conductive layers they contact. Therefore, the reliability of the display device decreases due to corrosion of the wiring pads exposed to reactive chemicals. Summary of the Invention

[0006] An exemplary embodiment of the present invention provides a display device including wiring pads with high reliability.

[0007] An exemplary embodiment of the present invention also provides a method for manufacturing a display device that improves process efficiency.

[0008] However, exemplary embodiments of the inventive concept are not limited to those set forth herein. The above and other embodiments of the inventive concept will become more apparent to those skilled in the art upon which this disclosure pertains from the following detailed description of exemplary embodiments of the inventive concept.

[0009] According to an exemplary embodiment of the present invention, a display device includes: a substrate having a display area and a pad area; a gate conductive layer disposed on the substrate, the gate conductive layer including a gate conductive metal layer and a gate cladding layer disposed on the gate conductive metal layer, the gate conductive layer forming a gate electrode disposed in the display area and wiring pads disposed in the pad area; an interlayer insulating film disposed on the gate conductive layer and covering the gate electrode, the wiring pads being exposed by pad openings; a data conductive layer disposed on the interlayer insulating film in the display area, the data conductive layer including a source electrode and a drain electrode; a passivation layer disposed on the data conductive layer and covering the source electrode and the drain electrode; a passivation layer disposed on the passivation layer; and a pixel electrode disposed on the passivation layer, the pixel electrode being connected to the source electrode through contact holes penetrating the passivation layer and the passivation layer; the passivation layer includes a first region in the display area overlapping with the pixel electrode and a second region in the display area not overlapping with the pixel electrode and having a height smaller than the height of the first region.

[0010] In an exemplary embodiment, the pad opening is formed by the interlayer insulating film and the via layer, and the interlayer insulating film and the via layer forming the inner sidewall of the pad opening are aligned with each other.

[0011] In an exemplary embodiment, the passivation layer is not disposed in the pad area.

[0012] In an exemplary embodiment, the via layer is directly disposed on the interlayer insulating film in the pad area.

[0013] In an exemplary embodiment, the pathway layer further includes a third region disposed in the pad area, and the third region has a height smaller than that of the second region.

[0014] In an exemplary embodiment, the interlayer insulating film includes a first portion disposed in the display area and a second portion disposed in the pad area and having a thickness less than that of the first portion, and the second portion overlaps with the third region of the via layer.

[0015] In an exemplary embodiment, the pad opening is formed by the interlayer insulating film and the passivation layer, and the interlayer insulating film and the passivation layer forming the inner sidewall of the pad opening are aligned with each other.

[0016] In an exemplary embodiment, the pathway layer is not disposed in the pad area.

[0017] In an exemplary embodiment, the passivation layer includes a third portion disposed in the display area and a fourth portion disposed in the pad area and having a thickness smaller than that of the third portion.

[0018] In an exemplary embodiment, the display device further includes a pixel defining film disposed on the pixel electrode, wherein the pixel defining film fills the second region of the via layer.

[0019] In an exemplary embodiment, the gate coating includes an indium zinc oxide (ZIO) film, an indium zinc oxide (IZO) film, an indium tin oxide (ITO) film, or a titanium (Ti) / molybdenum (Mo) / indium tin oxide (ITO) film.

[0020] In an exemplary embodiment, the gate conductive metal layer includes a gate main metal layer that contacts the gate cover layer from below and includes copper (Cu).

[0021] According to an exemplary embodiment of the present invention, a method of manufacturing a display device includes: forming a substrate including a display area and a pad area; forming a gate conductive layer on the substrate, the gate conductive layer including a gate conductive metal layer and a gate cladding layer deposited on the gate conductive metal layer, the gate conductive layer forming a gate electrode disposed in the display area and wiring pads disposed in the pad area; forming an interlayer insulating film on the gate conductive layer; forming a data conductive layer on the interlayer insulating film, the data conductive layer including a source electrode and a drain electrode disposed in the display area; forming a passivation layer on the data conductive layer; forming a via layer on the passivation layer, the via layer including a first opening overlapping the source electrode in the display area and a second opening overlapping the wiring pads in the pad area; forming a first material layer for forming pixel electrodes on the via layer; forming a first mask pattern on the first material layer; etching the first material layer by using the first mask pattern; and exposing the wiring pads by etching the interlayer insulating film overlapping the wiring pads using the remaining portion of the first mask pattern.

[0022] In an exemplary embodiment, etching the interlayer insulating film using the remaining portion of the first mask pattern includes performing a “full surface” etching process.

[0023] In an exemplary embodiment, due to the “whole surface” etching process, the portion of the pathway layer not covered by the first mask pattern is etched, such that the pathway layer is divided into a first region that overlaps with the pixel electrode and a second region that does not overlap with the pixel electrode and has a height smaller than that of the first region.

[0024] In an exemplary embodiment, forming the passivation layer includes: forming a second material layer for forming the passivation layer on the data conductive layer; forming a second mask pattern on the second material layer to expose the pad area and the portion of the second material layer that overlaps with the source electrode; and etching the passivation layer by using the second mask pattern.

[0025] In an exemplary embodiment, during the etching of the passivation layer, a portion of the interlayer insulating film located in the pad area is etched, such that the interlayer insulating film is divided into a first portion disposed in the display area and a second portion disposed in the pad area and having a thickness less than that of the first portion.

[0026] In an exemplary embodiment, the method further includes: forming the via layer on the unetched portion of the passivation layer; and removing the portion of the passivation layer exposed by the second opening of the via layer by performing a “whole surface” etching process.

[0027] In an exemplary embodiment, the gate coating includes an indium zinc oxide (ZIO) film, an indium zinc oxide (IZO) film, an indium tin oxide (ITO) film, or a titanium (Ti) / molybdenum (Mo) / indium tin oxide (ITO) film.

[0028] In an exemplary embodiment, the gate conductive metal layer includes a gate main metal layer that contacts the gate cover layer from below and includes copper (Cu).

[0029] According to the foregoing and other embodiments of the present invention, direct contact between the conductive layer forming the wiring pads and the reactive material can be prevented, and thus reliability can be improved.

[0030] Additionally, the gate overlay can be used as the contact electrode for the wiring pads. Therefore, since no additional masking process is required to form the contact electrodes for the wiring pads, process efficiency can be improved.

[0031] Other features and embodiments will be apparent from the following detailed description, drawings and claims. Attached Figure Description

[0032] The above and other embodiments and features of the present invention will become more apparent from the detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings, in which:

[0033] Figure 1 This is a top view of a display device according to an exemplary embodiment of the present invention;

[0034] Figure 2 This is an exemplary embodiment of the concept of the present invention. Figure 1 A cross-sectional view of the display device;

[0035] Figure 3 This is an exemplary embodiment of the concept of the present invention. Figure 1 A layout diagram of the circuit layer of the first display substrate of the display device;

[0036] Figure 4 This is an exemplary embodiment of the concept of the present invention. Figure 1 The equivalent circuit diagram of the pixels of the display device;

[0037] Figure 5 This is an exemplary embodiment of the concept of the present invention. Figure 1 A cross-sectional view of the first display substrate of the display device;

[0038] Figures 6 to 15 This illustrates the fabrication of an exemplary embodiment based on the concept of the present invention. Figure 5 A cross-sectional view of the process of the method for making the display device;

[0039] Figure 16 This is a cross-sectional view of a first display substrate of a display device according to another exemplary embodiment of the present invention; and

[0040] Figures 17 to 21 This illustrates the fabrication of an exemplary embodiment based on the concept of the present invention. Figure 16 A cross-sectional view of the process of the method for making a display device. Detailed Implementation

[0041] The inventive concept will now be described more fully below with reference to the accompanying drawings, in which exemplary embodiments of the inventive concept are illustrated. However, the inventive concept may be embodied in different forms and should not be construed as being limited to the exemplary embodiments set forth herein.

[0042] It will also be understood that when a layer is referred to as being "on" another layer or substrate, the layer may be directly on the other layer or substrate, or one or more intermediate layers may be present. Throughout the specification, the same reference numerals indicate the same components.

[0043] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms may be used only to distinguish one element from another. For example, without departing from the teachings of the inventive concept, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0044] Exemplary embodiments of the inventive concept will be described below with reference to the accompanying drawings.

[0045] Figure 1This is a top view of a display device according to an exemplary embodiment of the present invention.

[0046] Reference Figure 1 The display device 1 can be any type of electronic device that provides a display screen. For example, in Figure 1 In the exemplary embodiments shown, display device 1 is illustrated as a TV. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, in other exemplary embodiments, display device 1 may be a laptop computer, monitor, billboard, mobile phone, smartphone, tablet PC, electronic watch, smartwatch, watch phone, mobile communication terminal, electronic notebook, e-book reader, portable multimedia player (PMP), navigation device, game console, digital camera, Internet of Things (IoT) device, etc. In exemplary embodiments, display device 1 may have high definition or ultra-high definition such as 4K or 8K.

[0047] Display device 1 can be classified in various ways according to the image generating element of the device. For example, display device 1 can be an organic light-emitting diode (OLED) display device, an inorganic electroluminescent (EL) display device, a quantum dot light-emitting diode (QED) display device, a micro-scale light-emitting diode (micro-LED) display device, a plasma display panel (PDP) display device, a field emission display (FED) device, a cathode ray tube (CRT) display device, a liquid crystal display (LCD) device, or an electrophoretic display (EPD) device. However, exemplary embodiments of the present invention are not limited thereto. For ease of explanation, display device 1 will be described below as an OLED display device. However, without departing from the scope of the present invention, display device 1 can also be applied to various display devices other than OLED display devices.

[0048] As in Figure 1In the exemplary embodiments shown, in a plan view (e.g., when viewed from a third party towards DR3), the display device 1 may have a rectangular shape. However, in other exemplary embodiments, the display device 1 may have various other shapes, such as other polygonal shapes, spherical shapes, etc. In an exemplary embodiment in which the display device 1 is a TV, the display device 1 may be arranged such that the relatively long sides are aligned in the horizontal direction (e.g., extending in the first direction DR1) and the relatively short sides are aligned in the vertical direction (e.g., extending in the second direction DR2). However, exemplary embodiments of the inventive concept are not limited thereto. For example, the display device 1 may be arranged such that its relatively long sides are aligned in the vertical direction (e.g., extending in the second direction DR2) and its relatively short sides are aligned in the horizontal direction (e.g., extending in the first direction DR1). Alternatively, the display device 1 may be rotatably mounted such that its relatively long sides may be variably aligned either in the horizontal direction or in the vertical direction.

[0049] Display device 1 may include a display area DPA and a non-display area NDA. The display area DPA may be an effective area in which an image is displayed. Similar to display device 1, the display area DPA may have a rectangular shape in a plan view.

[0050] The display area DPA may include a plurality of pixels PX. Pixels PX may be arranged in both row and column directions. In a plan view (e.g., when viewed from a third direction DR3), pixels PX may have a rectangular or square shape. However, exemplary embodiments of the inventive concept are not limited thereto. For example, in another exemplary embodiment, in a plan view (e.g., on a third direction DR3), pixels PX may have a rhomboid shape such that the side of each pixel PX is oblique (e.g., extending obliquely) relative to the side of the display device 1. Pixels PX may include multiple sets of pixels PX displaying different colors. For example, in an exemplary embodiment, pixels PX may include a first color pixel PX for red pixels, a second color pixel PX for green pixels, and a third color pixel PX for blue pixels. However, exemplary embodiments of the inventive concept are not limited thereto. In an exemplary embodiment, pixels PX may be arranged alternately in a stripe or penTile manner.

[0051] The non-display area NDA can be disposed around the periphery of the display area DPA. The non-display area NDA can (e.g., in the first direction DR1 and / or the second direction DR2) surround the entire display area DPA or a portion of the display area DPA. The display area DPA can have a rectangular shape, and the non-display area NDA can be positioned (e.g., in the first direction DR1 and / or the second direction DR2) adjacent to all four sides of the display area DPA. The non-display area NDA can form the border of the display device 1.

[0052] The driving circuit or driving element for driving the display area DPA can be disposed in the non-display area NDA. For example, in the first non-display area NDA and the second non-display area NDA adjacent to the first and second opposite long sides of the display device 1 respectively (e.g., the portions of the non-display area on the lower and upper sides of the display device 1 in the second direction DR2), pad units can be disposed on the display substrate of the display device 1. External devices EXD can be mounted on the pad electrodes of the pad units. Examples of external devices EXD may include connection films, printed circuit boards (PCBs), driver integrated chips (DICs), connectors, wiring connection films, etc. However, examples of external devices EXD are not limited to these. In an exemplary embodiment, in the third non-display area NDA adjacent to the first opposite short side of the display device 1 (e.g., the portion of the non-display area on the left side of the display device 1 in the first direction DR1), the scan driving unit SDR can be directly formed on the display substrate of the display device 1.

[0053] Figure 2 yes Figure 1 A cross-sectional view of the display device.

[0054] exist Figure 2 The exemplary embodiment shown includes a top-emitting display device that emits light L in a direction (e.g., on a third-direction DR3) in which an emission layer EML is formed away from it (e.g., in a direction toward the second substrate 210). However, the exemplary embodiments of the present invention are not limited thereto. For example, in other exemplary embodiments, the display device 1 may be a bottom-emitting display device or a dual-emitting display device.

[0055] Reference Figure 2 The display device 1 may include an emissive layer EML, an encapsulation structure 170 covering the emissive layer EML, and a color control structure disposed on the encapsulation structure 170. In an exemplary embodiment, the color control structure may include a wavelength conversion layer WCL, a light transmission layer(s) TPL, and a color filter layer CFL. The display device 1 may also include a first display substrate 100 and a second display substrate 200 opposite to the first display substrate 100. For example, the first display substrate 100 and the second display substrate 200 may be spaced apart on a third-direction DR3, with a fill layer 300 disposed between them. The emissive layer EML, the encapsulation structure 170, and the color control structure (e.g., the wavelength conversion layer WCL, the light transmission layer TPL, and the color filter layer CFL) may be included in one of the first display substrate 100 and the second display substrate 200.

[0056] For example, in an exemplary embodiment, the first display substrate 100 may include a first substrate 110, an emission layer EML disposed on a first surface of the first substrate 110 (e.g., the top surface of the first substrate on the third-direction DR3), and an encapsulation structure 170 disposed on the emission layer EML (e.g., on the third-direction DR3). For example, in an exemplary embodiment, the second display substrate 200 may include a second substrate 210 and a color control structure (e.g., a wavelength conversion layer WCL, a light transmission layer TPL, and a color filter layer CFL) disposed on the first surface of the second substrate 210 facing the first substrate 110 (e.g., the bottom surface of the second substrate on the third-direction DR3). The color control structure may include a color filter layer CFL and a wavelength conversion layer WCL. The color control structure may also include a light transmission layer TPL disposed in some pixels at the same level as the wavelength conversion layer WCL (e.g., at a distance from the second substrate 210 on the third-direction DR3).

[0057] The filler layer 300 may be disposed (e.g., on a third-party DR3) between the package structure 170 and the color control structure. The filler layer 300 can bond the first display substrate 100 and the second display substrate 200, while filling the space between the first display substrate 100 and the second display substrate 200.

[0058] In an exemplary embodiment, the first substrate 110 of the first display substrate 100 may be an insulating substrate. The first substrate 110 may include a transparent material. For example, the first substrate 110 may include a transparent insulating material such as glass or quartz. In an exemplary embodiment, the first substrate 110 may be a rigid substrate. However, exemplary embodiments of the present invention are not limited thereto. Alternatively, the first substrate 110 may include a plastic material such as polyimide and may be flexible, and the first substrate 110 may be bendable, foldable, or rollable.

[0059] Multiple pixel electrodes (PXEs) can be disposed on a first surface of the first substrate 110 (e.g., the top surface of the first substrate in the third direction DR3). Pixel electrodes (PXEs) can be disposed within corresponding pixels (PX). Pixel electrodes (PXEs) of adjacent pixels (PX) can be separated. For example, pixel electrodes (PXEs) can be spaced apart in the first direction DR1 and / or the second direction DR2. A circuit layer (CCL) for driving the pixels (PX) can be disposed on the first substrate 110. In an exemplary embodiment, the circuit layer (CCL) can be disposed (e.g., on the third direction DR3) between the first substrate 110 and the pixel electrodes (PXEs). The circuit layer (CCL) will be described in detail later.

[0060] The pixel electrode (PXE) can be the first electrode of a light-emitting element, such as an anode electrode. In an exemplary embodiment, the pixel electrode (PXE) can have a stack of layers including: a layer of high work function material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3); and a layer of reflective material such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or mixtures thereof. The high work function material layer can be disposed on the reflective material layer, thereby being closer to the emitting layer (EML) than the reflective material layer. The pixel electrode (PXE) can have a multilayer structure of ITO / Mg, ITO / MgF, ITO / Ag, or ITO / Ag / ITO. However, exemplary embodiments of the inventive concept are not limited thereto.

[0061] A pixel defining film (PDL) may be disposed on a first surface of the first substrate 110 along the boundary between pixels (PX). The PDL may be disposed on a pixel electrode (PXE) and may include an opening exposing the pixel electrode (PXE) to define an emitter region (EMA). A non-emitter region (NEM) may be defined in the area where the PDL covers the pixel electrode (PXE) (e.g., the area excluding the opening). In an exemplary embodiment, the PDL may include an organic insulating material, such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). The PDL may also include inorganic materials. However, exemplary embodiments of the inventive concept are not limited thereto.

[0062] The emitter layer EML is disposed on the pixel electrode PXE exposed by the pixel-defining film PDL. For example, as in Figure 2 In the exemplary embodiments shown, the bottom surface of the emitter layer EML can be directly disposed on the top surface of the pixel electrode PXE. In the exemplary embodiment where the display device 1 is an OLED display device, the emitter layer EML may include an organic layer, which includes an organic material. The organic layer may include an organic light-emitting layer, and may also include a hole injection / transport layer and / or an electron injection / transport layer as an auxiliary layer for assisting light emission. In embodiments where the display device 1 is a micro-LED display device or a nano-scale LED (nano-LED) display device, the emitter layer EML may include an inorganic material such as an inorganic semiconductor.

[0063] In some exemplary embodiments, each of the emitting layers (EMLs) may have a columnar structure, wherein multiple organic light-emitting layers are stacked in the thickness direction (e.g., the third direction DR3), and charge-generating layers are disposed between them. In exemplary embodiments, the organic light-emitting layers may emit light of the same wavelength or may emit light of different wavelengths. At least some layers in each of the emitting layers (EMLs) of adjacent pixels (PXs) may be separate.

[0064] The emission layer EML can emit light of the same color in all pixels PX. For example, the emission layer EML can emit blue light or ultraviolet (UV) light, and the wavelength conversion layer WCL of the color control structure can convert the light of the pixels PX to display different colors.

[0065] Alternatively, the wavelength of light emitted by each of the emitting layers EML can vary from one pixel PX to another. For example, in an exemplary embodiment, the emitting layer EML can emit light of a first color in a first color pixel PX, light of a second color in a second color pixel PX, and light of a third color in a third color pixel PX.

[0066] The common electrode CME can be disposed on the emitter layer EML. The common electrode CME can contact not only the emitter layer EML, but also the top surface of the pixel defining film PDL. For example, as in... Figure 2 In the exemplary embodiment shown, the bottom surface of the common electrode CME can be directly disposed on the top surface of the emitter layer EML and the top surface of the pixel defining film PDL.

[0067] The common electrode CME can extend through the pixel PX and be connected. For example, in an exemplary embodiment, the common electrode CME can extend through each pixel PX along the entire surface of the first substrate 110 (e.g., in the first direction DR1). The common electrode CME can be the second electrode (e.g., cathode electrode) of each light-emitting element. However, exemplary embodiments of the inventive concept are not limited thereto.

[0068] In an exemplary embodiment, the common electrode CME may include a layer of a low work function material such as Li, Ca, LiF / Ca, LiF / Al, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF, Ba, or a compound or mixture thereof (e.g., a mixture of Ag and Mg). The common electrode CME may also include a transparent metal oxide layer disposed on the low work function material layer.

[0069] A pixel electrode (PXE), an emitter layer (EML), and a common electrode (CME) can form a light-emitting element (e.g., an OLED). Light can be emitted upwards from the emitter layer (EML) through the common electrode (CME).

[0070] The package structure 170 can be disposed on the common electrode CME. For example, as in Figure 2 In an exemplary embodiment, the bottom surface of the encapsulation structure 170 can be (e.g., on the third-party DR3) directly disposed on the top surface of the common electrode CME. The encapsulation structure 170 may include at least one thin-film encapsulation layer. For example, the encapsulation structure 170 may include a first inorganic film 171, an organic film 172, and a second inorganic film 173. For example, as in... Figure 2 In the exemplary embodiments shown, the first inorganic film 171, the organic film 172, and the second inorganic film 173 may be sequentially stacked on top of each other (e.g., on a third-direction DR3). In the exemplary embodiments, the first inorganic film 171 and the second inorganic film 173 may comprise silicon nitride, silicon oxide, or silicon oxynitride. The organic film 172 may comprise an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or BCB. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0071] The second display substrate 200 may be disposed on the encapsulation structure 170 (e.g., on the third-direction DR3) to face the encapsulation structure 170. In an exemplary embodiment, the second substrate 210 of the second display substrate 200 may include a transparent material. For example, the second substrate 210 may include a transparent insulating material such as glass or quartz. The second substrate 210 may be a rigid structure. However, exemplary embodiments of the inventive concept are not limited thereto. For example, in an alternative exemplary embodiment, the second substrate 210 may include a plastic material such as polyimide and may be flexible, and the second substrate 210 may therefore be bendable, foldable, or rollable.

[0072] The material, thickness, and transmittance of the second substrate 210 may be the same as or different from those of the first substrate 110. For example, in an exemplary embodiment, the second substrate 210 may have a higher transmittance than the first substrate 110 and may be thicker or thinner than the first substrate 110 (e.g., in terms of the distance between its top and bottom surfaces on the third-direction DR3).

[0073] A light-blocking member (BML) may be disposed along the boundary of a pixel (PX) on a first surface of a second substrate 210 (e.g., the bottom surface of the second substrate 210 on a third-direction DR3). The light-blocking member (BML) may overlap with a pixel-defining film (PDL) (e.g., on a third-direction DR3) and may be located within a non-emitting region (NEM). The light-blocking member (BML) may include openings that expose portions of the first surface of the second substrate 210 that overlap with the emitting region (EMA). In a plan view (e.g., when viewed from a third-direction DR3), the light-blocking member (BML) may be formed in a grid shape.

[0074] In an exemplary embodiment, the light-blocking member BML may comprise an organic material. The light-blocking member BML absorbs external light and thus reduces color distortion that may be caused by reflection of external light. The light-blocking member BML also prevents light emitted from the emitting layer EML from seeping into adjacent pixels PX, thereby improving image sharpness.

[0075] Light-blocking components (BMLs) can absorb all visible wavelengths. A BML can comprise a light-absorbing material. For example, a BML can be formed from a material used as a black matrix.

[0076] Alternatively, the light-blocking member BML can absorb light of a specific visible wavelength and transmit light of other wavelengths through it. For example, the light-blocking member BML may comprise the same material as the color filter layer CFL. For example, the light-blocking member BML may be formed of the same material as the blue color filter layer CFL3. In some exemplary embodiments, the light-blocking member BML may be integrally formed with the blue color filter layer CFL3.

[0077] In some exemplary embodiments, the display device 1 may not include the light-blocking member BML.

[0078] As in Figure 2 In the exemplary embodiment, the color filter layer CFL may be disposed on the portion of the first surface of the second substrate 210 exposed by the opening of the light blocking member BML. In the exemplary embodiment, the color filter layer CFL may also be disposed on the light blocking member BML.

[0079] A color filter layer CFL may include a first color filter layer CFL1 disposed in a first color pixel PX, a second color filter layer CFL2 disposed in a second color pixel PX, and a third color filter layer CFL3 disposed in a third color pixel PX. Each of the first color filter layer CFL1, the second color filter layer CFL2, and the third color filter layer CFL3 may include a colorant, such as a pigment or dye, capable of absorbing all wavelengths except a specific wavelength. For example, the first color filter layer CFL1, the second color filter layer CFL2, and the third color filter layer CFL3 may be a red color filter, a green color filter, and a blue color filter layer, respectively. Figure 2 In the exemplary embodiments shown, adjacent color filter layers CFLs are shown spaced apart from each other over the light-blocking member BML (e.g., in the first direction DR1). However, in some exemplary embodiments, adjacent color filter layers CFLs may partially overlap each other over the light-blocking member BML.

[0080] The first overlay 220 can be disposed on the color filter layer CFL. For example, as in Figure 2 In the exemplary embodiment shown, the top surface of the first coating 220 (e.g., on a third-party DR3) can directly contact the bottom surface of the color filter layer CFL. The first coating 220 can prevent impurities such as moisture, air, and other contaminants from penetrating and contaminating the color filter layer CFL. The first coating 220 can prevent the diffusion of colorants in the color filter layer CFL.

[0081] The first cladding layer 220 may be in direct contact with the first surface of the color filter layer CFL (e.g., the bottom surface of the color filter layer on the third-direction DR3). In an exemplary embodiment, the first cladding layer 220 may be formed of an inorganic material. For example, the first cladding layer 220 may include silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, or silicon oxynitride. However, exemplary embodiments of the inventive concept are not limited thereto.

[0082] A barrier PTL can be disposed on the first cladding layer 220. The barrier PTL can also be disposed within the non-emitting region (NEM). For example, as in... Figure 2 In the exemplary embodiments shown, the top surface of the blocking wall PTL (e.g., on the third-direction DR3) can directly contact the bottom surface of the first cladding 220 (e.g., on the third-direction DR3) in the non-emissive region NEM. The blocking wall PTL can be configured to overlap with the light-blocking member BML (e.g., on the third-direction DR3). The blocking wall PTL may include openings that expose the color filter layer CFL (e.g., extending in the first direction DR1). In the exemplary embodiments, the blocking wall PTL may include a photosensitive organic material. However, the exemplary embodiments of the inventive concept are not limited thereto. The blocking wall PTL may also include a light-shielding material.

[0083] The wavelength conversion layer (WCL) and / or the light transmission layer (TPL) can be disposed in the space exposed by the opening of the barrier wall (PTL). In an exemplary embodiment, the wavelength conversion layer (WCL) and the light transmission layer (TPL) can be formed by inkjet printing using the barrier wall (PTL) as a dam. However, exemplary embodiments of the inventive concept are not limited thereto.

[0084] In an exemplary embodiment in which the emitting layer EML emits light of a third color, the wavelength conversion layer WCL may include a first wavelength conversion pattern WCL1 and a second wavelength conversion pattern WCL2 respectively disposed in the first color pixel PX and the second color pixel PX. The light transmission layer TPL may be disposed in the third color pixel PX.

[0085] The first wavelength conversion pattern WCL1 may include a first matrix resin BRS1 and a first wavelength conversion material WCP1 disposed in the first matrix resin BRS1. The second wavelength conversion pattern WCL2 may include a second matrix resin BRS2 and a second wavelength conversion material WCP2 disposed in the second matrix resin BRS2. The light transmission layer TPL may include a third matrix resin BRS3 and a scatterer SCP disposed in the third matrix resin BRS3.

[0086] The first matrix resin BRS1, the second matrix resin BRS2, ​​and the third matrix resin BRS3 may comprise light-transmitting organic materials. For example, in an exemplary embodiment, the first matrix resin BRS1, the second matrix resin BRS2, ​​and the third matrix resin BRS3 may comprise epoxy resin, acrylic resin, cardo resin, or imide resin. However, exemplary embodiments of the present invention are not limited thereto. The first matrix resin BRS1, the second matrix resin BRS2, ​​and the third matrix resin BRS3 may be formed from the same material. However, exemplary embodiments of the present invention are not limited thereto.

[0087] The scatterer SCP can be particles of metal oxide or particles of organic material. In an exemplary embodiment, the metal oxide can be titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), indium oxide (In2O3), zinc oxide (ZnO), or tin oxide (SnO2), and the organic material can be acrylic resin or urethane resin.

[0088] The first wavelength conversion material WCP1 can convert a third color to a first color, and the second wavelength conversion material WCP2 can convert a third color to a second color. The first wavelength conversion material WCP1 and the second wavelength conversion material WCP2 can be quantum dots, quantum rods, or phosphors. In an exemplary embodiment, the quantum dots can include group IV nanocrystal materials, group II-VI compound nanocrystal materials, group III-V compound nanocrystal materials, group IV-VI compound nanocrystal materials, or combinations thereof. Each of the first wavelength conversion pattern WCL1 and the second wavelength conversion pattern WCL2 may further include a scatterer SCP that improves the wavelength conversion efficiency of the first wavelength conversion pattern WCL1 and the second wavelength conversion pattern WCL2.

[0089] A light-transmitting layer (TPL) located in the third-color pixel (PX) allows third-color light incident on it from the emission layer (EML) to pass through while maintaining the wavelength of the incident light. The scattering component (SCP) of the TPL can control the path of light emitted through it. The TPL may not include wavelength conversion material.

[0090] The second coating 230 can be disposed on the wavelength conversion layer WCL and the light transmission layer TPL. For example, as in Figure 2 In the exemplary embodiments shown, the top surface of the second cladding layer 230 (e.g., on the third-direction DR3) can directly contact the bottom surfaces of the wavelength conversion layer WCL and the light transmission layer TPL (e.g., on the third-direction DR3). In the exemplary embodiments, the second cladding layer 230 can be formed of an inorganic material. The second cladding layer 230 may include one selected from the aforementioned inorganic materials used to form the first cladding layer 220. For example, the second cladding layer 230 may be formed of the same material as the first cladding layer 220. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0091] A filler layer 300 may (e.g., on a third-party DR3) be disposed between the first display substrate 100 and the second display substrate 200. The filler layer 300 may fill the space between the first display substrate 100 and the second display substrate 200, and may bond the first display substrate 100 and the second display substrate 200 to each other. The filler layer 300 may be disposed between the encapsulation structure 170 of the first display substrate 100 and the second overlay 230 of the second display substrate 200. For example, as in… Figure 3In the exemplary embodiments shown, the bottom surface of the second cladding layer 230 (e.g., on the third-direction DR3) can directly contact the top surface of the filler layer 300 (e.g., on the third-direction DR3), and the top surface of the encapsulation structure 170 (e.g., on the third-direction DR3) can directly contact the bottom surface of the filler layer 300 (e.g., on the third-direction DR3). In the exemplary embodiments, the filler layer 300 can be formed of a Si-based organic material or an epoxy-based organic material. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0092] The circuit layer CCL of display device 1 will be described below.

[0093] Figure 1 yes Figure 3 The layout diagram of the circuit layer of the first display substrate of the display device.

[0094] Reference Figure 1 Multiple wirings are arranged on the first substrate 110. The wirings include scan line SCL, sensing signal line SSL, data line DTL, reference voltage line RVL, and first power supply line ELVDL.

[0095] The scan line SCL and the sensing signal line SSL can extend along the first direction DR1. The scan line SCL and the sensing signal line SSL can be connected to the scan driving unit SDR. The scan driving unit SDR can include a driving circuit system including a circuit layer CCL. In an exemplary embodiment, the scan driving unit SDR can be disposed in the third non-display area NDA of the first substrate 110 (e.g., the portion of the non-display area NDA located on the upper left side of the display device 1 along the first direction DR1). However, exemplary embodiments of the present invention are not limited thereto. Alternatively, the scan driving unit SDR can be disposed in the fourth non-display area NDA (e.g., the portion of the non-display area NDA located on the upper right side of the display device 1 along the first direction DR1) or in both the third and fourth non-display areas NDA. The scan driving unit SDR can be connected to the signal connection wiring CWL, and at least a first end of the signal connection wiring CWL can form a pad WPD_CW in the first non-display area NDA and / or in the second non-display area NDA, and thus can be connected to Figure 3 External device EXD.

[0096] The data line DTL and the reference voltage line RVL may extend along a second direction DR2 intersecting the first direction DR1. The first power line ELVDL may include a portion extending along the first direction DR1. The first power line ELVDL may also include a portion extending along the second direction DR2. In an exemplary embodiment, the first power line ELVDL may have a mesh structure. However, exemplary embodiments of the inventive concept are not limited thereto.

[0097] In addition to the pad WPD_CW located at at least the first end of the signal connection wiring CWL, the wiring pad WPD may also include at least the wiring pad WPD_DT located at the first end of the data line DTL, the wiring pad WPD_RV located at the first end of the reference voltage line RVL, and the wiring pad WPD_ELVD located at the first end of the first power line ELVDL. The wiring pad WPD may be located in the non-display area NDA. Figure 1 In the exemplary embodiment shown, the data line DTL's wiring pad WPD_DT (hereinafter, data pad WPD_DT) may be located in the first non-display area NDA, and the reference voltage line RVL's wiring pad WPD_RV (hereinafter, reference voltage pad WPD_RV) and the first power line ELVDL's wiring pad WPD_ELVD (hereinafter, first power pad WPD_ELVD) may be located in the second non-display area NDA. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, in another exemplary embodiment, the data pad WPD_DT, the reference voltage pad WPD_RV, and the first power pad WPD_ELVD may all be located in the same area (e.g., in the first non-display area NDA). Figure 4 The external device EXD can be mounted on the wiring pad WPD. In an exemplary embodiment, the external device EXD can be mounted on the wiring pad WPD via an anisotropic conductive film or via ultrasonic bonding.

[0098] A pixel PX located on a first substrate 110 includes a pixel driving circuit. The aforementioned wiring may pass through or surround the pixel PX to apply driving signals to the pixel driving circuit. Each of the pixel driving circuits may include at least one transistor and at least one capacitor. The number of transistors and capacitors disposed in each of the pixel driving circuits may vary. The pixel driving circuit will be described below as having a “3T1C” structure, which has three transistors and one capacitor. However, exemplary embodiments of the inventive concept are not limited thereto, and the positioning of the wiring pads WPD may vary. For example, the pixel driving circuit of the pixel PX may include various other structures, such as a “2T1C” structure (e.g., having two transistors and one capacitor), a “7T1C” structure (e.g., having seven transistors and one capacitor), a “6T1C” structure (e.g., having six transistors and one capacitor), etc.

[0099] Figure 1 yes Figure 4 The equivalent circuit diagram of the pixels of the display device.

[0100] Reference Figure 4The pixel PX of the display device 1 includes a light-emitting element EMD, three transistors (e.g., a driving transistor DTR, a first switching transistor STR1, and a second switching transistor STR2) and a storage capacitor CST.

[0101] The light-emitting element (EMD) emits light according to the current supplied to it via the driving transistor (DTR). In an exemplary embodiment, the light-emitting element (EMD) may be implemented as an OLED, micro-LED, or nano-LED.

[0102] The first electrode (e.g., anode electrode) of the light-emitting element EMD can be connected to the source electrode of the driving transistor DTR, and the second electrode (e.g., cathode electrode) of the light-emitting element EMD can be connected to a second power line ELVSL to which a low potential voltage (e.g., a second power supply voltage) is supplied. The second power supply voltage can be lower than the high potential voltage (e.g., the first power supply voltage) applied to the first power line ELVDL.

[0103] The driving transistor DTR controls the current flowing from the first power line ELVDL to the light-emitting element EMD based on the voltage difference between its gate and source electrodes. The gate electrode of the driving transistor DTR can be connected to the first source / drain electrode of the first switching transistor STR1. The source electrode of the driving transistor DTR can be connected to the first electrode of the light-emitting element EMD, and the drain electrode of the driving transistor DTR can be connected to the first power line ELVDL to which the first power supply voltage is supplied.

[0104] The first switching transistor STR1 is turned on by a scan signal from the scan line SCL to connect the data line DTL to the gate electrode of the driving transistor DTR. The gate electrode of the first switching transistor STR1 can be connected to the scan line SCL. The first source / drain electrode of the first switching transistor STR1 can be connected to the gate electrode of the driving transistor DTR, and the second source / drain electrode of the first switching transistor STR1 can be connected to the data line DTL.

[0105] The second switching transistor STR2 is turned on by a sensing signal from the sensing signal line SSL to connect the reference voltage line RVL to the source electrode of the driving transistor DTR. The gate electrode of the second switching transistor STR2 can be connected to the sensing signal line SSL. The first source / drain electrode of the second switching transistor STR2 can be connected to the reference voltage line RVL, and the second source / drain electrode of the second switching transistor STR2 can be connected to the source electrode of the driving transistor DTR.

[0106] In an exemplary embodiment, the first source / drain electrodes of the first switching transistor STR1 and the second switching transistor STR2 can be source electrodes, and the second source / drain electrodes of the first switching transistor STR1 and the second switching transistor STR2 can be drain electrodes. However, the exemplary embodiments of the present invention are not limited thereto. For example, in an optional embodiment, the first source / drain electrodes of the first switching transistor STR1 and the second switching transistor STR2 can be drain electrodes, and the second source / drain electrodes of the first switching transistor STR1 and the second switching transistor STR2 can be source electrodes.

[0107] A storage capacitor CST is formed between the gate and source electrodes of the driving transistor DTR. The storage capacitor CST stores the differential voltage between the gate and source electrodes of the driving transistor DTR.

[0108] The driving transistor DTR, the first switching transistor STR1, and the second switching transistor STR2 can be formed as a thin-film transistor (TFT). Figure 5 The diagram shows a driving transistor DTR and a first switching transistor STR1 and a second switching transistor STR2 as N-type metal-oxide-semiconductor field-effect transistors (MOSFETs). However, exemplary embodiments of the present invention are not limited thereto. For example, in an alternative embodiment, the driving transistor DTR and the first switching transistor STR1 and the second switching transistor STR2 may be formed as P-type MOSFETs. In another exemplary embodiment, at least one of the driving transistor DTR and the first switching transistor STR1 and the second switching transistor STR2 may be formed as an N-type MOSFET, and the other transistors may be formed as P-type MOSFETs.

[0109] Figure 1 yes Figure 5 A cross-sectional view of the first display substrate of the display device. Specifically, Figure 5 It is a cross-sectional view showing a portion of the display area DPA (specifically, the transistor region TRR and capacitor region CPR of pixel PX) and a portion of the non-display area NDA (specifically, the pad area PDA). Figure 5 The transistor region TRR is the area in which the driving transistor DTR is set. Figure 5 The circuit layer CCL of the first display substrate 100 is mainly shown, and for convenience, only the pixel defining film PDL up to the first display substrate 100 is shown.

[0110] Reference Figure 5The circuit layer CCL may include a semiconductor layer 150, a plurality of conductive layers, and a plurality of insulating layers disposed on the first substrate 110. In an exemplary embodiment, the semiconductor layer 150 may include an oxide semiconductor. In an exemplary embodiment, the plurality of conductive layers may include a lower metal layer 120, a gate conductive layer 130, a data conductive layer 140, and a pixel electrode PXE. In an exemplary embodiment, the plurality of insulating layers may include a buffer layer 161, a gate insulating film 162, an interlayer insulating film 163, a passivation film, and a pass-through layer 165.

[0111] The lower metal layer 120 can be disposed on the first substrate 110. For example, as in Figure 5 In the exemplary embodiment shown, the lower metal layer 120 may be directly disposed on the first substrate 110 (e.g., on a third-party DR3). The lower metal layer 120 may be a light-shielding layer protecting the semiconductor layer 150 from external light. The lower metal layer 120 may have a patterned shape. The lower metal layer 120 may be disposed in the transistor region TRR. The lower metal layer 120 may be configured to cover at least the channel region of the semiconductor layer 150 from below the semiconductor layer 150, or to cover the entire semiconductor layer 150. The lower metal layer 120 may be electrically connected to the source electrode SEL of the driving transistor DTR via a first contact hole CNT1 to suppress voltage variations in the driving transistor DTR. In the exemplary embodiment, the lower metal layer 120 may be formed as a double layer consisting of a stack of titanium (Ti) layers and copper (Cu) layers. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0112] A buffer layer 161 is disposed on the lower metal layer 120. The buffer layer 161 may be configured to cover the entire surface of the first substrate 110 on which the lower metal layer 120 is formed. For example, as in... Figure 5 In an exemplary embodiment, the buffer layer 161 may (e.g., on a third-party DR3) be directly disposed on the top surface of the lower metal layer 120 and the top surface of the first substrate 110. In an exemplary embodiment, the buffer layer 161 may comprise silicon nitride, silicon oxide, or silicon oxynitride. The buffer layer 161 may comprise SiN. x / SiO x The invention has two layers. However, exemplary embodiments of the inventive concept are not limited thereto.

[0113] A semiconductor layer 150 is disposed on a buffer layer 161. For example, as in... Figure 5In an exemplary embodiment, the semiconductor layer 150 may be directly disposed on the buffer layer 161 (e.g., on the third-party DR3). The semiconductor layer 150 is disposed in the transistor region TRR and forms the channel of the transistor DTR. In an exemplary embodiment, the semiconductor layer 150 may include an oxide semiconductor. The oxide semiconductor may include a binary compound (AB) comprising, for example, indium (In), zinc (Zn), gallium (Ga), tin (Sn), Ti, Al, hafnium (Hf), zirconium (Zr), or magnesium (Mg). x ), ternary compounds (AB) x C y ) or quaternary compounds (AB) x C y D z For example, semiconductor layer 150 may include indium tin zinc oxide (IGZO). However, exemplary embodiments of the present invention are not limited thereto.

[0114] A gate insulating film 162 is disposed on the semiconductor layer 150. In an exemplary embodiment, the gate insulating film 162 may be formed with the same pattern as the gate conductive layer 130. For example, the sidewalls of the gate insulating film 162 may be substantially aligned with the sidewalls of the gate conductive layer 130. However, exemplary embodiments of the present invention are not limited thereto. The gate insulating film 162 may comprise a silicon compound or a metal oxide. For example, the gate insulating film 162 may comprise silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, or titanium oxide. For example, the gate insulating film 162 may comprise SiO2. x Membrane. However, exemplary embodiments of the present invention are not limited thereto.

[0115] A gate conductive layer 130 is disposed on a gate insulating film 162. For example, as in Figure 4 In the exemplary embodiment shown, the gate conductive layer 130 may be directly disposed on the gate insulating film 162 (e.g., on the third-party DR3). The gate electrode GEL located in the transistor region TRR, the first electrode (or lower electrode) of the capacitor CST located in the capacitor region CPR, and the wiring pad WPD located in the pad region PDA may be formed by the gate conductive layer 130. Figure 5 The scan line SCL and the sensing signal line SSL can also be formed by the gate conductive layer 130.

[0116] The gate conductive layer 130 may include a gate conductive metal layer 131 and a gate capping layer 132 disposed on the gate conductive metal layer 131. In an exemplary embodiment, the gate conductive metal layer 131 may be formed as a single layer or as a multilayer film. For example, the gate conductive metal layer 131 may include a gate main metal layer 131a and a gate substrate layer 131b disposed below the gate main metal layer 131a.Figure 5 In an exemplary embodiment, the top surface of the gate substrate layer 131b can directly contact the bottom surface of the gate main metal layer 131a. The bottom surface of the gate cladding layer 132 can directly contact the top surface of the gate conductive metal layer 131. The gate substrate layer 131b, the gate main metal layer 131a, and the gate cladding layer 132 can all be formed of conductive material. In an exemplary embodiment, the gate substrate layer 131b, the gate main metal layer 131a, and the gate cladding layer 132 can be patterned using a single mask process. For example, the sidewalls of the gate substrate layer 131b, the gate main metal layer 131a, and the gate cladding layer 132 can be aligned. In some exemplary embodiments, the upper layer of the gate conductive layer 130 may not protrude beyond the lower layer of the gate conductive layer 130. For example, the gate conductive layer 130 may not include a top-protruding tip structure. In this embodiment, the sidewall of the lower layer of the gate conductive layer 130 may be aligned with the corresponding sidewall of the upper layer of the gate conductive layer 130, or (e.g., in the first direction DR1) protrude outward beyond the corresponding sidewall of the upper layer of the gate conductive layer 130. The gate conductive layer 130 may not include an insulating layer disposed between layers of the gate conductive layer that overlap each other in the thickness direction (e.g., in the third direction DR3).

[0117] The gate substrate layer 131b may contribute to the film formation properties of the gate main metal layer 131a (e.g., adhesion) or may prevent reactive materials from penetrating the gate main metal layer 131a from the gate insulating film 162. The gate main metal layer 131a may also prevent the diffusion of its material (e.g., Cu) into layers disposed beneath it. In an exemplary embodiment, the gate substrate layer 131b may comprise materials such as Ti, tantalum (Ta), Ca, Cr, Mg, or Ni. However, exemplary embodiments of the inventive concept are not limited thereto.

[0118] The gate main metal layer 131a can transmit signals and can be formed of a low-resistivity material. The gate main metal layer 131a can have a thickness greater than the gate substrate layer 131b and the gate capping layer 132 (e.g., its length on the third-direction DR3), and can be formed of a material with a lower resistance than the gate substrate layer 131b and the gate capping layer 132. In an exemplary embodiment, the gate main metal layer 131a may include materials such as Cu, Mo, Al, or Ag. However, exemplary embodiments of the inventive concept are not limited thereto.

[0119] A gate cladding layer 132 covers and protects the gate main metal layer 131a from above. The gate cladding layer 132 protects the gate main metal layer 131a from etchants or other chemicals used in the formation of layers or elements above the gate conductive layer 130. The gate cladding layer 132 also prevents material (e.g., Cu) from the gate main metal layer 131a from diffusing into layers disposed above it. The gate cladding layer 132 can be in direct contact with the gate main metal layer 131a.

[0120] The gate cap 132 can provide a contact electrode for the wiring pad WPD in the pad area PDA. Therefore, the gate cap 132 can be formed of a material suitable for use as a contact electrode for the wiring pad WPD. In an exemplary embodiment, the gate cap 132 may include at least one compound selected from indium zinc oxide (ZIO), IZO, and ITO. For example, the gate cap 132 may include a ZIO film, an IZO film, or an ITO film, or may be formed as a Ti / Mo / ITO multilayer film.

[0121] For example, the gate conductive layer 130 may include a gate substrate layer 131b comprising Ti, a gate main metal layer 131a comprising Cu, and a gate cladding layer 132 comprising ZIO. Therefore, the gate conductive layer 130 may comprise a Ti / Cu / ZIO trilayer. In embodiments where the gate cladding layer 132 is formed of ZIO, the gate cladding layer 132 and the underlying Cu layer may be etched together without creating any top-side spikes, and the gate cladding layer 132 may suitably serve as a contact electrode for the wiring pad (WPD). In another exemplary embodiment, the gate conductive layer 130 may be formed as a Ti / Mo / ITO trilayer, in which case the gate conductive layer 130 may have a Ti / Cu / Ti / Mo / ITO stack.

[0122] Because the gate conductive layer 130 includes a gate cladding layer 132 at its top portion, corrosion of the gate main metal layer 131a of the gate conductive metal layer 131 can be prevented. Therefore, the reliability of the wiring pad WPD is improved.

[0123] An interlayer insulating film 163 is disposed on the gate conductive layer 130. For example, as in Figure 5In the exemplary embodiment shown, the interlayer insulating film 163 is directly disposed on the gate conductive layer 130, which includes a gate overlay 132 disposed on the gate electrode GEL in the transistor region TRR, a first electrode of the capacitor CST in the capacitor region CPR, and a portion of the wiring pad WPD in the pad region PDA. In the exemplary embodiment, the interlayer insulating film 163 may include an inorganic insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, or zinc oxide. For example, the interlayer insulating film 163 may include SiON. However, the exemplary embodiments of the present invention are not limited thereto.

[0124] Interlayer insulating film 163 may include portions with different heights (e.g., the distance from the top surface of interlayer insulating film 163 to the top surface of the first substrate 110 on a third-direction DR3). For example, interlayer insulating film 163 may include a first portion 163_1 located in the display area DPA and a second portion 163_2 located in the non-display area NDA. The second portion 163_2 may have a thickness smaller than the thickness of the first portion 163_1 and a height smaller than the height of the first portion 163_1. The second portion 163_2 of interlayer insulating film 163 may be located in the non-display area NDA, such as at least near a portion of the gate conductive layer 130 in the pad area PDA. A first step portion STP1 may be defined between the first portion 163_1 and the second portion 163_2. The first step portion STP1 may be aligned with one side of the passivation layer 164. However, exemplary embodiments of the inventive concept are not limited thereto. In an exemplary embodiment where the interlayer insulating film 163 is relatively thin in the portion of the pad region PDA near the gate conductive layer 130, the contact electrodes of the wiring pads WPD, such as the gate overlay 132, can be readily exposed. The interlayer insulating film 163 is shown as having a flat top surface in the display region DPA (e.g., flat in the first direction DR1). However, exemplary embodiments of the inventive concept are not limited thereto. Alternatively, the interlayer insulating film 163 may have a surface shape that reflects any underlying stepped structure. In this embodiment, the thickness of portions of the interlayer insulating film 163 can be compared, for example, from the same flat reference surface (e.g., the top surface of the first substrate 110) where no underlying stepped structure exists.

[0125] A data conductive layer 140 is disposed on the interlayer insulating film 163. For example, as in Figure 5In the exemplary embodiment shown, the bottom surface of the data conductive layer 140 can be directly disposed on the top surface of the interlayer insulating film 163. The second electrode (or upper electrode) of the source electrode SEL and drain electrode DEL in the transistor region TRR and the capacitor CST in the capacitor region CPR can be formed by the data conductive layer 140. The source electrode SEL and drain electrode DEL in the transistor region TRR can be connected to the semiconductor layer 150 through the second contact hole CNT2 penetrating the interlayer insulating film 163. The source electrode SEL can be connected to the lower metal layer 120 through the first contact hole CNT1 penetrating the interlayer insulating film 163 and the buffer layer 161. The data line DTL, the reference voltage line RVL, and the first power line ELVDL can be formed by the data conductive layer 140. The data conductive layer 140 can not overlap with the portion of the gate conductive layer 130 located in the pad region PDA (e.g., on the third-party DR3). For example, as in Figure 5 In the exemplary embodiments shown, the data conductive layer 140 may not be formed in the pad region PDA. However, the exemplary embodiments of the present invention are not limited thereto. For example, in some exemplary embodiments, the data conductive layer 140 may be formed in the pad region PDA, but does not overlap with the portion of the gate conductive layer 130 located in the pad region PDA.

[0126] The data conductive layer 140 may include a data conductive metal layer 141 and a data capping layer 142 disposed on the data conductive metal layer 141. The data conductive metal layer 141 may be formed as a single layer or a multilayer film. For example, the data conductive metal layer 141 may include a main data metal layer 141a and a data substrate layer 141b disposed below the main data metal layer 141a. The data substrate layer 141b, the main data metal layer 141a, and the data capping layer 142 may all be formed of conductive materials. Figure 5 In the exemplary embodiment, the main data metal layer 141a can be directly disposed on the data substrate layer 141b (e.g., on the third-direction DR3), and the data overlay layer 142 can be directly disposed on the main data metal layer 141a (e.g., on the third-direction DR3). No insulating layer may be disposed between the layers of the data conductive layer 140 that overlap each other in the thickness direction (e.g., on the third-direction DR3). In the exemplary embodiment, the data substrate layer 141b, the main data metal layer 141a, and the data overlay layer 142 can be patterned using a single mask process. The shape of the sidewalls of the data conductive layer 140 can be substantially the same as the shape of the sidewalls of the gate conductive layer 130.

[0127] The data substrate layer 141b may contribute to the film formation properties (e.g., adhesion) of the main data metal layer 141a, or may prevent reactive materials from penetrating the main data metal layer 141a from the interlayer insulating film 163. In an exemplary embodiment, the data substrate layer 141b may include materials such as Ti, Ta, Ca, Cr, Mg, or Ni. However, exemplary embodiments of the inventive concept are not limited thereto.

[0128] The main data metal layer 141a can transmit signals and can be formed of a low-resistivity material. In an exemplary embodiment, the main data metal layer 141a can have a thickness greater than the thickness of the data substrate layer 141b and the data overlay layer 142 (e.g., length on the third-direction DR3), and can be formed of a material with a lower resistance than the data substrate layer 141b and the data overlay layer 142. In an exemplary embodiment, the main data metal layer 141a can include materials such as Cu, Mo, Al, or Ag. However, exemplary embodiments of the inventive concept are not limited thereto.

[0129] In an exemplary embodiment, a data overlay 142 covers and protects the main data metal layer 141a from above it. The data overlay 142 protects the main data metal layer 141a from etchants or other chemicals used in forming layers or elements (e.g., in forming the third contact via CNT3) above the conductive data layer 140. The data overlay 142 also prevents the via layer 165 from directly contacting the main data metal layer 141a, and thus prevents the main data metal layer 141a from being corroded by the material of the via layer 165. The data overlay 142 also prevents the material (e.g., Cu) of the main data metal layer 141a from diffusing into layers disposed above it. The data overlay 142 can be in direct contact with the main data metal layer 141a.

[0130] The data coating 142 may include ZIO, IZO, or ITO. For example, the data coating 142 may include a ZIO film, an IZO film, or an ITO film, or it may be formed as a Ti / Mo / ITO multilayer film.

[0131] For example, the data conductive layer 140 may comprise a three-layer structure of Ti / Cu / ZIO, or a stack of Ti / Cu / Ti / Mo / ITO. The data conductive layer 140 and the gate conductive layer 130 may comprise the same material and have the same stacked structure. However, exemplary embodiments of the inventive concept are not limited thereto.

[0132] A passivation layer 164 is disposed on the data conductive layer 140. For example, as in Figure 5In an exemplary embodiment, the passivation layer 164 may (e.g., on a third-party DR3) be directly disposed on the data conductive layer 140. The passivation layer 164 covers and protects the data conductive layer 140. In an exemplary embodiment, the passivation layer 164 may include an inorganic insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, or zinc oxide. However, exemplary embodiments of the inventive concept are not limited thereto. In an exemplary embodiment, the passivation layer 164 may be formed in the display area DPA and may not be formed in at least a portion of the non-display area NDA. The passivation layer 164 may not be formed on the portion of the gate conductive layer 130 located in the pad area PDA, and therefore may not overlap with the portion of the gate conductive layer 130 located in the pad area PDA. For example, the passivation layer 164 may not overlap with the relatively thin second portion 163_2 of the interlayer insulating film 163 in the pad area PDA. Figure 5 In an exemplary embodiment, the lateral end (or lateral side) of the passivation layer 164 (e.g., on the first direction DR1) may be aligned with the first step portion STP1 of the interlayer insulating film 163.

[0133] A via layer 165 is disposed on the passivation layer 164. The via layer 165 can be configured to cover the top surface of the passivation layer 164 and the side of the passivation layer 164 adjacent to the pad area PDA. In the pad area PDA, the via layer 165 can be (e.g., on a third-direction DR3) directly disposed on the passivation layer 164. Figure 5 In the exemplary embodiment shown, the pathway layer 165 may also be directly disposed on the passivation layer 164 in the display area DPA (e.g., on the third-party DR3).

[0134] In an exemplary embodiment, the pathway layer 165 may include an organic insulating material, such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or BCB. The pathway layer 165 may also include a photosensitive material. For example, the pathway layer 165 may include polyimide. However, exemplary embodiments of the present invention are not limited thereto.

[0135] The via layer 165 can be stepped. For example, the via layer 165 can have a stepped structure with different heights in different regions (e.g., the distance from the top surface of the via layer 165 to the top surface of the first substrate 110 on a third-direction DR3). The via layer 165 can include a first region 165_1 having a first height, a second region 165_2 having a second height smaller than the first height, and a third region 165_3 having a third height smaller than the second height. The height of the via layer 165 can be measured from a reference surface such as the top surface of the first substrate 110. The via layer 165 can have a generally flat surface, regardless of the presence and shape of the pattern formed underneath. The via layer 165 can be stepped at each boundary between the different regions.

[0136] The first region 165_1 and the second region 165_2 of the pass layer 165 may be located in the display area DPA. The first region 165_1 of the pass layer 165 may overlap with the pixel electrode PXE (e.g., on the third-direction DR3). The second region 165_2 of the pass layer 165 may be located in the non-emitting area NEM of the display area DPA and may not overlap with the pixel electrode PXE (e.g., on the third-direction DR3). The second region 165_2 of the pass layer 165 may be disposed along the periphery of the pixel electrode PXE and may form a grid-shaped groove in the display area DPA (e.g., in a plan view from the third-direction DR3).

[0137] The third region 165_3 of the pass layer 165 can be located in the pad area PDA of the non-display area NDA. Because the pass layer 165 is relatively thin in the pad area PDA, the external device EXD can be easily and efficiently mounted on the wiring pad WPD formed by the gate conductive layer 130. The third region 165_3 of the pass layer 165 can be configured to overlap with the second portion 163_2 of the interlayer insulating film 163.

[0138] The via layer 165 can form a pad-opening PDOP together with the interlayer insulating film 163. The pad-opening PDOP exposes a portion of the gate conductive layer 130 located in the pad region PDA, such as the gate overlay 132. Figure 5 In the exemplary embodiment shown, the via layer 165 and the interlayer insulating film 163 forming the inner sidewall of the pad-aperture PDOP can be aligned with each other in the pad-aperture PDOP. However, the exemplary embodiments of the present invention are not limited thereto. The inner sidewall of the pad-aperture PDOP can be configured (e.g., on the third-direction DR3) to overlap with the gate conductive layer 130.

[0139] The pixel electrode (PXE) is disposed on the pass-through layer 165. For example, in... Figure 2In the exemplary embodiment shown, the pixel electrode PXE can be (e.g., on the third-party DR3) directly disposed on the pass layer 165. The material of the pixel electrode PXE is as described above. Figure 5 As described. For example, a pixel electrode PXE may comprise a three-layer film of ITO / Ag / ITO.

[0140] In an exemplary embodiment, the pixel electrode PXE may be located in the display area DPA, but may not be located in the non-display area NDA. The pixel electrode PXE may overlap with the transistor region TRR and capacitor region CPR of the display area DPA (e.g., on the third-direction DR3). However, exemplary embodiments of the inventive concept are not limited thereto. The pixel electrode PXE may be connected to the source electrode SEL of the driving transistor DTR via a third contact hole CNT3 passing through the pass-through layer 165 and the passivation layer 164.

[0141] The pixel-defining film (PDL) is disposed on the pixel electrode (PXE). For example, as in... Figure 2 In the exemplary embodiment shown, the pixel defining film PDL can be directly disposed on the pixel electrode PXE (e.g., on the third-party DR3). The material of the pixel defining film PDL is as described above. Figure 5 As described. For example, a pixel-defined film (PDL) may include polyimide.

[0142] The pixel defining film (PDL) can be located in the display area (DPA) and may not be located in the non-display area (NDA). The PDL can be configured to overlap with the lateral edge of the pixel electrode (PXE) (e.g., on the third-direction DR3). The PDL can be positioned above the third contact hole (CNT3) to overlap with it (e.g., on the third-direction DR3). Figure 5 In the exemplary embodiment shown, the pixel defining film PDL can completely fill the interior of the third contact hole CNT3. The pixel defining film PDL can be disposed on the portion of the via layer 165 where the pixel electrode PXE is not formed. The pixel defining film PDL can fill the space (or groove) formed by the height difference between the first region 165_1 and the second region 165_2 of the via layer 165. For example, the height of the portion of the pixel defining film PDL overlapping the first region 165_1 of the via layer 165 can be the same as the height of the portion of the pixel defining film PDL overlapping the second region 165_2 of the via layer 165. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0143] The following will describe the production process. Figures 6 to 15 Methods for displaying devices.

[0144] Figure 5 It shows the production Figure 6A cross-sectional view of the process of the method for making a display device.

[0145] Reference Figure 6 A patterned lower metal layer 120 is formed on the first substrate 110. In an exemplary embodiment, the lower metal layer 120 can be formed by a mask process. For example, a material layer for forming the lower metal layer 120 can be deposited on the entire surface of the first substrate 110, and then the material layer can be patterned by photolithography, thereby forming the lower metal layer 120, as shown in... Figure 7 As shown in the image.

[0146] Reference Figure 7 A buffer layer 161 can be formed on the entire surface of the first substrate 110, in which the lower metal layer 120 is formed. For example, in... Figure 7 In the exemplary embodiment, a buffer layer 161 can be formed on the entire surface of the display area DPA and the pad area PDA. A semiconductor layer 150 is formed on the buffer layer 161. In the exemplary embodiment, the semiconductor layer 150 can be formed by a mask process. For example, an oxide semiconductor can be deposited on the entire surface of the buffer layer 161, and then the oxide semiconductor can be patterned by photolithography, thereby forming the semiconductor layer 150, as shown in the example. Figure 8 As shown in the image.

[0147] Reference Figure 9 A patterned gate insulating film 162 and a gate conductive layer 130 are formed on a buffer layer 161 in which a semiconductor layer 150 is formed. The gate insulating film 162 and the gate conductive layer 130 can be formed using a single mask process. For example, in an exemplary embodiment, a material layer for forming the gate insulating film 162 is deposited on the entire surface of the buffer layer 161 in which the semiconductor layer 150 is formed. Then, a material layer for forming the gate conductive metal layer 131 and a material layer for forming the gate capping layer 132 are sequentially deposited on the material layer for forming the gate insulating film 162. A photoresist layer is applied to the material layer for forming the gate capping layer 132, and then the photoresist layer is subjected to an exposure and development process to form a photoresist pattern. Using the photoresist pattern as an etch mask, the material layers for forming the gate capping layer 132, the material layers for forming the gate conductive metal layer 131, and the material layers for forming the gate insulating film 162 are sequentially etched. The photoresist pattern is then removed by a stripping or ashing process. In an alternative exemplary embodiment, instead of using only the photoresist pattern as an etch mask to pattern the gate insulating film 162, the patterned upper layer can be used as a hard mask for etching the lower layer. In this embodiment, the photoresist pattern can be used together with the hard mask as an etch mask. In another exemplary embodiment, the photoresist pattern is removed after the hard mask is formed, and the lower layer can be etched by using the hard mask as an etch mask.

[0148] Reference Figure 10 An interlayer insulating film 163 is stacked on a buffer layer 161 in which a gate conductive layer 130 is formed. A first contact hole CNT1 is formed to expose a portion of the lower metal layer 120, and a second contact hole CNT2 is formed to expose a portion of the semiconductor layer 150 (e.g., the source and drain regions). In an exemplary embodiment, the first contact hole CNT1 and the second contact hole CNT2 can be formed by a mask process. The first contact hole CNT1 and the second contact hole CNT2 can be formed sequentially using different masks. For example, an insulating layer for forming the interlayer insulating film 163 is deposited on the entire surface of the buffer layer 161 in which the gate conductive layer 130 is formed. A first photoresist pattern is formed on the insulating layer for forming the interlayer insulating film 163 to expose a portion of the lower metal layer 120, and the insulating layer and the buffer layer 161 for forming the interlayer insulating film 163 are etched using the first photoresist pattern as an etching mask to form the first contact hole CNT1 that exposes a portion of the lower metal layer 120. The first photoresist pattern is removed, and a second photoresist pattern is formed on the insulating layer used to form the interlayer insulating film 163 to expose a portion of the semiconductor layer 150. The insulating layer used to form the interlayer insulating film 163 is etched using the first photoresist pattern as an etching mask, thereby forming the second contact hole CNT2.

[0149] The first contact hole CNT1 and the second contact hole CNT2 can be formed using the same mask. In this embodiment, the semiconductor layer 150 may be exposed to the etchant during the etching of the buffer layer 161 used to form the first contact hole CNT1. However, because the first contact hole CNT1 is formed first, and then the second contact hole CNT2 is formed using a separate mask, damage to the surface of the semiconductor layer 150 can be suppressed or reduced.

[0150] No contact holes or openings may be formed on the portion of the gate conductive layer 130 that overlaps with the pad area PDA, and the portion of the gate conductive layer 130 located in the pad area PDA may be covered by the interlayer insulating film 163.

[0151] Reference Figure 10 A patterned data conductive layer 140 is formed on the interlayer insulating film 163. In an exemplary embodiment, the data conductive layer 140 can be formed by a masking process. For example, material layers for forming the data conductive metal layer 141 and material layers for forming the data overlay 142 are sequentially deposited on the entire surface of the interlayer insulating film 163. Figure 10In the exemplary embodiment shown, material layers for forming the data conductive metal layer 141 and for forming the data overlay 142 can be deposited even in the first contact hole CNT1 and the second contact hole CNT2, such that the lower metal layer 120 and the semiconductor layer 150 can be connected. A photoresist layer is applied to the material layer for forming the data overlay 142, and then the photoresist layer is subjected to an exposure and development process to form a photoresist pattern. The material layers for forming the data conductive metal layer 141 and for forming the data overlay 142 are etched using the photoresist pattern as an etch mask. The photoresist pattern is then removed, such as by a stripping or ashing process, to form the data conductive layer 140, as... Figure 11 As shown.

[0152] Patterning of the data conductive layer 140 can be performed, and the interlayer insulating film 163 covers and protects the portion of the gate conductive layer 130 located in the pad region PDA. Therefore, the portion of the gate conductive layer 130 located in the pad region PDA is prevented from reacting with the etchant used in the patterning of the data conductive layer 140.

[0153] Reference Figure 11 A passivation layer 164 is formed on the interlayer insulating film 163 in which the data conductive layer 140 is formed, and a photoresist pattern is formed on the passivation layer 164.

[0154] A passivation layer 164 is deposited on the entire surface of the interlayer insulating film 163 in which the data conductive layer 140 is formed. In an exemplary embodiment, the passivation layer 164 can be deposited on the entire upper surface of the display area DPA and the pad area PDA. A photoresist layer is then formed on the passivation layer 164, and the photoresist layer is then subjected to exposure and development processes to form a photoresist pattern PR1. The photoresist pattern PR1 includes a first opening OP1 exposing the portion of the passivation layer 164 that overlaps with the source electrode SEL in the transistor region TRR, and a second opening OP2 exposing the pad area PDA. Figure 12 In the exemplary embodiment shown, the second opening OP2 may be formed in a portion of the display area DPA and may extend to the pad area PDA. For example, the width of the first opening OP1 (e.g., its length in a direction parallel to the top surface of the first substrate 110) may be less than or equal to the width of the source electrode SEL, and the width of the second opening OP2 may be greater than the width of the portion of the gate conductive layer 130 located in the pad area PDA. However, exemplary embodiments of the inventive concept are not limited thereto.

[0155] Reference Figure 12The passivation layer 164 is etched using a photoresist pattern PR1 as an etching mask. Therefore, the portion of the passivation layer 164 exposed by the first opening OP1 is etched away, forming a contact hole to expose the source electrode SEL in the transistor region TRR. The portion of the passivation layer 164 exposed by the second opening OP2 is also removed, exposing the interlayer insulating film 163 on the portion of the gate conductive layer 130 located in the pad region PDA. The passivation layer 164 is not exposed at least on the portion of the gate conductive layer 130 located in the pad region PDA, and the portion of the gate conductive layer 130 located in the pad region PDA does not overlap with the passivation layer 164 in the thickness direction.

[0156] In some exemplary embodiments, the portion of the interlayer insulating film 163 exposed by the second opening OP2 can be further etched, allowing the thickness of the interlayer insulating film 163 in the pad area PDA to be reduced (e.g., a first portion 163_1 and a second portion 163_2 can be formed). Figure 13 The interlayer insulating film 163 can be thinner in the portion of the gate conductive layer 130 located in the transistor region TRR or the capacitor region CPR compared to the etching process thereon. However, the portion of the gate conductive layer 130 located in the pad region PDA is still covered by the interlayer insulating film 163 and is not exposed by the etching process. The reduced thickness of the interlayer insulating film 163 in the pad region PDA allows subsequent “whole surface” etching processes to expose the portion of the gate conductive layer 130 located in the pad region PDA to be effectively performed.

[0157] Reference Figure 13 A patterned via layer 165 is formed on the top portion of the passivation layer 164, as well as the display area DPA and the pad area PDA, where the passivation layer 164 has been removed. The via layer 165 may have a generally flat surface and may have different heights in different areas. For example, the height of the via layer 165 is smaller in the pad area PDA than in the display area DPA.

[0158] The pass-through layer 165 may include a third opening OP3 and a fourth opening OP4. The third opening OP3 exposes the contact hole of the exposed source electrode SEL in the passivation layer 164, and the fourth opening OP4 exposes a portion of the interlayer insulating film 163 on the portion of the gate conductive layer 130 located in the pad region PDA. The third opening OP3 may form a third contact hole CNT3 together with the contact hole of the exposed source electrode SEL in the passivation layer 164. For example, as in... Figure 14In the exemplary embodiment shown, the width of the third opening OP3 (e.g., the length of the third opening in a direction parallel to the top surface of the first substrate 110) can be greater than the width of the contact hole of the exposed source electrode SEL of the passivation layer 164; and the width of the fourth opening OP4 can be less than the width of the portion of the interlayer insulating film 163 located in the pad region PDA with a reduced thickness, and can also be less than the width of the portion of the gate conductive layer 130 located in the pad region PDA. However, the exemplary embodiments of the present invention are not limited thereto.

[0159] In an exemplary embodiment, the via layer 165 may comprise, for example, an organic material, including a photosensitive material. In this embodiment, the via layer 165 is formed by applying an organic material layer for forming the via layer 165 and subjecting the organic material layer to exposure and development processes to form a third opening OP3 and a fourth opening OP4. In an exemplary embodiment, the via layer 165 with different heights in different regions can be formed by using a halftone mask or a slit mask.

[0160] When the via layer 165 is being applied, the via layer 165 may come into contact with the data conductive layer 140. However, because the data overlay layer 142 is formed on top of the data conductive layer 140, direct contact between the via layer 165 and the data conductive metal layer 141 is prevented. Therefore, any corrosion defects that might occur if the via layer 165 and the data conductive metal layer 141 were in direct contact with each other can be prevented.

[0161] Reference Figure 15 A patterned pixel electrode PXE is formed on the pass layer 165. In an exemplary embodiment, the pixel electrode PXE can be formed by a mask process. A material layer for forming the pixel electrode PXE is deposited on the entire surface of the pass layer 165. The material for forming the pixel electrode PXE can even be deposited in the third contact hole CNT3, and thus can be connected to the source electrode SEL.

[0162] A photoresist layer is applied to the material layer used to form the pixel electrode PXE, and then the photoresist layer is subjected to an exposure and development process to form a photoresist pattern PR2 having the shape used to form the pixel electrode PXE. The material layer used to form the pixel electrode PXE is then etched using the photoresist pattern PR2 as an etching mask. In an exemplary embodiment, the material layer used to form the pixel electrode PXE can be etched by wet etching. However, exemplary embodiments of the inventive concept are not limited thereto. A portion of the gate conductive layer 130 located in the pad region PDA is covered and protected by a portion of the interlayer insulating film 163 having a reduced thickness. Therefore, the portion of the gate conductive layer 130 located in the pad region PDA is prevented from contacting and being damaged by the etchant used in the etching of the pixel electrode PXE.

[0163] Reference Figures 6 to 15 A "whole surface" etching process (e.g., an etching process for the entire exposed upper surface) is performed using the photoresist pattern PR2 left on the pixel electrode PXE, thereby removing the interlayer insulating film 163 from the portion of the gate conductive layer 130 located in the pad region PDA to expose the gate conductive layer 130, such as the gate overlay 132. This forms a pad opening PDOP that exposes a portion of the gate conductive layer 130. The via layer 165 and the interlayer insulating film 163 forming the pad opening PDOP can be aligned with each other within the pad opening PDOP. Therefore, the sidewalls of the pad opening PDOP can be substantially flat. The portion of the gate conductive layer 130 exposed by the pad opening PDOP can be used as a wiring pad WPD. Figure 5 In an exemplary embodiment, the gate overlay 132, formed together with the gate conductive metal layer 131 through a single mask process, can be used as a contact electrode for the wiring pad WPD. Therefore, no additional mask process is required to form the contact electrode for the wiring pad WPD, and thus process efficiency can be improved.

[0164] During the "full surface" etching process, the pixel electrode PXE is covered and protected by the photoresist pattern PR2. However, portions of the via layer 165 not covered by the photoresist pattern PR2 can be exposed and partially etched together with the interlayer insulating film 163. Therefore, the height or thickness of the exposed portions of the via layer 165 can be reduced. Thus, the via layer 165 can have a stepped structure with different heights in different regions. For example, the first region 165_1 of the via layer 165 covered by the pixel electrode PXE in the display area DPA can maintain a first height, and the second region 165_2 of the via layer 165 not covered by the pixel electrode PXE can have a second height smaller than the first height. The height of the via layer 165 can also be reduced in the pad area PDA, allowing the formation of a third region 165_3 with a third height. The photoresist pattern PR2 is then removed, for example, by ashing or stripping processes.

[0165] Reference Figures 6 to 15 A patterned pixel-defining film (PDL) is formed on a via layer 165 in which pixel electrodes (PXEs) are formed. In an exemplary embodiment, the pixel-defining film (PDL) may include an organic material comprising a photosensitive material. In this embodiment, the pixel-defining film (PDL) can be formed by applying an organic material layer for forming the PDL and subjecting the organic material layer to exposure and development processes.

[0166] The pixel defining film (PDL) can be formed along the boundary of the pixel PX and can partially overlap with the pixel electrode PXE. The PDL can be formed to overlap with the third contact hole CNT3. In embodiments where the pixel electrode PXE does not completely fill the third contact hole CNT3 but only partially fills it, the PDL can completely fill the third contact hole CNT3. The PDL can also fill the second region 165_2 of the pass layer 165, which has a relatively small height, and thus can compensate for height differences in the second region 165_2 of the pass layer 165.

[0167] according to Figures 1 to 15 An exemplary embodiment of the invention eliminates the need for additional masking processes for the contact electrodes used to form the wiring pads (WPDs). This reduces the number of required masking processes and improves the efficiency of the manufacturing process.

[0168] Other exemplary embodiments of the inventive concept will be described below, focusing primarily on... Figure 16 Differences in exemplary embodiments.

[0169] Figure 6 Display device and Figure 16 The difference in the display device lies in the structure of the data conductive layer 140_1. Figure 6 Display device and Figure 16 The difference in display devices also lies in the stacked structure of the insulating layers in the pad area of ​​the PDA.

[0170] Reference Figure 16 The data conductive layer 140_1 does not include the data overlay layer 142. The data conductive layer 140_1 includes a data conductive metal layer 141, which comprises a data substrate layer 141b and a main data metal layer 141a. (As in...) Figure 16 In the exemplary embodiment shown, the main data metal layer 141a can be directly disposed on the data substrate layer 141b. However, the data conductive layer 140_1 does not include the data overlay 142 disposed on the data conductive metal layer 141. The top surface of the data conductive layer 140_1 is formed by the main data metal layer 141a.

[0171] The interlayer insulating film 163a does not have a stepped structure. For example, the thickness of the interlayer insulating film 163a is substantially the same in both the pad area PDA and the display area DPA.

[0172] A passivation layer 164a is disposed on the display area DPA and in the pad area PDA. The passivation layer 164a has a stepped structure with different thicknesses in different regions. For example, in an exemplary embodiment, the passivation layer 164a may include a third portion 164a_3 located in the display area DPA and a fourth portion 164a_4 located in the pad area PDA. Figure 16 In the exemplary embodiment shown, the fourth portion 164a_4 may have a thickness smaller than that of the third portion 164a_3. The fourth portion 164a_4 of the passivation layer 164a may be located in the non-display area NDA, such as the portion located in the pad area PDA at least near the gate conductive layer 130. The second step portion STP2 may be defined between the third portion 164a_3 and the fourth portion 164a_4.

[0173] In an exemplary embodiment where the passivation layer 164a is relatively thin in the portion of the pad region PDA near the gate conductive layer 130, the contact electrodes of the wiring pad WPD can be easily exposed. Simultaneously, the passivation layer 164a, formed of an inorganic material, can have a surface shape that reflects any underlying stepped structure. In this embodiment, the thickness of a portion of the passivation layer 164a can be compared, for example, to a portion measured from the same flat reference surface (e.g., the top surface of the interlayer insulating film 163a) where no underlying stepped structure exists.

[0174] The via layer 165a may not be located in the pad area of ​​the PDA. Therefore, the via layer 165a may include a first region 165a_1 with a first height and a second region 165a_2 with a second height smaller than the first height. For example, in... Figure 5 In the exemplary embodiment shown, the second region 165a_2 may be located on the portion of the display area DPA adjacent to the pad area PDA, and the first region 165a_1 may be located on other portions of the display area DPA. However, the via layer 165a differs from the second region by not including a third region having a third height. Figures 17 to 21 An exemplary embodiment is provided. The side of the via layer 165 facing the pad area PDA can be aligned with the second step portion STP2 of the passivation layer 164a. Furthermore, the passivation layer 164a and the interlayer insulating film 163a forming the pad opening PDOP can be aligned with each other in the pad opening PDOP.

[0175] Figure 16 It shows the production Figures 6 to 9 A cross-sectional view of the process of the method for making a display device.

[0176] The process of forming a patterned lower metal layer 120, a patterned buffer layer 161, a semiconductor layer 150, a gate insulating film 162, and a gate conductive layer 130, as well as an interlayer insulating film 163a, on a first substrate 110, and forming a first contact hole CNT1 and a second contact hole CNT2, is as follows: Figure 17 Their corresponding parts are the same.

[0177] Reference Figure 10 A patterned data conductive layer 140_1 is formed on the interlayer insulating film 163a. ​​The data conductive layer 140_1 differs from other layers by not including a data overlay 142 (e.g., disposed above the main data metal layer 141a). Figure 10 The data conductive layer 140. The main data metal layer 141a forms the top surface of the data conductive layer 140. The data conductive layer 140_1 is connected to... Figure 18 The data conductive layer 140 is formed in essentially the same way, and therefore its detailed description will be omitted.

[0178] Reference Figure 18 A passivation layer 164a is formed on the interlayer insulating film 163a in which the data conductive layer 140_1 is formed. For example, in Figures 16 to 21 In the exemplary embodiment shown, a passivation layer 164a can be formed over the entire display area DPA and pad area PDA. A patterned via layer 165a is formed on the passivation layer 164a. Figures 6 to 15 In an exemplary embodiment, with Figure 19 Unlike the exemplary embodiment, the via layer 165a is formed directly on the passivation layer 164a without etching the passivation layer 164a. Therefore, the passivation layer 164a can be disposed on the entire pad area PDA and the entire display area DPA.

[0179] In an exemplary embodiment, the via layer 165a may have a generally flat surface and may have different heights in different areas. For example, the height of the via layer 165a may be smaller in the pad area PDA than in the display area DPA.

[0180] The pass-through layer 165a may include a third opening OP3 and a fourth opening OP4, the third opening OP3 exposing the portion of the passivation layer 164a located on the source electrode SEL, and the fourth opening OP4 exposing a portion of the passivation layer 164a located on the portion of the gate conductive layer 130 located in the pad area PDA.

[0181] In an exemplary embodiment, the pathway layer 165a may comprise an organic material including a photosensitive material, and can be formed by applying an organic material layer for forming the pathway layer 165a and subjecting the organic material layer to exposure and development processes to form an opening. The pathway layer 165a can be formed with different heights in different regions by using a halftone mask or a slit mask.

[0182] The data conductive layer 140_1 does not include a data overlay. However, because the data conductive layer 140_1 is covered by the passivation layer 164a, the pass layer 165a and the data conductive layer 140_1 are not in direct contact with each other when the pass layer 165a is applied. Therefore, any corrosion defects that might occur if the pass layer 165a and the data conductive metal layer 141 were in direct contact with each other can be prevented.

[0183] Then, refer to Figure 19 A full-surface etching process is performed to remove the portion of passivation layer 164a exposed by the third opening OP3 and the portion of passivation layer 164a exposed by the fourth opening OP4. This forms the third contact hole CNT3, exposing the surface of the source electrode SEL, and exposes a portion of the interlayer insulating film 163a located on the portion of the first gate conductive layer 130 located in the pad region PDA. In an exemplary embodiment, the full-surface etching process can be a dry etching process. The portion of the via layer 165a exposed by the full-surface etching process can also be etched together with the passivation layer 164a, allowing a reduction in the height or thickness of the via layer 165a. A partial etching process can be further performed on the portion of the interlayer insulating film 163a exposed by the fourth opening OP4, allowing a further reduction in the thickness of the interlayer insulating film 163a in the pad region PDA. For example, due to Figure 20 In the "full surface" and partial etching process, the interlayer insulating film 163a can be made thinner on the portion of the gate conductive layer 130 located in the pad region PDA than on the portion of the gate conductive layer 130 located in the display region DPA. However, the portion of the gate conductive layer 130 located in the pad region PDA is still covered by the interlayer insulating film 163a and is not exposed. By reducing the thickness of the interlayer insulating film 163a in the pad region PDA, the subsequent "full surface" etching process for exposing the portion of the gate conductive layer 130 located in the pad region PDA can be performed more efficiently.

[0184] Reference Figure 21A patterned pixel electrode PXE is formed on the pass layer 165a. The pixel electrode PXE can be formed by a mask process. For example, a material layer for forming the pixel electrode PXE is deposited on the entire surface of the pass layer 165a. The material for forming the pixel electrode PXE can even be deposited in the third contact hole CNT3, and thus can be connected to the source electrode SEL.

[0185] A photoresist layer is applied to the material layer used to form the pixel electrode PXE, and then the photoresist layer is subjected to exposure and development processes to form a photoresist pattern PR3 having the shape used to form the pixel electrode PXE. Subsequently, the material layer used to form the pixel electrode PXE is etched using the photoresist pattern PR3 as an etching mask. The material layer used to form the pixel electrode PXE can be etched by wet etching. However, exemplary embodiments of the inventive concept are not limited thereto. The portion of the gate conductive layer 130 located in the pad region PDA is covered and protected by a portion of the interlayer insulating film 163a having a reduced thickness. Therefore, the portion of the gate conductive layer 130 located in the pad region PDA is prevented from contacting and being damaged by the etchant used in etching the pixel electrode PXE.

[0186] Reference Figures 17 to 21 A “whole surface” etching process is performed using the photoresist pattern PR3 left on the pixel electrode PXE, thereby removing the interlayer insulating film 163 from the portion of the gate conductive layer 130 located in the pad area PDA to expose the gate conductive layer 130, such as the gate overlay 132.

[0187] The exposed portion of the gate conductive layer 130 located in the pad area PDA can be used as a wiring pad WPD. Figure 21 In an exemplary embodiment, the gate overlay 132, formed together with the gate conductive metal layer 131 through a single mask process, can be used as a contact electrode for the wiring pad WPD. Therefore, no additional mask process is required to form the contact electrode for the wiring pad WPD, thus improving process efficiency.

[0188] Simultaneously, during the "whole surface" etching process, the pixel electrode PXE is covered and protected by the photoresist pattern PR3. However, the via layer 165a, which is not covered by the photoresist pattern PR3, can be exposed and can be partially etched together with the interlayer insulating film 163a. ​​Therefore, the height or thickness of the exposed portion of the via layer 165a can be reduced. Thus, the via layer 165a can have a stepped structure with different heights in different regions. The first region 165a_1 of the via layer 165a, covered by the pixel electrode PXE located in the display area DPA, can have a first height, and the second region 165a_2 of the via layer 165a, which is not covered by the pixel electrode PXE, can have a second height smaller than the first height. The via layer 165a, which has a relatively small thickness in the pad area PDA, can be completely removed from the pad area PDA by the "whole surface" etching process. Once the via layer 165a is removed from the pad area PDA, the passivation layer 164a is exposed. Figure 21 The "full surface" etching process also reduces the thickness of the passivation layer 164a, allowing it to be divided into a third part 164a_3 and a fourth part 164a_4. For example, in... Figure 16 In the exemplary embodiment shown, the third portion 164a_3 of the passivation layer 164a may be disposed in the display area DPA, and the fourth portion 164a_4 of the passivation layer 164a may be disposed on the edge of the display area DPA and on a portion of the pad area PDA. The second step portion STP2 may be defined between the third portion 164a_3 and the fourth portion 164a_4. The photoresist pattern PR3 is removed, for example, by ashing or stripping processes.

[0189] Reference Figures 17 to 21 A patterned pixel-defining film (PDL) is formed on the pass layer 165a in which the pixel electrode (PXE) is formed. The pixel-defining film (PDL) may contain, for example, an organic material including a photosensitive material. In this embodiment, the pixel-defining film (PDL) can be formed by applying an organic material layer for forming the PDL and subjecting the organic material layer to exposure and development processes.

[0190] The pixel defining film (PDL) can be formed along the boundary of the pixel PX and can partially overlap with the pixel electrode PXE. The PDL can be formed to overlap with the third contact hole CNT3. In embodiments where the pixel electrode PXE does not completely fill the third contact hole CNT3 but only partially fills it, the PDL can completely fill the third contact hole CNT3. The PDL can also fill the second region 165a_2 of the pass layer 165a, which has a relatively small height, and thus can compensate for the height difference in the second region 165a_2 of the pass layer 165a.

[0191] according to ​ In the exemplary embodiment, no additional masking process is required for the contact electrodes of the wiring pads (WPD). Furthermore, in the exemplary embodiment where no data overlay is disposed in the data conductive layer 140_1, direct contact between the data conductive metal layer 141 of the data conductive layer 140_1 and the via layer 165a is prevented, thus preventing corrosion defects. Additionally, since the passivation layer 164a can be etched using the third opening OP3 of the via layer 165a without the need for an additional mask, the number of required masking processes is reduced, thereby further improving process efficiency.

[0192] In concluding this detailed description, those skilled in the art will understand that many variations and modifications can be made to the exemplary embodiments without substantially departing from the principles of the inventive concept. Therefore, the disclosed exemplary embodiments of the inventive concept are used only in a general and descriptive sense and are not intended to be limiting.

Claims

1. A display device, wherein, The display device includes: The substrate includes the display area and the pad area; A gate conductive layer is disposed on the substrate, the gate conductive layer comprising: A gate conductive metal layer and a gate overlay disposed on the gate conductive metal layer; and The gate conductive layer forms a gate electrode disposed in the display area and a wiring pad disposed in the pad area; An interlayer insulating film is disposed on the gate conductive layer and covers the gate electrode, wherein the wiring pads are exposed by pad openings; A data conductive layer is disposed on the interlayer insulating film in the display area, and the data conductive layer includes a source electrode and a drain electrode; A passivation layer is disposed on the data conductive layer and covers the source electrode and the drain electrode; A pathway layer is disposed on the passivation layer; and A pixel electrode is disposed on the via layer, and the pixel electrode is connected to the source electrode through a contact hole penetrating the via layer and the passivation layer. in, The pathway layer includes a first region in the display area that overlaps with the pixel electrode and a second region in the display area that does not overlap with the pixel electrode and has a height smaller than that of the first region.

2. The display device according to claim 1, wherein: The pad opening is formed by the interlayer insulating film and the pathway layer; and The interlayer insulating film and the via layer form aligned inner sidewalls of the pad openings.

3. The display device according to claim 2, wherein, The passivation layer is not located in the pad area.

4. The display device according to claim 3, wherein, The pathway layer is directly disposed on the interlayer insulating film in the pad area.

5. The display device according to claim 2, wherein: The pathway layer further includes a third region disposed in the pad area; and The third region has a height that is smaller than that of the second region.

6. The display device according to claim 5, wherein: The interlayer insulating film includes a first portion disposed in the display area and a second portion disposed in the pad area and having a thickness less than that of the first portion; and The second part overlaps with the third region of the pathway layer.

7. The display device according to claim 1, wherein: The pad opening is formed by the interlayer insulating film and the passivation layer; and The interlayer insulating film and the passivation layer form aligned inner sidewalls of the pad openings.

8. The display device according to claim 7, wherein, The pathway layer is not located in the pad area.

9. The display device according to claim 7, wherein, The passivation layer includes a third portion disposed in the display area and a fourth portion disposed in the pad area and having a thickness smaller than that of the third portion.

10. The display device according to claim 1, wherein, The display device further includes: A pixel defining film is disposed on the pixel electrode and fills the second region of the via layer.

11. The display device according to claim 1, wherein, The gate coating comprises at least one selected from indium zinc oxide film, zinc indium oxide film, indium tin oxide film, and titanium / molybdenum / indium tin oxide film.

12. The display device according to claim 11, wherein, The gate conductive metal layer includes a gate main metal layer that contacts the gate cladding from below the gate cladding, and the gate main metal layer includes copper.

13. A method for manufacturing a display device, wherein, The method includes: Forming a substrate that includes a display area and a pad area; A gate conductive layer is formed on the substrate. The gate conductive layer includes a gate conductive metal layer and a gate cladding layer deposited on the gate conductive metal layer. The gate conductive layer forms a gate electrode disposed in the display area and a wiring pad disposed in the pad area. An interlayer insulating film is formed on the gate conductive layer; A data conductive layer is formed on the interlayer insulating film, the data conductive layer including a source electrode and a drain electrode disposed in the display area; A passivation layer is formed on the data conductive layer; A via layer is formed on the passivation layer, the via layer including a first opening overlapping the source electrode in the display area and a second opening overlapping the wiring pad in the pad area; A first material layer for forming pixel electrodes is formed on the via layer, a first mask pattern is formed on the first material layer, and the first material layer is etched using the first mask pattern; and The wiring pads are exposed by etching the interlayer insulating film that overlaps with the wiring pads using the remaining portion of the first mask pattern.

14. The method according to claim 13, wherein, The etching of the interlayer insulating film using the remaining portion of the first mask pattern is performed by a full surface etching process.

15. The method according to claim 14, wherein, The portion of the pathway layer not covered by the first mask pattern is etched using the entire surface etching process, and the pathway layer is divided into a first region that overlaps with the pixel electrode and a second region that does not overlap with the pixel electrode and has a height smaller than that of the first region.

16. The method according to claim 13, wherein, The formation of the passivation layer includes: A second material layer is formed on the data conductive layer; A second mask pattern is formed on the second material layer to expose the pad area and the portion of the second material layer that overlaps with the source electrode; and The passivation layer is etched using the second mask pattern.

17. The method according to claim 16, wherein, During the etching of the passivation layer, the portion of the interlayer insulating film located in the pad area is etched to divide the interlayer insulating film into a first portion disposed in the display area and a second portion disposed in the pad area and having a thickness smaller than that of the first portion.

18. The method according to claim 13, wherein, The method further includes: The via layer is formed on the unetched portion of the passivation layer; and The portion of the passivation layer exposed by the second opening of the via layer is removed by performing a full surface etching process.

19. The method according to claim 13, wherein, The gate coating comprises at least one selected from indium zinc oxide film, zinc indium oxide film, indium tin oxide film, and titanium / molybdenum / indium tin oxide film.

20. The method according to claim 19, wherein, The gate conductive metal layer includes a gate main metal layer that is in contact with the gate cover layer from below the gate cover layer and includes copper.

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